JP4923886B2 - Level shift circuit and DC-DC converter - Google Patents

Description

  The present invention relates to a technology of a level shift circuit in which an output secondary side operates at an operating potential different from an operating potential on an input primary side and transmits a signal to a predetermined system.

First, FIG. 4 will be described. This figure shows a first configuration example of a conventional level shift circuit. This configuration example is disclosed in Patent Document 1.
The level shift circuit shown in FIG. 4 has the power supply potentials V1H and V1L in the primary system and the power supply potentials V2H and V2L in the secondary system, and the amplitude of V1H-V1L input to the primary side. Is converted into a signal of V2H-V2L amplitude on the secondary side.

  In the circuit of FIG. 4, when the circuit input IN is at the H (high) level (that is, V1H), M41 of the N-channel MOS transistors M41 and M42 is turned off and M42 is turned on by the action of the inverter U41. Of the P-channel MOS transistors M43 and M44, M43 is turned on and M44 is turned off. Accordingly, the circuit output OUT at this time becomes H level (that is, V2H) by the action of the inverter U42.

  On the other hand, in this circuit, when the circuit input IN is at L (low) level (ie, V1L), M41 is turned on by the action of U41, and M42 is turned off, so that M43 is turned off and M44 is turned on. Accordingly, the circuit output OUT at this time becomes L level (that is, V2L) by the action of U42.

  The constant voltage diodes (Zener diodes) D41 and D42 are for preventing an excessive negative voltage when V2H is regarded as a reference potential from being applied to the gates of M44 and M43 and the input of U42. is there. On the source side of each of M41 and M42, the series connection of the capacitor C41 and the resistor R41 and the series connection of the capacitor C42 and the resistor R44 are connected in parallel to the source resistance R42 of the M41 and the source resistance R43 of the M42, respectively. ing. C41 and C42 increase the source current of M41 and M42 during the period in which the on / off state of M41 and M42 transitions to ensure the response speed of the circuit, while decreasing the source current in a steady state. It functions as current control means.

Next, FIG. 5 will be described. This figure shows a second configuration example of a conventional level shift circuit. This configuration example is disclosed in Patent Document 2.
In FIG. 5, inverters U51 and U52 constituting a latch circuit, a capacitor C51, and an inverter U53 constitute a level shift circuit.

  In the circuit of FIG. 5, when the circuit input IN transitions from the L level (ie, V1L) to the H level (ie, V1H), a pulse current that increases the potential of the input of U51 flows through C51. The output becomes L level. Accordingly, the circuit output OUT at this time becomes L level (that is, V2L) by the action of U53.

  On the other hand, when the circuit input IN transitions from the H level (ie, V1H) to the L level (ie, V1L), a pulse current that decreases the potential of the input of U51 flows through C51. Becomes H level. Accordingly, the circuit output OUT at this time becomes L level (that is, V2L) by the action of U53.

In the steady state, the state of the circuit of FIG. 5 is maintained by the latch circuit composed of U51 and U52, so that the amount of current flowing through the circuit is suppressed.
Japanese Patent Laid-Open No. 9-200020 JP 2004-363740 A

The conventional level shift circuit described above has the following problems.
First, in the first configuration example shown in FIG. 4, a current flows constantly to either D41 or D42. That is, when M41 is in the on state, a current flows through a path of D41 → M41 → R42, and when M42 is in an on state, a current flows through the path of D42 → M42 → R43. For this reason, low power consumption is insufficient, and when the potential difference between the primary side and the secondary side is large, it is necessary to use high voltage transistors as M41 and M42.

  Further, in the second configuration example shown in FIG. 5, the pulse is first input to the circuit input IN after the power is turned on (the signal voltage input to the circuit input IN first transits). During this time, the state of the circuit output OUT is indefinite because the state of the latch circuit composed of U51 and U52 is not fixed.

  The present invention has been made in view of the above-described problems, and a problem to be solved is to provide a level shift circuit that consumes less power in a steady state and can guarantee the determination of an output state even immediately after power-on. At the same time, a DC-DC converter including the level shift circuit is provided.

A level shift circuit according to one aspect of the present invention is a level shift circuit in which an output secondary side operates at an operation potential different from an operation potential on an input primary side and transmits a signal to a predetermined system. The first switch is turned on when the potential is high and turned off when the potential of the input signal is low, and is turned off when the potential of the input signal is high. A latch circuit configured by mutually connecting the input and output of the second switch that is turned on when the potential is at a low level, and the first and second inverters operating between the power supply potentials on the secondary side; A first diode connected between one end of the first switch and an input terminal of the first inverter; an end of the second switch; and an input end of the second inverter The the second diode has, the potential of the first switches of the other end and the second switch the other end to the primary side of the high level is applied which is connected between the The input signal is input to the latch circuit only through the first and second diodes , and this feature solves the problems described above.

  According to this configuration, in a steady state in which the potential of the input signal does not change at a high level or a low level, power is not consumed, and the state of the latch circuit transitions due to a change in the input signal. However, since it is determined by the potential of the input signal, the output state is guaranteed even immediately after the power is turned on.

  A DC-DC converter characterized in that the above-described level shift circuit according to the present invention is provided on a signal transmission path for controlling the operation of the high-side switching element is also according to the present invention.

  Since the level shift circuit according to the present invention is configured as described above, the power consumption in the steady state is small, and the output state is ensured even immediately after the power is turned on.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
First, FIG. 1 will be described. This figure shows the configuration of a level shift circuit embodying the present invention. This level shift circuit has power supply potentials V1H and V1L on the primary side, that is, the low-voltage side system, and has a power supply potential V2H and V2L different from the primary side on the secondary side, that is, the high-voltage side system. It has a function of converting a V1H-V1L amplitude signal input to the primary side into a secondary side V2H-V2L amplitude signal.

  The circuit shown in FIG. 1 includes an inverter U11, P-channel MOS transistors (MOSFETs) M11 and M12, diodes D11 and D12, and a latch circuit 10. Here, the latch circuit 10 is configured such that the inputs and outputs of the inverters U12 and U13 are connected to each other via resistors R11 and R12. U11 operates between V1H and V1L which are power supply potentials on the primary side, and U12 and U13 operate so as to operate between V2H and V2L which are power supply potentials on the secondary side, respectively. It is configured. Note that the output of U13 is led to the output OUT of the circuit of FIG.

  The input of U12 of the latch circuit 10 is also connected to the cathode of D11, and the anode of D11 is connected to the drain of M11. The input of U13 of the latch circuit 10 is also connected to the cathode of D12, and the anode of D12 is connected to the drain of M12. The primary level signal input to the circuit input IN is inverted and input to the gate of M11, which is the first switch, via U11. Further, the level signal is directly input to the M12 gate as the second switch without being inverted. Further, the power supply potential V1H on the primary side is applied to the sources of M11 and M12.

The operation of the level shift circuit shown in FIG. 1 will be described below. Here, a case where the power supply potential V2L on the secondary side is equal to or lower than the power supply potential V1L on the primary side will be described.
In this case, when the circuit input IN is at the H level (that is, V1H), M11 is turned on (the drain-source is in a conductive state), and the potential of the drain becomes almost H level, while M12 is turned off (drain) -The source is cut off), so that D11 becomes conductive and D12 becomes cut off. Accordingly, at this time, the cathode of D11 (that is, the input of U12) is almost at the H level, so that the latch circuit 10 stores this and the circuit output OUT maintains the H level (that is, V2H).

  On the other hand, in this case, when the circuit input IN is at the L level (that is, V1L), M11 is turned off, while M12 is turned on and the drain potential becomes almost H level, so that D11 is cut off. D12 becomes conductive. Accordingly, at this time, the cathode of D12 (that is, the input of U13) is substantially at the H level, so that the latch circuit 10 stores this and the circuit output OUT maintains the L level (that is, V2L).

  Thus, in the level shift circuit shown in FIG. 1, the state of the circuit in the steady state where the input level to the circuit input IN is not changed is held by the latch circuit 10, and the level shift circuit shown in FIG. Since there is no steady current flow path as in the circuit, power consumption in the steady state is minimal, and the determination of the output state is guaranteed even immediately after the power is turned on. Further, in the circuit of FIG. 1, even if the potential difference between the primary side and the secondary side is large, if a high withstand voltage is used for D11 and D12, the high withstand voltage that is expensive with respect to M11 and M12 is used. Things are never required.

Next, FIG. 2 will be described. This figure shows the configuration of a DC-DC converter (power converter) that implements the present invention, which is one example of use of the level shift circuit shown in FIG.
The level shift circuit shown in FIG. 1 is a latch circuit when the secondary power supply potential V2L is always high enough that D11 and D12 do not transition from the cutoff state to the conductive state even when M11 and M12 are turned on. Since the state of 10 is not fixed, the circuit output OUT is indefinite. In addition, when the power supply potential V2L on the secondary side is raised after any one of D11 and D12 transitions to the conductive state even once, the level immediately before the rise held by the latch circuit 10 is the circuit output. Output from OUT. Such a level shift circuit can also be used in a circuit as shown in FIG.

  The circuit shown in FIG. 2 is a step-down DC-DC converter having an H-side NMOS configuration. This circuit controls an N channel MOS transistor (MOSFET) M21 which is a switching element on the H (High) side and an N channel MOS transistor (MOSFET) M22 which is a switching element (synchronous rectifying element) on the L (Low) side. The output voltage VOUT is generated from the input voltage PVDD by alternately conducting at a predetermined time ratio based on the control signal output from the circuit 22.

  In FIG. 2, the output signal of the control circuit 22 immediately after power-on is such that the L-side M22 is turned on and the H-side M21 is turned off. Here, since the source of M22 is connected to the ground GND, at this time, the connection point M between the source of M21 and the drain of M22 is approximately the ground potential. Further, a capacitor Cb is connected between the connection point M and the cathode of the diode D21. Since the voltage VINT of the power source for driving the control circuit 22 is applied to the anode of D21, charging of Cb is performed. Done. The driver DR21 that drives the gate of the M21 on the H side operates by a voltage generated at both ends of the Cb. The driver DR22 that drives the gate of the M21 on the L side operates with the same power supply voltage VINT as the control circuit 22.

  Next, M22 on the L side is turned off, and then M21 on the H side is turned on. Here, since the input voltage PVDD is applied to the drain of M21, the potential at the connection point M rises from the ground potential to approximately the voltage PVDD. However, at this time, the potential at the connection point BOOT between the cathode of D21 and Cb also rises in the same manner with the voltage at both ends of Cb added to the potential at the connection point M. Therefore, a voltage necessary for the DR 21 to drive the H-side M 21 is secured at this time. Further, when the potential at the connection point BOOT rises and becomes higher than the potential of the voltage VINT, D21 is cut off, so that the charge stored in Cb by the above-described charging is discharged to the drive power source side of the control circuit 22. There is nothing.

  Thereafter, M21 on the H side is turned off, and then M22 on the L side is turned on. Then, the potential at the connection point M again becomes approximately the ground potential. At this time, Cb is charged through D21 to which the voltage VINT is applied to the anode.

  Thereafter, the above-described operation is repeated every time the H-side M21 and the L-side M22 are alternately turned on and off as described above at a predetermined time ratio. Here, a series connection of an inductance L and a capacitor Cout is inserted between the connection point M and the ground GND. Therefore, from the connection point VOUT between L and Cout, a direct current voltage obtained by smoothing the signal (square wave signal) generated at the connection point M in the above-described repetitive operation by the low-pass filter composed of L and Cout can be obtained. it can.

  The circuit shown in FIG. 2 operates as described above. That is, since the DR 21 operates with the potential at the connection point M as a reference, the control signal output from the control circuit 22 cannot be directly received during the period when the potential at the connection point M is higher than the ground potential. Therefore, in the circuit of FIG. 2, among the four transmission lines that transmit the control signals (enable signal and clock signal) output from the control circuit 22 to each of DR21 and DR22, on the two transmission lines toward DR21. In the figure, level shift circuits 21a and 21b are respectively inserted.

  In FIG. 2, the circuit shown in FIG. 1 can be used as a level shift circuit 21a that performs level shift of an enable signal transmitted from the control circuit 22 to the DR 21. At this time, the power supply potentials V1H and V1L on the primary side in the circuit of FIG. 1 are the potentials VINT and GND (ground potential) of the drive power supply of the control circuit 22 in FIG. 2, respectively, and the secondary side in the circuit of FIG. The power supply potentials V2H and V2L are the potential at the connection point BOOT and the potential at the connection point M, respectively. The DR21 enable signal output from the control circuit is input to the input IN of the circuit of FIG. 1, and the output OUT of the circuit of FIG. 1 is connected to the enable input of the DR21.

  Since the circuit of FIG. 2 operates as described above, the potential of the connection point M (that is, the potential of V2L in FIG. 1) generally varies between the ground potential and the input voltage PVDD, and this potential is equal to the ground potential ( That is, it is equal to or higher than the potential V1L in FIG. However, since the control circuit 22 must first charge Cb immediately after turning on the power to the circuit of FIG. 2, the DR 22 is controlled so that the M22 is turned on and the potential at the connection point M is always set to the ground potential. Then, since the state of the latch circuit 10 in FIG. 1 is determined at this time, the indefinite state of the circuit output OUT in FIG. 1 is immediately resolved immediately after the power is turned on. Therefore, for example, since the output of the DR21 in the initial state can be fixed to the L level by the determined enable signal, the operation of the DC-DC converter shown in FIG. 2 is not adversely affected.

  When the circuit shown in FIG. 1 is used as the level shift circuit 21a in FIG. 2 as described above, the control circuit 22 can control the operation enable of the DR 21 because the potential at the connection point M is the ground potential. The period is limited. However, the limitation that the operation enable of the DR 21 cannot be controlled outside this period does not become an operational problem of the DC-DC converter shown in FIG.

  In the DC-DC converter shown in FIG. 2, in FIG. 2, as the level shift circuit 21b for performing the level shift of the clock signal transmitted from the control circuit 22 to the DR 21, for example, the applicant of the present application precedes this application. The one disclosed in the specification of Japanese Patent Application No. 2005-338083 filed in Japanese Patent Application No. 2005-338083 can be used.

  3A will be described. FIG. 3A shows a configuration example of the level shift circuit 21b shown in FIG. The level shift circuit shown in FIG. 3A is disclosed in the above specification.

The circuit shown in FIG. 3A includes a latch circuit 30, a pulse generation circuit 31, and N-channel MOS transistors M31 and M32.
The latch circuit 30 is configured such that the inputs and outputs of the inverters U31 and U32 are connected to each other via resistors R31 and R32. Note that U31 and U32 are configured to operate between V2H and V2L, which are power supply potentials on the secondary side. The output of U32 is led to the output OUT of the circuit of FIG. 3A.

  The input of U31 of the latch circuit 30 is connected to the drain of M31, and the gate of M31 is connected to one output OUT1 of the pulse generation circuit 31. The input of U32 of the latch circuit 30 is connected to the drain of M32, and the gate of M32 is connected to the other output OUT2 of the pulse generation circuit 31. Note that the power supply potential V1L on the primary side is applied to the sources of M31 and M32.

  The primary level signal input to the input IN of the circuit shown in FIG. 3A is input to the input IN of the pulse generation circuit 31. The pulse generation circuit 31 is a circuit that outputs a pulse signal at the time of rising and falling of the signal input to the input IN to switch M31 and M32. Note that the pulse generation circuit 31 is configured to operate between V1H and V1L, which are power supply potentials on the primary side.

  Here, FIG. 3B and FIG. 3C will be described. FIG. 3B shows a specific configuration of the pulse generation circuit 31 in FIG. 3A, and FIG. 3C shows input / output waveforms of the pulse generation circuit 31.

As shown in FIG. 3B, the pulse generation circuit 31 includes a delay circuit 32, inverters U33 and U34, and 2-input NOR circuits U35 and U36.
The input IN of the pulse generation circuit 31 is connected to the input of the inverter U33, the input of the delay circuit 32, and one input of the NOR circuit U35. The output of the delay circuit 32 is connected to the input of the inverter U34 and one input of the NOR circuit U36. The output of the inverter U33 is connected to the other input of the NOR circuit U36, and the output of the inverter U34 is connected to the other input of the NOR circuit U35. The output of the NOR circuit U35 is connected to the output OUT1 of the pulse generation circuit 31, and is therefore connected to the gate of M31 in FIG. 3A. The output of the NOR circuit U36 is connected to the output OUT2 of the pulse generation circuit 31, and is therefore connected to the gate of M32 in FIG. 3A.

  The pulse generation circuit 31 is configured as described above. Therefore, a logical product of the inverted signal of the input signal to the circuit input IN and the delayed signal of the input signal by the delay circuit 32 is given to the gate of M31, and the circuit input IN is supplied to the gate of M32. A signal of a logical product of the input signal to and the inverted signal of the delay signal of the input signal by the delay circuit 32 is given.

  As shown in FIG. 3C, in the pulse generation circuit 31, when the input signal to the input IN rises, the level change of the signal is input to the inverter U33 and the delay circuit 32. At this time, since the inverted output from the inverter U33 and the delayed output from the delay circuit 32 are input to the NOR circuit U36, a pulse signal is generated as the output of the NOR circuit U36 as the output OUT2. The pulse width of this pulse signal is determined by the delay time of the delay circuit 32.

  When the input signal to the input IN falls, the level change of the signal is input to one input of the NOR circuit U35 and the delay circuit 32. At this time, the other input of the NOR circuit U35 receives the inverted output of the inverter U34 for the delayed output from the delay circuit 32. Therefore, a pulse signal is generated as an output of the NOR circuit U35 that is the output OUT1. The pulse width of this pulse signal is determined by the delay time of the delay circuit 32.

Based on the operation of the pulse generation circuit 31 described above, the circuit operation of FIG. 3A will be described.
First, when the input signal to the circuit input IN transitions from the L level to the H level, the pulse generated by the pulse generation circuit 31 is input from the output OUT2 to the gate of M32, so that M32 is turned on. Then, the potential at the input of U32 of the latch circuit 40 is lowered, and the output of the latch circuit 40 (that is, the output OUT of the circuit shown in FIG. 3A) becomes the H level (that is, V2H).

  Next, when the input signal to the circuit input IN transitions from the H level to the L level, the pulse generated by the pulse generation circuit 31 is input from the output OUT1 to the gate of M31, so that M31 is turned on. Then, the potential at the input of U31 of the latch circuit 40 is pulled down, and the output of the latch circuit 40 (that is, the output OUT of the circuit shown in FIG. 3A) becomes L level (that is, V2L).

  As described above, in the level shift circuit having the configuration shown in FIGS. 3A and 3B, in a steady state in which there is no potential change in the circuit input IN, both M31 and M32 are in an off state, so that the current is supplied. The power consumption is not consumed, and there is no restriction on the power supply potential V2L on the secondary side as in the level shift circuit shown in FIG. However, as in the conventional level shift circuit shown in FIG. 5, the pulse is first input to the circuit input IN after the power is turned on (the signal voltage input to the circuit input IN first transits). During this period, since the state of the latch circuit 30 is not fixed, the state of the circuit output OUT is indefinite. Therefore, immediately after the power is turned on, there is a risk that both M21 and M22 are conducted in the DC-DC converter of FIG. 2 and a through current flows. In order to prevent this, it is necessary to connect the output of the level shift circuit 21a whose value is determined immediately after power-on to the enable input of the DR21, and to shut off M21 immediately after power-on by this enable signal.

  When the circuit of FIG. 3A is used as the level shift circuit 21b in FIG. 2, the power supply potentials V1H and V1L on the primary side in the circuit of FIG. 3A are the potential VINT of the drive power supply of the control circuit 22 in FIG. And GND (ground potential), and the power supply potentials V2H and V2L on the secondary side in the circuit of FIG. 3A are the potential at the connection point BOOT and the potential at the connection point M, respectively. Then, the clock signal CK for DR21 output from the control circuit is input to the input IN of the circuit of FIG. 3A, and the output OUT of the circuit of FIG. 3A is connected to the clock input of DR21.

  Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and various improvements and modifications can be made without departing from the scope of the present invention.

It is a figure which shows the structure of the level shift circuit which implements this invention. It is a figure which shows the structure of the DC-DC converter which implements this invention. It is a figure which shows the structural example of the level shift circuit 21b shown in FIG. It is a figure which shows the specific structure of the pulse generation circuit 31 in FIG. 3A. 4 is a diagram showing input / output waveforms of a pulse generation circuit 31. FIG. It is a figure which shows the 1st structural example of the conventional level shift circuit. It is a figure which shows the 2nd structural example of the conventional level shift circuit.

Explanation of symbols

10, 30 Latch circuit 21a, 21b Level shift circuit 22 Control circuit 31 Pulse generation circuit 32 Delay circuit Cb, Cout, C41, C42, C51 Capacitor D11, D12, D21 Diode D41, D42 Constant voltage diode DR21, DR22 Driver L Inductor M11 M12, M43, M44 P-channel MOS transistors M21, M22, M31, M32, M41, M42 N-channel MOS transistors R11, R12, R31, R32, R41, R42, R43, R44 Resistors U11, U12, U13, U31, U32 , U33, U34,
U41, U42, U51, U52, U53 Inverter U35, U36 NOR circuit

Claims (6)

A level shift circuit that operates on the output secondary side with an operating potential different from the operating potential on the input primary side and transmits a signal to a predetermined system,
A first switch that is on when the potential of the input signal is high, and that is off when the potential of the input signal is low;
A second switch that is turned off when the potential of the input signal is high, and turned on when the potential of the input signal is low;
A latch circuit configured by mutually connecting the input and output of the first and second inverters operating between the power supply potentials on the secondary side;
A first diode connected between one end of the first switch and an input terminal of the first inverter;
A second diode connected between one end of the second switch and an input terminal of the second inverter;
Have
A primary high-level potential is applied to the other end of the first switch and the other end of the second switch, and the input signal to the latch circuit is input to the first and second A level shift circuit characterized by being performed only through the diode . The first switch is a P-channel MOS transistor in which an inverted signal of the input signal is input to a gate,
The second switch is a P-channel MOS transistor in which a non-inverted signal of the input signal is input to the gate.
The level shift circuit according to claim 1.   3. The level shift circuit according to claim 1, wherein input and output of the first and second inverters are connected to each other via a resistor in the latch circuit.   A DC-DC converter comprising the level shift circuit according to any one of claims 1 to 3 on a transmission line of a signal for controlling the operation of a high-side switching element.   The DC-DC converter according to claim 4, wherein the DC-DC converter is a step-down type.   6. The DC-DC converter according to claim 4, wherein the switching element is an N-channel MOS transistor.