JP4937866B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device, and more particularly to a technique effective when applied to a semiconductor device having a nonvolatile memory element.

  As a semiconductor device, for example, a nonvolatile semiconductor memory device called a flash memory is known. In the memory cell of this flash memory, a one-transistor method composed of one nonvolatile element, or two transistors in which one nonvolatile memory element and one selection MISFET (Metal Insulator Semiconductor Field Effect Transistor) are connected in series. The method is known. In a nonvolatile memory element, a floating gate type for storing information in a floating gate electrode (floating gate electrode) between a semiconductor substrate and a control gate electrode (control gate electrode), a semiconductor substrate and a gate electrode, An MNOS (Metal Nitride Oxide Semiconductor) type that uses an ON (oxide film / nitride film: Oxide / Nitride) film and stores information in this gate insulating film, An ONO (oxide film / nitride film / oxide film: Oxide / Nitride / Oxide) film is used as a gate insulating film (information storage insulating film) between the semiconductor substrate and the gate electrode, and information is stored in the gate insulating film. MONOS (Metal Oxide Nitride Oxide Semiconductor) type is known.

  In Japanese Patent Laid-Open No. 2002-164449, a memory gate electrode is disposed on the main surface of a semiconductor substrate with an information storage insulating film interposed therebetween, and switch gate electrodes are disposed on both sides of the memory gate electrode. A multi-storage type nonvolatile memory element is disclosed.

JP 2002-164449 A

For example, the MONOS type nonvolatile memory element erases data by injecting hot holes from the semiconductor substrate side into the silicon nitride film of the charge storage insulating film.
The charge storage insulating film deteriorates with the number of rewrites. For this reason, in the MONOS type nonvolatile memory element, the number of times of rewriting is limited due to deterioration of the charge storage insulating film during the erase operation.

  In view of this, the present inventor has studied the deterioration of the charge storage insulating film in order to improve the number of times of rewriting, and as a result, the gate width Wg (channel width) is increased to increase the drive current (Ids). It has been found that the deterioration of the insulating film can be suppressed. However, when the gate width is increased, the area occupied by the nonvolatile memory element (cell size) increases, and the degree of integration decreases.

  The MONOS type nonvolatile memory element is used for storing program data for operating a logic operation circuit such as a CPU or a DSP. The MONOS type nonvolatile memory element is also used for storing data (processed data) processed by executing the program. According to the market requirement survey of the present inventor, for example, a microcomputer in which a non-volatile memory and a logic operation circuit are mounted has a demand for a large-capacity high-speed non-volatile memory of 1 Mbyte or more, but requires a large number of rewrites. It was found that the memory capacity to do is very small at about 32 Kbytes. Therefore, the present inventor made the present invention by paying attention to the use of the MONOS type nonvolatile memory element.

An object of the present invention is to provide a technique capable of increasing the integration density and improving the number of rewrites of a semiconductor device having a nonvolatile memory element.
The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.

  The object is to mount a first MONOS type nonvolatile memory element and a second MONOS type nonvolatile memory element having a gate width wider than that of the first MONOS type nonvolatile memory element on the same substrate. One MONOS type nonvolatile memory element is used for storing program data with a small number of rewrites, and the second MONOS type nonvolatile memory element is used for storing process data (data processed by executing a program) with a large number of rewrites. Is achieved.

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
According to the present invention, high integration of a semiconductor device having a nonvolatile memory element and improvement in the number of rewrites can be achieved.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all the drawings for explaining the embodiments of the invention, those having the same function are given the same reference numerals, and their repeated explanation is omitted.

  In the first embodiment, an example in which the present invention is applied to a microcomputer having a non-volatile memory element for erasing data by discharging electrons injected into a silicon nitride film of a charge storage insulating film to a gate electrode will be described. To do.

1 to 12 are diagrams relating to a microcomputer (semiconductor device) according to a first embodiment of the present invention.
FIG. 1 is a plan layout view of a microcomputer;
2 is an equivalent circuit diagram showing a part of a nonvolatile memory module for program mounted on the microcomputer of FIG.
FIG. 3 is a schematic plan view showing a part of a nonvolatile memory module for program mounted on the microcomputer of FIG.
4 is a schematic cross-sectional view taken along line aa ′ of FIG.
5 is a schematic cross-sectional view taken along the line bb ′ of FIG.
6 is a schematic cross-sectional view taken along the line cc ′ of FIG.
FIG. 7 is a schematic plan view showing a part of a data non-volatile memory module mounted on the microcomputer of FIG.
FIG. 8 is a schematic plan view showing a part of a data non-volatile memory module mounted on the microcomputer of FIG.
9 is a schematic cross-sectional view taken along the line dd ′ of FIG.
10 is a schematic cross-sectional view taken along the line ee ′ of FIG.
11 is a schematic cross-sectional view taken along the line ff ′ of FIG.
FIG. 12 is a schematic plan view showing an IC card on which the microcomputer of FIG. 1 is mounted.

  As shown in FIG. 1, the microcomputer 20a according to the first embodiment is mainly composed of a p-type semiconductor substrate 1 (hereinafter simply referred to as a silicon substrate) made of, for example, single crystal silicon. The silicon substrate 1 has a rectangular planar shape that intersects the thickness direction. In the first embodiment, the silicon substrate 1 has a rectangular shape of about 5.14 mm × 5.24 mm, for example.

  On the main surface (circuit forming surface, element forming surface) of the silicon substrate 1, a non-volatile memory module (unit) 21 for programming, a non-volatile memory module 22 for data, a peripheral circuit module 23, a RAM (Random Access Memory). A module 24, a logical operation circuit module 25, and the like are mounted. Each of these modules is partitioned by a wiring channel region.

  The RAM module 24 is formed with a memory circuit such as a DRAM (Dynamic Random Access Memory) and an SRAM (Static Random Access Memory). In the logical operation circuit module 25, logical operation circuits such as a CPU (Central Processing Unit) and a DSP (Digital Signal Processor) are formed.

  In the non-volatile memory module for program 21, as shown in FIG. 2, a plurality of memory cells Mc1 are arranged in a matrix (array). One memory cell Mc1 is composed of one nonvolatile memory element Qm1 shown in FIG. In the data nonvolatile memory module 22, as shown in FIG. 7, a plurality of memory cells Mc2 are arranged in a matrix (array). One memory cell Mc2 includes one nonvolatile memory element Qm2 shown in FIG.

  As shown in FIGS. 2 and 3, the nonvolatile memory module 21 for programming includes a plurality of gate lines 16, a plurality of gate lines 17, a plurality of source lines 18, and a plurality of lines extending along the X direction. A bit line selection line CL is disposed, and a plurality of sub bit lines 15 and a plurality of main bit lines 19 extending along the Y direction are further disposed. Each sub bit line 15 is electrically connected to a sense amplifier SA provided corresponding to each sub bit line 15.

  As shown in FIGS. 7 and 8, the data nonvolatile memory module 22 includes a plurality of gate wirings 16 extending in the X direction and a plurality of gates, like the program nonvolatile memory module 21. A wiring 17, a plurality of source wirings 18, and a plurality of bit line selection lines CL are arranged, and a plurality of sub bit lines 15 and a plurality of main bit lines 19 extending along the Y direction are further arranged. Each sub bit line 15 is electrically connected to a sense amplifier SA provided corresponding to each sub bit line 15. The configuration of the memory array is the same as that of the non-volatile memory module for programming described above, but the memory cell has a longer length in the gate width direction (channel width direction) of the memory cell than the program memory. Designed to. Specifically, the gate width (channel width) Wp of the nonvolatile memory element Qm1 of the program nonvolatile memory module 21 and the gate width (channel width) of the nonvolatile memory element Qm2 of the data nonvolatile memory module 22 The relationship with Wd is formed so that Wd> Wp.

  On the main surface of the silicon substrate 1, as shown in FIG. 3, FIG. 5 and FIG. 6, and FIG. 8, FIG. 10 and FIG. 11, element isolation for partitioning an active region used as a transistor element formation region Region 2 is selectively formed. The element isolation region 2 is not limited to this, but is formed by, for example, a well-known STI (Shallow Trench Isolation) technique. In the element isolation region 2 by the STI technique, a shallow groove (for example, a groove having a depth of about 300 [nm]) is formed on the main surface of the silicon substrate 1, and then, for example, a silicon oxide film is formed on the main surface of the silicon substrate 1. An insulating film to be formed is formed by a CVD (Chemical Vapor Deposition) method, and then planarized by a CMP (Chemical Mechanical Polishing) method so that the insulating film remains selectively in the shallow groove. It is formed. Further, as another method for forming the element isolation region 2, it can be formed by a LOCOS (Local Oxidation of Silicon) method using a thermal oxidation method.

  In the program nonvolatile memory module 21, a p-type well region 3 is formed in the active region of the main surface of the silicon substrate 1 as shown in FIG. 4, and a memory cell is formed in the p-type well region 3. A nonvolatile memory element Qm1 that constitutes Mc1 is formed. 4 to 6, the nonvolatile memory element Qm1 includes a channel formation region, a charge storage insulating film 5 functioning as a charge storage portion, a memory gate electrode MG, a gate insulating film 8, and a control gate electrode CG. In this configuration, a control MISFET (pass transistor) and a MONOS FET are connected in series in an equivalent circuit.

  The memory gate electrode MG is provided in the active region of the main surface of the silicon substrate 1 with the charge storage insulating film 5 functioning as an information storage portion interposed therebetween. The memory gate electrode MG is formed of, for example, a polycrystalline silicon film into which an impurity for reducing the resistance value is introduced. An insulating film (cap insulating film) 6 made of, for example, a silicon oxide film is provided on the upper surface of the memory gate electrode MG so as to cover the upper surface.

  The charge storage insulating film 5 is formed of an ONO (oxide film / nitride film / oxide film: Oxide / Nitride / Oxide) film. In this embodiment, for example, a silicon oxide film (SiO) is formed from the main surface side of the silicon substrate 1. The ONO film is arranged in the order of 5a / silicon nitride film (SiN) 5b / silicon oxynitride film (SiON) 5c.

  Side wall spacers 7 formed in alignment with the memory gate electrode MG are provided on two side walls located on opposite sides of the memory gate electrode MG in the gate length direction of the memory gate electrode MG. Yes. The sidewall spacer 7 is formed of an insulating film made of, for example, a silicon oxide film.

  The control gate electrode CG is provided in the active region of the main surface of the silicon substrate 1 with the gate insulating film 8 interposed therebetween. The control gate electrode CG is provided next to the memory gate electrode MG in a state where the gate length is along the gate length direction of the memory gate electrode MG. In this embodiment, a part of the control gate electrode CG is mounted on the memory gate electrode MG, and the control gate electrode CG is electrically connected to the memory gate electrode MG by the insulating film 6 and one side wall spacer 7. Have been separated. The control gate electrode CG is formed of, for example, a polycrystalline silicon film into which an impurity for reducing the resistance value is introduced, and the gate insulating film 8 is formed of, for example, a silicon oxide film.

  Of the two side wall spacers 7, a side wall spacer 10 formed in alignment with the other side wall spacer 7 is provided outside the other side wall spacer 7 (opposite to the control gate electrode CG side). Is provided. Further, a sidewall spacer 10 formed in alignment with the control gate electrode CG is provided outside the control gate electrode CG. The sidewall spacer 10 is formed of an insulating film made of, for example, a silicon oxide film.

  The source region and the drain region have a pair of n-type semiconductor regions (extension regions) 9 and a pair of n-type semiconductor regions (contact regions) 11a and 11b. Of the pair of n-type semiconductor regions 9, one n-type semiconductor region 9 is provided on the main surface of the silicon substrate 1 in alignment with the other side wall spacer 7 (opposite to the control gate electrode CG side), The other n-type semiconductor region 9 is provided on the main surface of the silicon substrate 1 in alignment with the side wall spacer 10 provided outside the control gate electrode CG. Of the pair of n-type semiconductor regions (11a, 11b), one n-type semiconductor region 11b is provided on the main surface of the silicon substrate 1 in alignment with the sidewall spacer 10 on the other side (memory / gate electrode MG side). The other n-type semiconductor region 11a is provided on the main surface of the silicon substrate 1 in alignment with the sidewall spacer 10 on the control gate electrode CG side.

  The channel formation region is provided immediately below the control gate electrode CG and the memory gate electrode MG, in other words, in the surface layer portion of the silicon substrate 1 between the source region and the drain region. A p-type semiconductor region 4 is provided in the channel formation region. The p-type semiconductor region 4 is provided to face the memory gate electrode MG, and is pn-junctioned with one (MG side) of the n-type semiconductor region 9.

  The non-volatile memory element Qm1 adjacent in the Y direction has both a drain region (n-type semiconductor region 11a) and a source region (n-type semiconductor region 11b). As shown in FIG. 3, the n-type semiconductor region 11b extends along the X direction and is used as the source wiring 18 shown in FIG. That is, the source wiring 18 extending along the X direction is formed of the n-type semiconductor region 11b.

  As shown in FIGS. 3 and 5, the non-volatile memory element Qm1 adjacent in the X direction is formed by a part of the gate wiring 16 in which each memory gate electrode MG extends along the X direction. It is formed integrally with the gate wiring 16. Further, as shown in FIGS. 3 and 6, the non-volatile memory element Qm1 adjacent in the X direction is formed by a part of the gate wiring 17 in which each control gate electrode CG extends along the X direction. In this case, the gate wiring 17 is formed integrally. The gate wirings 16 and 17 are formed of, for example, a polycrystalline silicon film into which an impurity for reducing the resistance value is introduced.

  The nonvolatile memory element Qm1 disposed in the program nonvolatile memory module 21 is covered with an interlayer insulating film 12 provided on the main surface of the silicon substrate 1, as shown in FIGS. On the interlayer insulating film 12, a plurality of sub-bit lines 15 extending along the Y direction are arranged. The sub bit line 15 is formed of a conductive metal film such as an Al film, an Al alloy film, a Cu film, or a Cu alloy film, for example. The interlayer insulating film 12 is formed of, for example, a silicon oxide film.

  A connection hole 13 that reaches the n-type semiconductor region 11a from the surface of the interlayer insulating film 12 is provided on the drain region (n-type semiconductor region 11a) of the nonvolatile memory element Qm1 adjacent in the Y direction. A conductive plug 14 is embedded in the inside. The drain region (n-type semiconductor region 11a) of the nonvolatile memory element Qm1 adjacent in the Y direction is electrically connected to the sub bit line 15 extending on the interlayer insulating film 12 through the conductive plug 14. .

  As shown in FIGS. 7 and 8, the data nonvolatile memory module 22 basically has the same configuration as the program nonvolatile memory module 21. Also, the nonvolatile memory element Qm2 arranged in the data nonvolatile memory module 22 has basically the same configuration as the nonvolatile memory element Qm1 as shown in FIGS. However, the gate width (channel width) Wd of the nonvolatile memory element Qm2 is wider than the gate width (channel width) Wp of the nonvolatile memory element Qm1, as will be described in detail later.

  As shown in FIGS. 2 and 7, each of the nonvolatile memory elements Qm1 and Qm2 has a configuration in which a MONOS type FET and a control MISFET (pass transistor) are connected in series in an equivalent circuit, and the memory gate electrode MG. When hot electrons are injected into the trap in the silicon nitride film 5b in the lower charge storage insulating film 5, the threshold voltage of the MONOS FET (threshold voltage: Vth below the memory gate electrode MG) changes, and control is performed. The threshold voltage of the entire system in which the MISFET and the MONOS FET are connected in series (the threshold voltage of the entire system of the threshold voltage of the control gate electrode CG and the threshold voltage of the memory gate electrode MG) changes. That is, the nonvolatile memory elements Qm1 and Qm2 have a structure in which a memory operation is performed by controlling the threshold voltage of the drain current flowing between the source and the drain by storing charges in the charge storage insulating film 5.

  In the charge storage insulating film 5, the film for injecting hot electrons is not particularly limited to a silicon nitride (SiN) film, and for example, a film such as a silicon oxynitride (SiON) film contains nitrogen. It can also be formed of an insulating film. When formed of such a silicon oxynitride film, the withstand voltage of the charge storage insulating film 5 can be increased as compared with the silicon nitride film. For this reason, the resistance against deterioration of carrier mobility on the substrate surface (near the interface between the substrate and the charge storage insulating film) under the memory gate electrode MG according to the number of injections of hot electrons or hot holes as described later is increased. be able to.

  The write operation of the nonvolatile memory elements Qm1 and Qm2 is performed, for example, by 1 [V] on the n-type semiconductor region 11a in the drain region, 6 [V] on the n-type semiconductor region 11b in the source region, and 12 [V] on the memory gate electrode MG. V], a voltage of 1.5 [V] is applied to the control gate electrode CG, and a voltage of 0 [V] is applied to the p-type well region 3, and the charge is applied from the channel formation region side (substrate 1 side) under the memory gate electrode MG. This is done by injecting hot electrons into the silicon nitride film 5b of the storage insulating film 5. Hot electrons are injected by passing the silicon oxide film 5a under the charge storage insulating film 5.

  The erasing operation of the nonvolatile memory elements Qm1 and Qm2 is, for example, 0 [V] for the source region and drain region, 14 [V] for the memory gate electrode MG, and 0 [V] for the control gate electrode CG and the p-type well region 3. V] is applied to tunnel the silicon oxynitride film 5c on the upper layer of the charge storage insulating film 5 so that electrons are emitted from the silicon nitride film 5b of the charge storage insulating film 5 to the memory gate electrode MG. Is done by.

  The read operation of the nonvolatile memory elements Qm1 and Qm2 is, for example, 0 [V] in the source region, 1.5 [V] in the drain region, and 1.5 [V] in the memory gate electrode MG and the control gate electrode CG. This is performed by applying a potential of 0 [V] to the p-type well region 3.

  The gate width Wgm2 (see FIG. 10) under the memory gate electrode MG of the nonvolatile memory element Qm2 is wider than the gate width Wgm1 (see FIG. 5) under the memory gate electrode MG of the nonvolatile memory element Qm1. The gate width Wgc2 (see FIG. 11) under the control gate electrode CG of the nonvolatile memory element Qm2 is wider than the gate width Wgc1 (see FIG. 6) under the control gate electrode CG of the nonvolatile memory element Qm1. Yes. That is, the gate width (channel width) Wd of the nonvolatile memory element Qm2 is wider than the gate width (channel width) Wp of the nonvolatile memory element Qm1. In the first embodiment, the gate width of the nonvolatile memory element Qm2 is, for example, about three times the gate width of the nonvolatile memory element Qm1.

  In the program nonvolatile memory module 21 and the data nonvolatile memory module 22, the gate wirings 16 and 17 are arranged on the active region and the element isolation region as shown in FIGS. 5 and 6 and FIGS. 10 and 11. 2 is extended. Accordingly, in the nonvolatile memory elements Qm1 and Qm2, the gate width (Wgm1, Wgm2) under the memory gate electrode MG and the gate width (Wgc1, Wgc2) under the control gate electrode CG are defined by the element isolation region 2. The The gate length under the memory gate electrode MG and the gate length under the control gate electrode CG are defined by the length between the source region / drain region. In the first embodiment, the gate lengths of the nonvolatile memory elements Qm1 and Qm2 are, for example, about 0.5 μm, the gate width of the nonvolatile memory element Qm1 is, for example, about 0.32 μm, and the gate width of the nonvolatile memory element Qm2 is, for example, 1. It is about 0 μm.

The nonvolatile memory element Qm1 arranged in the program nonvolatile memory module 21 is used for storing program data for operating a logic operation circuit such as a CPU or DSP arranged in the logic operation circuit module 25. The nonvolatile memory element Qm2 arranged in the data nonvolatile memory module 22 is used for storing processed data processed by the execution of the program. That is, the microcomputer 20a according to the first embodiment includes the MONOS type nonvolatile memory element Qm1 and the MONOS type nonvolatile memory element Qm2 having a gate width wider than that of the MONOS type nonvolatile memory element Qm1 on the same substrate. The MONOS type nonvolatile memory element Qm1 is used for storing program data with a small number of rewrites, and the MONOS type nonvolatile memory element Qm2 is used for storing process data with a large number of rewrites.
The microcomputer 20a configured as described above is mounted on a non-contact type IC card 30 as shown in FIG.

Here, the number of rewrites of the MONOS type nonvolatile memory element will be described.
FIG. 13 is a diagram showing the relationship between the number of rewrites and the rewrite time, and FIG. 14 is a diagram showing a deterioration model of the charge storage insulating film due to the erase operation.

  In the nonvolatile memory element Qm1 of the first embodiment, hot electrons are injected into the silicon nitride film 5b of the charge storage insulating film 5 from the channel formation region side (substrate 1 side) below the memory gate electrode MG. Is written, the silicon oxynitride film 5c on the upper layer of the charge storage insulating film 5 is tunneled, and electrons are emitted from the silicon nitride film 5b of the charge storage insulating film 5 to the memory gate electrode MG. Is rewritten. In such a nonvolatile memory element Qm1, as shown in FIG. 13, the rewrite time is delayed by about 1000 times, so that the rewrite operation as a product cannot be performed. This is attributed to the deterioration of the charge storage insulating film during the erase operation. Since the nonvolatile memory element Qm1 erases data by pulling the entire surface of the FN by applying a positive bias to the memory gate electrode MG, as shown in FIG. 14, the silicon oxynitride film 5c mainly deteriorates. Conceivable.

  FIG. 15 is a diagram showing the rewrite frequency dependency of the erase time when the gate width W (memory cell width) of the nonvolatile memory element is changed, and FIG. 16 is a diagram showing the gate width W (memory of the nonvolatile memory element). It is a figure which shows the relationship between the threshold voltage (Vth @ Erase) when changing the width | variety of a cell), and a drive current (Ids @ Erase). Although the gate width W is different, the erase state is defined where the same current flows. In the case of this example, as shown in FIG. 15, it is possible to effectively guarantee the number of rewrites of two digits or more by increasing the gate width W (memory cell width) of the nonvolatile memory element by about three times. Become. This is because the erased state is defined where the same current flows. As shown in FIG. 16, the erased state is determined by whether or not a specified drive current Ids (Ids @ Erase) flows at a certain voltage (Vth @ Erase). When the gate width W (memory cell width) of the nonvolatile memory element is large, the driving capability is large, so that the fluctuation range of Vth can be reduced effectively, and the erasing stress that causes deterioration is reduced. Can do. Therefore, since the deterioration can be suppressed and the rewrite resistance can be improved, the number of rewrites can be increased.

However, in the above example, since the size of the nonvolatile memory element (memory cell) is about three times, the degree of integration is lowered. Therefore, as in the first embodiment, the nonvolatile memory element Qm1 with a small gate width W is used for storing program data with a small number of rewrites, and the nonvolatile memory element Qm2 with a wide gate width W is processed with a large number of rewrites. By using the nonvolatile memory element Qm2 having a wide gate width W for storing program data with a small number of rewrites, and using the nonvolatile memory element Qm2 having a wide gate width W for a large number of rewrites. Compared with the case where it is used for data storage, it is possible to suppress a decrease in the degree of integration due to the wide gate width W of the nonvolatile memory element, that is, to achieve high integration.
As described above, according to the first embodiment, it is possible to improve the number of rewrites and the high integration of the microcomputer 20a.

  In the first embodiment described above, an example in which a nonvolatile memory element used for storing program data and a nonvolatile memory element used for storing processing data are divided into two nonvolatile memory modules is described. However, in the second embodiment, an example will be described in which a nonvolatile memory element for storing program data and a nonvolatile memory element for storing processing data are mounted together to constitute one nonvolatile memory module.

FIGS. 17 to 21 are diagrams related to a microcomputer that is Embodiment 2 of the present invention.
FIG. 17 is a plan layout view of a microcomputer;
18 is an equivalent circuit diagram showing a part of the nonvolatile memory module of FIG.
19 is a schematic plan view showing a part of the nonvolatile memory module of FIG.
20 is a schematic cross-sectional view taken along the line gg ′ of FIG.
FIG. 21 is a schematic cross-sectional view taken along the line hh ′ of FIG.

  As shown in FIG. 17, in the microcomputer 20b of the second embodiment, a nonvolatile memory module 26, a peripheral circuit module 23, a RAM module 24, a logical operation circuit module 25, and the like are mounted on the main surface of the silicon substrate 1. Has been. Each of these modules is partitioned by a wiring channel region.

  As shown in FIGS. 18 and 19, the nonvolatile memory module 26 includes a first cell column including a plurality of memory cells Mc1 (nonvolatile memory elements Qm1) arranged along the Y direction, and a Y direction. A plurality of second cell columns made up of a plurality of memory cells Mc2 (nonvolatile memory elements Qm2) arranged along the X direction are alternately arranged along the X direction.

  As shown in FIGS. 19 and 20, the non-volatile memory elements Qm1 and Qm2 adjacent in the X direction are formed by a part of the gate wiring 16 in which each memory gate electrode MG extends along the X direction. In this case, the gate wiring 16 is formed integrally. Further, the non-volatile memory elements Qm1 and Qm2 adjacent in the X direction are formed by a part of the gate wiring 17 in which each control gate electrode CG extends along the X direction, as shown in FIGS. In other words, it is formed integrally with the gate wiring 17.

  The non-volatile memory element Qm1 is used for storing program data for operating a logic operation circuit such as a CPU or DSP arranged in the logic operation circuit module 25. The nonvolatile memory element Qm2 is used for storing processing data processed by executing the program. That is, the non-volatile memory module 26 is used for storing the non-volatile memory element Qm1 used for storing program data and the memory for processing data, and has a gate width Wd wider than the gate width Wp of the non-volatile memory element Qm1. The nonvolatile memory element Qm2 is mixedly mounted. That is, the relationship between the gate width (channel width) Wp of the nonvolatile memory element Qm1 and the gate width (channel width) Wd of the nonvolatile memory element Qm2 is formed such that Wd> Wp.

In the microcomputer 20b configured as described above, the number of rewrites can be improved and the integration can be increased as in the first embodiment.
Further, since the sense amplifier SA has a configuration common to the nonvolatile memory element Qm1 used for storing program data and the nonvolatile memory element Qm2 used for storing processing data, the sense amplifier SA is compared with the first embodiment. Thus, the nonvolatile memory module can be miniaturized.

  In the first and second embodiments described above, the present invention is applied to a microcomputer having a nonvolatile memory element that erases data by discharging electrons injected into the silicon nitride film of the charge storage insulating film to the gate electrode. In the second embodiment, data is erased by injecting hot holes into the silicon nitride film of the charge storage insulating film from the channel formation region side (substrate 1 side) under the memory gate electrode. An example in which the present invention is applied to a microcomputer having a nonvolatile memory element to be performed will be described.

22 to 29 are diagrams related to a microcomputer that is Embodiment 3 of the present invention.
FIG. 22 is a schematic plan view showing a part of a program non-volatile memory module mounted on a microcomputer;
23 is a schematic cross-sectional view taken along the line ii ′ of FIG.
24 is a schematic cross-sectional view taken along the line j ′ of FIG.
25 is a schematic cross-sectional view taken along the line kk ′ of FIG.
FIG. 26 is a schematic plan view showing a part of a non-volatile memory module for data mounted on a microcomputer;
27 is a schematic cross-sectional view taken along line ll ′ of FIG.
28 is a schematic cross-sectional view along the line mm ′ of FIG.
FIG. 29 is a schematic sectional view taken along line nn ′ of FIG.

  The microcomputer according to the third embodiment basically has the same configuration as that of the microcomputer according to the first embodiment, and the element structures of the memory cells Mc1 and Mc2 are different.

  In the non-volatile memory module for program (21), a plurality of memory cells Mc1 shown in FIG. 22 are arranged in a matrix. One memory cell Mc1 includes one nonvolatile memory element Qm3 shown in FIG. In the data non-volatile memory module (22), a plurality of memory cells Mc2 shown in FIG. 26 are arranged in a matrix. One memory cell Mc2 includes one nonvolatile memory element Qm4 shown in FIG.

  As shown in FIG. 23, the nonvolatile memory element Qm3 includes a channel formation region, a gate insulating film 42, a control gate electrode CG, a charge storage insulating film 5 functioning as a charge storage portion, a memory gate electrode MG, and a source region. In addition, a control MISFET (pass transistor) and a MONOS type FET are connected in series as an equivalent circuit.

  The control gate electrode CG is provided in the active region of the main surface of the silicon substrate 1 with a gate insulating film 42 made of, for example, a silicon oxide film interposed therebetween. The charge storage insulating film 5 is formed on one of the two side wall surfaces opposite to each other in the channel length direction of the control gate electrode CG, on the one side wall surface and the main surface of the silicon substrate 1. It is provided along. The memory gate electrode MG has a charge storage insulating film 5 interposed between the silicon substrate 1 and the control gate electrode CG, and is adjacent to the control gate electrode CG, specifically, one of the control gate electrodes CG. Is provided on the side wall surface side. The control gate electrode CG and the memory gate electrode MG are arranged along the gate length direction.

  The charge storage insulating film 5 is formed of an ONO (oxide film / nitride film / oxide film: Oxide / Nitride / Oxide) film. In this embodiment, for example, a silicon oxide film (SiO) is formed from the main surface side of the silicon substrate 1. The ONO films are arranged in the order of 5a / silicon nitride film (SiN) 5b / silicon oxide film (SiO) 5d.

  On the other side wall surface side of the control gate electrode CG (side wall surface side opposite to the side wall surface on which the memory gate electrode MG is provided), a side wall spacer formed in alignment with the control gate electrode CG 45 and a sidewall spacer 45 formed in alignment with the memory gate electrode MG is provided outside the memory gate electrode MG. These sidewall spacers 45 are formed of an insulating film made of, for example, a silicon oxide film.

  The source region and the drain region include a pair of n-type semiconductor regions (extension regions) 44 and a pair of n-type semiconductor regions (contact regions) 46a and 46b. Of the pair of n-type semiconductor regions 44, one n-type semiconductor region 44 is provided on the main surface of the silicon substrate 1 in alignment with the control gate electrode CG, and the other n-type semiconductor region 44 is a memory gate. The main surface of the silicon substrate 1 is provided in alignment with the electrode MG. Of the pair of n-type semiconductor regions (46a, 46b), one n-type semiconductor region 46a is provided on the main surface of the silicon substrate 1 in alignment with the side wall spacer 45 on the control gate electrode CG side, The n-type semiconductor region 46 b is provided on the main surface of the silicon substrate 1 in alignment with the sidewall spacer 45 outside the memory gate electrode MG.

  The channel formation region is provided immediately below the control gate electrode CG and the memory gate electrode MG, in other words, in the surface layer portion of the silicon substrate 1 between the source region and the drain region. In the channel formation region, p-type semiconductor regions 41 and 43 are provided. The p-type semiconductor region 41 is provided to face the control gate electrode CG and is pn-junction with the n-type semiconductor region 44 on the control gate electrode CG side. The p-type semiconductor region 43 is provided opposite to the memory gate electrode MG, is in contact with the p-type semiconductor region 41, and is pn-junction with the n-type semiconductor region 44 on the memory gate electrode MG side.

  The non-volatile memory element Qm3 adjacent in the Y direction has both a drain region (n-type semiconductor region 46a) and a source region (n-type semiconductor region 46b). As shown in FIG. 22, the n-type semiconductor region 46 b extends along the X direction and is used as the source wiring 18.

  As shown in FIGS. 22 and 24, the nonvolatile memory element Qm3 adjacent in the X direction is formed by a part of the gate wiring 16 in which each memory gate electrode MG extends along the X direction, in other words. It is formed integrally with the gate wiring 16. Further, as shown in FIGS. 22 and 25, the non-volatile memory element Qm3 adjacent in the X direction is formed by a part of the gate wiring 17 in which each control gate electrode CG extends along the X direction. In this case, the gate wiring 17 is formed integrally.

  The nonvolatile memory element Qm3 arranged in the nonvolatile memory module for program (21) is covered with an interlayer insulating film 12 provided on the main surface of the silicon substrate 1, as shown in FIGS. A plurality of sub bit lines 15 extending along the Y direction are arranged on the interlayer insulating film 12.

  A connection hole 13 that reaches the n-type semiconductor region 46a from the surface of the interlayer insulating film 12 is provided on the drain region (n-type semiconductor region 46a) of the nonvolatile memory element Qm3 adjacent in the X direction. A conductive plug 14 is embedded in the inside. The drain region (n-type semiconductor region 46a) of the nonvolatile memory element Qm3 adjacent in the X direction is electrically connected to the sub bit line 15 extending on the interlayer insulating film 12 through the conductive plug 14. .

  The data non-volatile memory module (22) has basically the same configuration as the program non-volatile memory module (21). Also, the nonvolatile memory element Qm4 arranged in the data nonvolatile memory module (22) has basically the same configuration as the nonvolatile memory element Qm3 as shown in FIGS. However, the gate width (channel width) Wd of the nonvolatile memory element Qm4 is wider than the gate width (channel width) Wp of the nonvolatile memory element Qm3, as in the first embodiment.

  The nonvolatile memory elements Qm3 and Qm4 have a structure in which a MONOS type FET and a control MISFET (pass transistor) are connected in series in an equivalent circuit, and are nitrided in the charge storage insulating film 5 below the memory gate electrode MG. When hot electrons are injected into the trap in the silicon film 5b, the threshold voltage of the MONOS FET (threshold voltage: Vth under the memory gate electrode MG) changes, and the control MISFET and the MONOS FET are connected in series. The threshold voltage of the entire system (the threshold voltage of the entire system between the threshold voltage of the control gate electrode CG and the threshold voltage of the memory gate electrode MG) changes. That is, the nonvolatile memory elements Qm3 and Qm4 have a structure in which a memory operation is performed by controlling the threshold voltage of the drain current flowing between the source and the drain by storing charges in the charge storage insulating film 5.

  For example, the write operation of the nonvolatile memory elements Qm3 and Qm4 is 1 [V] in the n-type semiconductor region 46a of the drain region, 6 [V] in the n-type semiconductor region 46b of the source region, and 12 [V] in the memory gate electrode MG. V], a voltage of 1.5 [V] is applied to the control gate electrode CG, and a voltage of 0 [V] is applied to the p-type well region 3, and the charge is applied from the channel formation region side (substrate 1 side) under the memory gate electrode MG. This is done by injecting hot electrons into the silicon nitride film 5b of the storage insulating film 5. Hot electrons are injected by passing the silicon oxide film 5a under the charge storage insulating film 5.

  The erase operations of the nonvolatile memory elements Qm3 and Qm4 are, for example, 0 [V] in the drain region, 7 [V] in the source region, −6 [V] in the memory gate electrode MG, the control gate electrode CG and the p-type A potential of 0 [V] is applied to the well region 3 to pass through the silicon oxide film 5a under the charge storage insulating film 5, and from the channel formation region side (substrate 1 side) under the memory gate electrode MG. This is done by injecting hot holes into the silicon nitride film 5b of the charge storage insulating film 5.

  The read operations of the nonvolatile memory elements Qm3 and Qm4 are, for example, 0 [V] for the source region, 1.5 [V] for the drain region, and 1.5 [V] for the memory gate electrode MG and the control gate electrode CG. This is performed by applying a potential of 0 [V] to the p-type well region 3.

  The gate width Wgm4 (see FIG. 28) under the memory gate electrode MG of the nonvolatile memory element Qm4 is wider than the gate width Wgm3 (see FIG. 24) under the memory gate electrode MG of the nonvolatile memory element Qm3. The gate width Wgc4 (see FIG. 29) under the control gate electrode CG of the nonvolatile memory element Qm4 is wider than the gate width Wgc3 (see FIG. 25) under the control gate electrode CG of the nonvolatile memory element Qm3. Yes. That is, the gate width (channel width) Wd of the nonvolatile memory element Qm4 is wider than the gate width (channel width) Wp of the nonvolatile memory element Qm3. In the first embodiment, the gate width of the nonvolatile memory element Qm4 is, for example, about three times the gate width of the nonvolatile memory element Qm3.

  In the nonvolatile memory module for program (21) and the nonvolatile memory module for data (22), the gate wirings 16 and 17 are arranged on the active region as shown in FIGS. 24 and 25, and FIGS. And it extends on the element isolation region 2. Therefore, in the nonvolatile memory elements Qm3 and Qm4, the gate width (Wgm3, Wgm4) under the memory gate electrode MG and the gate width (Wgc3, Wgc4) under the control gate electrode CG are defined by the element isolation region 2. The The gate length under the memory gate electrode MG and the gate length under the control gate electrode CG are defined by the length between the source region / drain region. In the third embodiment, the gate lengths of the nonvolatile memory elements Qm3 and Qm4 are, for example, about 0.25 μm, the gate width of the nonvolatile memory element Qm3 is, for example, about 0.3 μm, and the gate width of the nonvolatile memory element Qm4 is, for example, 1. It is about 0 μm.

  The nonvolatile memory element Qm3 arranged in the program nonvolatile memory module (21) stores program data for operating a logic operation circuit such as a CPU or DSP arranged in the logic operation circuit module (25). used. The nonvolatile memory element Qm4 arranged in the data nonvolatile memory module (22) is used for storing processed data processed by executing the program.

Here, the number of rewrites of the MONOS type nonvolatile memory element will be described.
In the nonvolatile memory element Qm3 of the third embodiment, hot electrons are injected into the silicon nitride film 5b of the charge storage insulating film 5 from the channel formation region side (substrate 1 side) below the memory gate electrode MG. Is written, the silicon oxide film 5a under the charge storage insulating film 5 is passed, and the silicon nitride of the charge storage insulating film 5 from the channel formation region side (substrate 1 side) under the memory gate electrode MG. Data is rewritten by injecting hot holes into the film 5b. In such a nonvolatile memory element Qm3, as in the nonvolatile memory element Qm1, the rewriting time is delayed by about 1000 times, so that the rewriting operation as a product cannot be performed. This is attributed to the deterioration of the charge storage insulating film during the erase operation. Since the nonvolatile memory element Qm3 erases data by hot hole injection from the edge of the source region, it is considered that the silicon oxide film 5a mainly deteriorates as shown in FIG.

  Also in the nonvolatile memory element Qm3, by increasing the gate width W (memory cell width) by about three times, it is possible to guarantee the number of rewrites of two digits or more practically as in the first embodiment. Become.

  By using the nonvolatile memory element Qm3 having a small gate width W for storing program data with a small number of rewrites, and using the nonvolatile memory element Qm4 having a wide gate width W for storing process data having a large number of rewrites, Compared to the case where the nonvolatile memory element Qm4 having a wide gate width W is used for storing program data with a small number of rewrites and the nonvolatile memory element Qm4 having a wide gate width W is used for storing process data having a large number of rewrites. Thus, it is possible to suppress a decrease in the degree of integration due to the wide gate width W of the nonvolatile memory element, that is, to achieve high integration.

  Thus, also in the third embodiment, it is possible to improve the number of times of rewriting and high integration of the microcomputer.

  In the third embodiment, the configuration of the non-volatile memory module is divided into a non-volatile memory module for program and a memory module for storing processing data as in the first embodiment. However, it is of course possible to configure one nonvolatile memory module by mixing two memory modules in the same manner as in the second embodiment, and the same effects as in the second embodiment can be obtained.

  In the second embodiment described above, the nonvolatile memory element with a small gate width W is used for storing program data with a small number of rewrites, and the nonvolatile memory element with a wide gate width W is used for storing process data with a large number of rewrites. In the fourth embodiment, the gate width W of both nonvolatile memory elements is made the same, and a nonvolatile memory cell for storing program data is formed by one nonvolatile memory element. The non-volatile memory cell for data is formed of 1 bit by a plurality of non-volatile memory elements.

  In the fourth embodiment, as in the second embodiment described above, a nonvolatile memory element for storing program data and a nonvolatile memory element for storing processing data as shown in FIG. A description will be given based on an example in which a module is configured.

FIGS. 31 to 36 are diagrams related to a microcomputer that is Embodiment 4 of the present invention.
FIG. 31 is an equivalent circuit diagram showing a part of a nonvolatile memory module;
32 is a schematic plan view showing a part of the nonvolatile memory module of FIG.
33 is a schematic cross-sectional view taken along the line oo ′ of FIG.
34 is a schematic sectional view taken along the line pp ′ of FIG.
35 is a schematic cross-sectional view taken along the line qq ′ of FIG.
FIG. 36 is a schematic plan view showing connection of sub-bit lines to the nonvolatile memory module of FIG.

  As shown in FIGS. 31 and 32, the nonvolatile memory module includes a first cell column including a plurality of memory cells Mc1 (nonvolatile memory elements Qm5) arranged along the Y direction, and a Y direction. A plurality of second cell columns made up of a plurality of memory cells Mc2 (two nonvolatile memory elements Qm6 and Qm7) are alternately arranged along the X direction. These nonvolatile memory elements Qm5, Qm6, and Qm7 have the same structure as the nonvolatile memory element Qm1 described in the first embodiment, and are formed in the same process. That is, various dimensions such as the gate width W are the same.

  The memory cell Mc1 is configured to include a nonvolatile memory element Qm5, and is used for storing program data as in the first to third embodiments.

  The memory cell Mc2 is configured to include a plurality of nonvolatile storage elements Qm6 and Qm7, and is used for storing processing data in the same manner as in the first to third embodiments. In the nonvolatile memory elements Qm6 and Qm7, the gate wiring 16 integrated with the control gate electrode CG, the gate wiring 17 integrated with the memory gate electrode MG, and the source wiring 18 are common to the nonvolatile memory element Qm5. However, the sub bit line 15 is provided separately from the nonvolatile memory element Qm5, and is electrically connected to a sense amplifier SA provided corresponding to each sub bit line 15.

  Here, as shown in FIG. 31, the sub bit line 15 of the memory cell Mc2 is common to the nonvolatile memory elements Qm6 and Qm7. For example, as shown in FIG. 36, the metal wiring (subbit line) 15 passing above the memory cell Mc2 is electrically connected to the drain regions of the nonvolatile memory elements Qm6 and Qm7 via the plug 14, as shown in FIG. It is realized by being connected. Thus, by making the sub-bit lines of the nonvolatile memory elements Qm6 and Qm7 common, the voltage relationships of the nonvolatile memory elements Qm6 and Qm7 in the write, erase and read operations become the same. Therefore, the effective channel width of the memory cell Mc2 with respect to the memory cell Mc1 can be increased.

  Further, the metal wiring (sub-bit line) 15 is formed so as to cover the upper part of the nonvolatile memory elements Qm6 and Qm7. However, as shown in FIG. 37, as another method, the nonvolatile memory elements Qm6 and Qm7 are formed. A method of shunting a part of the metal wiring (sub-bit line) 15 that passes above each of the wirings by another wiring 50 is also conceivable. Thus, the wiring layout is not limited to the contents described in the present embodiment, and various changes can be made according to design matters.

  As described above, in the fourth embodiment, the gate width W of the data nonvolatile memory cell of the memory cell Mc2 is changed only by changing the wiring layout without changing the structure of the nonvolatile memory element Qm of each of the memory cells Mc1 and Mc2. The (channel width W) can be determined empirically. As a result, the gate width W of the data nonvolatile memory can be set large, and the memory capacity of the program nonvolatile memory cell and the data nonvolatile memory cell can be easily allocated. The memory cell rewrite tolerance can be improved.

  In the fourth embodiment, the example in which the sub-bit lines 15 of the two nonvolatile memory elements Qm6 and Qm7 are shared is shown. However, it is of course possible to share three or more nonvolatile memory elements in the sub-bit line 15. Is possible. Therefore, it is possible to easily design a nonvolatile memory cell that can obtain a desired number of rewrites.

  On the other hand, in the fourth embodiment, there is a concern that the degree of integration of the data non-volatile memory is low because an element isolation region is required in the memory cell Mc2 as compared with the cases described in the first to third embodiments. is there. Therefore, it is desirable to use it appropriately according to the priority application in consideration of the degree of integration, reliability or production cost.

  In addition, the fourth embodiment has been described based on the second embodiment described above. However, the present invention is not limited to this, and can be applied to other forms such as the first or third embodiment. The same effect can be obtained.

  Although the invention made by the present inventor has been specifically described based on the above-described embodiment, the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the invention. Of course.

1 is a plan layout diagram of a microcomputer that is Embodiment 1 of the present invention. FIG. FIG. 2 is an equivalent circuit diagram showing a part of a nonvolatile memory module for program installed in the microcomputer of FIG. 1. FIG. 2 is a schematic plan view showing a part of a nonvolatile memory module for program installed in the microcomputer of FIG. 1. FIG. 4 is a schematic cross-sectional view taken along the line a-a ′ in FIG. 3. FIG. 4 is a schematic cross-sectional view taken along line b-b ′ in FIG. 3. FIG. 4 is a schematic cross-sectional view taken along the line c-c ′ in FIG. 3. FIG. 2 is a schematic plan view showing a part of a data non-volatile memory module mounted on the microcomputer of FIG. 1. FIG. 2 is a schematic plan view showing a part of a data non-volatile memory module mounted on the microcomputer of FIG. 1. It is typical sectional drawing which follows the d-d 'line | wire of FIG. It is typical sectional drawing which follows the e-e 'line | wire of FIG. It is typical sectional drawing which follows the f-f 'line | wire of FIG. FIG. 2 is a schematic plan view showing an IC card on which the microcomputer of FIG. 1 is mounted. It is a figure which shows the relationship between the frequency | count of rewriting of a non-volatile memory element, and rewriting time. It is a figure which shows the deterioration model of the insulating film for charge storage by the erase operation of a non-volatile memory element. It is a figure which shows the rewrite frequency dependence of the erasing time when changing the gate width W (memory cell width) of a non-volatile memory element. It is a figure which shows the relationship between the threshold voltage (Vth @ Erase) and drive current (Ids @ Erase) when the gate width W (memory cell width) of a non-volatile memory element is changed. It is a plane layout figure of the microcomputer which is Example 2 of this invention. FIG. 18 is an equivalent circuit diagram showing a part of the nonvolatile memory module of FIG. 17. FIG. 18 is a schematic plan view showing a part of the nonvolatile memory module of FIG. 17. FIG. 20 is a schematic cross-sectional view taken along the line g-g ′ of FIG. 19. FIG. 20 is a schematic cross-sectional view taken along the line h-h ′ in FIG. 19. It is a typical top view which shows a part of program non-volatile memory module mounted in the microcomputer which is Example 3 of this invention. It is typical sectional drawing which follows the i-i 'line | wire of FIG. It is typical sectional drawing in alignment with the j-j 'line | wire of FIG. It is typical sectional drawing which follows the k-k 'line | wire of FIG. It is a typical top view which shows a part of data non-volatile memory module mounted in the microcomputer which is Example 3 of this invention. FIG. 27 is a schematic cross-sectional view taken along line l-l ′ of FIG. 26. FIG. 27 is a schematic cross-sectional view taken along line m-m ′ of FIG. 26. FIG. 27 is a schematic cross-sectional view taken along the line n-n ′ of FIG. 26. It is a figure which shows the deterioration model of the insulating film for charge storage by the erase operation of a non-volatile memory element. FIG. 10 is an equivalent circuit diagram illustrating a part of the nonvolatile memory module according to Example 4; FIG. 32 is a schematic plan view showing a part of the nonvolatile memory module of FIG. 31. FIG. 33 is a schematic cross-sectional view taken along the line o-o ′ of FIG. 32. FIG. 33 is a schematic cross-sectional view taken along the line p-p ′ of FIG. 32. FIG. 33 is a schematic cross-sectional view taken along the line q-q ′ of FIG. 32. FIG. 32 is a schematic plan view showing connection of sub-bit lines to the nonvolatile memory module of FIG. 31. FIG. 32 is a schematic plan view showing a modification of FIG. 31.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Silicon substrate, 2 ... Element isolation region, 3 ... p-type well region, 4 ... p-type semiconductor region, 5 ... Charge storage insulating film, 5a ... Silicon oxide film, 5b ... Silicon nitride film, 5c ... Silicon oxynitride 5 ... Silicon oxide film, 6 ... Insulating film, 7 ... Side wall spacer, 8 ... Gate insulating film, 9 ... N-type semiconductor region, 10 ... Side wall spacer, 11 ... N-type semiconductor region, 12 ... Interlayer insulating film , 13: connection hole, 14 ... conductive plug, 15 ... sub-bit line, 16, 17 ... gate wiring, 18 ... source wiring, 19 ... main bit line,
20a, 20b ... microcomputer (semiconductor device), 21 ... non-volatile memory module for program, 22 ... non-volatile memory module for data, 23 ... peripheral circuit module, 24 ... RAM module, 25 ... logic operation circuit module, 26: Non-volatile memory module,
41 ... p-type semiconductor region, 42 ... gate insulating film, 43 ... p-type semiconductor region, 44 ... n-type semiconductor region, 45 ... side wall spacer, 46a, 46b ... n-type semiconductor region,
CG ... control gate electrode, MG ... memory gate electrode, Mc1, Mc2 ... memory cell, Qm1-Qm7 ... nonvolatile memory element.

Claims (9)

In a semiconductor device having a first nonvolatile memory element, a second nonvolatile memory element, and a third nonvolatile memory element formed on a semiconductor substrate,
The first nonvolatile memory element, the second nonvolatile memory element, and the third nonvolatile memory element include a first gate electrode and a semiconductor substrate formed on the semiconductor substrate with a charge storage film interposed therebetween. Having a source region and a drain region formed therein,
The first nonvolatile memory cell is formed of the first nonvolatile memory element,
A second nonvolatile memory cell is formed of the second nonvolatile memory element and the third nonvolatile memory element,
The number of rewrites of the second nonvolatile memory cell is greater than that of the first nonvolatile memory cell,
In the first nonvolatile memory cell, 1 bit is formed by the first nonvolatile memory element,
In the second nonvolatile memory cell, the voltage relationship between the second nonvolatile memory element and the third nonvolatile memory element in writing and erasing is the same.
The second nonvolatile memory element and the first gate electrode of the third nonvolatile memory element are formed integrally,
The source regions of the second nonvolatile memory element and the third nonvolatile memory element are common,
The drain regions of the second nonvolatile memory element and the third nonvolatile memory element are connected by a bit line formed on the second nonvolatile memory element and the third nonvolatile memory element. A semiconductor device characterized by that. In a semiconductor device having a first nonvolatile memory element, a second nonvolatile memory element, and a third nonvolatile memory element formed on a semiconductor substrate,
The first nonvolatile memory element, the second nonvolatile memory element, and the third nonvolatile memory element include a first gate electrode and a semiconductor substrate formed on the semiconductor substrate with a charge storage film interposed therebetween. Having a source region and a drain region formed therein,
The first nonvolatile memory cell is formed of the first nonvolatile memory element,
A second nonvolatile memory cell is formed of the second nonvolatile memory element and the third nonvolatile memory element,
The number of rewrites of the second nonvolatile memory cell is greater than that of the first nonvolatile memory cell,
In the first nonvolatile memory cell, 1 bit is formed by the first nonvolatile memory element,
In the second nonvolatile memory cell, the voltage relationship between the second nonvolatile memory element and the third nonvolatile memory element in writing and erasing is the same.
The second nonvolatile memory element and the first gate electrode of the third nonvolatile memory element are formed integrally,
The source regions of the second nonvolatile memory element and the third nonvolatile memory element are common,
The drain region of the second nonvolatile memory element is connected by a first bit line formed on the second nonvolatile memory element;
The drain region of the third nonvolatile memory element is connected by a second bit line formed on the third nonvolatile memory element;
The first bit line and the second bit line are shunted by a metal wiring formed in a layer different from the layer in which the first bit line and the second bit line are formed. apparatus. The semiconductor device according to claim 1 or 2 ,
The first nonvolatile memory cell is used for storing data constituting a program,
The semiconductor device according to claim 2, wherein the second nonvolatile memory cell is used for storing data processed by executing the program. The semiconductor device according to claim 1 or 2 ,
The first nonvolatile memory element, the second nonvolatile memory element, and the third nonvolatile memory element have the same gate width, respectively. The semiconductor device according to claim 1 ,
The first gate electrode extends in a first direction;
The source region extends in the first direction;
The bit line extends in a second direction perpendicular to the first direction. The semiconductor device according to claim 2 ,
The first gate electrode extends in a first direction;
The source region extends in the first direction;
The semiconductor device according to claim 1, wherein the first bit line and the second bit line extend in a second direction orthogonal to the first direction. The semiconductor device according to claim 1 or 2 ,
The first nonvolatile memory element, the second nonvolatile memory element, and the third nonvolatile memory element include a second gate electrode formed on the semiconductor substrate with a first gate insulating film interposed therebetween. ,
Said first gate electrode and the second gate electrode, the gate length direction, a semiconductor device characterized by being formed between the source area and the drain region. The semiconductor device according to claim 1 or 2 ,
The write operation of the first nonvolatile memory element, the second nonvolatile memory element, and the third nonvolatile memory element is performed by injecting hot electrons into the charge storage film,
An erasing operation of the first nonvolatile memory element, the second nonvolatile memory element, and the third nonvolatile memory element is performed by emitting electrons from the charge storage film. . The semiconductor device according to claim 1 or 2 ,
Before Symbol first nonvolatile memory element, said second nonvolatile memory element, and, the write operation of the third non-volatile storage elements is performed by injecting hot electrons into the charge storage layer,
2. The semiconductor device according to claim 1, wherein the erase operation of the nonvolatile memory element is performed by injecting hot holes into the charge storage film.

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