JP5044876B2 - Method for driving liquid crystal display device and liquid crystal display device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a liquid crystal display device and an OLED display device.
[0002]
[Prior art]
FIG. 11 shows an example of a liquid crystal display device using a conventional thin film transistor. Reference numeral 101 denotes a thin film transistor for driving a pixel of a liquid crystal display device, which is a p-channel transistor. Reference numeral 102 denotes a pixel storage capacitor, and reference numeral 103 denotes a liquid crystal capacitive load. Reference numeral 104 denotes a source line connected to the source terminal of the pixel transistor 101, 105 denotes a gate line connected to the gate of the pixel transistor 101, and 106 denotes a storage capacitor 102 and a common electrode connected to the counter electrode of the liquid crystal. A gate line driving circuit 107 drives the gate line. Reference numeral 108 denotes a source line driving circuit for driving the source line 104. Note that a pixel in the present invention is an optical switch that controls the brightness and darkness of light, which is the minimum structural unit of an image displayed on a liquid crystal display device.
[0003]
The gate driver circuit 107 sequentially scans the gate line 105, applies a voltage for turning on the pixel transistor 101 connected to the same gate line to the gate line, and applies a voltage corresponding to image data to be displayed by the source driver circuit 108 to the source line 104. To charge the storage capacitor 102 and the liquid crystal 103 to a desired voltage via the pixel transistor 101. Next, a voltage for turning off the pixel transistor 101 on the same gate line is applied to the gate line 105. After the pixel transistor is turned off, the voltage applied to the storage capacitor 102 and the liquid crystal 103 is held until the next scan. . The entire screen is displayed by sequentially scanning and sequentially turning on the gate lines 105.
[0004]
The gate line driver circuit 107 sequentially shifts the scan data using a shift register having approximately the number of stages corresponding to the number of gate lines. FIG. 12 shows the timing of scanning data in the case of VGA (pixel number 640 × 480) display. G1 to G480 in FIG. 12 indicate outputs of the shift register from the first stage to the 480th stage (final stage). Reference numeral 111 denotes a vertical scanning period (one field period). A horizontal scanning period 112 corresponds to a period in which the L level is applied to the gate line and the pixel transistors on the same gate line are turned on.
[0005]
Although there is actually a blanking period, it is omitted from the figure because it is not directly related to the present invention.
[0006]
FIG. 13 shows an example of the configuration of one stage constituting the shift register. Reference numeral 121 denotes an inverter having a function of inverting input data and outputting it. The example of FIG. 13A is a D flip-flop composed of a feedback 128 by two inverters 121b and 121c and one inverter 121a. Reference numerals 126 and 127 denote switches, which use transistors such as transfer gates, and correspond to SW1 and SW2 in FIG. 13, respectively. The D flip-flop in FIG. 13A has the logical function shown in FIG. 13B, and when the switch 126 is on and the switch 127 is off, the input data is processed with the same logic. Output. When the switch 126 is off and the switch 127 is on, the previously input data that is held is output. Note that the switch 127 can be omitted by making the inverter 121c constituting the feedback high resistance.
[0007]
FIG. 13C shows an example in which the inverter 121 is composed of only transistors having the same polarity. 123 is a pMOS transistor, and 124 is a resistor. The source line of the pMOS transistor 123 is connected to the power source 122, the drain electrode is connected to the resistor 124, and the other contact of the resistor 124 is connected to the ground potential 129. By using the input as the gate line of the pMOS transistor 123 and the output as the drain electrode, an inverter function can be configured.
[0008]
FIG. 14 shows an example of a four-stage shift register configuration using the D flip-flop shown in FIG. Reference numerals 139 to 142 denote D flip-flops in the first to fourth stages, and reference numerals 131 to 134 denote pMOS transistors for performing a switching operation, and the D flip-flops 139 to 142 in the first to fourth stages respectively. It controls the operation.
Reference numerals 135 to 138 denote signals for controlling on / off of the transistors 131 to 134. Hereinafter, the operation of the shift register will be described with reference to FIG.
[0009]
The first stage of the shift register is controlled by a control signal 135. By setting the control signal 135 to the L level, the switching transistor 131 is turned on, and the signal of the input terminal 143 appears at the output 144 of the first stage. Further, by setting the control signal 135 to the H level, the transistor switch 131 is turned off, and the signal level of the output 144 is held in the previous state by the effect of the D flip-flop regardless of the change in the signal of the input terminal 143. . The functions are the same for the D flip-flops and switching transistors at each stage. By sequentially switching the L level and the H level for the control signals 135 to 138 of each stage, the signal level of the input terminal 143 can be shifted in the order of the terminals 144, 145, 146, and 147.
[0010]
FIG. 15 is a timing chart showing a data shift operation when the control signal of the shift register is two clocks (CLK1 and CLK2) that are 180 ° out of phase with a duty cycle of 50%. When CLK1 is input to the control terminal 135, CLK2 is input to the control terminal 136, and a signal indicated by D is input to the input terminal 143, the signal Q1 is input to the terminal 144 and the signal Q2 is input to the terminal 145 in synchronization with CLK1 and CLK2. Appears.
[0011]
Similarly, a gate line driving circuit that sequentially shifts scanning data can be configured by configuring a shift register having approximately the number of stages corresponding to the number of gate lines.
[0012]
[Problems to be solved by the invention]
In flat panel displays such as liquid crystal display devices and OLED display devices, low power, narrow frame, and high-quality display performance are of great commercial value, and cost reduction is a major issue in manufacturing.
[0013]
In the configuration of FIG. 13C, since the pMOS transistor 123 is in the on state when the inverter has an H output, a through current indicated by 125 is generated from the power supply 122 toward the ground 129, and current consumption The increase was a problem.
[0014]
In addition, when the shift register is controlled by the two-phase clock having the duty cycle of 50% shown in the example of FIG. 15, two clock signals that are inverted at the same time as shown in 148 are required. If one of the clock signals is mixed with the other clock signal due to the skew of the clock signal, the on / off state of the switching transistor is unstable, and latch data A stable state is likely to occur, and there is a concern about the malfunction of the scanning data shift function.
[0015]
As a method for operating the shift register stably, there is a method using four clock signals whose phases are shifted by 90 °. FIG. 16 is a timing chart showing a data shift operation when the control signal of the shift register is four clocks (CLK1, CLK2, CLK3, CLK4). When CLK1 is input to the control terminal 135, CLK2 is input to the control terminal 136, CLK3 is input to the control terminal 137, CLK4 is input to the control terminal 138, and a signal indicated by D is input to the input terminal 143, it is synchronized with CLK1, CLK2, CLK3, and CLK4. Thus, the signal Q1 appears at the terminal 144, the signal Q2 appears at the terminal 145, the signal Q3 appears at the terminal 146, and the signal Q4 appears at the terminal 147, so that the data can be shifted stably. However, in this configuration, the wiring density increases with the increase in the number of control signal wirings, and the circuit configuration becomes complicated. Therefore, it is difficult to narrow the frame of the liquid crystal display panel and the area of the circuit board. There was a problem of causing the change.
[0016]
In view of such circumstances, in the present invention, the power consumption of the drive circuit is reduced, and even in the case where only the transistor having the same polarity as the pixel transistor is used, a highly reliable operation can be realized, and the image quality is high and the cost is low. An object is to provide a liquid crystal display device and an OLED display device.
[0017]
The OLED is an abbreviation for organic writing emission diode.
[0018]
[Means for Solving the Problems]
In order to achieve the above object, the present invention provides a pixel driving transistor formed of a liquid crystal display pixel and a thin film transistor, a source line driving circuit for driving a source line of the pixel driving transistor, and a gate of the pixel driving transistor. In an active matrix liquid crystal display device having a gate line driving circuit for driving a line, the source line driving circuit or the gate line driving circuit has a shift register having a plurality of cascaded m stages (m> 3). Each stage of the shift register includes a switch for switching between a standby state and a non-standby state and a standby state determination unit, and the standby state is a power consumption of a transistor circuit constituting each stage of the shift register. The amount is smaller than that in the non-standby state, and the stand-by state discriminating means outputs and outputs the previous stage (n-1). To determine the output of the next stage (n + 1), those stages (n) is except when contributing to the data transfer, and switches the equivalent stage (n) in the standby state.
[0019]
According to this configuration, power consumption other than the transistor circuit that contributes to the shift operation of data transmitted by the shift register can be suppressed, and a shift register with a low power consumption operation can be realized.
[0020]
The present invention also provides a pixel driving transistor formed by a liquid crystal display pixel and a thin film transistor, a source line driving circuit for driving a source line of the pixel driving transistor, and a gate line driving for driving a gate line of the pixel driving transistor. In an active matrix liquid crystal display device having a circuit, the source line driving circuit or the gate line driving circuit is composed of a shift register composed of a plurality of cascaded stages composed of transistors having only the same polarity, Each stage of the shift register is connected to a clock signal having a phase shift instead of a duty cycle of 50%.
[0021]
According to this configuration, the unstable state of the latch data due to the skew of the clock signal can be eliminated, and the shift register composed of transistors having only the same polarity can be operated with high reliability using only the two-phase clock signal. It has the effect that it can be made.
[0022]
The present invention also provides a pixel driving transistor formed by a liquid crystal display pixel and a thin film transistor, a source line driving circuit for driving a source line of the pixel driving transistor, and a gate line driving for driving a gate line of the pixel driving transistor. In an active matrix liquid crystal display device having a circuit, the gate line driving circuit has a shift register having a plurality of cascaded m stages (m> 3), and selects a gate line corresponding to a scanning signal. Scanning signal pulses and a plurality of gate line selection pulses for selecting a plurality of arbitrary gate lines at the same time are scanned at different phases in the same field, and a thin film transistor is connected to each selected gate line. An ON voltage is applied to set the state, and the pixel electrode of the gate line corresponding to the scanning signal corresponds to one scanning line That the image signal is written, the pixel electrode of any plurality of gate lines corresponding to the plurality gate line selection pulse is characterized in that it is charged to a constant potential at the same time.
[0023]
The constant potential at which the pixel electrodes of any number of gate lines corresponding to the plurality of gate line selection pulses are simultaneously charged is a black signal level, and black signal writing is inserted for each field in which an image is written. It is characterized by.
[0024]
According to this structure, it has the effect | action that the improvement of the moving image visibility of a liquid crystal display device is realizable.
[0025]
The present invention also provides a pixel driving transistor formed by a liquid crystal display pixel and a thin film transistor, a source line driving circuit for driving a source line of the pixel driving transistor, and a gate line driving for driving a gate line of the pixel driving transistor. An active matrix type liquid crystal display device having a storage capacitor line driving circuit for driving a storage capacitor line forming an auxiliary capacitor between a circuit and the liquid crystal display pixel, the driving method of which is an image signal applied to the pixel electrode The adjacent storage capacitor line in which an auxiliary capacitor is formed between the pixel electrode to which the image signal voltage is applied during a period in which an on-voltage that turns on the thin film transistor to apply a voltage is applied to the gate line A predetermined compensation voltage is applied to the first compensation voltage, and the predetermined compensation voltage is a first compensation voltage, a second compensation voltage, and a third compensation voltage. After the first and second compensation voltages are alternately applied to the same scanning signal wiring for each field and the image signal voltage is charged to the pixel electrode, the potential of each storage capacitor line is Is the third compensation voltage.
[0026]
According to this configuration, the third compensation voltage can be set to an intermediate potential between the first and second compensation voltages, and the first and second compensation voltage signals are applied to the storage capacitor line. Only the storage capacitor line corresponding to the selected gate line is sufficient, and the power consumption of the shift register for the compensation voltage signal can be reduced. In addition, the pixel potential can be controlled by the compensation voltage, the amplitude of the image signal voltage can be reduced, and a low power consumption source line driver circuit can be realized. In addition, a high-quality liquid crystal display device can be realized in which the DC component applied to the liquid crystal is removed by making the potential center of the image signal voltage and the opposite potential the same potential, and the occurrence of flicker and burn-in phenomenon is suppressed. It has the action. Also, when the display image changes due to the dynamic behavior of the capacitive coupling voltage due to the dielectric anisotropy of the liquid crystal material, an overdrive voltage is automatically applied in the direction to amplify the change, and the high-speed response of the liquid crystal It has the effect | action that a drive is realizable.
[0027]
Further, the present invention provides the liquid crystal display device according to claim 5, wherein an auxiliary is provided between the shift register portion constituting the gate line driving circuit for driving the gate line of the pixel driving transistor and the liquid crystal display pixel. It is characterized in that the shift register portion constituting the storage capacitor line driving circuit for driving the storage capacitor line forming the capacitor is made common.
[0028]
According to this configuration, the liquid crystal driving circuit with low power consumption and high-speed response can be realized in a small area.
[0029]
According to the present invention, in a liquid crystal display device using thin film transistors, the driving circuit of the liquid crystal display device according to any one of claims 1 to 6 is formed on the same glass substrate by using the same process for forming a pixel transistor. It is characterized by forming in.
[0030]
According to this configuration, the number of parts can be reduced and an inexpensive liquid crystal display device can be realized.
[0031]
According to the present invention, in a liquid crystal display device using thin film transistors, the driving circuit of the liquid crystal display device according to any one of claims 1 to 6 is formed on the same glass substrate by using the same process for forming a pixel transistor. The drive circuit is provided on both sides of the display screen, and drive signals are applied from both sides of the screen.
[0032]
According to this configuration, a sufficient driving voltage can be applied even when the gate wiring resistance or the storage capacitor line resistance is high, and there is an effect that a liquid crystal display device with a high quality image can be realized.
[0033]
According to the present invention, in a liquid crystal display device using a thin film transistor, a driving circuit is formed on the same glass substrate using the same process for forming a pixel transistor, and the driving circuit has a plurality of functions. The switching of the plurality of functions may be performed by changing the connection of the array mask plate with the same peripheral circuit, or causing only the wiring involved in the function to be selected to cause dielectric breakdown of the contact portion. It is characterized by having a spare wiring for applying a high voltage that can be output or a large current that can melt the connection.
[0034]
According to this configuration, even when a plurality of functions are switched and used, a signal wiring such as a switching signal and a control circuit for the switching signal are unnecessary, and peripheral components are shared regardless of the mode after the function switching. It is possible to realize an inexpensive and multifunctional liquid crystal display device.
[0035]
Further, the present invention is characterized in that the above-mentioned liquid crystal display device is replaced with an OLED display device. Instead of a liquid crystal layer or a liquid crystal cell, an OLED layer can be used.
[0036]
DETAILED DESCRIPTION OF THE INVENTION
Each embodiment of the present invention will be described below. Although not shown, the liquid crystal display device of the present invention has a liquid crystal layer and a liquid crystal cell.
(Embodiment 1)
First, Embodiment 1 of the present invention will be described with reference to the drawings. In addition, the same part as a prior art example attaches | subjects the same code | symbol, and abbreviate | omits description.
[0037]
Also in the present invention (Embodiment 1), the configuration of the liquid crystal display device is the same as that of the conventional example, as shown in FIG. In the present invention (Embodiment 1), the inverter is configured as shown in FIG. Reference numeral 11 denotes a driving transistor, and reference numeral 12 denotes a load transistor, each of which is a p-channel transistor. The source line of the driving transistor 11 is connected to the power source 122, the drain electrode is connected to the source line of the load transistor 12, and the drain electrode of the load transistor 12 is connected to the ground potential 129. The input 14 (IN) is the gate line of the driving transistor 11 and the output 13 (OUT) is the drain electrode. A standby state switching signal 15 (SB) is input to the gate line of the load transistor 12. When the standby state switching signal 15 is at L level, the load transistor 12 acts as a load having a gate-on resistance as its resistance value, and an inverted signal of the input 14 can be obtained at the output 13 and acts as an inverter.
[0038]
Further, when the standby state switching signal 15 is at H level, the load transistor 12 is turned off and becomes high resistance. Also in this case, when the input 14 is at the L level, the H level appears at the output 13 and the inverter operation is performed. When the input 14 is at the H level, the drive transistor 11 is also turned off and has a high resistance. Therefore, a level divided by the off resistance value of the drive transistor 11 and the off resistance value of the load transistor 12 appears in the output 13. . As described above, the configuration of FIG. 1A has the logical function shown in FIG.
[0039]
Thus, in the standby state, the through current 125 can be cut to reduce power consumption, and a low power consumption inverter circuit can be configured.
[0040]
FIG. 2 shows a shift register configured using an inverter circuit in a D flip-flop. Reference numeral 21 denotes an inverter which uses the low power consumption inverter circuit described above. Reference numeral 22 denotes an input terminal. 23 is the output of the first-stage shift register, and 24 is the output of the second-stage shift register. Reference numerals 25 and 28 denote p-channel transistors for performing a switching operation, and control the operations of the first-stage and second-stage D flip-flops, respectively. Reference numerals 26 and 27 denote signals for controlling on / off of the transistors 25 and 28, respectively.
[0041]
FIG. 3 shows the data in the case where the control signals 26 and 27 of the shift register of FIG. 2 are set as two-phase clocks (CLK1 and CLK2) with asymmetric duty cycles set so as not to overlap the on-voltage periods. 6 is a timing chart showing a shift operation. When CLK1 is input to the control terminal 26, CLK2 is input to the control terminal 27, and the signal indicated by D is input to the input terminal 22, the signal Q1 appears at the terminal 23 and the signal Q2 appears at the terminal 24.
[0042]
The switching transistor 25 (SW1) and the switching transistor 28 (SW2) are turned on and off in synchronization with CLK1 and CLK2, but are not simultaneously turned on. Therefore, according to this configuration, since the data is transmitted to the next-stage shift register after the previous value is reliably held, a highly reliable data shift operation is possible.
[0043]
By using a similar configuration and configuring a shift register having stages corresponding to the number of gate lines, a highly reliable gate line driving circuit that sequentially shifts scan data can be configured.
[0044]
FIG. 4 (a) shows the configuration of a shift register having a standby state discriminating means by a D flip-flop using the low power consumption inverter circuit 21. FIG. FIG. 4B shows the timing chart.
[0045]
Reference numeral 41 denotes a D flip-flop composed of the low power consumption inverter circuit 21, and the standby state switching signal 15 described with reference to FIG. 42 is a standby state determination means, which outputs an output (Qn-2) of the (n-2) th stage, an output (Qn-1) of the (n-1) th stage, and an output (Qn) of the (n) th stage. The input AND circuit, and its output is input to the (SB) stage SB terminal.
[0046]
A clock signal 43 is input to the odd-numbered D flip-flops, and a clock signal 44 is input to the even-numbered D flip-flops. 45 is a start pulse input terminal of the shift register.
[0047]
In this configuration, since the level of the data to be shifted is L level, the output of the standby state determination unit 42 having the AND logic operation function has a data width of three stages.
[0048]
The effect of the standby state determination means in the present invention (Embodiment 1) will be described by paying attention to the fifth stage D flip-flop.
[0049]
The output of the standby state discriminating means 42 corresponding to the fifth stage D flip-flop has a waveform shown by SB5 in FIG. In this case, since the standby state switching signal is at the H level in the shaded portion 46, the load transistor of the inverter constituting the fifth stage D flip-flop is switched off, and the low power consumption in which the generation of the through current is suppressed. It will be in the standby state. In the section 47, the standby state switching signal is at the L level, and the load transistors of the inverters constituting the fifth stage D flip-flops are turned on to enter a non-standby state that functions as a normal inverter operation.
[0050]
The section of the hatched portion 46 corresponds to a section where the fifth-stage D flip-flop does not contribute to data shift, and the section 47 corresponds to a section where the fifth-stage D flip-flop contributes to data shift.
[0051]
As described above, by selectively turning off the inverter circuit in the D flip-flop which is not involved in the function as the shift register, the power consumption of the shift register operation in the screen scanning of the gate driving circuit can be reduced.
[0052]
The liquid crystal display device of the above embodiment can be configured in place of an OLED display device. An OLED display device is configured by replacing a liquid crystal cell including a liquid crystal layer with an OLED layer.
[0053]
(Embodiment 2)
Next, a second embodiment of the present invention will be described with reference to the drawings.
[0054]
5 and 6 show the configuration of the liquid crystal display device of the present invention (Embodiment 2). The same parts as those in the conventional example in FIG.
[0055]
Reference numeral 51 in FIG. 5 denotes a storage capacitor line, which forms an auxiliary capacitor 102 between the liquid crystal display pixels. Reference numeral 52 denotes a gate line driving circuit and a storage capacitor line driving circuit, which are configured using the shift register of the present invention (Embodiment 1). The gate line driving circuit and the storage capacitor line driving circuit are configured by sharing one shift register.
[0056]
Accordingly, the shift register of the gate line driver circuit and the storage capacitor line driver circuit can suppress the generation of a through current in a flip-flop at a stage that does not contribute to data shift, and can reduce power consumption of the liquid crystal display device. did it.
[0057]
Next, how the liquid crystal display device of the present invention (Embodiment 2) is driven will be described below.
[0058]
FIG. 6 shows details of one pixel in an equivalent circuit, and a gate-drain capacitance 61 (Cgd) exists between the drain electrode of the pixel transistor 101 and the gate line 105.
[0059]
FIG. 7 is a drive voltage waveform diagram showing the drive method of the present invention (Embodiment 2). 7A shows the waveforms of the image signal voltage Vs and the counter voltage Vc, and FIGS. 7B to 7D show the waveform of the scanning signal voltage (Sn) sequentially applied to the n-th gate line (Gn). VGn) and a compensation voltage waveform (Vcstn) sequentially applied to the n-th storage capacitor line (Cstn).
[0060]
The image signal voltage Vs is a voltage whose polarity is inverted with respect to the counter voltage Vc every scanning period (1H). In the scanning signal voltages VG1 to VG3, Vgon and Vgoff are voltages that turn on and off the pixel transistor 101, respectively. In the compensation signal voltages Vcst1 to Vcst3, Vep, Vem, and Vec are compensation voltages given to the storage capacitor 102 (Cs), and Vep and Vem are switched and applied to each scanning signal wiring that is sequentially scanned.
[0061]
The compensation voltages Vep and Vem are applied at the same time as the ON voltage is applied to the gate line, and after a time for completing charging of a desired potential to the pixel has elapsed, Vep and Vem are applied to the storage capacitor line. Vec which is an intermediate potential is applied. The compensation voltages Vep and Vem are switched between Vep and Vem in synchronization with the polarity of the image signal voltage Vs for each field.
[0062]
By driving the liquid crystal panel as described above, the liquid crystal pixel voltage Vlc applied to the liquid crystal of each pixel when the pixel transistor 101 is turned off is
Vlc (+) = Vs−Vc + [Cs · (Vec−Vem) −Cgd · (Vgon−Vgoff)] / (Cs + CLC + Cgd)
Or
Vlc (−) = Vs−Vc− [Cs · (Vep−Vec) + Cgd · (Vgon−Vgoff)] / (Cs + CLC + Cgd)
Is calculated by The liquid crystal pixel voltage Vlc has two types of positive and negative voltages with respect to the polarity inversion for each field of the image signal voltage Vs. Therefore, the positive side is defined as Vlc (+) and the negative side is defined as Vlc (−) with respect to the counter voltage Vc.
[0063]
Here, the liquid crystal can be AC driven by setting the compensation voltages Vep and Vem so that the effective values of Vlc (+) and Vlc (−) are equal.
[0064]
In this manner, the pixel potential can be controlled with the compensation voltage, the amplitude of the image signal voltage can be reduced, and low power consumption can be realized in the source line driver circuit portion.
[0065]
In addition, by making the potential center of the image signal voltage Vs and the counter potential Vc the same potential, a DC component applied to the liquid crystal is removed, and a high-quality liquid crystal display device that suppresses the occurrence of flicker and image sticking is realized. I was able to.
[0066]
Further, by using the third compensation voltage Vec set to an intermediate potential between the compensation voltage Vep and the compensation voltage Vem, compared to the driving method of the same principle using only two potentials Vep and Vem as the compensation voltage, The compensation voltage signal may be applied to the storage capacitor line only to the storage capacitor line corresponding to the selected gate line, and the power consumption of the shift register for the compensation voltage signal can be reduced.
[0067]
Note that the timing at which the compensation voltage changes from Vem to Vec and the timing at which the compensation voltage changes from Vep to Vec are not limited to those shown in FIG. 7, and the scanning signal voltage applied to the gate line at this stage becomes Vgoff, and the pixel electrode After the image signal voltage Vs is charged, the timing may change during several H periods.
[0068]
In addition, because of the dielectric anisotropy of the liquid crystal material, the liquid crystal pixel capacity varies depending on the potential written to the pixel, and the liquid crystal pixel capacity during black writing is larger than the liquid crystal pixel capacity during white writing. Therefore, according to the driving method of the present invention, when the display image changes, the dynamic behavior of the capacitive coupling voltage caused by the dielectric anisotropy of the liquid crystal material automatically increases the change. In addition, since an overdrive voltage is applied to the pixel electrode, high-speed response driving of the liquid crystal can be realized.
[0069]
In addition, 52 gate line driving circuits and storage capacitor line driving circuits are provided on both sides of the screen, and the gate line and the storage capacitor line are driven from both sides of the screen.
[0070]
With this configuration, a sufficient on-voltage can be applied even when the gate wiring resistance is high, and a large-screen liquid crystal display device with high display quality can be realized.
[0071]
The liquid crystal display device of the above embodiment can be configured in place of an OLED display device. An OLED display device is configured by replacing a liquid crystal cell including a liquid crystal layer with an OLED layer.
[0072]
(Embodiment 3)
Next, Embodiment 3 of the present invention will be described with reference to the drawings.
[0073]
FIG. 8A shows the configuration of the gate drive circuit of the liquid crystal display device of the present invention (Embodiment 3). Reference numeral 81 denotes a shift register, which uses a shift register that can operate with low power consumption and constitutes the drive circuit shown in the present invention (Embodiment 1) and the present invention (Embodiment 2). Further, 82 is an output signal selection circuit, and 83 is an output signal switching signal. Reference numeral 84 denotes an output of the output signal selection circuit, and each output is connected to a gate line.
[0074]
FIG. 8B is a circuit configuration example of the output signal selection circuit 82. The output signal selection circuit 82 is provided for each stage of the shift register 81, and generates a gate drive signal from each output signal of the (n−1), (n), and (n + 1) stages of the shift register. It has a function.
[0075]
The operation of the output signal selection circuit 82 will be described below.
[0076]
When the output signal switching signal 83 is “H”, the output signal data of the (n−1) stage, (n) stage, and (n + 1) stage in the shift register are “0”, “1”, “0”. In the case of '(scanning signal pulse), the gate line corresponding to the scanning signal is selected and a voltage for turning on the thin film transistor is output, and in other cases, the output is an off voltage.
[0077]
When the output signal switching signal 83 is “L”, the output signal data of the (n−1) stage and (n) stage in the shift register are “1” and “1” (multiple gate line selection pulse trains). ), A gate line corresponding to the scanning signal is selected, and a voltage for turning on the thin film transistor is output. In other cases, the output is an off voltage.
[0078]
In such a configuration, a scanning signal pulse for selecting a gate line corresponding to a scanning signal and a plurality of gate line selection pulse trains for selecting an arbitrary plurality of gate lines at once can be sequentially scanned simultaneously.
[0079]
In the liquid crystal display device including the gate driver having the function described above, an image signal corresponding to one scanning line is written from the source line to the pixel electrode of the gate line corresponding to the scanning signal, and the plurality It is possible to have a configuration in which the pixel electrodes of any number of gate lines corresponding to the gate line selection pulse train are charged to the black image signal potential at the same time.
[0080]
Using the above configuration, a liquid crystal display device has been developed in which black signal writing can be inserted for each field in which an image is written. FIG. 9 is a timing chart of the gate selection pulse signal in the present invention (Embodiment 3). In FIG. 9, 86 is an image signal writing period, and 85 is a black signal insertion period. Reference numeral 87 denotes one field period.
[0081]
After displaying an image, by assigning a black signal insertion period to a period in which a plurality of gate lines are selected at once, black signal writing can be inserted for each field while ensuring a sufficient image writing time. I was able to.
[0082]
In the present embodiment, after four lines (Gn, Gn-1, Gn-2, Gn-3) are sequentially written, four lines (Gn-4, Gn-5, Gn-6) are written. , Gn-7) are selected all at once, and writing by a black signal is performed simultaneously.
[0083]
In this way, when displaying a moving image on the liquid crystal display device, the afterimage blur caused by the charge retention effect due to the capacitance of the liquid crystal pixels is eliminated by the strobe effect due to black insertion, and the video visibility is improved. A liquid crystal display device was realized.
[0084]
The liquid crystal display device of the above embodiment can be configured in place of an OLED display device. An OLED display device is configured by replacing a liquid crystal cell including a liquid crystal layer with an OLED layer.
[0085]
(Embodiment 4)
In the present invention (Embodiment 4), the drive circuit of the present invention (Embodiments 1 to 3) is formed on the same glass substrate by using the same process for forming pixel transistors.
[0086]
Accordingly, the pixel and the drive circuit can be manufactured in a lump by the thin film transistor manufacturing process, and the components constituting the drive circuit can be reduced. In addition, since the pixel transistor and the transistor used in the driver circuit can be configured by the same p-channel transistor, the number of thin film transistors can be reduced, and a liquid crystal display device can be manufactured by a simple thin film transistor manufacturing process. .
[0087]
The liquid crystal display device of the above embodiment can be configured in place of an OLED display device. An OLED display device is configured by replacing a liquid crystal cell including a liquid crystal layer with an OLED layer.
[0088]
(Embodiment 5)
Next, a fifth embodiment of the present invention will be described with reference to the drawings.
[0089]
FIG. 10 shows the configuration of the gate drive circuit of the liquid crystal display device of the present invention (Embodiment 5). The shift register in FIG. 10 is a shift register that can operate with low power consumption and constitutes the drive circuit shown in the present invention (Embodiment 1), the present invention (Embodiment 2), and the present invention (Embodiment 3). Used. Here, description of the standby state switching signal input to the D flip-flop 41 and the standby state determination means is omitted.
[0090]
Further, as shown in the present invention (Embodiment 4), these driver circuits are formed on the same glass substrate by using the same process for forming pixel transistors.
[0091]
FIG. 10A shows a configuration when the drive circuit shifts data in the order of Qn, Qn + 1, and Qn + 2 (forward scanning), and 95 indicates the scanning direction.
[0092]
FIG. 10B shows a configuration when the driving circuit shifts data in the order of Qn, Qn−1, and Qn−2 (reverse scanning), and 96 indicates the scanning direction.
[0093]
The connection 97 of the clock signal for controlling the operation of the D flip-flop and the connection 94 connecting the data input terminal 91 of each D flip-flop and the output Qn of each stage are shown in FIG. 10 (a) or 10 (b). By switching in this way, the forward scanning function and the backward scanning function can be switched using the same clock signal and the same D flip-flop.
[0094]
Therefore, when the forward scan function and the backward scan function are switched and used, the function can be switched only by changing the connection of the array mask plate in the exposure process.
[0095]
In this way, signal wiring for the switching signal and the control circuit for the switching signal are unnecessary, and peripheral components and the signal control circuit configuration can be shared regardless of the mode after the function switching. A functional liquid crystal display device was realized.
[0096]
In the present invention, the pixel transistor and the transistor used in the driver circuit are described as a p-channel transistor. However, even when the transistor is an n-channel transistor, the effect of the present invention is the same.
[0097]
The liquid crystal display device of the above embodiment can be configured in place of an OLED display device. An OLED display device is configured by replacing a liquid crystal cell including a liquid crystal layer with an OLED layer.
[0098]
【Effect of the invention】
As is apparent from the above description, even when the power consumption of the shift register portion of the drive circuit is reduced and only the transistor having the same polarity as the pixel transistor is used, the operation reliability is high and high image quality is achieved. It has an effective effect that it can provide an inexpensive liquid crystal display device, and has a great industrial value.
[Brief description of the drawings]
FIG. 1A is a configuration diagram of an inverter circuit according to the present invention.
(B) The figure explaining the logic of the inverter circuit structure of this invention
FIG. 2 is a structural diagram of a shift register according to the present invention.
FIG. 3 is a timing chart showing a shift register operation by a two-phase clock having an asymmetric duty cycle according to the present invention.
FIG. 4A is a configuration example diagram of a shift register including a standby state determination unit of the present invention.
(B) Timing chart explaining operation of (a) above
FIG. 5 is a configuration diagram of a liquid crystal display device according to a second embodiment of the present invention.
FIG. 6 is an equivalent circuit diagram for one pixel in the liquid crystal display device according to the second embodiment of the present invention.
7 is an explanatory diagram of a driving method in a liquid crystal display device according to a second embodiment of the present invention. FIG.
8A is a configuration diagram of a gate drive circuit of a liquid crystal display device according to a third embodiment of the present invention. FIG.
(B) Output signal selection circuit diagram in Embodiment 3 of the present invention
FIG. 9 is a timing chart of an output signal switching signal and a gate selection pulse signal according to the third embodiment of the present invention.
FIG. 10A is a shift register configuration diagram in which the forward scanning function is selected in the fifth embodiment of the present invention.
(B) Shift register configuration diagram in which the backward scanning function is selected in the fifth embodiment of the present invention
FIG. 11 is a configuration diagram of a liquid crystal display device using a conventional thin film transistor.
FIG. 12 is a conventional example of scanning data timing in the case of VGA (pixel number: 640 × 480) display.
FIG. 13A is a diagram illustrating an example of the configuration of a D flip-flop per stage that constitutes a conventional shift register.
(B) A diagram for explaining the logic of the D flip-flop shown in (a).
(C) Conventional example in which the inverter of the D flip-flop shown in (a) is configured by a pMOS transistor.
FIG. 14 is an example of a four-stage shift register configuration using D flip-flops.
FIG. 15 is a timing chart showing a shift register operation by a two-phase clock having a duty cycle of 50% in the conventional example.
FIG. 16 is a timing chart showing a shift register operation using a four-phase clock having a duty cycle of 50% in a conventional example.
[Explanation of symbols]
11 p-channel drive transistor
12 p-channel load transistor
13 Low power inverter circuit output
14 Input of low power consumption inverter circuit
15 Standby state switching signal for low power consumption inverter circuit
21 Low power inverter circuit
22 Shift register input using low power consumption inverter
23 Output of first stage of shift register using low power consumption inverter
24 Second output of shift register using low power consumption inverter
25 Switching transistor for controlling the first stage D flip-flop
26 Signal for controlling the transistor 25
27 Signal for controlling transistor 28
28 Switching transistor for controlling the second stage D flip-flop
41 D flip-flop composed of low power consumption inverter circuit 21
42 Standby state determination means
43 Clock signal input to odd-numbered stage D flip-flop
44 Clock signal input to D flip-flop at even stage
45 Shift pulse start pulse input pin
46 5th stage D flip-flop low power consumption standby state section
47 Non-standby state section in which the fifth stage D flip-flop operates normally
51 Storage capacity line
52. A gate line driving circuit and a storage capacitor line driving circuit integrated with a shift register
61 Gate-drain capacitance (Cgd)
81 Shift register in the present invention (Embodiment 3)
82 Output signal selection circuit
83 Output signal switching signal (SET)
84 Output of output signal selection circuit 82
85 Black signal insertion period in the present invention (Embodiment 3)
86 Image signal writing period in the present invention (Embodiment 3)
87 1 field period
91 Data input terminal of D flip-flop
94 Connection for connecting data input terminal 91 of D flip-flop and output Qn of each stage
95 Forward scan direction in the present invention (Embodiment 5)
96 Reverse Scanning Direction in the Present Invention (Embodiment 5)
97 Connection of clock signals for controlling the operation of the D flip-flop in the present invention (Embodiment 5)
101 Thin film transistor for driving a pixel of a liquid crystal display device
102 pixel storage capacity
103 liquid crystal
104 Source line
105 gate line
106 Common electrode
107 Gate line drive circuit
108 Source line drive circuit
111 Vertical scanning period
112 Horizontal scanning period
121 Conventional inverter
122 power supply
123 Conventional p-channel transistor
124 resistance
125 Through current
126 Switch (SW1) constituting the flip-flop of the conventional example
127 Switch (SW2) constituting conventional flip-flop
Output feedback unit in 128 D flip-flop configuration
129 Ground potential
131 First-stage switching transistor of conventional shift register
132 Second-stage switching transistor of conventional shift register
133 Switching transistor in the second stage of the conventional shift register
134 Switching Transistor of Fourth Stage of Conventional Shift Register
135 Signal for controlling on / off of transistor 131
136 Signal for controlling on / off of transistor 132
137 Signal for controlling on / off of transistor 133
138 Signal for controlling on / off of transistor 134
139 First stage D flip-flop in conventional shift register
140 Second-stage D flip-flop in conventional shift register
141 Third-stage D flip-flop in conventional shift register
142 Fourth-stage D flip-flop in conventional shift register
143 Input terminal in conventional shift register
144 Output terminal of the first stage in the conventional shift register
145 Second-stage output terminal in conventional shift register
146 Third stage output terminal in the conventional shift register
147 Fourth output terminal in conventional shift register
148 Two-phase clock signal waveform that reverses simultaneously

Claims (4)

An active matrix having a liquid crystal display pixel, a pixel driving transistor formed by a thin film transistor, a source line driving circuit for driving a source line of the pixel driving transistor, and a gate line driving circuit for driving a gate line of the pixel driving transistor Type liquid crystal display device,
The source line driver circuit or the gate line driver circuit has a shift register composed of a plurality of cascaded m stages (m> 3),
The n (m ≧ n ≧ 3) stage of the shift register inputs the output of the (n-2) stage shift register, the (n-1) stage output, and the n stage output. A standby state determination unit comprising an AND circuit, and a D flip-flop for inputting an output of the standby state determination unit as a standby state switching signal;
In the D flip-flop, an input signal is connected to a gate electrode, a power source line is connected to a source electrode, a drain transistor is used as an output, a standby state switching signal is connected to a gate electrode, and a source electrode is driven It is composed of a load transistor connected to the drain electrode of the transistor, and is configured by using an inverter circuit that suppresses the through current in the standby state, so that the standby state is the power of the transistor circuit constituting each stage of the shift register. The consumption is smaller than that in the non-standby state.
A liquid crystal display device characterized by the above. The first stage of the shift register receives the start pulse and the output of the shift register of the first stage as a standby state determination unit composed of an AND circuit, and the output of the standby state determination unit is input as a standby state switching signal. D flip-flop
The second stage of the shift register is a standby state determination means comprising an AND circuit that receives a start pulse, an output of the first stage shift register, and an output of the second stage shift register, and the standby state 2. The liquid crystal display device according to claim 1, further comprising a D flip-flop for inputting an output of the discriminating means as a standby state switching signal.   3. The liquid crystal display device according to claim 1, wherein the drive circuit and the pixel transistor of the liquid crystal display device according to claim 1 are formed on the same glass substrate by using the same process.   A liquid crystal display device in which the drive circuit of the liquid crystal display device according to any one of claims 1 to 3 and the pixel transistor are formed on the same glass substrate using the same process, wherein the drive circuit displays A liquid crystal display device provided on both sides of a screen, wherein drive signals are applied from both sides of the screen.

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