JP5049691B2 - Semiconductor integrated circuit - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit, and further to a technique for optimizing a high-speed performance or a low power consumption performance with respect to variations after manufacture in the semiconductor integrated circuit.

  With the miniaturization of the semiconductor manufacturing process, the variation of the threshold voltage (Vth) of the MOS transistor is increasing. When Vth of the manufactured MOS transistor decreases due to variations in Vth, a leakage current called a subthreshold leakage current increases and the power consumption of the circuit increases. Further, when Vth of a manufactured MOS transistor increases due to variations in Vth, the on-current of the transistor decreases, the operation speed of the circuit decreases, and the operation performance of an LSI (Large Scale Integrated circuit) decreases. A substrate bias technique is known as a technique for adjusting Vth during operation of an LSI after manufacture. Vth can be changed by applying a predetermined substrate bias voltage to a semiconductor substrate (referred to as “well” in the case of CMOS) on which a MOS transistor is formed. Japanese Patent Application Laid-Open No. 2004-151561 discloses a technique for changing a Vth of a MOS transistor by applying a substrate bias voltage to each circuit block including a plurality of MOS transistors. Patent Document 2 discloses a technique for connecting a substrate electrode of only a MOS transistor constituting a circuit element included in a path that controls a speed in a circuit and applying a substrate bias voltage for reducing Vth only to the substrate electrode. It is disclosed.

JP 2000-286387 A JP 2004-172627 A

  With the progress of process technology for manufacturing LSIs, miniaturization of transistors in LSIs is progressing. For example, in 2006, mass production of fine transistors having a transistor gate length of 50 nm was carried out. As transistor miniaturization progresses, the variation in Vth of the transistor increases, and the Vth of the transistor that actually constitutes the manufactured circuit greatly deviates from the Vth of the transistor at the time of design. For example, when the Vth at the time of manufacture is lower than the Vth at the time of design, the power consumption increases due to an increase in the leakage current of the transistor, and the power consumption specification cannot be satisfied. Conversely, when the Vth at the time of manufacture becomes higher than the Vth at the time of design, the operating current of the transistor decreases, the operating speed decreases, and the operating speed specification cannot be satisfied. LSIs that do not satisfy the specifications cannot be shipped as non-defective products, which greatly reduces the manufacturing yield.

  In Patent Document 1, the operation performance of a circuit block is adjusted by controlling the substrate bias for each circuit block including a plurality of MOS transistors. In this technique, Vth of a MOS transistor configured in a circuit block unit is controlled. However, there is a possibility that the scale of a transistor included in a circuit block may increase with the miniaturization of the transistor. Further, the performance variation of the transistors in the circuit block is not improved. Further, when adjusting the Vth by changing the substrate bias potential in order to optimize the Vth changed due to the variation of the transistors, it is necessary to measure how much the Vth has changed due to the variation. However, since the circuit block includes a large number of transistors, it is difficult to measure the variation of Vth of the transistors in the entire circuit, and it is also difficult to select the transistor to be measured in order to determine the substrate bias. .

  In Patent Document 2, it is possible to apply a substrate bias so as to improve the speed by lowering Vth of only the transistors that affect the speed performance of the circuit. However, since the transistor that affects the speed performance needs to be determined at the time of circuit design before manufacturing the LSI, it is not possible to compensate for the performance changed due to the Vth variation of the transistor. Furthermore, since it is necessary to finely control the substrate bias, the area overhead is large.

  An object of the present invention is to ensure the performance at the time of circuit design and to improve the manufacturing yield by compensating for the Vth variation of the MOS transistor in the LSI.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  A representative one of the inventions disclosed in the present application will be briefly described as follows.

  That is, the semiconductor integrated circuit includes a first flip-flop capable of storing input data in synchronization with a clock signal, a combinational circuit that captures an output signal of the first flip-flop, and an output signal of the combinational circuit as the clock signal. And a second flip-flop capable of storing in synchronization. At this time, for each combinational circuit sandwiched between the first flip-flop and the second flip-flop, a threshold adjustment circuit capable of adjusting the threshold voltage of the transistors constituting the combinational circuit is provided. This achieves an improvement in manufacturing yield.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, by compensating for the Vth variation of the MOS transistor in the LSI, it is possible to ensure the performance at the time of circuit design and to improve the manufacturing yield.

1. Representative Embodiment First, an outline of a typical embodiment of the invention disclosed in the present application will be described. The reference numerals of the drawings referred to with parentheses in the outline description of the representative embodiments merely exemplify what are included in the concept of the components to which the reference numerals are attached.

  [1] A semiconductor integrated circuit (SOC) according to a typical embodiment of the present invention includes a first flip-flop (FF1) capable of storing input data in synchronization with a clock signal, and an output of the first flip-flop. A combinational circuit (LOGIC1) that captures signals, and a second flip-flop (FF2) that can store an output signal of the combinational circuit in synchronization with the clock signal. A threshold adjustment circuit (100) capable of adjusting the threshold voltage of the transistors constituting the combination circuit is provided for each combination circuit sandwiched between the first flip-flop and the second flip-flop.

  [2] The combination circuit includes a p-channel MOS transistor (PMOS) and an n-channel MOS transistor (NMOS), and back gates are commonly connected to the MOS transistors having the same conductivity type.

  [3] The threshold adjustment circuit includes a first adjustment circuit (10) capable of adjusting a back gate of a p-channel MOS transistor and a second adjustment circuit (20) capable of adjusting a back gate of an n-channel MOS transistor. ).

  [4] The first adjustment circuit includes a first register (REG1) capable of holding back gate potential control information for the p-channel MOS transistor, and the p-channel MOS based on the held information in the first register. A first control circuit (VBPCNT) capable of changing the potential of the back gate of the transistor; a second register (REG2) capable of holding back gate potential control information for the n-channel MOS transistor; and the second register holding information. And a second control circuit (VBNCNT) capable of changing the potential of the back gate of the n-channel MOS transistor.

  [5] The first control circuit and the second control circuit may include a selector that can selectively supply a plurality of potentials having different levels to the back gates of the plurality of transistors based on the back gate potential control information. 5. The semiconductor integrated circuit according to claim 4, further comprising:

  [6] In the combinational circuit, a data path is formed by the transistor.

  [7] The transistor forming the combinational circuit includes a diffusion layer, a well region, and an insulating film (BOX) interposed between the diffusion layer and the well region. The well region is used as a back gate.

  [8] The first flip-flop circuit and the second flip-flop circuit include a determination circuit (EOR) that can determine whether or not an input signal satisfies a timing constraint.

  [9] The combination circuit includes a power supply cell (BBCELL) for supplying power to the back gate, and the power supply cells are arranged at a ratio of one to a plurality of logic cells each having a predetermined logic function. .

  [10] When the operating speed of the combinational circuit is faster than a design value, the threshold voltage is raised by supplying a negative bias voltage to the back gate of the transistor by the threshold adjustment circuit. When the operation speed of the circuit is slower than the design value, the threshold voltage is lowered by supplying a positive bias voltage to the back gate of the transistor by the threshold adjustment circuit.

2. DESCRIPTION OF EMBODIMENT <First Embodiment>
FIG. 22 shows a microcomputer as an example of a semiconductor integrated circuit according to the present invention.

  The microcomputer is not particularly limited, but is formed on one semiconductor substrate such as a single crystal silicon substrate by a known semiconductor integrated circuit manufacturing technique.

  In FIG. 22, SOC is a semiconductor chip on which a microcomputer is formed, CPU is a processor, ALU is an arithmetic circuit such as a data path in the processor, CONT is a control circuit in the CPU, DREG is a register circuit in the CPU, and CACHE is a CPU The cache memory, SRAM is a built-in memory built in the SOC, IP is a circuit block having various functions, BUS is a circuit for controlling the bus, and I / O is a circuit for controlling the input / output circuit. In the ALU, CONT, and IP shown here, a plurality of combinational circuits sandwiched between FFs are mounted. By adjusting the substrate bias for each circuit, the performance of each combinational circuit is improved. Optimized.

  Here, a case where a reverse bias is applied to an n-channel MOS transistor will be described. When the Vth of the n-channel MOS transistor and the p-channel MOS transistor varies separately, different substrate biases can be controlled by storing different data in the registers for controlling the respective substrate biases. .

  Although the method of switching three types of voltages is shown here, the basic effect is the same even if the method of switching two or more types of voltages is used, although the range in which Vth can be controlled is different. It can be realized with a similar circuit configuration.

  FIG. 1 shows a configuration example of a main part in the SOC.

  In FIG. 1, FF1 and FF2 are flip-flops for holding data, LOGIC1 is a combinational circuit sandwiched between FF1 and FF2, NAND1 is a NAND circuit, INV1 is an inverter circuit, and REG1 and REG2 control the back gate potential. It is a register circuit for storing data for the purpose. VDD is a high potential power source, and VSS is a low potential power source. VBP is a substrate power supply for supplying the substrate potential of the p-channel MOS transistor PMOS in LOGIC1, and VBN is a substrate power supply for supplying the substrate potential of the n-channel MOS transistor NMOS in LOGIC1. VBPCNT is a control circuit that controls the VBP potential, VBNCNT is a control circuit that controls the VBN potential, VBPSEL is a signal that specifies the VBP potential, VBNSEL is a signal that specifies the VBN potential, and VBPS1 to VBPS3 are power supply potentials selected by VBPCNT. The power supply lines VBNS1 to VBNS3 are power supply lines that supply a power supply potential selected by VBNCNT. In this circuit configuration, the substrate potentials of the n-channel MOS transistor and the p-channel MOS transistor can be changed for each combinational circuit existing between FF1 and FF2 in accordance with the data stored in the REG.

Here, 100 is a threshold adjustment circuit capable of adjusting the threshold voltage (Vth) of the MOS transistor. The threshold adjustment circuit 100 includes a first adjustment circuit 10 that can adjust the Vth of a p-channel MOS transistor, and a second adjustment circuit 20 that can adjust the Vth of an n-channel MOS transistor. The first adjustment circuit 10 includes the REG1 and the VBPCNT. The VBPCNT includes a selector SEL1 that can select VBPS1, VBPS2, and VBPS3 according to VBPSEL.
The second adjustment circuit 20 includes the REG2 and the VBNCNT. The VBNCNT includes a selector SEL2 that can select VBNS1, VBNS2, and VBNS3 in accordance with VBNSEL.

  FIG. 2 shows a cross section of the MOS transistor.

  In FIG. 2, GATE is a gate electrode, DRAIN is a drain electrode, SOURCE is a source electrode, BAKC-GATE is a back gate electrode, STI is element isolation, and SUBSTRATE is a silicon substrate. STI is a layer for isolating each transistor element made of an insulator such as SiO2. In the MOS transistor, the current flowing between the source and the drain can be changed by changing the gate voltage.

  FIG. 3 shows the current characteristics of the 65-nm process n-channel MOS transistor (the relationship between the gate voltage of the MOS transistor and the current between the source and drain).

  It can be seen that the source-drain current is increased by changing the gate voltage from about 0V to about 1.0V. The reason why the current increases at 0 V or less is that leakage current such as GIDL (Gate Induced Drain Leakage) current increases. Further, the current characteristics change by changing the voltage of the back gate of the transistor. In FIG. 3, I1 is when the back gate voltage of the n-channel MOS transistor is 0.5V, I2 is 0V, that is, equal to the source voltage, and I3 is when the back gate voltage is -1.0V. The current characteristics are shown. The application of the back gate voltage is called “back bias”. A state in which the back gate voltage is equal to the source voltage is defined as a back bias “0”, a state in which a positive voltage is applied is a forward back gate bias (forward substrate bias), and a state in which a negative voltage is applied is a reverse back gate bias (reverse) Directional substrate bias). The forward back gate bias increases the current between the source and the drain, and the reverse back gate bias decreases the current. When the gate voltage is 0V, the transistor is not operating, but a current flows between the source and the drain. This current is called a subthreshold leakage current, and the circuit is not operating. It is a flowing current. When this leakage current increases, the power consumption of the circuit increases. That is, when the forward bias is applied, the leakage current increases, so that the power consumption increases. Conversely, when the reverse bias is applied, the leakage current decreases and the power consumption can be reduced. Further, the current between the source and drain when the gate voltage is 1.0 V is called “on-current” and is a current required for the circuit to operate. When the on-current increases, the operation speed of the circuit increases. Conversely, when the on-current decreases, the operation speed of the circuit decreases. That is, the operation speed of the circuit can be improved by the forward back gate bias, and conversely, the operation speed of the circuit can be reduced by the reverse back gate bias.

  FIG. 4 shows a distribution of threshold values (Vth) of transistors when an LSI is manufactured.

  It has been found that the Vth of a transistor varies according to a normal distribution after manufacture. For example, in FIG. 4, the VAR2 region has a value substantially equal to Vth at the time of design, and the power and operation speed performance are values substantially equal to those at the time of design. In the VAR1 region, the value of Vth is lower than that at the time of design, so that the operation speed is higher than that at the time of design, but the power consumption increases. On the contrary, in the VAR3 region, the value of Vth is higher than that at the time of design, so that power consumption is reduced as compared with the value at the time of design, but the operation speed is also reduced.

  As can be seen from FIG. 3 and FIG. 4, it can be seen that the current characteristics greatly change due to variations in Vth of the transistors, which affects the circuit performance. In particular, when the LSI manufacturing process is larger than 130 nm, the Vth variation between the chips in the average value of the Vth of the transistors in the chip is larger than the Vth variation between the transistors in the chip, so that Vth can be compensated for each chip. Thus, it is possible to bring the performance of the LSI that has fluctuated due to Vth variation closer to the design value. However, in a manufacturing process called a deep submicron process in which the LSI manufacturing process is smaller than 90 nm, the Vth variation of transistors in the same LSI chip increases, and the Vth compensation on a chip basis cannot satisfy the design value. ing. Further, in the 65 nm process advanced one generation from the 90 nm process, it is necessary to compensate for Vth in a very fine circuit unit due to an increase in the number of transistors mounted in a chip and an increase in performance variation. In the circuit shown in FIG. 1, a combinational circuit (LOGIC1) sandwiched between flip-flops (FF), which is the minimum unit for determining timing in an LSI logic circuit, is used as a unit, and the substrate or well, that is, the MOS transistor is used in that unit. By connecting the back gate node, the substrate potential can be controlled for each unit. In other words, when the operating speed of the combinational circuit is faster than the designed value, Vth is lower than the designed value. Therefore, Vth is increased by the reverse back gate bias, the leakage current is reduced, and the power consumption is reduced. Conversely, when the operating speed is lower than the designed value, Vth is higher than the designed value, so Vth is lowered by the forward back gate bias to improve the operating speed. In this way, by appropriately adjusting the substrate bias according to the circuit performance after manufacturing, the speed performance and power performance are brought close to the design values, and conventionally treated as a defective product as a non-defective LSI, and the yield is improved. Can do. The substrate bias potentials VBPS 1 to 3 and VBNS 1 to 3 can be applied from the outside of the LSI through a power supply terminal.

  FIG. 5 shows the relationship between the state of Vth and the potential of each node in FIG. 1 in each state.

  VBPS 1 to 3 and VBNS 1 to 3 are potentials to be selected as substrate potentials of the p-channel type MOS transistor and the n-channel type MOS transistor, respectively, depending on the state of Vth of the combinational circuit sandwiched between the FFs after manufacture. Is applied to the substrate of the p-channel MOS transistor and the n-channel MOS transistor. STATE 1 shows a state where Vth is lower than the design value due to Vth variation. In this state, reverse bias is applied because it is necessary to increase Vth. That is, VBPS1 is connected to VBP which is the substrate of the p-channel MOS transistor, and 2.0 V which is higher than the source potential is applied. Further, VBNS1 is connected to VBN which is the substrate of the n-channel MOS transistor, and −1.0 V which is lower than the source potential is applied. As a result, a reverse substrate bias is applied to the MOS transistor to increase Vth, thereby reducing a leakage current and reducing power consumption. STATE 2 shows a state where Vth is close to the design value. In this state, since it is not necessary to adjust Vth, the same potential as the source potential is applied. Therefore, VBP, which is the substrate of the p-channel MOS transistor, is connected to VBPS2, and 1.0 V, which is the same potential as the source potential, is applied. Further, VBNS2 is connected to VBN which is the substrate of the n-channel MOS transistor, and 0 V which is the same potential as the source potential is applied. STATE 3 shows a state in which Vth is higher than the design value due to variations in Vth. In this state, since it is necessary to lower Vth, forward bias is performed. That is, VBPS3 is connected to VBP which is the substrate of the p-channel MOS transistor, and 0.5 V which is lower than the source potential is applied. Further, VBNS3 is connected to VBN, which is the substrate of the n-channel MOS transistor, and 0.5 V that is higher than the source potential is applied. As a result, a forward substrate bias is applied to the MOS transistor, Vth is reduced, and the on-current of the transistor is increased, thereby improving the operation speed.

  Here, the potential of the reverse substrate bias is set to -1.0 V. However, when Vth needs to be further adjusted, it can be set to a voltage lower than -1.0 V. On the contrary, when the width for increasing Vth may be small, it is possible to set the potential higher than -1.0V.

  Similarly, although the forward bias voltage is also set to 0.5 V, it can be set to a different potential from the relationship of the amount by which Vth is changed.

  FIG. 6 shows a layout example of logic cells constituting a circuit when a substrate bias is applied.

  In FIG. 6, STCELL is an inverter cell which is an example of a logic cell, BNDWELL is a well boundary, VDD is a power supply line, VSS is a ground potential power supply line, and VBP is a power supply line of n well potential which is a substrate of a p-channel MOS transistor. , VBN is a p-well potential power source line which is an n-channel MOS transistor substrate, BNCON is a well contact for supplying power to a p-well which is an n-channel MOS transistor substrate, and BPCON is a p-channel MOS transistor substrate. A well contact for supplying power to a certain n-well, METAL is a metal wiring layer for wiring, CONT is a contact, DIFF is a diffusion layer, and POLY is polysilicon serving as a gate of a transistor. Since it is necessary to set the substrate potential to a voltage different from the power supply voltage, a substrate feed line VBP / VBN is required separately from VDD / VSS.

  FIG. 7 shows a cross section of the logic cell. This cross section corresponds to a cross section taken along line A-A 'in FIG.

In FIG. 7, GATE is a transistor gate electrode, n ⁺ is an n-type channel diffusion layer, p ⁺ is a p-type channel diffusion layer, pwell is a p-well, nwell is an n-well, and deep-nwell is a deep n-well. An n-type well, psub, formed in a deeper portion of the well, indicates a p-type silicon substrate. In this MOS transistor, a different potential needs to be applied to each combinational circuit sandwiched between FFs, so that a triple well structure is required. In the triple well structure, since the p-well and the silicon substrate are insulated by the deep n-well, different potentials can be applied to the p-well for each combinational circuit sandwiched between the FFs. Further, by separating the deep n well for each combinational circuit, a different potential can be applied to the n well for each combinational circuit sandwiched between FFs.

  FIG. 8 shows a layout example when the logic cells shown in FIG. 6 are arranged. In FIG. 8, pwell is a p-well which is a substrate of an n-channel MOS transistor, nwell is an n-well which is a substrate of a p-channel MOS transistor, deep-nwell is an n-type well called a deep n-well, and psub is a p-type. A region written on a silicon substrate and a dotted line indicates one logic cell. A region surrounded by the deep n-well represents the above one combinational circuit, and two combinational circuits are shown in FIG. The logic cells shown in FIG. 6 are regularly arranged and surrounded by a deep n-well to make the n-well and p-well of each combinational circuit common, and from other combinational circuits, the p-type is a substrate. Separated by a silicon substrate. In order to separate deep n-wells, it is necessary to take a margin of distance, resulting in area overhead. In this example, an example of a circuit such as a data path capable of regularly laying out combination circuits is shown. Area overhead in separating wells is minimized.

  FIG. 9 shows a procedure for determining the substrate bias.

  First, the power supply voltage VDD and the clock signal frequency CLK are set (901). Next, the potential of VBN is set to VBNS3, and the potential of VBP is set to VBPS3 (902). The circuit is actually operated to check whether the timing constraint is satisfied (903). If the timing constraint is not satisfied, the chip does not operate even if Vth is decreased by applying a forward bias, so that this chip becomes a defective product (904). If the timing constraint is satisfied, then the VBN potential is set to VBNS2 and the VBP potential is set to VBPS2 (905). The circuit is actually operated again to check whether the timing constraint is satisfied (906). When the timing constraint is not satisfied, only when VBN and VBP are set to VBNS3 and VBPS3 (907), respectively, this circuit satisfies the speed performance, so that VBN can be connected to VBNS3 and VBP can be connected to VBPS3. Information is set in the substrate bias setting register in the circuit of FIG. 1 (910). If the timing constraint is satisfied, then the VBN potential is set to VBNS3 and the VBP potential is set to VBPS3. The circuit is actually operated again to check whether the timing constraint is satisfied. In the case of not satisfying the timing constraint, this circuit satisfies the speed performance when VBN and VBP are set to VBNS2 and VBPS2, respectively, so that VBN can be connected to VBNS2 and VBP can be connected to VBPS2. Set the substrate bias setting register. When the timing constraint is satisfied, this circuit satisfies the speed performance regardless of whether VBN and VBP are set to VBNS1 to 3 and VBPS1 to 3, respectively, so that VBN can be connected to VBNS1 and VBP can be connected to VBPS1. A substrate bias setting register in the circuit of FIG. 1 is set. As a result, Vth can be set so as to increase Vth of the MOS transistors constituting the circuit within a range satisfying the operation speed, and thus the LSI can be operated with a high operation speed and low power consumption. Whether or not the timing constraint is satisfied can be implemented by performing a normal LSI operation check. In particular, in the current LSI test, it is possible to detect in which path of scanning an error has occurred, so it is possible to check whether a timing error has occurred for each path between FFs. The potential of the substrate bias can be determined for each combinational circuit that is sandwiched.

  According to the above example, the following effects can be obtained.

  (1) By changing the substrate bias, the variation in Vth can be corrected and the LSI can meet the design specifications. Further, by making the correction unit a combinational circuit sandwiched between FFs, it is possible to cope with the Vth variation of the transistors in the chip, which are increased in a miniaturized manufacturing process, and the unit for changing Vth is FF. It is possible to easily check the timing constraints by limiting the interval.

  (2) By compensating for the Vth variation of the MOS transistor in the LSI, the performance at the time of circuit design can be ensured, thereby improving the manufacturing yield.

  (3) The logic cells shown in FIG. 6 are regularly arranged, and the outside is surrounded by a deep n-well to make the n-well and p-well of each combinational circuit common. Isolation with a p-type silicon substrate minimizes the area overhead when isolating the deep n-well.

Second Embodiment
FIG. 10 shows a layout example when a combinational circuit sandwiched between FFs such as a CPU control circuit is applied to a circuit that cannot be laid out regularly.

  In FIG. 10, deep-nwell indicates a deep n-well region, AREAA indicates a region where a transistor can actually be disposed in the deep n-well, and psub indicates a p-type silicon substrate. In a CPU control circuit or the like, a logically grouped circuit sandwiched between FFs is complicated as shown in the area surrounded by the deep n-well in FIG. 10 in the actual layout on silicon. Be placed. For this reason, it is necessary to provide a margin for separating the deep n-well between each combinational circuit, so there is a very large area overhead, and the area where transistors can actually be arranged is considerably narrow. However, there is a sufficient merit if the area overhead due to mounting this circuit can be absorbed by improving the yield by applying the substrate bias. Further, although it is written in an intricate form in FIG. 10, if the circuit layout can be solidified so as to be close to that in FIG. 8 when actually laying out, the area overhead is minimized and the effect of the present invention is maximized. It is possible.

<Third Embodiment>
FIG. 11 shows a configuration example of a flip-flop circuit that can check whether the timing constraint is satisfied.

  In the first embodiment, an LSI test flow is used to determine the substrate bias. However, in that case, it is necessary to modify the LSI test flow. Application of the flip-flop circuit shown in FIG. 11 makes it possible to check timing constraints with a minimum change in the LSI test flow.

  The flip-flop circuit shown in FIG. 11 includes two FFs, inverters INV1 and INV2, and an exclusive OR (EOR). FF is a flip-flop circuit capable of holding 1-bit data, CLK is a clock signal for controlling the flip-flop, D is an input of FF, Q is an output of FF, DD is a signal obtained by delaying input signal DD, and QD is delayed The output signals QD and ERR of the FF that have captured the signal DD are signals that are high when the timing constraint is not satisfied. Such a flip-flop circuit is applied to FF1 and FF2 in FIG.

  The operation of this circuit will be described with reference to FIGS.

  FIG. 12 shows an operation waveform when the timing constraint is satisfied.

  D is an output of the combinational circuit placed before FF, and DD is a signal obtained by delaying the signal by inverters (INV1, INV2). Since the values of D and DD change to new values at the moment when the clock signal (CLK) rises from low to high, the same value is captured and output as Q and QD in the FF that captures D and DD. Since the respective values are equal, the output ERR obtained by taking the exclusive OR of them by EOR is low, and it can be seen that no timing error has occurred.

  FIG. 13 shows an operation waveform when the output of the combinational circuit placed before the FF is slow and does not satisfy the timing constraint.

  At the instant when the clock signal rises from low to high, the value of D changes, but when the delay time of the combinational circuit in front of this FF is large, the value of DD does not change to a new value. Therefore, the FF that captures D and DD captures different values and outputs them as Q and QD. Therefore, the exclusive OR of the output becomes high, and it is detected that a timing error has occurred.

  In the circuit of the first embodiment, it is necessary to test whether or not a timing error occurs during the LSI test, and to measure the operation speed of the circuit at that stage. If the circuit performance changes due to the influence, it can not cope. When this circuit is used, it is possible to measure the operation performance in the state of actual operation. Therefore, if the circuit configuration includes means for rewriting the value of the register REG for controlling the substrate bias by this ERR output, It is possible to determine the substrate bias to be applied without testing the LSI. Furthermore, after the LSI is shipped, even if the performance changes due to operating conditions or aging of the transistors, the substrate bias application conditions may be changed to make the circuit compatible with changes in operating conditions, such as aging. it can. Further, if this circuit configuration is used, the performance of the LSI can be corrected according to the conditions after shipment, so the test conditions before shipment can be relaxed and the yield can be improved.

<Fourth embodiment>
FIG. 14 shows a circuit for controlling the substrate bias.

  In the first embodiment, VBNS 1 to 3 and VBPS 1 to 3 are supplied from the outside. However, in this example, no voltage other than the power supply voltage is applied from the outside. In FIG. 14, VDD is a high potential side power source and VSS is a low potential side power source. VBP is a substrate power supply for supplying the substrate potential of the p-channel MOS transistor, and VBN is a substrate power supply for supplying the substrate potential of the n-channel MOS transistor. VBPCNT is a control circuit for controlling the VBP potential, and VBNCNT is a control circuit for controlling the VBN potential. VBPSEL is a signal designating the VBP potential, and VBNSEL is a signal designating the VBN potential. VBPS1 to VBPS3 are power supply lines for supplying a power supply potential selected by VBPCNT, VBNS1 to VBNS3 are power supply lines for supplying a power supply potential selected by VBNCNT, and CP1 to CP3 are charge pump circuits.

  In this example, the circuit other than the circuit described in FIG. 14 is equivalent to the circuit of the first embodiment.

  Since it is necessary to apply 2.0 V to VBPS1, it is necessary to generate a potential different from the power supply voltage. Therefore, it is necessary to make a potential of 2.0 V from a power supply potential of 1.0 V using the charge pump CP1. Since VBPS2 is equal to the power supply voltage 1.0V, the power supply voltage VDD is supplied. Since it is necessary to apply 0.5 V to VBPS3, a voltage of 0.5 V is generated from a power supply potential of 1.0 V using the charge pump CP2. Since it is necessary to apply −1.0 V to VBNS1, a voltage of −1.0 V is generated using the charge pump CP3. Since 0V equal to the ground potential is applied to VBNS2, it is connected to VSS. Since 0.5 V needs to be applied to VBNS3, the same voltage as VBPS3 can be used, and is connected to the output of charge pump CP2. Thus, the substrate bias potential can be generated internally without being applied from the outside.

<Fifth Embodiment>
FIG. 15 shows a cross section of a MOS transistor used in the fifth embodiment.

  Unlike the bulk CMOS transistor in the first embodiment, this MOS transistor has an oxide film called a buried oxide film (BOX) under the diffusion layers that become the source and drain electrodes of the transistor, and the channel portion is completely A fully depleted transistor that is depleted is used. A transistor having such a structure is called a “thin film BOX / FD-SOI transistor”. In FIG. 15, GATE is a gate electrode, DRAIN is a drain electrode, SOURCE is a source electrode, BOX is a buried oxide film, BAKC-GATE is a well electrode under the buried oxide film, STI is element isolation, and SUBSTRATE is a silicon substrate. The structure of the thin film BOX • FD-SOI transistor is different from the bulk CMOS transistor of FIG. 2 in that there is a BOX called a buried oxide film. The presence of this BOX layer makes it possible to control the Vth of the transistor as in the bulk CMOS transistor of FIG. 2 if the potential of the well below the BOX layer is controlled as a back gate. Further, since the BOX layer is present, the back gate is insulated from the source and drain, and no current flows from the source and drain to the back gate even when the back gate voltage is varied. When the circuit described in the first embodiment is configured, there are various advantages by replacing the transistor with the thin-film BOX • FD-SOI transistor.

FIG. 16 shows a cross section of a thin-film BOX / FD-SOI transistor when the substrate bias is controlled. In FIG. 16, GATE is a transistor gate electrode, n ⁺ is an n-type channel diffusion layer, p ⁺ is a p-type channel diffusion layer, pwell is a p-well, nwell is an n-well, and deep-nwell is a deep n-well. An n-type well formed in a deeper portion of the well, psub indicates a p-type silicon substrate, and STI and DTI indicate element isolation. In this example, two types of element isolation, STI and DTI, are used. STI is element isolation that reaches from the surface of the semiconductor silicon to a depth below the BOX layer, and isolates each transistor from the power supply of the adjacent transistors and wells. DTI is element isolation that reaches the depth below a deep well structure called a deep n well from the surface of semiconductor silicon. By using this element isolation, the well can be isolated and insulated for each transistor element. As a result, wells having different potentials can be brought close to each other, and the area overhead is small even if the unit for changing the well potential on the LSI is made finer.

  FIG. 17 shows a layout example when logic cells for controlling the substrate bias are arranged.

  In FIG. 17, pwell is a p-well that is a substrate of an n-channel MOS transistor, nwell is an n-well that is a substrate of a p-channel MOS transistor, deep-nwell is an n-type well called a deep n-well, and psub is a p-type. A combinational circuit in which a silicon substrate, a region written in a dotted line is one logic cell, and comb1 and comb2 have a common back gate node. By using a thin-film BOX / FD-SOI transistor, the well can be separated using element isolation, so there is no need to separate the deep n well by the combinational circuit, and the area between the combinational circuits to which different substrate biases are applied is small. It can be seen that the area overhead is smaller than in FIG.

  FIG. 18 shows the relationship between the state of Vth and the potential of each node in FIG. 1 in each state.

  When the thin-film BOX • FD-SOI transistor is used, as shown in FIG. 16, an oxide layer (BOX) exists between the diffusion layer and the well serving as the back gate. In a bulk CMOS transistor, in the case of forward back gate bias, the PN junction between the diffusion layer and the well is turned on as a diode and a large current flows, so the forward bias voltage can only be about 0.5V. However, in the thin-film BOX / FD-SOI transistor, a forward bias voltage higher than 0.5 V can be applied because a BOX layer which is an insulator is interposed between the diffusion layer and the well, as shown in FIG. The substrate bias can be related. FIG. 18 is almost the same as FIG. 5 showing the relationship of potentials when a bulk CMOS transistor is used, and only different portions will be described here. In FIG. 18, a potential of 0 V is applied to VBPS3 that supplies the forward bias of the p-channel MOS transistor, and a potential of 1.0 V is applied to VBNS3 that supplies the forward bias of the n-channel MOS transistor. In STATE 3 where necessary, 0V and 1.0V potentials are applied to VBP and VBN. As a result, the value of Vth can be adjusted to be larger than that described with reference to FIG. 5, and the range for adjusting the circuit performance is also increased.

<Sixth Embodiment>
FIG. 19 shows a circuit configuration equivalent to the circuit described in the second embodiment, in which a combination circuit sandwiched between FFs such as a CPU control circuit cannot be regularly laid out. A layout example in the case of using an SOI transistor is shown. In FIG. 19, deep-nwell indicates a deep n-well region, AREAA indicates a region where a transistor can actually be disposed in the deep n-well, and psub indicates a p-type silicon substrate. In a CPU control circuit or the like, a logically grouped circuit sandwiched between FFs is complicated as shown in the area surrounded by the deep n-well in FIG. 10 in the actual layout on silicon. Be placed. For this reason, it is necessary to provide a margin for separating the deep n-well between the combinational circuits. When thin-film BOX / FD-SOI transistors are used, the wells between the combinational circuits can be isolated using element isolation, so there is no need to change deep n-wells by combinational circuits, and the area overhead is greatly reduced. A region where the signal can be arranged can occupy a large area in the LSI. This situation can be seen at a glance by comparing FIG. 10 and FIG. 19, and the area overhead can be greatly reduced by applying the thin film BOX / FD-SOI transistor.

<Seventh embodiment>
FIG. 20 shows another configuration example of the circuit for controlling the VBP potential in the first embodiment.

  This circuit includes an operational amplifier (OPAMP), and the value of the reference potential REF1 is applied to VBP.

  FIG. 21 shows a circuit for generating the reference potential REF1.

  The highest voltage applied to REF1 is applied to VHIGH, and the lowest voltage applied to REF1 is applied to VLOW. The voltage is divided by resistors R1 and R2, and the divided potentials are switched to switches SW1, SW2, and SW2. REF1 can be formed by selecting using SW3. For example, when the voltage shown in FIG. 18 is applied, VHIGH is set to 2.0V, VLOW is set to 0V, and in the state 1 of STATE1 in FIG. 18, if the switch is turned on by ON1, 2.0V is applied to REF1, and VBP Becomes 2.0V. In the state 2 of STATE 2 in FIG. 18, when the switch is turned on by ON 2, 1.0 V is applied to REF 1 and the potential of VBP becomes 1.0 V. In the state of STATE3 in FIG. 18, if the switch is turned on by ON3, 0V is applied to REF1, and the potential of VBP becomes 0V.

  Thus, the potential of VBP can be easily generated by using the resistors R1, R2, the switches SW1, SW2, SW3, and OPAMP. With respect to VBN, a potential can be generated with a similar circuit configuration.

  In this example, the voltage is generated using the resistors R1 and R2. However, a potential can also be generated by connecting transistors or the like in series. Further, the switch can be easily configured from a combination of CMOS transistors.

<Eighth Embodiment>
FIG. 23 shows a layout example of logic cells constituting a circuit when a substrate bias is applied.

  In FIG. 23, STCELL is an inverter cell which is an example of a logic cell, BNDWELL is a well boundary, and BBCELL is a cell for supplying power to the substrate. VDD is a high potential power source, and VSS is a low potential power source. VBP is an n-well potential power line that is a substrate of a p-channel MOS transistor, and VBN is a p-well potential power line that is a substrate of an n-channel MOS transistor. BNCON is a well contact for supplying power to the p-well which is the substrate of the n-channel MOS transistor, and BPCON is a well contact for supplying power to the n-well which is the substrate of the p-channel MOS transistor. Legends of metal wiring used for the wiring layer are the same as those in FIG. In this example, the wiring of VBP and VBN is not taken in all the logic cells, but the substrate bias is controlled by arranging several feeding wells BBCELL in the common well with some wells in common. If this configuration is used, it is not necessary to add a wiring for applying a substrate bias in the cell, so that the area overhead can be reduced.

<Ninth Embodiment>
FIG. 24 shows the relationship between the state of Vth and the potential of each node in FIG. 1 in each state.

  As in the fifth embodiment, this example can be applied to a circuit having the configuration shown in FIG. 1 using a thin film BOX / FD-SOI transistor. Since a higher forward back gate bias is possible by using a thin-film BOX • FD-SOI transistor, a forward back gate bias voltage of 2.0 V at the maximum is applied in this example. For example, no substrate bias is applied to the reverse back gate bias state (STATE 1) in the fifth embodiment, and a forward back gate bias voltage of 1.0 V is applied to the state in which the substrate bias is not applied (STATE 2) in the fifth embodiment. Further, a higher 2.0V forward back gate bias voltage is applied to the 1.0V forward back gate bias state (STATE 3) in the fifth embodiment. As a result, Vth can be set lower than in the fifth embodiment, and the operation speed of the circuit can be improved. Therefore, if this example is used in a high-speed circuit such as a CPU, the operation speed of the circuit can be easily improved.

  Although the invention made by the present inventor has been specifically described above, the present invention is not limited thereto, and it goes without saying that various changes can be made without departing from the scope of the invention.

  For example, a combinational circuit sandwiched between flip-flops can be an FPGA.

  In the above description, the case where the invention made mainly by the present inventor is applied to the microcomputer which is the field of use as the background has been described. However, the present invention is not limited to this and is applied to various semiconductor integrated circuits. can do.

1 is a circuit diagram illustrating a configuration example of a main part of a microcomputer as an example of a semiconductor integrated circuit according to the present invention. It is sectional drawing of a MOS transistor. It is a current characteristic diagram of an n-channel MOS transistor of 65 nm process. It is explanatory drawing of distribution of the threshold value (Vth) of a transistor at the time of manufacturing LSI. FIG. 2 is an explanatory diagram of a relationship between a state of Vth and a potential of each node in FIG. 1 in each state. It is layout explanatory drawing of the logic cell which comprises the circuit at the time of applying a substrate bias. It is sectional drawing of the said logic cell. FIG. 7 is an explanatory diagram of a layout when the logic cells shown in FIG. 6 are arranged. It is a flowchart of substrate bias determination. It is layout explanatory drawing of a combinational circuit. It is a circuit diagram of a configuration example of a flip-flop circuit capable of checking whether or not timing constraints are satisfied. FIG. 12 is a waveform diagram for explaining the operation of the circuit shown in FIG. 11. FIG. 12 is another waveform diagram for explaining the operation of the circuit shown in FIG. 11. It is a block diagram of a circuit for controlling a substrate bias. It is sectional drawing of the MOS transistor used by 5th Embodiment. It is sectional drawing of a thin film BOX * FD-SOI transistor in the case of controlling a substrate bias. It is a layout explanatory drawing at the time of arrange | positioning the logic cell which controls a substrate bias. FIG. 2 is an explanatory diagram of a relationship between a state of Vth and a potential of each node in FIG. 1 in each state. It is layout explanatory drawing at the time of using a thin film BOX * FD-SOI transistor. FIG. 5 is a circuit diagram showing another configuration example of a circuit for controlling the VBP potential in the first embodiment. FIG. 21 is a circuit diagram illustrating a configuration example of a circuit that generates a reference potential REF1 used in the circuit illustrated in FIG. 20. 1 is a block diagram illustrating an example of the overall configuration of a microcomputer as an example of a semiconductor integrated circuit according to the present invention. It is layout explanatory drawing of the logic cell which comprises the circuit at the time of applying a substrate bias. FIG. 2 is an explanatory diagram of a relationship between a state of Vth and a potential of each node in FIG. 1 in each state.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 1st adjustment circuit 20 2nd adjustment circuit 100 Threshold adjustment circuit SOC Semiconductor integrated circuit FF1, FF2 Flip-flop LOGIC1 Combination circuit PMOS p channel type MOS transistor NMOS n channel type MOS transistor REG1, REG2 Register VBPCNT, VBNCNT Control circuit BOX Embedded oxide film EOR Exclusive OR

Claims (10)

A first flip-flop capable of storing input data in synchronization with a clock signal;
A combinational circuit for capturing the output signal of the first flip-flop;
A semiconductor integrated circuit comprising a plurality of second flip-flops capable of storing an output signal of the combinational circuit in synchronization with the clock signal,
A semiconductor comprising a threshold adjustment circuit capable of adjusting a threshold voltage of a transistor constituting the combination circuit for each combination circuit sandwiched between the first flip-flop and the second flip-flop. Integrated circuit. The combinational circuit includes a p-channel MOS transistor and an n-channel MOS transistor,
2. The semiconductor integrated circuit according to claim 1, wherein a back gate is commonly connected to each MOS transistor having the same conductivity type. The threshold adjustment circuit includes a first adjustment circuit capable of adjusting a back gate of a p-channel MOS transistor;
2. A semiconductor integrated circuit according to claim 1, further comprising a second adjustment circuit capable of adjusting a back gate of the n-channel MOS transistor. The first adjustment circuit comprises a first register capable of holding the first back gate potential control information for said p-channel type MOS transistor,
Based on the information held in the first register, comprises a first control circuit capable of changing a potential of the back gate of the p-channel type MOS transistor,
The second adjustment circuit includes a second register capable of holding second back gate potential control information for the n-channel MOS transistor,
It said based on the second register holding information, the n-channel type MOS and the second control circuit capable of changing a potential of the back gate of the transistor, comprising a third aspect a semiconductor integrated circuit according. Said first control circuit and the second control circuit, based on the first back-gate voltage control information and the second back gate potential control information selectively the p-channel MOS multiple potential levels different from each other the back gate and the n-channel type MOS to the back gate of the transistor comprises a respective first selector and a second selector capable of supplying claim 4 semiconductor integrated circuit according transistor.   The semiconductor integrated circuit according to claim 1, wherein the combinational circuit forms a data path by the transistor. The transistor forming the combination circuit includes a diffusion layer serving as a source and a drain, the well region, and by an insulating film interposed between the diffusion layer and the well region, the well region is a back gate The semiconductor integrated circuit according to claim 1. The first flip-flop and the second flip-flop circuit, a semiconductor integrated circuit according to claim 1, wherein comprising a decision circuit input signal to enable determination of whether they meet the timing constraints. The combinational circuit includes a power supply cell for supplying power to the back gate,
4. The semiconductor integrated circuit according to claim 3 , wherein said power feeding cells are arranged at a ratio of one to a plurality of logic cells each having a predetermined logic function. When the operation speed of the combinational circuit is faster than the design value, the threshold voltage is raised by supplying a negative bias voltage to the back gate of the transistor by the threshold adjustment circuit. If the speed is slower than the design value, by the threshold adjustment circuit, the semiconductor integrated circuit according to claim 1, wherein the threshold voltage is formed by lowering by the above back gate of the transistor is positive bias voltage is supplied .

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