JP5174479B2 - Level conversion circuit - Google Patents

Description

  The present invention relates to a level conversion circuit for converting the amplitude of a signal, and more particularly to a level conversion circuit configured by using one type of conductive insulated gate field effect transistor.

  Level conversion circuits for converting the voltage level and amplitude of a signal are widely known. For example, Patent Document 1 below discloses a level conversion circuit configured using only transistors of the same conductivity type as transistors. Thus, by arranging the conductivity types of the transistors, the manufacturing process can be simplified and the cost can be reduced.

  The level conversion circuit shown in FIG. 19 of Patent Document 1 is configured such that the initial value of the output is set to a constant level (reset operation) in response to a predetermined reset signal (POR). Thereby, it is possible to stabilize the initial operation of the device in which the level conversion circuit is incorporated. In Patent Document 1, as shown in FIG. 21, a power-on reset circuit that generates a power-on reset signal that is activated during a predetermined period when power is turned on is used as a reset circuit that performs a reset operation.

  Further, as another configuration example of the power-on reset circuit, the one disclosed in Patent Document 2 is also known.

JP 2005-12356 A JP-A 63-246919

  The power-on reset circuit of FIG. 21 of Patent Document 1 is configured by combining a relatively large number of circuits, and requires a considerable circuit occupation area. Therefore, a reset circuit with a small occupation area is desired in the level conversion circuit.

  Further, the level conversion circuit of FIG. 19 of Patent Document 1 is configured using only N-type transistors. In the level conversion circuit, the transistor (6) (hereinafter referred to as “pull-down transistor”) that pulls down the output terminal (node 2) is turned on while the input signal (IN) is at the H level, and the output signal is set to the L level. The Therefore, during the period when the input signal is at the H level, it is necessary to maintain the gate-source voltage above the threshold voltage so that the pull-down transistor is kept on.

  However, in the level conversion circuit, there is a concern that the gate voltage of the pull-down transistor is lowered due to the leakage current of the transistor (200) connected to the gate of the pull-down transistor. Therefore, when the pulse width of the input signal is very wide (H level period is long), the gate-source voltage cannot be maintained above the threshold voltage, and the pull-down transistor is turned off and output. The signal level may be reversed unnecessarily.

  The present invention is intended to solve the above problems, and provides a reset circuit with a small occupation area and a wider pulse width in a level conversion circuit in which only a single conductivity type transistor is used as a transistor. It is an object of the present invention to provide a level conversion circuit that can cope with an input signal having.

The level conversion circuit according to the present invention includes a first power supply and a second power supply, and an input signal having an amplitude smaller than a voltage difference between the first power supply and the second power supply corresponds to the voltage of the first power supply. A level conversion circuit for converting a level between a voltage level to be changed and a voltage level corresponding to the voltage of the second power supply, the input terminal receiving the input signal, and the level-converted signal being output A first output node; a reset terminal that receives a predetermined reset signal; and a gate connected between the first output node and the first power supply and connected to the input terminal via a first capacitive element. A conductive first transistor, a first node connected to a gate of the first transistor, and a first node connected to the first power supply, and a gate connected to the reset terminal via a second capacitor element; A second transistor of a predetermined conductivity type, a first current driving element connected between the second power supply and the first output node, a second node connected to the gate of the second transistor, and the first power supply And a third current driving element connected between the gate of the first transistor and a third power source .

  According to the present invention, all transistors used are of the same conductivity type, which can contribute to simplification of the manufacturing process and cost reduction. An input signal is supplied to the gate of the first transistor for outputting the signal after level conversion through coupling by the first capacitor. Therefore, regardless of the voltage level of the input signal, a signal level-converted to a voltage level corresponding to the first and second power supplies can be output.

  The reset circuit that initializes the first node to a predetermined level has a simple configuration including the second transistor, the second capacitor element, and the second current driving element, and can be formed with a small occupation area.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In addition, in order to avoid duplication and redundant description, elements having the same or corresponding functions are denoted by the same reference symbols in the respective drawings.

  The transistor used in each embodiment is an insulated gate field effect transistor. In the insulated gate field effect transistor, the electric conductivity between the drain region and the source region in the semiconductor layer is controlled by the electric field in the gate insulating film. As a material of the semiconductor layer in which the drain region and the source region are formed, an organic semiconductor such as polysilicon, amorphous silicon, or pentacene, a compound semiconductor such as single crystal silicon or ZnO, or the like can be used.

  As is well known, each transistor has a control electrode (gate (electrode) in the narrow sense), one current electrode (drain (electrode) or source (electrode) in the narrow sense)), and the other current electrode (in the narrow sense, the drain (electrode) or the source (electrode)). In a narrow sense, it is an element having at least three electrodes including a source (electrode) or a drain (electrode). The transistor functions as a switching element in which a channel is formed between the drain and the source by applying a predetermined voltage to the gate. The drain and source of the transistor have basically the same structure, and their names are interchanged depending on the applied voltage condition. For example, in the case of an N-type transistor, an electrode having a relatively high potential is referred to as a drain and a low electrode is referred to as a source (in the case of a P-type transistor, the opposite is true).

  Unless otherwise specified, these transistors may be formed on a semiconductor substrate, or may be a thin film transistor (TFT) formed on an insulating substrate such as glass. The substrate over which the transistor is formed may be a single crystal substrate or an insulating substrate such as SOI, glass, or resin.

  In this specification, “connection” between two elements, between two nodes, or between one element and one node is a connection through other elements (elements, switches, etc.). Will be described as including a state that is substantially equivalent to a direct connection. For example, even if two elements are connected via a switch, if they can function in the same way as when they are directly connected, the two elements are “connected”. Express.

<Embodiment 1>
FIG. 1 is a diagram showing a configuration of a level conversion circuit according to Embodiment 1 of the present invention. In the present embodiment, a level conversion circuit configured using N-type transistors will be described. An N-type transistor is in an active state (on state, conductive state) when the gate is at a high (H) level with respect to the source, and is also in an inactive state (off state, non-conductive state) at a low (L) level. In this embodiment, the signal H level is described as an active level and the L level is described as an inactive level.

  The level conversion circuit of FIG. 1 uses an input signal INS having an H level of the voltage VDD and an L level of the reference voltage GND as a negative voltage VH of which the H level is equal to or higher than the voltage VDD and the L level is lower than the reference voltage GND. The signal is converted into an output signal / OUTS that is a voltage -VL. However, the logical value (high (H) or low (L)) of the output signal / OUTS takes a value obtained by inverting the input signal INS. The voltage VH may be the same voltage as the voltage VDD or a different voltage. That is, this level conversion circuit converts the input signal INS (amplitude: VDD−GND) into an output signal / OUTS (amplitude: VH − (− VL) = VH + VL) having a larger amplitude. The reference voltage GND is a reference level for each voltage, and is usually a ground voltage level.

  As shown in FIG. 1, the level conversion circuit includes transistors Q4A, Q5A, Q6A, resistance elements R1A, R2A, and capacitance elements C1A, C2A. The transistors Q4A, Q5A, Q6A used in this level conversion circuit are all N-type insulated gate field effect transistors.

  Between the high-side power supply (second power supply) node S4 to which the voltage VH is supplied and the low-side power supply (first power supply) node S3 to which the voltage -VL is supplied, the resistance element R1A and the transistor Q4A (first Transistors) are connected in series. In the present embodiment, the connection node N4A (first output node) between the resistance element R1A and the transistor Q4A serves as the output terminal OUT for outputting the output signal / OUTS. That is, the resistor element R1A is connected between the high-side power supply node S4 and the output terminal OUT (node N4A), and the transistor Q4A is connected between the output terminal OUT and the low-side power supply node S3.

  The capacitive element C1A (first capacitive element) is connected between the input terminal IN to which the input signal INS is supplied and the node N1A (first node) to which the gate of the transistor Q4A is connected, and the input terminal IN and the node N1A are connected. Are capacitively coupled.

  Transistor Q5A (third transistor) and transistor Q6A (second transistor) are both connected between node N1A and low-side power supply node S3. However, the gate of the transistor Q5A is connected to the node N4A (output terminal OUT), and the gate of the transistor Q6A is connected to the reset terminal RST to which a predetermined reset signal RSTS is supplied via the capacitive element C2A (second capacitive element). The Capacitance element C2A capacitively couples node N2A (second node) to which the gate of transistor Q6A is connected to reset terminal RST. Resistance element R2A is connected between node N2A and low-side power supply node S3.

  A circuit composed of the capacitive element C2A, the transistor Q6A, and the resistance element R2A constitutes a reset circuit for setting the initial value of the output terminal OUT of the level conversion circuit to a constant value. The reset circuit sets the initial value of the output signal / OUTS to the H level (voltage VH) by turning off the transistor Q4A according to the reset signal RSTS. The resistance element R1A functions as a current driving element that controls a current flowing from the high-side power supply node S4 to the output terminal OUT (node N4A). Similarly, the resistance element R2A generates a current flowing from the node N2A to the low-side power supply node S3. It functions as a current drive element to be controlled. Here, the resistance values of the resistance elements R1A and R2A are defined as R1 and R2, respectively, and the capacitance values of the capacitance elements C1A and C2A are defined as C1 and C2, respectively.

  FIG. 2 is a signal waveform diagram showing an operation of the level conversion circuit shown in FIG. The operation of the level conversion circuit shown in FIG. 1 will be described below with reference to FIG. Here, each of the input signal INS and the reset signal RSTS input to the level conversion circuit is an external circuit (not shown) that is driven by a high-side voltage source of the voltage VDD (a circuit outside the substrate on which the level conversion circuit is formed). The H level is a signal having a voltage VDD and the L level is a signal having a reference voltage GND. The reset signal RSTS is assumed to be a power-on reset signal that is activated (becomes H level) for a certain period immediately after the voltage sources are turned on.

  The time t0 is an initial state immediately after the voltage sources of the voltages VH, -VL, and VDD are turned on, and the input signal INS and the reset signal RSTS at this time are both at the L level (GND).

  Immediately after the voltage source is turned on, the voltage level (potential) of the node N1A of the level conversion circuit is in an indefinite state. For example, in the case where the voltage source is disconnected due to a power failure or the like from the state where each voltage source is supplied, an H level voltage may remain at the node N1A depending on the operating state at the time of disconnection. In that case, the transistor Q4A is turned on when the voltage source is turned on, and the output terminal OUT (output signal / OUTS) becomes L level.

  When the input signal INS changes from the L level to the H level from this state, the voltage level of the node N1A is increased by the amount of the change due to the coupling through the capacitive element C1A, but the level of the transistor Q4A remains unchanged. Since it is kept on, the level of the output terminal OUT does not change from the L level. Subsequently, even if the input signal INS changes from the H level to the L level, the node N1A is lowered by the change amount, but still remains at the H level, and the output signal / OUTS is maintained at the L level. That is, in the level conversion circuit, a malfunction occurs in which the output signal / OUTS does not change according to the input signal INS.

  Here, as shown in FIG. 2, an H level (−VL + VXH) is assumed as the level of the initial state of the node N1A. Therefore, at time t0, the transistor Q4A is on, and the output terminal OUT (output signal / OUTS) becomes L level. Note that the L level voltage of the output signal / OUTS at this time is −VL + ΔVL1. Voltage ΔVL1 is an output offset voltage determined by the ratio of the on-resistance of resistance element R1A and transistor Q4A.

  Since the output terminal OUT is at the L level, the transistor Q5A is off. Further, since the node N2A becomes L level (−VL) through the resistance element R2A, the transistor Q6A is also turned off.

  At time t1, when the reset signal RSTS changes from the L level (GND) to the H level (VDD), this voltage change is transmitted to the gate (node N2A) of the transistor Q6A via the capacitive element C2A. The node N2A has a parasitic capacitance including the gate capacitance and wiring capacitance of the transistor Q6A, and the parasitic capacitance functions to suppress a voltage change of the node N2A at this time. In the present embodiment, the capacitance value C2 of the capacitive element C2A is set sufficiently large with respect to the parasitic capacitance, and the voltage change at the node N2A at time t1 is VDD as is the voltage change of the reset signal RSTS. To do. That is, at time t1, the voltage at the node N2A rises from −VL by VDD to VDD−VL.

  When the voltage at the node N2A rises, the gate-source voltage of the transistor Q6A becomes VDD. Then, transistor Q6A is turned on (the threshold voltage of transistor Q6A is set sufficiently lower than voltage VDD), and node N1A is initialized to the L level. Accordingly, the transistor Q4A is turned off, the output terminal OUT is charged from the high-side power supply node S4 via the resistance element R1A, and the initial value of the output signal / OUTS becomes the H level (VH). When the output signal / OUTS becomes H level, the transistor Q5A is turned on, and the node N1A is set to L level with low impedance together with the transistor Q6A.

  As described above, in the level conversion circuit according to the present embodiment, immediately after the voltage source is turned on, the reset circuit including the capacitive element C2A, the resistive element R2A, and the transistor Q6A sets the node N1A to the L level according to the reset signal RSTS. As a result, the reset operation for initializing the output signal / OUTS to the H level is performed, so that the problem of malfunction described above is solved.

  In the reset circuit, the reset signal RSTS is supplied to the gate of the transistor Q6A that initializes the level of the node N1A through capacitive coupling by the capacitive element C2A. Therefore, the reset operation is performed regardless of the voltage level of the reset signal RSTS. It can be performed. Therefore, a signal supplied from the outside can easily correspond to the reset signal RSTS. Since the reset circuit has a simple configuration including the capacitive element C2A, the resistive element R2A, and the transistor Q6A, it can be realized with a small occupation area.

  Referring to FIG. 2 again, when the voltage level of node N2A rises from −VL at time t1, node N2A is discharged through resistance element R2A, but resistance element R2A has a high resistance value. It functions as a current limiting element that limits the current flowing from the node N2A to the low-side power supply node S3. Therefore, the time constant determined by the product of the resistance value R2 of the resistance element R2A and the capacitance value C2 of the capacitance element C2A is sufficiently larger than the active period (period of H level) of the reset signal RSTS, and the voltage of the node N2A The level gradually decreases from VDD-VL according to its time constant.

  When reset signal RSTS changes from H level (VDD) to L level (GND) at time t2, this voltage change is transmitted to node N2A via capacitive element C2A, and the voltage level of node N2A decreases by VDD. As shown in FIG. 2, if the voltage level of the node N2A at the time t2 has decreased by the voltage ΔVH from the time t1, the voltage level of the node N2A becomes lower than −VL accordingly, and −VL−ΔVH L level. As a result, the transistor Q6A is turned off, but since the transistor Q5A is turned on, the node N1A continues to be at the L level (−VL) with low impedance.

  After time t2, the level of the node N2A gradually increases toward the voltage −VL according to the time constant determined by the resistance element R2A and the capacitance element C2A.

  At time t3, when the input signal INS changes from the L level (GND) to the H level (VDD), this voltage change is transmitted to the node N1A via the capacitive element C1A. Node N1A has a parasitic capacitance such as a gate capacitance and a wiring capacitance of transistor Q4A, which acts to suppress a voltage change at node N1A. Here, it is assumed that the capacitance value C1 of the capacitive element C1A is set to be sufficiently larger than the parasitic capacitance, and the voltage change of the node N1A is VDD as is the voltage change of the input signal INS. That is, the voltage at the node N1A rises from −VL by VDD to VDD−VL.

  When the voltage at the node N1A rises to VDD-VL, the gate-source voltage of the transistor Q4A becomes VDD. Then, the transistor Q4A is turned on (the threshold voltage of the transistor Q4A is set sufficiently lower than the voltage VDD), and the voltage level of the output terminal OUT (output signal / OUTS) is lowered to −VL + ΔVL2 and becomes the L level. . Here, voltage ΔVL2 is an output offset voltage determined by the ratio of the on-resistance of resistance element R1A and transistor Q4A.

  The difference between the output offset voltage ΔVL1 at time t1 and the output offset voltage ΔVL2 at time t3 is due to the difference in voltage level of the gate (node N1A) of the transistor Q4A. Usually, since VXH ≦ VDD, a relationship of ΔVL1 ≧ ΔVL2 is established.

  When the input signal INS changes from the H level (VDD) to the L level (GND) at time t4, this voltage change is transmitted to the node N1A through the capacitive element C1A, and the voltage level of the node N1A decreases by VDD. . As a result, the transistor Q4A is turned off, the output terminal OUT is charged through the resistance element R1A, and the output signal / OUTS becomes H level (VH) again.

  Thereafter, every time the input signal INS becomes the H level (VDD), the operations from the time t3 to the time t4 are repeated.

  The level conversion circuit of the present embodiment can convert the input signal INS that changes between the voltages VDD and GND into the output signal / OUTS that changes between the voltage VH and the voltage −VL + ΔVL2 by the above operation. . The value of the voltage ΔVL2 needs to be set to such a small value that the L level (−VL + ΔVL2) of the output signal / OUTS falls below the input logic threshold level of the next stage circuit of the level conversion circuit. The value of voltage ΔVL2 is determined by the value of channel resistance when the gate-source voltage of transistor Q4A is VDD and the resistance value R1 of resistance element R1A. By appropriately setting these parameters, the voltage ΔVL2 can be made sufficiently small.

  Here, the resistance value of the resistance element R1A is preferably large as long as a sufficient rising speed of the output signal / OUTS can be obtained. When the resistance value of resistance element R1A is small, it is necessary to further reduce the on-resistance of transistor Q4A in order to reduce voltage ΔVL2, and therefore, when outputting L level output signal / OUTS, resistance element R1A and transistor Q4A This is because a problem arises that the through current flowing through the channel increases and the power consumption increases. That is, it is desirable that the resistance element R1A functions as a current limiting element for the purpose of reducing the voltage ΔVL2 and reducing power consumption.

[Modification 1]
In the above description, an example in which the reset signal RSTS generated by the external circuit is input to the reset terminal RST of the level conversion circuit has been described. In the first modification, the reset signal RSTS is generated by an internal circuit (a circuit on the same substrate as the level conversion circuit) as shown in FIG.

  FIG. 3 schematically shows a power-on reset circuit POR that generates the reset signal RSTS. The power-on reset circuit POR in FIG. 3 outputs a single pulse (power-on reset signal) as the reset signal RSTS when the voltage source VH is turned on. That is, as shown in FIG. 4, the reset signal RSTS is activated (becomes H level) almost simultaneously with the rise of the voltage source of the voltage VH, and deactivated (becomes L level) after a predetermined time. Is a single pulse.

  That is, the reset signal RSTS output from the power-on reset circuit POR in FIG. 3 is at the L level of the reference voltage GND before the voltage source of the voltage VH is turned on, and when the voltage source of the voltage VH is turned on (the power supply level is stable or reaches a predetermined level). Change to H level of the voltage VH. When a certain time has elapsed, the reset signal RSTS returns to the L level of the reference voltage GND, and maintains the L level in the subsequent steady state.

  For example, FIG. 1 of Patent Document 2 discloses an example of a power-on reset circuit that is driven by one high-side voltage source and one low-side voltage source and can be configured using transistors of the same conductivity type. Yes. In the circuit of FIG. 1, two N-type transistors and four inverters are shown. As the inverters, for example, an inverter in which both the driver element and the load element are N-type transistors, or the driver element is N If an inverter in which a type transistor and a load element are constituted by resistance elements is employed, the conductivity type of the transistor constituting the power-on reset circuit can be made only N type.

  If the voltage VH is used as the high-side power supply voltage and the reference voltage GND is used as the low-side power supply voltage, the power-on reset circuit POR shown in FIG. 3 can be realized using the circuit shown in FIG. In particular, if a resistive element is used as the load element of the inverter in the output stage of the circuit of FIG. 1 of Patent Document 2 (inverter 14 in FIG. 1 of Patent Document 2), the H level is the voltage VH and the L level is the reference voltage GND. A power-on reset signal (reset terminal RST) as shown in FIG. 4 can be obtained.

  As described above, if a circuit configured using only N-type transistors is employed as the power-on reset circuit POR in FIG. 3, the same level conversion circuit as illustrated in FIG. The advantage is that the process for forming it becomes easier.

  Also in this modification, the operation of the level conversion circuit shown in FIG. 1 is the same as that described with reference to FIG. That is, in the level conversion circuit, when the voltage source is turned on (time t1), the transistor Q6A is turned on according to the reset signal RSTS generated by the internal circuit, and the node N1A is initialized to the voltage −VL. As a result, the transistor Q4A is turned off, and the initial value of the output signal / OUTS of the level conversion circuit becomes H level (VH).

  As described above, the malfunction caused by the unstable level of the node N1A when the voltage source is turned on by the reset operation for appropriately initializing the levels of the node N1A and the output terminal OUT (output signal / OUTS) of the level conversion circuit. Can solve the problem.

  In the circuit shown in FIG. 1 of Patent Document 2, the voltage VDD may be used as the high-side power supply voltage of the inverter that outputs the power-on reset signal. In this case, the H level as shown in FIG. A power-on reset signal (reset terminal RST) of VDD can be obtained.

[Modification 2]
As described above, the resistance element R1A of the level conversion circuit of FIG. 1 functions as a current driving element that controls the current flowing from the high-side power supply node S4 to the output terminal OUT (node N4A), and similarly the resistance element R2A. Functions as a current driving element for controlling the current flowing from the node N2A to the low-side power supply node S3.

  FIG. 5 is a broad circuit diagram in which the resistance elements R1A and R2A in the circuit diagram of FIG. 1 are replaced with functional blocks of the current drive elements I1A and I2A (first and second current drive elements), respectively. The current driving elements I1A and I2A may be configured using elements other than the resistance elements as long as they have current driving power (capability of flowing current) of the same level as the resistance elements R1A and R2A in FIG. Good. Here again, the current driving element I2A functions as a current limiting element that limits the current flowing from the node N2A to the low-side power supply node S3.

  For example, as shown in FIG. 6A, as a current driving element I1A connected between the high-side power supply node S4 and the output terminal OUT (node N4A), a constant current source CS1A having a current driving capability comparable to that of the resistance element R1A. May be used. When the constant current source CS1A is used as the current driving element I1A, the rising speed of the output signal / OUTS (charging speed of the output terminal OUT) can be accurately set by adjusting the driving current of the constant current source CS1A. In this case, the L level of the output signal / OUTS is determined according to the current flowing through the constant current source CS1A and the on-resistance of the transistor Q4A.

  Similarly, as the current driving element I2A connected between the node N2A and the low-side power supply node S3, as shown in FIG. 6B, a constant current source CS2A having a current driving capability comparable to that of the resistance element R2A is used. Also good. When the constant current source CS2A is used as the current drive element I2A, the discharge speed of the node N1A can be accurately set by adjusting the drive current of the constant current source CS2A. If the drive current amount of the constant current source CS2A is made sufficiently small, the voltage drop amount ΔVH (see FIG. 2) of the node N2A can be made sufficiently small.

[Modification 3]
In this modification, an example in which N-type transistors are used as the current driving elements I1A and I2A is shown. That is, as the current driving element I1A, as shown in FIG. 7A, a transistor Q1A having a gate and a drain connected to the high-side power supply node S4 and a source connected to the output terminal OUT (node N4A) is used. That is, the transistor Q1A is diode-connected and operates in a resistance mode (the on-resistance functions as a resistance element). The on-resistance is set to the same level as the resistance element R1A in FIG. In this case, the L level of output signal / OUTS is determined by the on-resistance ratio of transistors Q1A and Q4A.

  Similarly, as the current driving element I2A, as shown in FIG. 7B, a transistor Q2A having a gate and a source connected to the node N2A and a drain connected to the low-side power supply node S3 is used. That is, the transistor Q2A is diode-connected and operates in a resistance mode. The on-resistance of transistor Q2A is set to the same level as resistance element R2A in FIG.

  As the current driving element I2A, as shown in FIG. 7C, a transistor Q2A having a source connected to the node N2A and a drain connected to the low-side power supply node S3 is used, and the reference is supplied to the reference voltage GND. You may connect with power supply node S1. Also in this case, the on-resistance of the transistor Q2A is set to be approximately the same as that of the resistance element R2A in FIG. 1, and the transistor Q2A operates in the resistance mode, but operates in the non-saturated region. In the example of FIG. 7C, since the voltage at which the transistor Q2A is turned on may be supplied to the gate of the transistor Q2A, for example, the voltage VDD or the voltage VH is supplied instead of the reference voltage GND. May be.

  In this way, by configuring the current driving elements I1A and I2A with transistors having limited driving capability, it is possible to realize the current driving elements I1A and I2A having a small occupation area. In addition, since the current driving elements I1A and I2A are composed of the same N-type transistors as the other transistors Q4A, Q5A, and Q6A, they can be formed by the same process, and the number of manufacturing steps can be reduced.

  As described above, according to the first embodiment, in the level conversion circuit configured using only N-type transistors as the transistors, the reset operation can be performed by the reset circuit having a small occupation area.

<Embodiment 2>
In the second embodiment, a level conversion circuit according to the present invention configured using P-type transistors will be described. The P-type transistor is in an active state (on state, conductive state) when the gate is at the L level with respect to the source, and is also in an inactive state (off state, inactive state) at the H level. The description will be made assuming that the L level of the signal is the active level and the H level is the inactive level.

  FIG. 8 is a diagram showing a configuration of the level conversion circuit according to the second embodiment. This level conversion circuit converts an input signal INS whose H level is the voltage VDD and L level is the reference voltage GND into an output signal / OUTS whose H level is the voltage VHG and L level is the voltage VLW. . The voltage VHG is higher than the voltage VDD. The voltage VLW may be the same as the reference voltage GND, higher than the reference voltage GND, or lower than the reference voltage GND, but the amplitude of the output signal / OUTS (VHG−VLG) is the amplitude of the input signal INS. It is set to be larger than (VDD-GND). In actual use, the voltage VLW is set to be the same as the low-side voltage level (voltage −VL) when an N-type transistor is used.

  As shown in FIG. 8, the level conversion circuit includes transistors Q4B, Q5B, and Q6B, capacitive elements C1B and C2B, and current drive elements I1B and I2B. The transistors Q4B, Q5B, Q6B used in this level conversion circuit are all P-type insulated gate field effect transistors.

  The current drive elements I1B and I2B may have any predetermined current drive capability as in the case of the current drive elements I1A and I2A of the first embodiment, and operate in, for example, a resistance element, a constant current source, and a resistance mode. A p-type transistor or the like can be used.

  Between the low-side power supply (second power supply) node S5 supplied with the voltage VLW and the high-side power supply (first power supply) node S6 supplied with the voltage VLG, the current drive element I1B (first current drive element) ) And transistor Q4B (first transistor) are connected in series. In the present embodiment, the connection node N4B (first output node) between the current drive element I1B and the transistor Q4B serves as the output terminal OUT for outputting the output signal / OUTS. That is, the current driver I1B is connected between the low-side power supply node S5 and the output terminal OUT (node N4B), and the transistor Q4B is connected between the output terminal OUT and the high-side power supply node S6.

  The capacitive element C1B (first capacitive element) is connected between the input terminal IN to which the input signal INS is input and a node N1B (first node) to which the gate of the transistor Q4B is connected, and the input terminal IN and the node N1B Capacitive coupling between the two.

  Transistors Q5B and Q6B are both connected between node N1B and high-side power supply node S6, but the gate of transistor Q5B (third transistor) is connected to output terminal OUT (node N4B), and transistor Q6B (second transistor). Is connected to a reset terminal RST to which a predetermined reset signal RSTS is input via a capacitive element C2B (second capacitive element). That is, the capacitive element C2B capacitively couples the node (node N2B) connected to the gate of the transistor Q6B and the reset terminal RST. Current drive element I2B (second current drive element) is connected between node N2B and high-side power supply node S6.

  A circuit including the capacitive element C2B, the transistor Q6B, and the current driving element I2B functions as a reset circuit that performs a reset operation that initializes the levels of the node N1B and the output terminal OUT. That is, the reset circuit sets the output signal / OUTS to the L level (VLW) by setting the node N1B to the H level according to the reset signal RSTS and turning off the transistor Q4B.

  FIG. 9 is a signal waveform diagram showing an operation of the level conversion circuit shown in FIG. The operation of the level conversion circuit shown in FIG. 8 will be described below with reference to FIG. Here, each of the input signal INS and the reset signal RSTS input to the level conversion circuit is generated by an external circuit (not shown) driven by a high-side voltage source of the voltage VDD. That is, the input signal INS and the reset signal RSTS are signals whose H level is the voltage VDD and L level is the reference voltage GND, respectively. The reset signal RSTS is a power-on reset signal that is activated (becomes L level) for a certain period immediately after the voltage sources are turned on.

  The time t10 is an initial state immediately after the voltage sources of the voltages VHG, VLW, and VDD are turned on, and the input signal INS and the reset signal RSTS at this time are both at the H level (VDD). Further, an L level (voltage VXL) is assumed as the initial state level of the node N1B. Therefore, at time t10, the transistor Q4B is on and the output terminal OUT (output signal / OUTS) is at the H level. Note that the H level voltage of the output signal / OUTS at this time is VHG + ΔVH1. Voltage ΔVH1 is an output offset voltage determined by the current flowing through current driving element I1B and the on-resistance of transistor Q4B.

  Since the output terminal OUT is at the H level, the transistor Q5B is off. Further, since the node N2B is charged through the current driving element I2B and becomes H level (VHG), the transistor Q6B is also turned off.

  At time t11, when the reset signal RSTS changes from H level (VDD) to L level (GND), this voltage change is transmitted to the gate (node N2B) of the transistor Q6B through the capacitive element C2B. The node N2B has a parasitic capacitance including the gate capacitance and the wiring capacitance of the transistor Q6B, and the parasitic capacitance works to suppress the voltage change of the node N2B at this time. In the present embodiment, the capacitance value C2 of the capacitive element C2B is set sufficiently large with respect to the parasitic capacitance, and the voltage change at the node N2B at time t11 is VDD as is the voltage change of the reset signal RSTS. To do. In other words, at time t11, the voltage at the node N2B decreases from VHG by VDD to VHG-VDD.

  When the voltage at the node N2B decreases in this way, the gate-source voltage of the transistor Q6B becomes VDD. Then, transistor Q6B is turned on (the threshold voltage of transistor Q6B is set sufficiently smaller than voltage VDD), and node N1B is initialized to the H level. Responsively, transistor Q4B is turned off, output terminal OUT is discharged to low-side power supply node S5 via current drive element I1B, and the initial value of output signal / OUTS becomes L level (VHG-VLW).

  Thus, in the level conversion circuit of the present embodiment, the node N1B can be initialized to the H level and the output signal / OUTS can be initialized to the L level immediately after the voltage source is turned on. A malfunction due to the unstable level of the node N1B is prevented.

  Further, when the output signal / OUTS becomes L level, the transistor Q5B is turned on, and the node N1B is set to the low impedance H level together with the transistor Q6B.

  Note that when the voltage level of the node N2B falls from VHG at time t11, the node N2B is charged through the current driving element I2B, but the time constant determined by the current driving element I2B and the capacitive element C2B is the reset signal RSTS. If it is set to be sufficiently larger than the active period (period when it becomes L level), the voltage level of the node N2B rises little by little from VHG-VDD according to its time constant.

  When reset signal RSTS changes from L level (GND) to H level (VDD) at time t12, this voltage change is transmitted to node N2B via capacitive element C2B, and the voltage level of node N2B rises by VDD. As shown in FIG. 9, if the voltage level of the node N2B at time t12 has increased by the voltage ΔVL from time t11, the voltage level of the node N2B becomes higher than VHG correspondingly and becomes the H level of VHG + ΔVL. . As a result, the transistor Q6B is turned off. However, since the transistor Q5B is turned on, the node N1B is continuously at the low impedance H level (VHG).

  After time t12, the level of the node N2B gradually decreases toward the voltage VLG according to the time constant determined by the current driving element I2B and the capacitive element C2B.

  At time t13, when the input signal INS changes from the H level (VDD) to the L level (GND), this voltage change is transmitted to the node N1B via the capacitive element C1B. Node N1B has parasitic capacitances such as the gate capacitance and wiring capacitance of transistor Q4B, and this acts to suppress voltage change at node N1B. However, here, it is assumed that the capacitance value C1 of the capacitive element C1B is set to be sufficiently larger than the parasitic capacitance, and the voltage change of the node N1B is VDD as is the voltage change of the input signal INS. That is, the voltage at the node N1B drops from VHG by VDD to VHG-VDD.

  When the voltage at the node N1B decreases in this way, the gate-source voltage of the transistor Q4B becomes VDD. Then, the transistor Q4B is turned on (the threshold voltage of the transistor Q4B is set sufficiently smaller than the voltage VDD), and the voltage level of the output terminal OUT (output signal / OUTS) rises to VHG−ΔVH2 and becomes H level. Become. Voltage ΔVH2 is an output offset voltage determined by the current flowing through current drive element I1B and the on-resistance of transistor Q4B.

  The difference between the output offset voltage ΔVH1 at time t11 and the output offset voltage ΔVH2 at time t13 is due to the difference in voltage level of the gate (node N1B) of the transistor Q4B. Usually, VXL ≦ VDD, so that ΔVH1 ≧ ΔVH2.

  When the input signal INS rises from the L level (GND) to the H level (VDD) at time t14, this voltage change is transmitted to the node N1B via the capacitive element C1B, and the voltage level of the node N1B rises by VDD. . As a result, the transistor Q4B is turned off, the output terminal OUT is discharged by the current drive element I1B, and the output signal / OUTS becomes L level (VLW) again.

  Thereafter, each time the input signal INS becomes L level (GND), the operations from the time t13 to the time t14 are repeated.

  Through the above operation, the level conversion circuit of the present embodiment can convert the input signal INS that changes between the voltages VDD and GND into the output signal / OUTS that changes between the voltage VHG−ΔVH2 and the voltage VLW. . In particular, if the output signal / OUTS sufficiently changes to the high side and the low side so as to straddle the input logic threshold value of the next stage circuit of the level conversion circuit, the level conversion circuit converts the level of the high level voltage. Can be used.

  In the level conversion circuit according to the present embodiment, the gate voltage of the transistor Q4B for setting the output signal / OUTS to the H level is changed according to the input signal INS using capacitive coupling via the capacitive element C1B. According to this configuration, it is possible to generate the output signal / OUTS having an H level voltage (VH) higher than the H level voltage (VDD) of the input signal INS using only a P-type transistor as a transistor. Similarly to the first embodiment, the reset operation for setting initial values of node N1B and output signal / OUTS can be performed by a reset circuit having a small occupation area.

<Embodiment 3>
In the level conversion circuit of the first embodiment shown in FIG. 5, when the output terminal OUT (node N4A) is at the L level according to the H level of the input signal INS, the transistor Q4A is kept on. Node N1A is at H level. At this time, the transistors Q5A and Q6A are in the off state, and the node N1A is in the high impedance state. Meanwhile, the charge at the node N1A is gradually discharged by the leak current (off leak current) between the drain and source of the transistors Q5A and Q6A.

  Therefore, when the H level period of the input signal INS (the period between the time t3 and the time t4 in FIG. 2) becomes longer, the level of the node N1A becomes the inverter circuit (the current drive element I1A is loaded by the current drive element I1A). It is conceivable that the threshold voltage of the device, transistor Q4A, becomes a drive device). If so, a malfunction occurs in which the output level is inverted unnecessarily and becomes H level. This phenomenon becomes more prominent because the off-leak current of the transistor Q5A increases as the output offset voltage ΔVL2 in FIG. 2 increases.

  FIG. 10 is a diagram showing the configuration of the level conversion circuit according to the third embodiment of the present invention. The level conversion circuit of FIG. 10 is obtained by adding a push-pull circuit 1A for suppressing the leakage current of the transistor Q5A to the circuit of FIG.

  As shown in FIG. 10, the push-pull circuit 1A includes N-type transistors Q8A and Q9A connected in series between the high-side power supply node S4D and the low-side power supply node S3, and a connection node between the transistors Q8A and Q9A. (Node N5A) is an output node of the push-pull circuit 1A. Transistor Q5A has its gate connected to node N5A. The gate of the transistor Q8A (fifth transistor) connected between the node N5A and the high-side power supply node S4D is connected to the node N4A (output terminal OUT). The gate of the transistor Q9A (fourth transistor) connected between the node N5A and the low-side power supply node S3 is connected to the node N1A.

  The voltage VHA supplied to the high-side power supply node S4D may be any voltage that can turn it on when supplied to the gate of the transistor Q5A. For example, the voltage VH, VDD or the reference voltage GND is used. Can be used.

  The operation of the level conversion circuit of FIG. 10 is basically the same as that of the circuit of FIG. 5 except that the transistor Q5A is driven not by the output signal / OUTS but by the output signal of the push-pull circuit 1A (voltage signal of the node N5A). Since it is the same as the operation (FIG. 2), detailed description is omitted, and here, the operation of the push-pull circuit 1A and the transistor Q5A will be described.

  As described above, since the current driving element I1A and the transistor Q4A constitute an inverter circuit, the node N1A and the output terminal OUT (node N4A) are at opposite levels. When the node N1A is at the H level, the transistor Q4A is turned on, so that the output terminal OUT is at the L level of the voltage −VL + ΔVL2. In this case, in the push-pull circuit 1A, the transistor Q8A is turned off and the transistor Q9A is turned on. Since no current flows from node Q5A into node N5A, node N5A is at the L level of voltage -VL. That is, the gate voltage when the transistor Q5A is off is reduced by the offset voltage ΔVL2 compared to the case of FIG. 5, and the off-leak current can be reduced.

  When the node N1A is at L level, the transistor Q4A is turned off and the output terminal OUT becomes H level of the voltage VH. In this case, in the push-pull circuit 1A, the transistor Q8A is turned on and the transistor Q9A is turned off. Therefore, the node N5A becomes the H level of the voltage VHA, the transistor Q5A is turned on, and the node N1A is set to the L level of low impedance.

  Thus, according to the level conversion circuit of the third embodiment, the offset voltage (ΔVL2 in FIG. 2) applied to the gate of the transistor Q5A while the transistor Q5A is off can be eliminated. Therefore, the off-leakage current of the transistor Q5A can be reduced and the H level of the node N1A can be maintained for a long period of time, so that it is possible to prevent malfunction when level conversion is performed on the input signal INS having a wide pulse width. Since the push-pull circuit 1A is composed of only N-type transistors, the conductivity type of the transistors constituting the level conversion circuit is only N-type as in the case of the first embodiment. This can contribute to cost reduction.

<Embodiment 4>
The problem that occurs when the active period of the input signal INS becomes longer in the level conversion circuit of the first embodiment also occurs in the level conversion circuit (FIG. 8) of the second embodiment.

  That is, in the level conversion circuit of the second embodiment shown in FIG. 8, the transistor Q4B is kept on when the output terminal OUT (node N4B) is at the H level according to the L level of the input signal INS. Therefore, the node N1B is at the L level. At this time, the transistors Q5B and Q6B are in an off state, and the node N1B is in a high impedance state. Meanwhile, the node N1B is gradually charged by the off-leak current between the drain and source of the transistors Q5B and Q6B.

  Therefore, when the L level period of the input signal INS (the interval between the time t13 and the time t14 in FIG. 9) becomes longer, the voltage difference between the high-side power supply node S6 and the node N1B is different between the current driving element I1B and the transistor Q4B. It can be considered that the voltage is smaller than the threshold voltage of the inverter circuit (current drive element I1B is a load element and transistor Q4B is a drive element). If this happens, a malfunction occurs in which the output level is inverted unnecessarily and becomes L level. This phenomenon becomes more conspicuous because the off-leakage current of the transistor Q5B increases as the output offset voltage ΔVH2 in FIG. 2 increases.

  FIG. 11 is a diagram showing a configuration of a level conversion circuit according to the fourth embodiment of the present invention. The level conversion circuit of FIG. 11 is obtained by adding a push-pull circuit 1B for suppressing the leakage current of the transistor Q5B to the circuit of FIG.

  As shown in FIG. 11, the push-pull circuit 1B includes P-type transistors Q8B and Q9B connected in series between the low-side power supply node S5D and the high-side power supply node S6, and a connection node between the transistors Q8B and Q9B. N5B is an output node of the push-pull circuit 1B. Transistor Q5B has its gate connected to node N5B. The gate of the transistor Q8B (fifth transistor) connected between the node N5B and the low-side power supply node S5D is connected to the node N4B (output terminal OUT). The gate of the transistor Q9B (fourth transistor) connected between the node N5B and the high-side power supply node S6 is connected to the node N1B.

  The voltage VLA supplied to the low-side power supply node S5D may be any voltage that can turn it on when supplied to the gate of the transistor Q5B. For example, the voltage VDD, VLW, or the reference voltage GND is used. Can be used.

  The operation of the level conversion circuit of FIG. 11 is basically the same as that of the circuit of FIG. 8 except that the transistor Q5B is driven not by the output signal / OUTS but by the output signal of the push-pull circuit 1B (voltage signal of the node N5B). Since it is the same as the operation (FIG. 9), detailed description is omitted, and here, the operation of the push-pull circuit 1B and the transistor Q5B will be described.

  As described above, since the current driving element I1B and the transistor Q4B form an inverter circuit, the node N1B and the output terminal OUT (node N4B) are at opposite levels. When the node N1B is at L level, the transistor Q4B is turned on and the output terminal OUT becomes H level of the voltage VHG−ΔVH2. In this case, in the push-pull circuit 1B, the transistor Q8B is turned off and the transistor Q9B is turned on. At this time, no current flows through transistor Q8B, so node N5B is at the H level of voltage VHG. That is, the gate voltage when the transistor Q5B is off is higher by the offset voltage ΔVH2 than in the case of FIG. 8, and the off-leak current can be reduced.

  When node N1B is at H level, transistor Q4B is turned off and output terminal OUT is at L level of voltage VLW. In this case, in the push-pull circuit 1A, the transistor Q8B is turned on and the transistor Q9B is turned off. Therefore, the node N5B becomes the L level of the voltage VLA, the transistor Q5B is turned on, and the node N1B is set to the H level of low impedance.

  Thus, according to the level conversion circuit of the fourth embodiment, the offset voltage (ΔVH2 in FIG. 9) applied to the gate of the transistor Q5B while the transistor Q5B is off can be eliminated. Therefore, the off-leakage current of the transistor Q5B can be reduced and the L level of the node N1B can be maintained for a long period of time, so that it is possible to prevent malfunction when level conversion is performed on the input signal INS having a wide pulse width. In the push-pull circuit 1B, the push-pull circuit 1B is composed only of P-type transistors, so that the conductivity type of the transistors constituting the level conversion circuit is only P-type, as in the second embodiment. Contributes to simplification of manufacturing process and cost reduction.

<Embodiment 5>
FIG. 12 is a diagram showing a configuration of a level conversion circuit according to the fifth embodiment of the present invention. The level conversion circuit has a current driving element I3A (third current driving element) connected between a high-side power supply (third power supply) node S7 and a node N1A to which a predetermined voltage VHD is supplied, with respect to the circuit of FIG. ) Is provided.

  When a leak current is generated between the drain and source of the transistors Q5A and Q6A in FIG. 5, the voltage level of the node N1A is increased when the pulse width of the input signal INS (interval between time t3 and time t4 in FIG. 2) is increased. As described in the third embodiment, the inverter circuit composed of the current driving element I1A and the transistor Q4A is likely to malfunction. In the level conversion circuit of the present embodiment, the current driving element I3A supplies electric charge to the node N1A so as to compensate for the leakage current of the transistors Q5A and Q6A, thereby preventing the level of the node N1A from being lowered and causing the malfunction. The problem is solved.

  The basic operation of the level conversion circuit of FIG. 12 is the same as the operation of the circuit of FIG. 5 (FIG. 2), and detailed description thereof is omitted. However, in the level conversion circuit, the input signal INS is at the H level. When the transistors Q5A and Q6A are turned off, the voltage level of the node N1A approaches VHD. If the voltage VHD is too high, the voltage level of the node N1A will not return to the L level when the input signal INS next changes to the L level, and the output of the inverter circuit composed of the current drive element I1A and the transistor Q4A cannot be inverted. Therefore, the voltage VHD is set so as to satisfy the conditions described below.

That is, the value of the voltage VHD is such that when the voltage of the node N1A is VHD and the input signal INS changes from the H level to the L level, the level of the node N1A is the threshold of the inverter composed of the current drive element I1A and the transistor Q4A. Must be set below the value voltage level. In the circuit of FIG. 12, if the threshold voltage of the inverter circuit composed of the current drive element I1A and the transistor Q4A is VTN, the amplitude of the input terminal INS is VDD, and the parasitic capacitance of the node N1A can be ignored, the following equation (1 ) Must be satisfied.
VHD-VDD <VTN-VL (1)
By transforming this equation (1),
VHD <VDD + VTN−VL (2)
And can.

  That is, the voltage VHD is the sum (VTN + VDD) of the threshold voltage of the inverter circuit composed of the current driving element I1A and the transistor Q4A and the amplitude of the input signal INS when the low-side power supply node S3 (−VL) is used as a reference. Need to be set lower.

At the same time, voltage VHD needs to be at a level that can maintain the output of the inverter circuit composed of current drive element I1A and transistor Q4A inactive (L level) when applied to node N1A. That is, the voltage VHD needs to satisfy the following equation (3).
VHD> VTN-VL (3)

That is, voltage VHD needs to be set higher than the threshold voltage of the inverter circuit composed of current drive element I1A and transistor Q4A when the low-side power supply node S3 is used as a reference. Summarizing the above equations (2) and (3), the condition that the voltage VHD should satisfy is the following equation (4).
VTN−VL <VHD <VDD + VTN−VL (4)

  Since the leakage current between the drain and source of the transistors Q5A and Q6A is very small, the current driving element I3A may have a small current driving capability. On the contrary, if the current driving capability of the current driving element I3A is larger than necessary, when the transistor Q5A or the transistor Q6A is turned on, the L level voltage of the node N1A is increased, so that the operation margin is reduced and the power consumption is reduced. Problems such as increase occur. Therefore, it is desirable that the current driving capability of the current driving element I3A be small as long as the leakage current of the transistors Q5A and Q6A can be compensated. That is, the current driving element I3A is a current limiting element that limits the current flowing from the high-side power supply node S7 to the node N1A.

  Hereinafter, a specific configuration as a modification of the current driving element I3A illustrated in FIG. 12 will be described.

[Modification 1]
The current driving element I3A can be a resistance element R3A as shown in FIG. In the figure, the resistance element R3A has a current driving capability that can compensate for the leakage currents of the transistors Q5A and Q5B, and a voltage that satisfies the above equation (4) is supplied as the power supply VHD.

[Modification 2]
Further, the current driving element I3A can also be configured by a constant current source CS3A as shown in FIG. In the figure, the constant current source CS3A has a current driving capability that can compensate for the leakage currents of the transistors Q5A and Q5B, and a voltage that satisfies the above equation (4) is supplied as the power supply VHD.

[Modification 3]
Further, as shown in FIG. 13C, the current driving element I3A can also be configured using an N-type transistor Q3A that operates in a resistance mode (an on-resistance functions as a resistance element). In the figure, the transistor Q3A has a current driving capability sufficient to compensate for the leakage currents of the transistors Q5A and Q5B, and a voltage satisfying the above equation (4) is supplied as the power supply VHD supplied to the drain of the transistor Q3A. Is done. The gate of the transistor Q3A is connected to the high-side power supply node S7D to which a predetermined voltage VHDD is supplied.

  Voltage VHDD is set to a voltage higher than VHD + Vthn (Vthn is a threshold voltage of transistor Q3A) so that transistor Q3A operates in a non-saturated region. By doing so, transistor Q3A can raise node N1A to the level of voltage VHD.

  Thus, by configuring the current driving element I3A with a transistor having a limited driving capability, it is possible to realize the current driving element I3A having a small occupation area. Further, since the current driving element I3A is composed of the same N-type transistors as the other transistors Q4A, Q5A, and Q6A, they can be formed in the same process, and the number of manufacturing steps can be reduced.

[Modification 4]
Here, a practical example with respect to FIG. When −VL = −VDD, the condition to be satisfied by the voltage VHD is VHD <VTN from the equation (2). In this case, the reference voltage GND can be used as the voltage VHD that satisfies the condition. That is, as shown in FIG. 13D, the drain of the transistor Q3A can be connected to the reference power supply node S1 to which the reference voltage GND is supplied.

  The voltage VDD or the voltage VH can be used as a voltage supplied to the gate of the transistor Q3A to operate in the non-saturated region. That is, the gate of the transistor Q3A may be connected to the power supply node S2 to which the voltage VDD is supplied or the high side power supply node S4 to which the voltage VH is supplied.

<Embodiment 6>
FIG. 14 is a diagram showing a configuration of a level conversion circuit according to the sixth embodiment of the present invention. The level conversion circuit has a current drive element I3B (third current drive element) connected between a low-side power supply (third power supply) node S8 and a node N1B to which a predetermined voltage VLD is supplied, with respect to the circuit of FIG. ) Is provided.

  When a leakage current is generated between the drain and source of the transistors Q5B and Q6B in FIG. 8, the voltage level of the node N1B is increased when the pulse width of the input signal INS (interval between time t13 and time t14 in FIG. 9) is increased. As described in the fourth embodiment, the inverter circuit configured to increase and the inverter circuit including the current driving element I1B and the transistor Q4B is likely to malfunction. In the level conversion circuit of the present embodiment, the current drive element I3B extracts charges from the node N1B so as to compensate for the leakage currents of the transistors Q5B and Q6B, thereby preventing the level of the node N1B from increasing, and the problem of the malfunction described above. Has solved.

  The basic operation of the level conversion circuit of FIG. 14 is the same as the operation of the circuit of FIG. 8 (FIG. 9), and detailed description thereof is omitted. However, in the level conversion circuit, the input signal INS is at the L level. When the transistors Q5B and Q6B are turned off, the voltage level of the node N1B approaches VLD. If the voltage VLD is too low, the voltage level of the node N1B will not return to the H level when the input signal INS next changes to the H level, and the output of the inverter circuit composed of the current drive element I1B and the transistor Q4B cannot be inverted. Therefore, the voltage VLD is set so as to satisfy the conditions described below.

That is, the value of the voltage VLD is such that when the voltage of the node N1B is VLD and the input signal INS changes from the L level to the H level, the level of the node N1B is the threshold of the inverter composed of the current drive element I1B and the transistor Q4B. Must be set to exceed the value voltage level. In the circuit of FIG. 14, if the absolute value of the threshold voltage of the inverter circuit composed of the current drive element I1B and the transistor Q4B is VTP, the amplitude of the input terminal INS is VDD, and the parasitic capacitance of the node N1B can be ignored, Equation (5) must be satisfied.
VLD + VDD> VHG-VTP (5)
By transforming this equation (5),
VLD> VHG-VTP-VDD (6)
VLD> VHG− (VTP + VDD) (7)
And can.

  That is, the voltage VLD is based on the sum (VTP + VDD) of the threshold voltage of the inverter circuit composed of the current drive element I1B and the transistor Q4B and the amplitude of the input signal INS when the high-side power supply node S6 (VHG) is used as a reference. Also needs to be set low.

At the same time, voltage VLD needs to be at a level that can maintain the output of the inverter circuit composed of current drive element I1B and transistor Q4B inactive (H level) when applied to node N1B. That is, the voltage VLD needs to satisfy the following equation (8).
VLD <VHG-VTP (8)

That is, voltage VLD needs to be set lower than the threshold voltage of the inverter circuit composed of current drive element I1B and transistor Q4B with respect to high-side power supply node S6. Summarizing the above equations (6) and (8), the condition that the voltage VLD should satisfy is the following equation (9).
VHG- (VTP + VDD) <VLD <VHG-VTP (9)

  Since the leakage current between the drain and source of the transistors Q5B and Q6B is very small, the current driving element I3B may have a small current driving capability. On the contrary, if the current driving capability of the current driving element I3B is larger than necessary, when the transistor Q5B or the transistor Q6B is turned on, the H-level voltage of the node N1B is lowered, so that the operation margin is reduced and the power consumption is reduced. Problems such as increase occur. Therefore, it is desirable that the current driving capability of the current driving element I3B be small as long as the leakage current of the transistors Q5B and Q6B can be compensated. That is, the current driving element I3A is a current limiting element that limits the current flowing from the high-side power supply node S7 to the node N1A.

  Hereinafter, a specific configuration as a modification of the current driving element I3B illustrated in FIG. 14 will be described.

[Modification 1]
The current driving element I3B can be a resistance element R3B as shown in FIG. In the figure, the resistance element R3B has a current driving capability sufficient to compensate for the leakage currents of the transistors Q5B and Q5B, and a voltage satisfying the above equation (9) is supplied as the power supply VLD.

[Modification 2]
Further, the current driving element I3B can be configured by a constant current source CS3B as shown in FIG. In the figure, the constant current source CS3B has a current driving capability sufficient to compensate for the leakage currents of the transistors Q5B and Q5B, and a voltage satisfying the above equation (9) is supplied as the power supply VLD.

[Modification 3]
Further, as shown in FIG. 15C, the current driving element I3B can also be configured using a P-type transistor Q3B that operates in a resistance mode (an on-resistance functions as a resistance element). In the figure, the transistor Q3B has a current driving capability sufficient to compensate for the leakage currents of the transistors Q5B and Q5B, and a voltage satisfying the above equation (9) is supplied as the power supply VLD supplied to the drain of the transistor Q3B. Is done. The gate of the transistor Q3B is connected to the low-side power supply node S8D to which a predetermined voltage VLDD is supplied.

  Voltage VLDD is set to a voltage lower than VLD−Vthp (Vthp is the threshold voltage of transistor Q3B) so that transistor Q3B operates in the non-saturation region. By doing so, transistor Q3B can lower node N1B to the level of voltage VLD.

  Thus, by configuring the current driving element I3B with a transistor having a limited driving capability, it is possible to realize the current driving element I3B having a small occupation area. Further, since the current driving element I3B is composed of the same P-type transistor as the other transistors Q4B, Q5B, and Q6B, they can be formed by the same process, and the number of manufacturing steps can be reduced.

[Modification 4]
Here, a practical example of FIG. In the case of VHG = 2 · VDD, the condition to be satisfied by the voltage VLD is VLD> VDD−VTP from the equation (7). In this case, the voltage VDD can be used as the voltage VLD that satisfies the condition. That is, as shown in FIG. 15D, the drain of the transistor Q3B can be connected to the power supply node S2 to which the voltage VDD is supplied.

  Further, the reference voltage GND or the voltage VLW can be used as a voltage supplied to the gate of the transistor Q3B to operate in the non-saturation region. That is, the gate of the transistor Q3B may be connected to the reference power supply node S1 to which the reference voltage GND is supplied or the low-side power supply node S5 to which the voltage VLW is supplied.

<Embodiment 7>
FIG. 16 is a diagram showing a configuration of the level conversion circuit according to the seventh embodiment of the present invention. The level conversion circuit is a circuit in which a bootstrap type load circuit 20A is provided as a current driving element I1A with respect to the circuit of FIG.

  The bootstrap type load circuit 20A includes N-type transistors Q1A and Q7A and a capacitive element C3A. The transistor Q1A (sixth transistor) is connected between the high-side power supply node S4 to which the voltage VH is supplied and the node N4A (output terminal OUT). Transistor Q7A (seventh transistor) has its gate and drain connected to high-side power supply node S4, and its source connected to node N3A (third node) to which the gate of transistor Q1A is connected (that is, transistor Q7A is diode-connected). ing). The capacitive element C3A (third capacitive element) is connected between the node N4A (output terminal OUT) and the node N3A. Other configurations are the same as those in FIG.

  The operation of the level conversion circuit of FIG. 16 is basically the same as the operation of the circuit of FIG. 5 (FIG. 2), so detailed description thereof will be omitted. Here, the operation related to the bootstrap type load circuit 20A will be described. . FIG. 17 is a signal waveform diagram illustrating the operation of the level conversion circuit according to the present embodiment. The input terminal IN and the output terminal before and after the active period of the input signal INS (corresponding to time t3 to time t4 in FIG. 2). The voltage waveforms at OUT (node N4A) and node N3A are shown.

  In the level conversion circuit of FIG. 16, when the input signal INS changes from L level (GND) to H level (VDD) at time t3, the node N1A becomes H level (VDD−VL), so that the transistor Q4A is turned on. The output terminal OUT (output signal / OUTS) is at the L level of the voltage −VL. That is, the source of the transistor Q1A becomes the voltage −VL.

  When the output terminal OUT decreases to the voltage −VL, the voltage at the node N3A also decreases due to the coupling through the capacitive element C3A. At this time, since the transistor Q7A is in the on state, the node N3A becomes the voltage VH−Vthn (Vthn is the threshold voltage of the transistor Q7A).

  Therefore, the gate-source voltage of the transistor Q1A is VH−Vthn − (− VL). Usually, since this value is larger than the threshold voltage of the transistor Q1A, the transistor Q1A is turned on, and the output terminal OUT (output signal / OUTS) is a voltage determined by the current driving power (ON resistance) of the transistors Q1A and Q4A. Become a level. The on-resistance of the transistor Q1A is set sufficiently higher than the on-resistance of the transistor Q4A, and the output signal / OUTS is at the L level with a voltage sufficiently close to −VL.

  At time t4, when the input signal INS changes from the H level (VDD) to the L level (GND), the node N1A becomes the L level and the transistor Q4A is turned off. Then, the output terminal OUT is charged through the transistor Q1A, and its voltage level rises.

  This voltage increase at the output terminal OUT is transmitted to the node N3A via the capacitive element C3A. At this time, the voltage of the node N3A exceeds VH−Vthn, the transistor Q7A is turned off, and the node N3A is in a floating state. Then, the voltage at the node N3A further increases as the voltage at the output terminal OUT increases.

  As a result, the node N3A is boosted by the amplitude of the output signal / OUTS, the voltage of the node N3A becomes higher than VH + Vthn, and the transistor Q1A operates in the non-saturated region. That is, the transistor Q1A raises the voltage of the output terminal OUT (output signal / OUTS) to VH.

  As described above, according to the level conversion circuit of FIG. 16, the transistor Q1A is turned on at high speed and sufficiently in a non-saturated state by the bootstrap action of the capacitive element C3A, and the output terminal OUT can be charged at high speed. . Therefore, the rising speed of the output signal / OUTS is faster than that of the circuit of FIG. 12 using the current driving element I1A such as a resistance element.

  Further, when the output signal / OUTS changes from the H level to the L level (time t4), the transistor Q7A is in a non-conductive state at that time, so that the voltage at the node N3A decreases at a high speed due to the coupling through the capacitive element C3A. To VH-Vthn. As a result, the transistor Q1A has a sufficiently small current driving force (an on-resistance becomes sufficiently large). Therefore, the output terminal OUT is discharged at high speed via the transistor Q4A and becomes L level.

  That is, according to the level conversion circuit of this embodiment, the rising and falling speeds of the output signal / OUTS can be increased, so that the operation can be speeded up.

[Example of change]
Here, a modification example in which the technique of the seventh embodiment is applied to a level conversion circuit configured using P-type transistors is shown.

  FIG. 18 is a diagram showing a configuration of a level conversion circuit according to this modification. The level conversion circuit is a circuit in which a bootstrap load circuit 20B is provided as a current driving element I1B with respect to the circuit of FIG.

  The bootstrap type load circuit 20B includes P-type transistors Q1B and Q7B and a capacitive element C3B. The transistor Q1B (sixth transistor) is connected between the low-side power supply node S5 to which the voltage VLW is supplied and the node N4B (output terminal OUT). Transistor Q7B (seventh transistor) has its gate and drain connected to low-side power supply node S5, and its source connected to node N3B (third node) to which the gate of transistor Q1B is connected. The capacitive element C3B (third capacitive element) is connected between the node N4B (output terminal OUT) and the node N3B. Other configurations are the same as those in FIG.

  Since the operation of the level conversion circuit of FIG. 18 is basically the same as the operation of the circuit of FIG. 8 (FIG. 9), detailed description thereof will be omitted, and the operation related to the bootstrap load circuit 20B will be described here. . FIG. 19 is a signal waveform diagram illustrating the operation of the level conversion circuit according to this modification. The input terminal IN and the output terminal OUT before and after the active period of the input signal INS (corresponding to the time t13 to the time t14 in FIG. 9). The voltage waveforms at (node N4A) and node N3B are shown.

  In the level conversion circuit of FIG. 18, when the input signal INS is changed from the H level (VDD) to the L level (GND) at time t13, the node N1B is changed to the L level (VHG−VDD), so that the transistor Q4B is turned on. The output terminal OUT (output signal / OUTS) is at the H level of the voltage VHG. That is, the source of the transistor Q1B becomes the voltage VHG.

  When the output terminal OUT rises to the voltage VHG, the voltage at the node N3B also rises due to the coupling through the capacitive element C3B. At this time, since the transistor Q7B is in the on state, the node N3B becomes the voltage VLW + Vthp (Vthp is the threshold voltage of the transistor Q7B).

  Therefore, the gate-source voltage of the transistor Q1B is VHG− (VLW + Vthp). Usually, since this value is larger than the threshold voltage of the transistor Q1B, the transistor Q1B is turned on, and the output terminal OUT (output signal / OUTS) is a voltage determined by the current driving power (ON resistance) of the transistors Q1B and Q4B. Become a level. The on-resistance of the transistor Q1B is set sufficiently higher than the on-resistance of the transistor Q4B, and the output signal / OUTS is at an H level having a voltage sufficiently close to VHG.

  At time t14, when the input signal INS changes from L level (GND) to H level (VDD), the node N1B becomes H level and the transistor Q4B is turned off. Then, the output terminal OUT is discharged through the transistor Q1B, and its voltage level is lowered.

  This voltage drop at the output terminal OUT is transmitted to the node N3B through the capacitive element C3B. At this time, the voltage of the node N3B falls below VLW + Vthp, the transistor Q7B is turned off, and the node N3B is in a floating state. Then, the voltage at the node N3B further decreases as the voltage at the output terminal OUT decreases.

  As a result, the voltage of the node N3B decreases by the amplitude of the output signal / OUTS, the voltage of the node N3B becomes lower than VLW−Vthp, and the transistor Q1B operates in the non-saturated region. That is, the transistor Q1B reduces the voltage of the output terminal OUT (output signal / OUTS) to VLW.

  As described above, according to the level conversion circuit of FIG. 18, the transistor Q1B can be turned on at high speed and sufficiently in a non-saturated state by the bootstrap action of the capacitive element C3B, and the output terminal OUT can be discharged at high speed. . Therefore, the rising speed of the output signal / OUTS is faster than that of the circuit of FIG. 14 using the current driving element I1B such as a resistance element.

  Further, when the output signal / OUTS changes from the L level to the H level (time t14), the transistor Q7B is in a non-conductive state at that time, so that the voltage at the node N3B rises at a high speed due to the coupling through the capacitive element C3B. To VLW + Vthp. As a result, the transistor Q1B has a sufficiently small current driving capability (an on-resistance becomes sufficiently large). Therefore, the output terminal OUT is charged at high speed via the transistor Q4B and becomes H level.

  That is, according to the level conversion circuit of the present modification, the falling and rising speeds of the output signal / OUTS can be increased in the level conversion circuit configured using P-type transistors.

<Eighth embodiment>
FIG. 20 is a diagram showing the configuration of the level conversion circuit according to the eighth embodiment of the present invention. In the configuration of the level conversion circuit, a push-pull circuit 40A is further provided for the circuit of FIG.

  The push-pull circuit 40A includes N-type transistors Q1DA and Q4DA (eighth and ninth transistors) connected in series between the high-side power supply node S4 and the low-side power supply node S3, and between the transistors Q1DA and Q4DA. The connection node N4DA (second output node) is the output node. As shown in FIG. 20, in the level conversion circuit, the output terminal OUT for outputting the output signal / OUTS is not the node N4A but the output node N4DA of the push-pull circuit 40A.

  The gate of the transistor Q1DA connected between the output terminal OUT (node N4DA) and the high-side power supply node S4 is connected to the node N3A of the bootstrap load circuit 20A. The gate of the transistor Q4DA connected between the output terminal OUT and the low-side power supply node S3 is connected to the node N1A.

  Since the operation of the level conversion circuit in FIG. 20 is basically the same as the operation of the circuit in FIG. 5 (FIG. 2), detailed description thereof is omitted, and here it relates to the bootstrap load circuit 20A and the push-pull circuit 40A. The operation | movement which performs is demonstrated. FIG. 21 is a signal waveform diagram showing the operation of the level conversion circuit according to the present embodiment. The input terminal IN and the node N1A before and after the active period of the input signal INS (corresponding to the time t3 to the time t4 in FIG. 2). , N3A and the output terminal OUT voltage waveforms.

  In the level conversion circuit of FIG. 20, when the input signal INS is changed from L level (GND) to H level (VDD) at time t3, the node N1A is changed to H level (VDD-VL), so that the transistor Q4A is turned on. Node N4A is at the L level of voltage -VL. That is, the source of the transistor Q1A becomes the voltage −VL.

  When the node N4A decreases to the voltage −VL, the voltage at the node N3A also decreases due to the coupling through the capacitive element C3A. At this time, since the transistor Q7A is in the on state, the node N3A becomes the voltage VH−Vthn (Vthn is the threshold voltage of the transistor Q7A).

  Therefore, the gate-source voltage of the transistor Q1A is VH−Vthn − (− VL), and the transistor Q1A is turned on. Therefore, the node N4A has a voltage level determined by the current driving power (ON resistance) of the transistors Q1A and Q4A. The on-resistance of the transistor Q1A is set sufficiently higher than the on-resistance of the transistor Q4A, and the output signal / OUTS is at the L level with a voltage sufficiently close to −VL.

  Thus, since the node N1A becomes H level, the transistor Q4DA of the push-pull circuit 40A is turned on. At this time, the transistor Q1DA is also turned on by the voltage of the node N3A (VH−Vthn − (− VL)), but the on resistance of the transistor Q1A is set sufficiently higher than the on resistance of the transistor Q4A, and the output signal / OUTS is at the L level with a voltage sufficiently close to -VL.

  At time t4, when the input signal INS changes from the H level (VDD) to the L level (GND), the node N1A becomes the L level and the transistor Q4A is turned off. Node N4A is then charged through transistor Q1A and its voltage level rises.

  This voltage increase at node N4A is transmitted to node N3A via capacitive element C3A. At this time, the voltage of the node N3A exceeds VH−Vthn, the transistor Q7A is turned off, and the node N3A is in a floating state. Then, the voltage at the node N3A further increases as the voltage at the output terminal OUT increases. As a result, the voltage at the node N3A becomes higher than VH + Vthn, and the transistor Q1A operates in the non-saturated region to raise the voltage at the node N4A.

  The voltage increase at the node N4A at this time is fed back to the node N3A again through the capacitive element C3A. As a result, the voltage level of the node N3A further rises, and the transistor Q1A can charge the node N4A at high speed to the voltage VH. Note that the voltage level of the node N3A at this time further rises from the precharge voltage VH-Vthn before feedback by a voltage change (VH + VL) of the node N4A.

  As a result, similarly to the transistor Q1A, the transistor Q1AD is turned on at a high speed and sufficiently in a non-saturated state, and the output terminal OUT can be charged at a high speed. When the input signal INS falls, since the transistor Q4DA is turned off together with the transistor Q4A, the output terminal OUT (output signal / OUTS) rises at a high speed.

  The above feedback effect (bootstrap action) can also be obtained in the circuit of FIG. 16, but when a capacitive load is connected to the output terminal OUT, the effect that the rising speed of the output signal / OUTS can be reduced is Get smaller.

  On the other hand, in the circuit of FIG. 20, the output terminal OUT is charged by the transistor Q1DA, and the node N4A used for the bootstrap operation is charged by another transistor Q1A. Therefore, the voltage level of the node N3A can be increased at high speed without being affected by the load connected to the output terminal OUT. Therefore, charging of the output terminal OUT is performed at a higher speed than the circuit shown in FIG.

  Further, even when the output signal / OUTS falls, the node N3A can be quickly returned to the precharge voltage VH-Vthn without being affected by the load connected to the output terminal OUT. That is, since the current driving capability of the transistor Q1DA can be quickly reduced, the falling speed of the output signal / OUTS is also increased.

[Modification 1]
FIG. 22 is a diagram illustrating a modification of the level conversion circuit according to the present embodiment. In the level conversion circuit, the gate of the transistor Q5A is connected to the output terminal OUT (the output node N4DA of the push-pull circuit 40A) instead of the node N4A to the circuit of FIG. By doing so, the parasitic capacitance of the node N4A becomes considerably smaller than the gate capacitance of the transistor Q5A, and the voltage change of the node N4A is accelerated. Accordingly, the voltage change at the node N3A is also accelerated, so that the operation of the transistor Q1DA, that is, the charge / discharge operation of the output terminal OUT is accelerated. As a result, the rising and falling speeds of the output signal / OUTS are increased.

[Modification 2]
Here, a modification example in which the technique of the eighth embodiment is applied to a level conversion circuit configured using P-type transistors is shown.

  FIG. 23 is a diagram showing a configuration of a level conversion circuit according to this modification. In the configuration of the level conversion circuit, a push-pull circuit 40B is further provided for the circuit of FIG.

  The push-pull circuit 40B is composed of P-type transistors Q1DB and Q4DB (eighth and ninth transistors) connected in series between the low-side power supply node S5 and the high-side power supply node S6, and between the transistors Q1DB and Q4DB. The connection node N4DB is the output node. As shown in FIG. 23, in the level conversion circuit, the output terminal OUT for outputting the output signal / OUTS is not the node N4B but the output node N4DB of the push-pull circuit 40B.

  The gate of the transistor Q1DB connected between the output terminal OUT and the low-side power supply node S5 is connected to the node N3B of the bootstrap type load circuit 20B. The gate of the transistor Q4DB connected between the output terminal OUT and the high-side power supply node S6 is connected to the node N1B.

  The operation of the level conversion circuit of FIG. 23 is basically the same as the operation of the circuit of FIG. 18 (FIG. 19) except that the output signal / OUTS is output through the push-pull circuit 40B (description is omitted). ).

  Also in this modified example, the operation speed is increased based on the same theory as described in FIGS. That is, in the circuit of FIG. 23, the output terminal OUT is discharged by the transistor Q1DB, and the node N4B used for the bootstrap operation is discharged by another transistor Q1B. Therefore, the voltage level of the node N3B can be lowered at high speed without being affected by the load connected to the output terminal OUT. Therefore, the current driving capability of the transistor Q1DB can be increased at a high speed, and the output terminal OUT can be discharged at a higher speed than in the circuit of FIG. As a result, the falling speed of the output signal / OUTS is increased.

  Further, even when the output signal / OUTS rises, the node N3B can be quickly returned to the precharge voltage VLW + Vthp without being affected by the load connected to the output terminal OUT. That is, since the current driving capability of the transistor Q1DB can be quickly reduced, the rising speed of the output signal / OUTS is also increased.

[Modification 3]
Here, the above-described modification 1 is applied to the circuit of FIG. FIG. 24 is a diagram showing the modification example. In the level conversion circuit, the gate of the transistor Q5B is connected to the output terminal OUT (the output node N4DB of the push-pull circuit 40B) instead of the node N4B to the circuit of FIG. By doing so, the parasitic capacitance of the node N4B becomes considerably smaller than the gate capacitance of the transistor Q5B, and the voltage change of the node N4B is accelerated. Accordingly, the voltage change at the node N3B is also accelerated, so that the operation of the transistor Q1DB, that is, the charge / discharge operation of the output terminal OUT is accelerated. As a result, the rising and falling speeds of the output signal / OUTS are increased.

<Embodiment 9>
FIG. 25 is a diagram showing the configuration of the level conversion circuit according to the ninth embodiment of the present invention. The level conversion circuit also converts the input signal INS given to the input terminal IN into a signal whose H level is the voltage VH and L level is the voltage -VL. The logic value (high or low) of the signal OUTS is configured to take the same value as the input signal INS.

  As shown in FIG. 25, the level conversion circuit according to the present embodiment includes a plurality of circuits including an input stage circuit 100, a push-pull circuit 110, a bootstrap type driving circuit 120, and an output driving circuit 130. In these circuits, the voltage VH of the high-side power supply node S4 is supplied via the high-side power supply line 102, and the voltage -VL of the low-side power supply node S3 is supplied via the low-side power supply line 104.

  In the following description, unless otherwise indicated, the influence on the voltage level of each node due to the parasitic capacitance and the current driving capability (or on-resistance) of the transistor is ignored. That is, even in a ratio type circuit in which the output voltage is determined by the on-resistance ratio of the transistor, the output voltage will be described as changing between the voltages VH and -VL. The threshold voltages of the transistors constituting the level conversion circuit are all equal, and the value is Vthn.

  The input stage circuit 100 has the same configuration as the level conversion circuit of FIG. That is, the input stage circuit 100 includes N-type transistors Q1A, Q4A to Q7A, capacitive elements C1A, C2A, C3A, and current drive elements I2A, I3A. Capacitance element C1A transmits input signal INS input to input signal INS to node N1A (the gate of transistor Q4A).

  A circuit including transistors Q1A and Q7A and a capacitive element C3A provided between the node N4A and the high-side power supply line 102 corresponds to the bootstrap type load circuit 20A included in the level conversion circuit of FIG. The current flowing from the high-side power supply line 102 to the node N4A serving as the output node of the stage circuit 100 is controlled.

  Transistors Q5A and Q6A are connected between node N1A and low-side power supply line 104. Of these, the transistor Q5A whose gate is connected to the node N4A functions to turn on when the node N4A is at the H level and maintain the node N1A at the L level (−VL). The reset signal RSTS input to the reset terminal RST is transmitted to the gate (node N2A) of the transistor Q6A via the capacitive element C2A. The transistor Q6A sets the node N1A to the L level (−) according to the reset signal RSTS. VL).

  The current driving element I2A connected between the node N2A and the low-side power supply line 104 controls the current flowing from the node N2A to the low-side power supply line 104, and between the high-side power supply node S7 and the node N1A. The connected current driving element I3A compensates for the leakage current of the transistors Q5A and Q6A.

  The operation of the input stage circuit 100 is the same as that of the level conversion circuit of FIG. That is, when the input signal INS rises to H level (VDD), the node N1A becomes H level, the transistor Q4A is turned on, and the output node N4A becomes L level corresponding to the voltage −VL. When the input signal INS falls to L level (GND), the node N1A becomes L level, the transistor Q4A is turned off, and the output node N4A is charged through a load circuit including the transistors Q1A, Q7A and the capacitive element C3A. The voltage VH becomes the H level.

  The push-pull circuit 110 has the same configuration as the push-pull circuit 1A included in the level conversion circuit of FIG. 10, and is an N-type connected in series between the high-side power line 102 and the low-side power line 104. The connection node N5A between the transistors Q8A and Q9A is the output node (third output node) (unlike in the case of FIG. 10, the node N5A is not connected to the gate of the transistor Q5A).

  The push-pull circuit 110 is driven by the voltages at the nodes N1A and N4A. That is, the gate of the transistor Q8A connected between the high-side power line 102 and the node N5A is connected to the node N4A, and the gate of the transistor Q9A connected between the node N5A and the low-side power line 104 is connected to the node N1A. To do.

  The operation of the push-pull circuit 110 is as follows. That is, when the node N1A of the input stage circuit 100 becomes H level, the transistor Q9A becomes conductive, discharging the node N5A and lowering its voltage level. In the input stage circuit 100, the voltage level of the node N4A decreases as the node N1A becomes H level. At this time, the voltage difference between the node N4A and the node N5A becomes Vthn or less, and the transistor Q8A is turned off. As a result, the node N5A becomes the L level of the voltage -VL.

  Further, when the node N1A of the input stage circuit 100 becomes L level, the transistor Q9A is turned off. In the input stage circuit 100, the node N4A becomes H level following the transition of the node N1A to L level, so that the transistor Q8A is turned on, whereby the node N5A becomes H level of the voltage VH-Vthn.

  As described above, in the push-pull circuit 110, after the gate voltage of the transistor Q9A is changed, the gate voltage of the transistor Q8A is changed. That is, when the node N5A is charged, the transistor Q8A is turned on after the transistor Q9A is turned off, so that almost no through current (DC current flowing from the high-side power supply node S4 to the low-side power supply node S3) is generated. On the other hand, when the node N5A is discharged, the transistor Q8A is turned off after the transistor Q9A is turned on, so that a through current flows during that time.

  Here, considering the offset voltage ΔV (corresponding to ΔVL2 in FIG. 2) at the node N4A of the input stage circuit 100, the gate voltage when the transistor Q8A is in the OFF state is −VL + ΔV. Voltage ΔV is set sufficiently smaller than threshold voltage Vthn of transistor Q8A, and transistor Q8A is reliably turned off. Therefore, in the push-pull circuit 110, a direct current (through current) is consumed only in a very short period of time, ie, a switching period when the node N5A is discharged (from when the transistor Q9A is turned on until the transistor Q8A is turned off). .

  The bootstrap type driving circuit 120 includes N-type transistors Q10A, Q11A, Q12A and a capacitive element C4A. As can be seen from FIG. 25, the circuit including the transistors Q1A, Q4A, Q7A and the capacitive element C3A in the input stage circuit 100. And a circuit having substantially the same configuration.

  The transistor Q12A has a gate connected to the output node N5A of the push-pull circuit 110, and is between the node N7A (fourth output node) that is the output node of the bootstrap type drive circuit 120 and the low-side power line 104. Connecting.

  A circuit composed of the transistors Q10A and Q11A and the capacitive element C4A constitutes a bootstrap type load circuit, and controls a current flowing from the high-side power supply line 102 into the node N5A. Transistor Q11A is connected between node N7A and high-side power supply line 102. Transistor Q10A has its gate and drain connected to high-side power supply line 102, and its source connected to a node (node N6A) to which the gate of transistor Q11A is connected (that is, transistor Q10A is diode-connected). Capacitance element C4A is connected between nodes N7A and N6A.

  The operation of the bootstrap type driving circuit 120 is substantially the same as that of the input stage circuit 100. That is, when the output node N5A of the push-pull circuit 110 becomes H level, the transistor Q12A is turned on, and the node N7A is set to L level corresponding to the voltage −VL (more precisely, determined by the on-resistance ratio of the transistors Q11A and Q12A). Voltage level). Further, when the node N5A becomes L level, the transistor Q12A is turned off, and the node IN7A is charged through the bootstrap type load circuit including the transistors Q10A and Q11A and the capacitive element C4A, and the voltage level rises.

  Since the gate (node N6A) of transistor Q11A is charged through transistor Q10A, the voltage in the steady state is VH-Vthn, but is boosted by the bootstrap action of capacitive element C4A when the voltage level of node N7A rises. . As a result, transistor Q11A operates in a non-saturated manner, and the H level of node N7A can be raised to voltage VH. Therefore, the level of the output node N7A of the bootstrap driving circuit 120 changes between the voltage VH and the voltage −VL.

  The output driving circuit 130 constitutes a ratioless bootstrap driving circuit, and includes N-type transistors Q13A to Q20A and a capacitive element C5A.

  The transistors Q13A and Q14A are connected in series between the high-side power line 102 and the low-side power line 104. When the connection node between the transistors Q13A and Q14A is a node N8A, the gate of the transistor Q13A connected between the high-side power supply line 102 and the node N8A is connected to the output node N4A of the input stage circuit 100. The gate of the transistor Q14A connected between the node N8A and the low-side power supply line 104 is connected to an output terminal OUT (node N11A) described later. That is, the transistor Q13A charges the node N8A with the current from the high-side power supply line 102 according to the voltage level of the node N4A. The transistor Q14A charges the charge of the node N8A according to the voltage level of the output terminal OUT (output signal OUTS). Is discharged to the low-side power supply line 104.

  The transistors Q17A and Q18A are also connected in series between the high-side power line 102 and the low-side power line 104. When the connection node between the transistors Q17A and Q18A is a node N10A, the gate of the transistor Q17A connected between the high-side power supply line 102 and the node N10A is connected to the output node N7A of the bootstrap type drive circuit 120. That is, the transistor Q17A charges the node N10A with the current from the high-side power supply line 102 according to the voltage level of the node N7A, and the transistor Q18A charges the charge of the node N10A according to the voltage level of the node N5A. It discharges to

  Similarly, the transistors Q15A and Q16A are also connected in series between the high-side power line 102 and the low-side power line 104. When the connection node between the transistors Q15A and Q16A is a node N9A, the gate of the transistor Q15A connected between the high-side power supply line 102 and the node N9A is connected to the node N10A, and between the node N9A and the low-side power supply line 104 The gate of transistor Q16A connected to is connected to node N8A. Capacitance element C5A is connected between nodes N9A and N10A. That is, the transistor Q15A charges the node N9A with the current from the high-side power supply line 102 according to the voltage level of the node N10A, and the transistor Q16A charges the charge at the node N9A according to the voltage level of the node N8A. It discharges to

  Further, the transistors Q19A and Q20A are also connected in series between the high-side power line 102 and the low-side power line 104. A connection node N11A (fifth output node) between the transistors Q19A and Q20A is the output terminal OUT of the level conversion circuit, from which an output signal OUTS is output. The gate of the transistor Q19A connected between the high-side power line 102 and the output terminal OUT is connected to the node N10A, and the gate of the transistor Q20A connected between the output terminal OUT and the low-side power line 104 is a push-pull circuit. 110 is connected to output node N5A. That is, the transistor Q19A charges the output terminal OUT with the current from the high-side power supply line 102 according to the voltage level of the node N10A, and the transistor Q20A charges the charge at the node N9A according to the voltage level of the node N5A. 104 is discharged.

  The gate of the transistor Q18A connected between the node N10A and the low-side power supply line 104 is connected to the output node N5A of the push-pull circuit 110. That is, the capacitive element C5A capacitively couples between the node N9A and the node N10A.

  In the output drive circuit 130, as will be described in detail below, the through current path from the high-side power supply line 102 to the low-side power supply line 104 is interrupted by using the delay in voltage change at each node. As a result, an increase in current consumption is suppressed. Further, the output signal OUTS accurately changes between the voltages VH and -VL by the operation of the output driving circuit 130.

  FIG. 26 is a signal waveform diagram showing an operation of the level conversion circuit (FIG. 25) according to the present embodiment. The operation of the level conversion circuit will be described below with reference to FIG.

  First, as an initial state, it is assumed that the input signal INS supplied to the input terminal IN is at the L level of the reference voltage GND and the node N1A is at the L level of the voltage −VL. At this time, since the transistor Q4A is off, the node N4A is at the H level (VH). Since transistor Q8A is on and transistor Q9A is off, node N5A is at the H level (VH−Vthn). Therefore, transistors Q8A, Q12A, Q13A, Q18A, and Q20A are on. Therefore, since the node N7A is at the L level (−VL) and the transistor Q17A is in the off state, the node N10A is at the L level (−VL) and the transistors Q15A and Q19A are in the off state. Therefore, the output terminal OUT is at the L level (−VL), and the transistor Q14A is in the off state. Therefore, the node N8A is at the H level (VH−Vthn) and the transistor Q16A is in the on state, so the node N9A is at the L level (−VL).

  From this initial state, when the input signal INS rises to the H level of the voltage VDD, in the input stage circuit 100, the node N1A becomes the H level (VDD−VL), the transistor Q4A is turned on, and the node N4A is substantially at the voltage −. It becomes L level of VL. Here, it is assumed that the current driving capability of the transistors Q1A and Q4A is set sufficiently large (the on-resistance is set sufficiently small), and the output offset voltage of the input stage circuit 100 can be ignored.

  At this time, in the push-pull circuit 110, the transistor Q9A is turned on in response to an increase in the voltage level of the node N1A of the input stage circuit 100, the node N5A is discharged, and the voltage level starts to decrease. Since the output node N4A of the input stage circuit 100 is lowered to the L level (−VL), the transistor Q8A is turned off because the gate-source voltage becomes lower than the threshold voltage. Therefore, the node N5A is at the L level of the voltage -VL.

  When node N5A becomes L level, transistor Q12A of bootstrap type drive circuit 120 is turned off, and node N7A is charged through transistor Q11A. At this time, the node N6A is boosted by the bootstrap action of the capacitive element C4A, and the transistor Q11A operates in a non-saturated state, so that the node N7A becomes the H level of the voltage VH.

  In the output drive circuit 130, the following operation is performed. First, when the output node N4A of the input stage circuit 100 becomes L level (−VL), the transistor Q13A is turned off. However, since the output signal OUT remains at the L level (−VL) at this time, the transistor Q14A is also in the off state. Therefore, node N8A is kept in the floating state and is maintained at the H level of voltage VH-Vthn.

  Further, when the output node N5A of the push-pull circuit 110 becomes L level (−VL), the transistors Q18A and Q20A are turned off. Further, when the output node N7A of the bootstrap type driving circuit 120 becomes H level (VH), the transistor Q17A is turned on, the node N10A is charged, and its voltage level rises. As described above, the voltage change at the node N7A occurs in response to the voltage change at the node N5A. Therefore, when charging the node N10A, the transistor Q18A is turned off before the transistor Q17A is turned on. Thereby, at this time, generation of a through current through the transistors Q17A and Q18A is prevented.

  The node N10A is capacitively coupled to the node N9A via the capacitive element C5A. At this time, the node N8A is maintained at the H level and the transistor Q16A is in the on state, so that the voltage level of the node N10A increases. Also, the node N9A is maintained at the L level almost at the voltage -VL. Further, when the charging of the node N10A proceeds and the gate-source voltage of the transistor Q15A exceeds the threshold voltage, it is turned on, but the transistor Q15A is set to have a sufficiently higher on-resistance than the transistor Q16A. Also, the node N9A is maintained at the L level almost at the voltage -VL. As a result, node N10A rises to voltage VH-Vthn and becomes H level.

  When the node N10A becomes H level (VH−Vthn), the transistor Q19A is turned on, the output terminal OUT is charged, and its voltage level rises. Even when the output terminal OUT is charged, since the transistor Q20A is turned off before the transistor Q19A is turned on, generation of a through current through the transistors Q19A and Q20A is prevented.

  As the charging of the output terminal OUT proceeds, the transistor Q14A is turned on, and the node N8A is discharged to the L level (−VL). Accordingly, since transistor Q16A is turned off, node N9A is charged through transistor Q15A, and the voltage level rises. Since the increase in the voltage level of node N9A is transmitted to node N10A via capacitive element C5A, the voltage level of node N10A also increases. When the voltage level of the node N10A rises, the transistor Q17A is turned off and the node N10A enters the floating state. Therefore, the voltage level of the node N10A further rises and becomes a voltage VH + ΔVB higher than the voltage VH (ΔVB is equal to the node N9A). And the ratio of the parasitic capacitance associated with the node N10A and the capacitance value of the capacitive element C5A).

  Thus, in the output drive circuit 130, when the transistor Q19A charges the output terminal OUT to increase the voltage level of the output terminal OUT, the voltage increase is fed back to the node N10A (the gate of the transistor Q19A). Is obtained. As a result, the voltage level of the node N10A rises, so that the transistor Q19A has a high current driving capability and performs a non-saturated operation. Therefore, the output terminal OUT is charged at high speed and becomes the L level of the voltage VH.

  Note that at this time, the transistor Q15A also performs non-saturated operation, so that the voltage level of the node N9A becomes VH. As described above, the transistor Q15A is turned on when the node N10A is charged, and the transistor Q16A is turned off when the node N8A is subsequently discharged. That is, since the transistor Q15A is turned on before the transistor Q16A is turned off, a through current flows through the transistors Q15A and Q16A during that time. However, an increase in current consumption can be prevented if the current driving capability of the transistors Q15A and Q16A is made sufficiently small.

  The period in which the through current is generated is only a short period from when the transistor Q19A is turned on together with the transistor Q15A until the output signal OUT is charged and becomes H level. The larger the current driving capability of the transistor Q19A, the shorter the period, and the smaller the current consumed by the through current. In particular, when the load capacity applied to the output terminal OUT is large, it is desirable to set the current driving capability of the transistor Q19A sufficiently large in order to prevent the output terminal OUT from being charged for a long time. The output drive circuit 130 is a ratioless circuit, and no through current is generated in the steady state. Therefore, even if the current drive capability of the transistor Q19A is set large, the power consumption in the steady state is not increased.

  Referring to FIGS. 26 and 27 again, when the input signal INS falls from the H level (VDD) to the L level (GND), the node N1A of the input stage circuit 100 becomes the L level (−VL), and accordingly the transistor Q4A is turned off and node N4A is charged. At this time, a bootstrap operation is performed by the capacitive element C3A (refer to the description of the circuit of FIG. 16 in Embodiment 7 for details), and the node N4A becomes the H level of the voltage VH.

  As the voltage levels at the nodes N1A and N4A increase, the transistor Q9A is turned off and the transistor Q8A is turned on in the push-pull circuit 110, so that the node N5A is charged and becomes H level (VH−Vthn). At this time, since the transistor Q9A is turned off before the transistor Q8A is turned on, no through current flows through the transistors Q8A and Q9A.

  When the output node N5A of the push-pull circuit 110 becomes H level, in the bootstrap type driving circuit 120, the transistor Q12A is turned on, and the node N7A is discharged to L level (−VL).

  In the output drive circuit 130, the transistors Q18A and Q20A are turned on when the node N5A becomes H level, and the transistor Q17A is turned off when the node N7A becomes L level. Therefore, the node N10A and the output signal OUT are discharged. Since the transistors Q19A and Q15A are turned off when the node N10A becomes L level, the output signal OUTS becomes L level of the voltage −VL.

  Since the transistor Q13A is turned on when the output node N4A of the input stage circuit 100 becomes H level, when the transistor Q14A is turned off because the output terminal OUT becomes L level, the node N8A is charged and voltage It becomes H level of VH-Vthn. Responsively, transistor Q16A is turned on, and node N9A is at the L level of voltage -VL.

  When the node N8A is charged, the transistor Q13A is turned on before the transistor Q14A is turned off. Therefore, the through-current flows through the transistors Q13A and Q14A until the transistor Q13A is turned on and the transistor Q14A is turned off. Flowing. However, since the output signal OUT is discharged at high speed and becomes L level (−VL), the period is very short and the amount of through current is very small. Further, when discharging the node N9A, the transistor Q15A is turned off before the transistor Q16A is turned on, so that no through current flows through the transistors Q15A and Q16A.

  With the above operation, the level conversion circuit returns to the initial state. Thereafter, the operation described above is repeated according to the level change of the input signal INS.

  In a steady state, there is no through current path from the high-side power supply line 102 to the low-side power supply line 104 in the output drive circuit 130. Therefore, the driving capability of the transistors Q19A and Q20A can be set large, and even when the output load capacity of the output terminal OUT is large, the output terminal OUT is charged and discharged at high speed and the level of the output signal OUTS is increased. Can be changed.

  Since the input stage circuit 100 and the bootstrap type driving circuit 120 are ratio type circuits in which the output voltage is determined by the on-resistance ratio of the transistors, the transistors Q1A, Q4A and Q11A are respectively output while the nodes N4A, N7A are at the L level. Through current flows through Q12A. However, since the voltage levels of the nodes N4A and N7A change complementarily, the through currents of the input stage circuit 100 and the bootstrap type drive circuit 120 do not flow simultaneously, but flow one by one according to the voltage level of the input signal INS. . That is, the DC power consumption is about the same as the power consumption of the level conversion circuit having one bootstrap type load circuit.

  As described above, in the level conversion circuit according to the ninth embodiment, the through current in the steady state is based on the signal (voltage level of the node N4A) subjected to level conversion by the input stage circuit 100 (level conversion circuit in FIG. 16). An output signal OUTS is output by the output driving circuit 130 which is a ratioless type bootstrap circuit in which no occurrence occurs. Since the input stage circuit 100 is a ratio type circuit, the driving capability is limited in order to suppress the through current. However, since the output driving circuit 130 does not have the limitation, the driving capability can be set high. Therefore, it is possible to change the voltage level of the output signal OUTS at high speed even when the load capacitance applied to the output terminal OUT is large while suppressing an increase in current consumption.

[Modification 1]
As a modification of the level conversion circuit of FIG. 25, the gate of the transistor Q5A may be connected to the output node N5A of the push-pull circuit 110 as shown in FIG. Since the parasitic capacitance of the output node N4A of the input stage circuit 100 is reduced by the gate capacitance of the transistor Q5A than in the configuration of FIG. 25, the effect that the rise of the node N4A is accelerated is obtained. Note that, unlike the transistor Q1A in which the driving capability is limited in order to suppress the through current of the input stage circuit 100, the transistor Q8A of the push-pull circuit 110 in which no through current is generated has a high driving capability. Even if the capacitance is increased by the gate capacitance of transistor Q5A, the rising speed of the voltage level of node N5A is not reduced.

[Modification 2]
In the level conversion circuit of FIG. 25, the example of using the circuit of FIG. 16 as the input stage circuit 100 is shown, but the circuit of FIG. 20 or FIG. 22 may be used instead. FIG. 28 shows a modified example using the circuit of FIG. 22 as the input stage circuit 100.

[Modification 3]
25, 27, and 28 show examples of level conversion circuits configured using N-type transistors. As shown in the second embodiment, the same level conversion circuits as those of P-type transistors are used. It is also possible to configure using Although not shown, P-type transistors are used instead of N-type transistors in the circuit configurations of FIGS. 25, 27, and 28, and the polarity of the power supply voltage is reversed (shown in FIGS. 25, 27, and 28). The low-side power supply voltage VLW is supplied to the power supply line 102 and the voltage VHG is also supplied to the power supply line 104), and the voltage polarity of each signal is reversed (the active level is set to L level and the inactive level is set to H level) do it.

<Embodiment 10>
As described above, according to the level conversion circuit of the ninth embodiment, it is possible to change the voltage level of the output signal OUTS at high speed even when the load capacitance applied to the output terminal OUT is large while suppressing an increase in current consumption. is there.

  The tenth embodiment shows an example in which the level conversion circuit of the ninth embodiment is provided for a liquid crystal display device. The gate line of the liquid crystal display device becomes a large capacitive load because the gate of the transistor of the liquid crystal pixel is connected. Therefore, a level conversion circuit for supplying a signal to a circuit (gate line driving circuit) for driving the circuit is desired to have a high driving capability, and the level conversion circuit of the ninth embodiment can be said to be suitable for it.

  FIG. 29 is a block diagram illustrating a configuration example of the liquid crystal display device 10 according to the tenth embodiment. Here, a display device using capacitive coupling driving technology is shown as an example. The display device includes a capacitor line that is capacitively coupled to the pixel electrode of the pixel, and supplies a signal having a predetermined amplitude (capacitor line drive signal) to the capacitor line, thereby displaying a display data signal written to the pixel electrode. The level can be adjusted.

  For example, the potential of the pixel electrode to which the positive polarity (+) display signal is written is increased (changes in the positive direction), and the potential of the pixel electrode to which the negative polarity (−) display signal is written is decreased (in the negative direction). Display signal can be amplified. As a result, the amplitude of the display signal supplied to the data line (source line) can be reduced, and the power consumed by the data line can be reduced. In addition, since the amplitude of the display signal is reduced, the amplitude of the drive signal for the scanning line (gate line) can also be reduced.

As shown in FIG. 29, the display device 10 includes a liquid crystal array unit 15, a gate line drive circuit (scanning line drive circuit in a broad sense) 11, a drive control circuit 13, and a level conversion circuit 14. The liquid crystal array unit 15 is composed of a plurality of pixels 25 arranged in a matrix, and gate lines GL ₁ , GL ₂ ,... GL _m (generic name “gate” corresponding to each row of pixels (pixel line). Line GL "), and data lines DL ₁ , DL ₂ ,... (Generic name“ data line DL ”) are provided corresponding to each pixel column (pixel column). In other words, the pixels 25 are provided in the vicinity of intersections of a plurality of gate lines (scanning lines in a broad sense) GL arranged in parallel to each other and a plurality of data lines data lines DL arranged so as to be orthogonal thereto. It is done. The capacitor line CCL _1, CCL ₂ for performing capacitive coupling drive, ..., CCL _m (collectively, "capacitance line CCL"), the gate lines GL _1, GL _2, ..., are provided along the respective GL _m .

In FIG. 29, the gate lines GL ₁ , GL ₂ , GL _{m of} the first row, the second row, and the last row, the capacitance lines CCL ₁ , CCL ₂ , CCL _m , the first column, The data lines DL ₁ and DL _{2 in} the second column and the six pixels 25 arranged at the intersections are representatively shown.

The gate lines GL ₁ , GL ₂ ,..., GL _m are respectively driven by gate line drive signals G ₁ , G ₂ ,..., G _m (generic name “gate line drive signal G”) generated by the gate line drive circuit 11. The The data lines DL _1, DL _2, ..., the DL _r, viewed from the drive control circuit 13 the data signals _{D 1, D 2, ...,} D r ( collectively, "display data signal D") are supplied. That is, each of the pixels 25 constituting the liquid crystal array unit 15 is driven by the gate line GL generated by the gate line driving circuit 11 and performs display according to the display data signal D from the drive control circuit 13.

  Each pixel 25 is formed on an insulating substrate such as glass or resin, and a liquid crystal element 28 is used as a display element. An N-type transistor is used as the pixel transistor 26 (active element in a broad sense) included in the pixel 25.

  The gate of the pixel transistor 26 is connected to the gate line GL, and the drain of the pixel transistor 26 is connected to the data line DL. The source of the pixel transistor 26 is connected to the pixel electrode Np. A storage capacitor element 27 and a liquid crystal element 28 are connected to the pixel electrode Np. The storage capacitor element 27 is connected between the pixel electrode Np and the capacitor line CCL corresponding to the pixel. The liquid crystal element 28 is connected between the pixel electrode Np and a common electrode (common electrode) Nc.

  In the pixel 25, when the gate line drive signal G for driving the corresponding gate line GL becomes the active level (H level), the pixel transistor 26 is turned on, and the voltage of the display data signal D supplied to the data line DL at that time is It is held in the holding capacitor element 27. The orientation of the liquid crystal in the liquid crystal element 28 changes according to the data (voltage) held in the holding capacitor element 27, and the display luminance of the pixel changes.

The drive control circuit 13 is composed of a single or a plurality of LSIs formed using a single crystal silicon substrate. The drive control circuit 13 is a source driver circuit (data signal output circuit) that outputs display data signals D ₁ , D ₂ , D ₃ ,... To be written to the pixels 25 to the data lines DL ₁ , DL ₂ , DL ₃ ,. A circuit for generating drive control signals (start signal st, clock signals clk, / clk and polarity control signals vfr, / vfr) necessary for operating the line drive circuit 11 and the capacitor line drive circuit 12, and a power supply voltage (voltage VH, VL, VCCH, VCCL) and the like.

  Further, the display device 10 includes a level conversion circuit 14 according to the present invention. The level conversion circuit 14 shifts the level of each drive control signal generated by the drive control circuit 13 to voltage level signals suitable for driving the gate line drive circuit 11 (start signal ST and clock signals CLK, / CLK). The level conversion circuit 14 is configured by using a plurality of level conversion circuits of the ninth embodiment (the circuit of FIG. 25), each of which uses an N-type transistor formed on the same insulating substrate as the pixel 25. Configured.

  Here, each drive control signal generated by the drive control circuit 13 is a signal whose H level is the voltage VDD and L level is the reference voltage GND, and is suitable for driving the gate line drive circuit 11 generated by the level conversion circuit 14. The signal having the voltage level is assumed to be a signal having the H level at the voltage VH and the L level at the voltage −VL.

  Each drive control signal generated by the drive control circuit 13 includes a start signal st, clock signals clk, / clk, and polarity control signals vfr, / vfr. The start signal st is a pulse signal that is activated at a timing corresponding to the start of each frame of the image signal. The clock signals clk, / clk are complementary signals (the active periods do not overlap), and the operation timing of the gate line driving circuit 11 is defined thereby. The polarity control signals vfr, / vfr are complementary signals whose levels are inverted every frame, and define the operation timing of the capacitor line driving circuit 12. Although details will be described later, the polarity control signals vfr, / vfr are operations corresponding to switching of the polarity of the voltage level of the pixel electrode Np of each pixel 25 (the polarity of the display data signal D written to the pixel 25). Is used as a control signal for causing the capacitor line driving circuit 12 to perform the above.

  The level conversion circuit 14 converts these signals into a start signal ST, clock signals CLK and / CLK, and polarity control signals VFR and / VFR, each having an H level voltage VH and an L level voltage −VL. That is, in the level conversion circuit 14, as in FIG. 25, the voltage VH is supplied to the high-side power supply node S4, and the voltage −VL is supplied to the low-side power supply node S3. In the present embodiment, the voltage VH and the voltage −VL are generated by the drive control circuit 13.

When the pixel matrix of the liquid crystal array unit 15 is driven by the gate line driving circuit 11, the start signal ST (start signal st) is activated at the timing at which scanning of the gate line GL is started. The gate line driving circuit 11 activates the start signal ST and activates the gate line driving signals G ₁ , G ₂ , G ₃ ,... In this order in synchronization with the activation timing of the clock signals CLK, / CLK. Make it.

  FIG. 30 is a timing chart showing the relationship between the drive control signal output from the drive control circuit 13 through the level conversion circuit 14 and the operation of the gate line drive circuit 11. As shown in FIG. 30, each of the clock signals CLK and / CLK is a pulse signal that is activated with a period of two horizontal periods (2H) of the display device 10, and both are in phase with each other by one horizontal period (1H). Is shifted. That is, the two clock signals CLK and / CLK constitute a two-phase clock that is shifted in phase by one horizontal period.

The start signal ST (start signal st) is activated at time t ₀ corresponding to the start of the frame period. The start signal ST is inactivated at time t ₁ immediately after that, and is maintained in an inactive state until the next frame period. At time t ₂ delayed by one horizontal period (1H) from time t ₀ , the clock signal CLK (clock signal clk) is activated, and at time t ₄ delayed by one horizontal period (1H) from time t ₂ , the clock signal / CLK (Clock signal / clk) is activated. Thereafter, the clock signals CLK and / CLK are alternately activated every horizontal period.

The gate line drive circuit 11 is composed of a plurality of cascade-connected shift registers (multi-stage shift registers), and gate line drive signals G ₁ , G ₂ , G ₃ ,. Hereinafter, each stage of the multistage shift register is referred to as a “unit shift register”). The start signal ST is input to the first stage unit shift register. The signals are sequentially transmitted from the first stage to the subsequent stage while being temporally shifted in synchronization with the clock signals CLK and / CLK. As a result, gate line drive signals G ₁ , G ₂ , G ₃ ,... Are output in this order from the gate line drive circuit 11 at a timing synchronized with the clock signals CLK, / CLK. As a result, the operation of activating the gate lines GL ₁ , GL ₂ , GL ₃ ,... In this order is repeated every horizontal period.

In the present embodiment, as shown in FIG. 29, the gate line driving circuit 11 includes, in addition to the m-th unit shift register (not shown) as the last stage, two-stage unit shift registers SR _{m + 1} , SR. _{m + 2} is provided. Since these unit shift registers SR _{m + 1} and SR _{m + 2} do not drive the gate line GL, they are hereinafter referred to as “dummy shift registers”. The output signals G _{m + 1} and G _{m + 2} of the dummy shift registers SR _{m + 1} and SR _{m + 2} do not drive the gate line GL, but are the same quality as the normal gate line driving signals G _{1 to} G _m. Therefore, they are referred to as “driving signals”.

  As the unit shift register constituting the gate line driving circuit 11 (multistage shift register), for example, the one disclosed in FIG. 7 of Japanese Patent Application Laid-Open No. 2004-103226 can be used. The unit shift registers SR are all composed of transistors of the same conductivity type, and can be driven using a two-phase clock signal.

  In the present embodiment, description will be made assuming that the gate line driving circuit 11 is configured by a shift register driven by two-phase clock signals CLK and / CLK. The required number of phases of the clock signal depends on the circuit configuration of the shift register constituting the clock signal.

As described above, the polarity control signals VFR and / VFR (polarity control signals vfr and / vfr) are signals that are inverted every frame period of the image signal. The polarity control signals VFR and / VFR are both input to the capacitor line driving circuit 12. The capacity line drive circuit 12 is a circuit that generates capacity line drive signals CC _{1 to} CC _m (generally “capacitance line drive signal CC”) for driving the capacity lines CCL _{1 to} CCL _m . In the capacitor line drive circuit 12, the polarity control signals VFR and / VFR are used as control signals for switching the polarity of the capacitor line drive signal CC in accordance with the change in the polarity of the display data signal D.

  Hereinafter, the capacitive line driving circuit 12 devised by the present inventor will be described. The capacitive coupling driving method using the capacitor line CCL includes a gate line inversion driving method for inverting the polarity of the display data signal D for each gate line GL, and a polarity of the display data signal D for each pixel 25 (for each data line DL). In this embodiment, the structure of the capacitor line driving circuit 12 used in the gate line inversion driving method will be described.

  FIG. 31 and FIG. 32 are circuit diagrams for explaining the configuration of the capacitor line driving circuit 12. The capacitance line drive circuit 12 is composed of a plurality of unit circuits that drive each of the capacitance lines CCL. FIG. 31 shows a unit circuit for driving the capacitor line CCL connected to the odd-numbered pixel line (odd row), and FIG. 32 shows a unit circuit for driving the capacitor line CCL connected to the even-numbered pixel line (even row). is there.

As shown in FIG. 29, the capacitor line driving circuit 12 includes the gate line driving signals G _{1 to} G _{m and the} driving signals G _{m + 1} and G _{m + 2} , clock signals CLK and / CLK, and polarity control signals VFR and / FR. The VFR is input, and capacitive line drive signals CC _{1 to} CC _m for driving the capacitive line CCL are generated based on these signals. In addition to the high-side power supply voltage VH and the low-side power supply voltage −VL, the power supply voltages supplied to the capacitor line drive circuit 12 include voltages VCCH and VCCL that respectively define the H level and L level of the capacitor line drive signal CC. Is supplied.

In the following, the odd-numbered gate line drive signals (G ₁ , G ₃ ,..., G _{n + 2} ,...) Are activated in synchronization with the clock signal CLK, and the even-numbered gate line drive signals (G ₂ , G _4). ,..., G _{n + 3} ,...) Are assumed to be activated in synchronization with the clock signal / CLK (n is an odd number). 31 and 32, it is assumed that the clock signal / CLK is input to the clock terminals CK100 of the odd-numbered unit circuits and the clock signal CLK is input to the clock terminals CK100 of the even-numbered unit circuits. To do.

  First, the unit circuits in the odd rows will be described. FIG. 31 representatively shows a unit circuit in the nth row.

As shown in FIG. 31, the unit circuit is configured by using only transistors of the same conductivity type, a polarity switching circuit for determining the polarity of the capacitor line drive signal CC _n, the polarity of the polarity switching circuit A level holding circuit for holding the levels of the switching signals PC and / PC and holding those levels with low impedance for one frame, and a capacitance line driving signal having a higher driving capability for the polarity switching signals PC and / PC It consists of an output circuit that converts it to CC _n and outputs it. Here, an example is shown in which an N-type transistor is used in the same manner as the pixel 25 in FIG. 29, but it is of course possible to use a P-type transistor.

The output circuit of the unit circuit as shown in FIG. 31, the output terminal OUT100 capacitance line drive signal CC _n, the transistor Q109 supplies an H-level voltage VCCH capacitance line drive signal CC _n, to the output terminal OUT100, capacity and a supplying transistor Q110 the L level voltage VCCL line drive signal CC _n. That is, the transistor Q109 is connected between the power supply terminal S104 supplied with the voltage VCCH and the output terminal OUT100, and the transistor Q110 is connected between the power supply terminal S103 supplied with the voltage VCCL and the output terminal OUT100. Yes. Here, nodes connected to the gate of the transistor Q109 and the gate of the transistor Q110 are defined as nodes N101 and N102, respectively.

The polarity switching circuit supplies polarity control signals VFR and / VFR to the nodes N101 and N102, respectively, according to the gate line driving signal G _{n + 2} input to the input terminal IN101. In other words, the polarity switching circuit is connected between the transistor Q101 connected between the input terminal IN102 to which the polarity control signal VFR is input and the node N101, and between the input terminal IN103 to which the polarity control signal / VFR is input and the node N102. The gates of the transistors Q101 and Q102 are both connected to an input terminal IN101 to which a gate line drive signal _{Gn + 2} is input.

Gate line driving signal G _{n + 2} is a signal for driving the gate line GL n _{+ 2} are two lines after the gate line GL _n corresponding to the unit circuit in the n-th row. Here, an easily obtainable gate line drive signal G _{n + 2} is used as a signal input to the input terminal IN101. However, any other signal can be used as long as it is activated at the same timing and has a predetermined voltage level. A signal may be used.

  A signal corresponding to the polarity control signal VFR supplied to the node N101 via the transistor Q101 becomes the polarity switching signal PC, and a signal corresponding to the polarity control signal / VFR supplied to the node N102 via the transistor Q102 Polarity switching signal / PC. Since the polarity control signals VFR and / VFR are complementary to each other, the polarity switching signals PC and / PC are also complementary to each other.

  The level holding circuit for holding the levels of the polarity switching signals PC and / PC is in principle a flip-flop (latch). As shown in FIG. 31, the level holding circuit includes six transistors Q103 to Q108 and two capacitive elements C101 and C102. The transistor Q103 is connected between the node N101 and the power supply terminal S1 to which the low-side power supply voltage −VL is supplied, and the gate thereof is connected to the node N102. Transistor Q104 is connected between node N102 and power supply terminal S1, and has its gate connected to node N101.

  The transistor Q105 is connected between the power supply terminal S2 to which the high-side power supply voltage VH is supplied and the node N101, and the transistor Q106 is connected between the second power supply terminal S2 and the node N102. A node to which the gate of the transistor Q105 is connected is defined as “node N103”, and a node to which the gate of the transistor Q106 is connected is defined as “node N104”. The node N103 is connected to the clock terminal CK100 to which the clock signal / CLK is input via the capacitive element C101, and the node N104 is connected to the clock terminal CK100 via the capacitive element C102.

  Transistor Q107 is connected between nodes N103 and N101, and transistor Q108 is connected between nodes N104 and N102. The gates of the transistors Q107 and Q108 are both connected to the power supply terminal S2.

  For example, when this level holding circuit holds the state where the node N101 (polarity switching signal PC) is at the H level and the node N102 (polarity switching signal / PC) is at the L level, the transistor Q103 is turned off and the transistor Q104 is turned on. At this time, the node N103 is charged through the transistor Q107 and becomes H level, and the node N104 is discharged through the transistor Q108 and becomes L level. As a result, the transistor Q105 is turned on and the transistor Q106 is turned off. Thereby, the H level of the polarity switching signal PC and the L level of the polarity switching signal / PC are maintained.

  At this time, since both the nodes N101 and N103 are at the H level, the transistor Q107 is off, and the node N103 is maintained at the H level in the floating state. Therefore, when the clock signal / CLK becomes H level, the node N103 is boosted by the coupling through the capacitive element C101, and the transistor Q105 is turned on in the non-saturated region. As a result, the polarity switching signal PC is maintained at the H level of the same voltage VH as that of the power supply terminal S2.

  On the other hand, the voltage level of node N104 also tends to rise due to coupling through capacitive element C102 when clock signal / CLK becomes H level. However, since the transistors Q108 and Q104 are on, the voltage rise at the node N104 is instantaneous and is maintained at almost the L level. That is, since the transistor Q106 is almost kept off, almost no through current flows through the transistors Q104 and Q106.

  The instantaneous voltage increase at the node N104 can be reduced by appropriately setting the on-resistance values of the transistors Q104 and Q108 and the capacitance value of the capacitive element C102, and the transistor Q106 can be more reliably maintained in the off state. Can do.

  Conversely, when the unit circuit holds the state in which the level holding circuit has the node N101 (polarity switching signal PC) at the L level and the node N102 (polarity switching signal / PC) at the H level, the transistor Q104 is turned on, Q103 turns off. Node N104 attains H level, transistor Q106 is turned on, and polarity switching signal / PC is maintained at H level. At the rising edge of clock signal / CLK, node N104 is boosted and transistor Q106 is turned on in the non-saturated region, so that polarity switching signal / PC is at the H level of voltage VH. On the other hand, since node N103 is substantially maintained at the L level and transistor Q105 is substantially maintained off, almost no through current flows through transistors Q105 and Q103.

  As described above, in the level holding circuit included in the unit circuit of FIG. 31, only the node that maintains the H level is pulled up without consuming almost any power, and the node that maintains the L level is pulled up. A selective pull-up operation is performed.

  Next, the unit circuits in even-numbered rows of the capacitor line driving circuit 12 will be described. FIG. 32 typically shows unit circuits in the (n + 1) th row (n is an odd number).

As shown in FIG. 32, the configuration of the unit circuit of the even-numbered row is almost the same as that of the unit circuit of the odd-numbered row (FIG. 31), but the capacity-line driving signal CC _{n + 1} of the even-numbered row Since the level needs to be inverted with respect to CC _n , the connections of the gates of the transistors Q109 and Q110 are interchanged with respect to FIG. Alternatively, the circuit configuration is not changed from that in FIG. 31, and the unit circuits in the even rows may be replaced with the polarity control signals VFR and / VFR input to the input terminals IN102 and IN103 (not shown).

  The signals input to the clock terminal CK100 in FIGS. 31 and 32 may be signals other than the clock signals CLK and / CLK as long as they are repetitive signals that alternate with a constant period. The clock signal input to the clock terminal CK100 is used to turn on the transistor Q105 (or Q106) in a non-saturation region at a constant period, whereby the H level voltage of the node N101 (or N102) due to the leakage current. The drop is compensated. As long as this leakage current can be sufficiently compensated, a clock signal having a lower frequency may be used, thereby reducing power consumption. However, the clock signal input to the clock terminal CK100 preferably has an active period that does not overlap with the active period of the signal input to the input terminal IN101.

Here, the gate line drive signals (G ₁ , G ₃ ,..., G _{n + 2} ,...) In the odd rows are activated in synchronization with the clock signal CLK, and the gate line drive signals (G ₂ , G ₄ ,. .., G _{n + 3} ,...) Are assumed to be activated in synchronization with the clock signal / CLK, so that the clock signal / CLK is input to the clock terminal CK100 of the odd-numbered unit circuit and the even-numbered row The clock signal CLK was input to the clock terminal CK100 of the unit circuit.

  Subsequently, the operation of the capacitor line driving circuit 12 according to the present embodiment will be described. Here, it is assumed that the threshold voltages of the transistors are all the same value Vth. Further, as described above, the voltages VCCL and VCCH supplied to the power supply terminals S103 and S104 are for defining the L level and H level voltages of the capacitance line drive signal CC, respectively. Since the capacitive line drive signal CC gives a constant voltage change to the pixel electrode by capacitive coupling, the voltages VCCH and VCCL are the voltage change amount that the voltage difference (amplitude of the capacitive line drive signal CC) gives to the pixel electrode. As long as the transistors Q109 and Q110 operate in the non-saturated region.

  FIG. 33 is a signal waveform diagram showing an operation of the capacitance line driving circuit 12. The polarity control signals VFR and / VFR are complementary to each other, and the levels alternate in the blanking period for each frame. Here, the period in which the polarity control signal VFR is at the H level is defined as “odd frame”, and the period at the L level is defined as “even frame”.

  Hereinafter, the operation of the capacitive line driving circuit 12 according to the present embodiment will be described. First, the operation of the unit circuit in the odd-numbered row will be described. Here, the operation of the unit circuit in the n-th row (FIG. 31) will be representatively described.

Referring to FIG. 33, at time t ₁ within the blanking period, when polarity control signals VFR, / VFR change to H level and L level, respectively, and become an odd frame, input terminal IN102 is set to voltage VH and input terminal IN103 is set. Are set to the voltage −VL, respectively. The levels of the nodes N101 to N104 and the output terminal OUT100 are determined by the operation in the immediately preceding frame period. Here, the nodes N101 and N103 and the output terminal OUT100 are at the L level, and the nodes N102 and N104 are at the H level.

In time t _2, the corresponding gate line driving signal G _n for driving the gate line GL _n becomes H level, the display data signal D is written in the n-th row of pixels 25. Then, at time t ₃ 1H after time t ₂ , the gate line drive signal G _n becomes L level.

Further at time t ₄ after 1H of time t _3, the gate line drive signal G _{n + 2} line after two becomes an H level (VH). Accordingly, the transistors Q101 and Q102 are turned on, and the levels of the polarity control signals VFR and / VFR are supplied to the nodes N101 and N102. More specifically, first, the node N102 (polarity switching signal / PC) becomes L level (−VL), and the transistors Q103 and Q110 are turned off. Since the transistor Q103 is turned off, the node N101 is charged through the transistor Q101, and the polarity switching signal PC becomes H level (VH−Vth). Accordingly, transistors Q104 and Q109 are turned on.

Node N104 is discharged through transistors Q108 and Q104 and becomes L level (−VL), and node N103 is charged through transistor Q107 and becomes H level (VH−Vth). The voltage VCCH as described above, the polarity switching signal / PC is set to a value in the range of transistor Q109 operates ratio saturated when it is H level, the capacitance line drive signal CC _n is the voltage VCCH H Become a level.

When the gate line drive signal G _{n + 2} becomes L at time t ₅ , the transistors Q101 and Q102 are turned off, so that the nodes N101 and N102 and the input terminals IN102 and IN103 are electrically separated. However, at this time, the H level of the polarity switching signal PC and the L level of the polarity switching signal / PC are held (latched) by the action of the level holding circuit described above.

At time t ₅ , the clock signal / CLK rises to the H level, so that the node N103 is boosted by the coupling through the capacitive element C101. Since node N103 is already charged to VH−Vth, the voltage level of node N103 becomes approximately 2 · VH−Vth by this boosting action. Accordingly, transistor Q105 is turned on in the non-saturated region, and node N101 rises to voltage VH.

When the clock signal / CLK becomes L level at time t _6, the transistor Q105 back to node-level N103 again VH-Vth is turned off, the node N101 is maintained in a high impedance state to the H-level voltage VH.

After time t ₆ , whenever the clock signal / CLK changes to the H level, the voltage level of the node N103 is boosted to about 2 · VH−Vth, the transistor Q105 is turned on in the non-saturated region, and the node N101 is set to the voltage VH. The operation of charging is repeated. Thereby, a decrease in the level of node N101 due to the leakage current is compensated, and polarity switching signal PC can be maintained at the H level of voltage VH. As a result, the transistor Q109 is maintained in the ON state in the non-saturation region, the said unit circuit can be maintained for one frame period, the H level (VCCH) of the capacitance line drive signal CC _n with low impedance.

At time t ₇ in the next blanking period, the polarity control signals VFR and / VFR change to L level and H level, respectively, and become even frames, but at this time, the transistors Q101 and Q102 are off. node N101 H level (polarity switching signal PC), without L-level change of the node N102 (polarity switching signal / PC), remains capacitance line drive signal CC _n is H level (VCCH).

Thereafter, at time t ₈ , the gate line drive signal G _n becomes H level, and the display data signal D is written to the pixels 25 in the nth row. The gate line drive signal G _n becomes L level at time t ₉ 1H after time t ₈ .

In addition the time t ₁₀ after the 1H time t _9, the gate line drive signal G _{n + 2} becomes an H level (VH). Accordingly, the transistors Q101 and Q102 are turned on, and the levels of the polarity control signals VFR and / VFR are supplied to the nodes N101 and N102. At this time, the polarity switching signal PC becomes L level (−VL) and the polarity switching signal / PC becomes H level (VH−Vth) by the operation opposite to the time t ₄ described above. Correspondingly transistor Q109 is turned off, the transistor Q110 is turned on, the capacitance line drive signal CC _n changes to the L level (VCCL).

When the gate line drive signal G _{n + 2} becomes L at time t ₁₁ , the transistors Q101 and Q102 are turned off, so that the nodes N101 and N102 and the input terminals IN102 and IN103 are electrically separated. However, at this time, the L level of the polarity switching signal PC and the H level of the polarity switching signal / PC are held (latched) by the action of the level holding circuit described above.

At time t ₁₁ , the clock signal / CLK rises to the H level, so that the node N104 is boosted by the coupling through the capacitive element C102. By this boosting action, the voltage level of the node N104 becomes approximately 2 · VH−Vth. In response, transistor Q106 is turned on in the non-saturated region, and node N102 rises to voltage VH.

When the clock signal / CLK becomes L level at time t _12, the transistor Q106 back to node-level N104 again VH-Vth is turned off, the node N101 is maintained in a high impedance state to the H-level voltage VH.

After time t ₆ , whenever the clock signal / CLK changes to the H level, the voltage level of the node N103 is boosted to about 2 · VH−Vth, and the operation of the transistor Q106 charging the node N101 to the voltage VH is repeated. As a result, the node N101 (polarity switching signal PC) maintains the H level of the voltage VH at the voltage VH. As a result, the transistor Q109 is maintained in the ON state in the non-saturation region, the said unit circuit can be maintained for one frame period, the L level (VCCL) of the capacitor line drive signal CC _n with low impedance.

  In this way, each of the odd-numbered unit circuits (FIG. 31) of the capacitor line driving circuit 12 writes the display data signal D to the corresponding pixel 25 in the odd-numbered frame (the activation of the corresponding gate line GL). After 1H from the (period), the capacitance line drive signal CC is changed from the L level to the H level. In an even frame, the capacitor line drive signal CC is changed from H level to L level after 1 H from the writing period of the display data signal D to the pixels 25 in the corresponding row.

  On the other hand, the operation of the unit circuit in the even-numbered row (FIG. 32) is almost the same as the operation of the unit circuit in the odd-numbered row described above. However, each of the even-numbered unit circuits changes the capacitance line drive signal CC from the H level to the L level 1H after the writing period of the display data signal D to the pixel 25 of the corresponding row in the odd-numbered frame. . In an even frame, the capacitor line drive signal CC is changed from the L level to the H level after 1 H of the writing period of the display data signal D to the pixels 25 in the corresponding row.

FIG. 34 is a signal waveform diagram showing the operation of the capacitor line drive circuit 12, and summarizes the behavior of the capacitor line drive signals CC in the odd and even rows. It can be seen that the level of each of the capacitance line drive signals CC changes 2H behind the rise of the gate line drive signal G corresponding to the same row (after 1H from the fall of the gate line drive signal G). . For example, the capacitance line drive signal CC _n corresponding to the n-th row (odd row) is delayed by 2H from the rise time of the gate line drive signal G _n corresponding to the same row (when the gate line drive signal G _n falls). After 1H, the level is reversed. Similarly, the level of the capacitor line drive signal CC _{n + 1} corresponding to the (n + 1) th row (even number row) is inverted with a delay of 2H from the rising edge of the gate line drive signal _{Gn + 1} . It can also be seen from the same figure that the direction of the level change of the capacitance line drive signal CC is reversed between the even-numbered rows and the several-hour rows within the same frame period.

  When capacitive coupling driving of the gate line inversion driving method is performed using the capacitive line driving signal CC whose level changes as shown in FIG. 34, when the display data signal D is written to each pixel 25, in the odd frame, the positive electrode is connected to the odd row. In the even frame, negative polarity is written in odd rows and positive polarity is written in even rows in even frames. To do. As a result, the voltage level of the pixel electrode Np to which the positive display data signal D is written is increased, the voltage level of the pixel electrode Np to which the negative display data signal D is written is decreased, and each display data signal D Will be amplified.

  As can be seen from the above description, the polarity control signals VFR and / VFR are used for the purpose of controlling the level of each capacitance line drive signal CC. They alternated during the blanking period and were fixed at a certain level during each frame period. However, since the unit circuit of the capacitive line driving circuit 12 shown in FIGS. 31 and 32 includes the level holding circuit for the polarity switching signals PC and / PC, strictly speaking, the polarity control signals VFR and / VFR are It is sufficient that each unit circuit has an appropriate value even at least for the active period of the signal input to the input terminal IN101, and it is not always necessary to maintain a constant level for one frame period. However, it should be noted that the power consumption increases when the alternating cycle of the polarity control signals VFR, / VFR is shortened (frequency is increased).

  In the above description, the level conversion circuit 14 has been described as being configured by using a plurality of the circuits of FIG. 25, but the circuit of FIG. 27 or FIG. 28 which is a modified example thereof can also be used. Since the pulse widths of the start signal st and the clock signals clk, / clk are narrow, the leakage currents of the transistors Q5A, Q6A in FIGS. May be omitted. Conversely, since the pulse widths of the polarity control signals vfr, / vfr are long corresponding to one frame period (about 16.7 ms), the current driving element I3A cannot be omitted in the circuit that performs the level conversion.

  Although not described, a power-on reset circuit for setting an initial value of the level conversion circuit 14 may also be formed on the same insulating substrate as the level conversion circuit 14 (the same insulating substrate as the pixel 25). In that case, the power-on reset circuit of FIG. 1 of Patent Document 2 described in the first modification of the first embodiment can be used. In that case, from the viewpoint of simplifying the manufacturing process, it is desirable that the power-on reset circuit is also configured using the same conductivity type (here, N-type) transistor as the pixel transistor 26 of the pixel 25.

FIG. 3 is a diagram illustrating a specific example of a configuration of a level conversion circuit according to the first embodiment. FIG. 3 is a signal waveform diagram illustrating an operation of the level conversion circuit according to the first embodiment. 6 is a diagram schematically showing a power-on reset circuit according to a modification of the first embodiment. FIG. It is a wave form diagram of a power-on reset signal. 1 is a diagram illustrating a configuration of a level conversion circuit according to a first embodiment. FIG. 3 is a diagram illustrating a configuration example of a current driving element in the first embodiment. FIG. 3 is a diagram illustrating a configuration example of a current driving element in the first embodiment. FIG. 6 is a diagram showing a configuration of a level conversion circuit according to a second embodiment. FIG. 6 is a signal waveform diagram showing an operation of the level conversion circuit according to the second embodiment. FIG. 6 is a diagram illustrating a configuration of a level conversion circuit according to a third embodiment. FIG. 10 is a diagram illustrating a configuration of a level conversion circuit according to a fourth embodiment. FIG. 10 is a diagram showing a configuration of a level conversion circuit according to a fifth embodiment. FIG. 10 is a diagram illustrating a configuration example of a current driving element in a fifth embodiment. FIG. 10 is a diagram illustrating a configuration of a level conversion circuit according to a sixth embodiment. FIG. 10 is a diagram illustrating a configuration example of a current driving element in a sixth embodiment. FIG. 10 is a diagram showing a configuration of a level conversion circuit according to a seventh embodiment. FIG. 10 is a signal waveform diagram showing an operation of the level conversion circuit according to the seventh embodiment. FIG. 20 is a diagram showing a modification example of the level conversion circuit according to the seventh embodiment. FIG. 10 is a signal waveform diagram showing an operation of the level conversion circuit according to the seventh embodiment. FIG. 10 is a diagram showing a configuration of a level conversion circuit according to an eighth embodiment. FIG. 10 is a signal waveform diagram illustrating an operation of a level conversion circuit according to an eighth embodiment. FIG. 20 is a diagram showing a modification example of the level conversion circuit according to the eighth embodiment. FIG. 20 is a diagram showing a modification example of the level conversion circuit according to the eighth embodiment. FIG. 20 is a diagram showing a modification example of the level conversion circuit according to the eighth embodiment. FIG. 10 is a diagram illustrating a configuration of a level conversion circuit according to a ninth embodiment. FIG. 20 is a signal waveform diagram illustrating an operation of a level conversion circuit according to the ninth embodiment. FIG. 20 is a diagram illustrating a modification example of the level conversion circuit according to the ninth embodiment. FIG. 20 is a diagram illustrating a modification example of the level conversion circuit according to the ninth embodiment. FIG. 16 is a schematic configuration diagram of an image display device according to a tenth embodiment. FIG. 22 is a signal waveform diagram illustrating an operation of the gate line driving circuit according to the tenth embodiment. FIG. 20 is a diagram showing a configuration of a unit circuit of a drive control circuit according to a tenth embodiment. FIG. 20 is a diagram showing a configuration of a unit circuit of a drive control circuit according to a tenth embodiment. FIG. 22 is a signal waveform diagram illustrating an operation of the drive control circuit according to the tenth embodiment. FIG. 22 is a signal waveform diagram illustrating an operation of the drive control circuit according to the tenth embodiment.

Explanation of symbols

  IN input terminal, INS input signal, OUT output terminal, OUTS output signal, RST reset terminal, I1A-I3A, I1B-I3B current drive element, POR power-on reset circuit, 1A, 1B, 40A, 40B push-pull circuit, 20A, 20B Bootstrap type load circuit, 100 input stage circuit, 110 push-pull circuit, 120 bootstrap type drive circuit, 130 output drive circuit.

Claims (4)

Having a first power source and a second power source;
An input signal having an amplitude smaller than the voltage difference between the first power supply and the second power supply changes between a voltage level corresponding to the voltage of the first power supply and a voltage level corresponding to the voltage of the second power supply. A level conversion circuit for converting a level into a signal,
An input terminal for receiving the input signal;
A first output node from which the level-converted signal is output;
A reset terminal for receiving a predetermined reset signal;
A first transistor of a predetermined conductivity type connected between the first output node and the first power supply and having a gate connected to the input terminal via a first capacitive element;
A second transistor of the predetermined conductivity type having a gate connected between the first node to which the gate of the first transistor is connected and the first power supply and connected to the reset terminal via a second capacitor;
A first current driving element connected between the second power source and the first output node;
A second current driving element connected between the second node to which the gate of the second transistor is connected and the first power supply ;
A level conversion circuit comprising: a third current driving element connected between the gate of the first transistor and a third power source . The third current driving element is a current limiting element.
The level conversion circuit according to claim 1. The first current driving element and the first transistor constitute an inverter,
The voltage level of the third power source is
Set between the threshold voltage of the inverter based on the voltage of the first power supply and the sum of the threshold voltage of the inverter and the amplitude voltage of the input signal based on the voltage of the first power supply Be done
The level conversion circuit according to claim 1 or 2. Having a first power source and a second power source;
An input signal having an amplitude smaller than the voltage difference between the first power supply and the second power supply changes between a voltage level corresponding to the voltage of the first power supply and a voltage level corresponding to the voltage of the second power supply. A level conversion circuit for converting a level into a signal,
An input terminal for receiving the input signal;
A first output node from which the level-converted signal is output;
A reset terminal for receiving a predetermined reset signal;
A first transistor of a predetermined conductivity type connected between the first output node and the first power supply and having a gate connected to the input terminal via a first capacitive element;
A second transistor of the predetermined conductivity type having a gate connected between the first node to which the gate of the first transistor is connected and the first power supply and connected to the reset terminal via a second capacitor;
A first current driving element connected between the second power source and the first output node;
A second current driving element connected between the second node to which the gate of the second transistor is connected and the first power supply;
A third transistor of the predetermined conductivity type connected between the first node and the first power source;
A fourth transistor of the predetermined conductivity type connected between the gate of the third transistor and the first power supply and having a gate connected to the first node;
A fifth transistor of the predetermined conductivity type connected between the gate of the third transistor and the second power supply and having a gate connected to the first output node;
A level conversion circuit characterized by that.

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