JP5248905B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a high breakdown voltage type semiconductor element having an element isolation layer formed on a silicon substrate by an STI method and a method for manufacturing the same.

In general, a high breakdown voltage type semiconductor element is used with a high gate voltage of 9 to 100 V. Therefore, a parasitic transistor is easily formed in the element formation region. When this parasitic transistor operates, the high breakdown voltage type semiconductor element operates normally. No longer.
For this reason, a channel stopper layer is formed immediately below the element isolation layer, and the threshold value of the parasitic transistor is increased to suppress the operation of the parasitic transistor.

Further, in the high breakdown voltage type semiconductor element, the breakdown voltage of the element is determined by the distance d (see FIG. 1) which is the distance between the opposite end portions of the low concentration diffusion layer and the channel stopper layer, as shown in FIG. The junction breakdown voltage Bvj decreases as the distance d decreases, and the breakdown voltage of the high breakdown voltage type semiconductor element decreases.
On the other hand, in recent years, high-voltage semiconductor elements have been rapidly miniaturized, and the influence of the distance d on the formation pitch of the semiconductor elements cannot be ignored. Using a resist mask formed by photolithography If a channel stopper layer is formed using a resist mask formed by photolithography after the element isolation layer is formed, the alignment of the resist mask in the two photolithography steps will be misaligned. In order to satisfy the characteristics, the distance d between the low-concentration diffusion layer and the channel stopper layer needs to be adjusted to a distance plus a margin, and the distance d must be set wide. This is one factor that makes it difficult to reduce the size of the device.

For this reason, in the conventional high breakdown voltage type semiconductor element, when the element isolation layer is formed by the LOCOS method, a silicon oxide film is formed on the P-type silicon substrate by the thermal oxidation method, and the silicon oxide film is formed thereon by the CVD method. A silicon nitride film, a polycrystalline silicon film, and a second silicon nitride film are formed, and a resist mask exposing the element isolation region is formed by photolithography, and the second silicon nitride film and the polycrystalline silicon are formed using the resist mask as a mask. The film and the first silicon nitride film are etched and removed by dry etching. After removing the resist mask, an element isolation layer is formed in the element isolation region by high-temperature oxidation by the LOCOS method, and the polycrystalline silicon film is oxidized. Using this ridge as a mask, a P-type impurity is implanted into a region under the element isolation layer, and a channel stop is formed immediately below the element isolation layer. The layers were formed in a self-aligned manner, thereby preventing the deviation of the mask alignment at the time of ion implantation (e.g., see Patent Document 1.).
JP-A-8-306768 (page 3, paragraph 0014-paragraph 0018, FIG. 1)

  However, in the conventional technique described above, the distance d between the low-concentration diffusion layer and the channel stopper layer in the high-breakdown-voltage semiconductor element (referred to as a high-breakdown-voltage element) is set to a predetermined distance without considering the alignment margin of the resist mask. Therefore, it is an effective means for miniaturization of the high breakdown voltage element. However, the channel stopper layer is formed in a self-aligning manner by utilizing the high temperature oxidation of the silicon layer peculiar to the LOCOS (Local Oxidation of Silicon) method. Therefore, the element isolation layer is formed by the STI (Shallow Trench Isolation) method, which is advantageous for downsizing of the high breakdown voltage element because the element isolation layer can be formed with higher accuracy than the LOCOS method. There is a problem that it cannot be applied to the formation of the channel stopper layer.

  For this reason, when the channel stopper layer is formed using a resist mask formed by photolithography after the element isolation layer is formed by the STI method, it is necessary to consider the alignment margin of the resist mask. The distance d to the channel stopper layer must be set wider than a predetermined distance, which causes a problem that it is difficult to reduce the size of the high breakdown voltage element.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide means for forming a channel stopper layer in a self-aligned manner when an element isolation layer is formed by the STI method.

  In order to solve the above problems, the present invention provides a silicon substrate in which an element formation region and an element isolation region surrounding the element formation region are set, and an isolation formed in the element isolation region of the silicon substrate. A groove, a protrusion formed at the center of the groove bottom of the separation groove by the silicon substrate and having a height lower than the groove depth of the separation groove, and an insulating material embedded in the separation groove; An element isolation layer having the protrusions, and a channel stopper layer formed by diffusing a first conductivity type impurity in a silicon substrate immediately below the protrusions.

  Further, a method for manufacturing a semiconductor element includes a step of preparing a silicon substrate in which an element formation region and an element isolation region surrounding the element formation region are set, and a step of forming a silicon oxide film on the silicon substrate; Forming a silicon nitride film on the silicon oxide film; forming an opening exposing the silicon oxide film in the element isolation region of the silicon nitride film; and opening the silicon nitride film Forming an insulating material layer on the entire surface of the silicon substrate including the inside of the silicon substrate; and etching the insulating material layer by anisotropic etching to form the insulating material layer on a side surface of the opening of the silicon nitride film. A step of forming a groove reaching the silicon oxide film in a central portion of the element isolation region; and a silicon material is embedded in the groove to leave the remaining insulating material And forming a silicon material layer in the center of the element isolation region, and anisotropic etching using the silicon nitride film in which the opening is formed as a mask, the silicon oxide film, the silicon material layer, and Etching the silicon substrate to form an isolation groove in the element isolation region, and forming a protrusion having a height lower than the depth of the isolation groove at the center of the groove bottom; insulating the isolation groove; Embedding a material to form an element isolation layer in which the protrusion is embedded; forming a resist mask exposing the element isolation layer on the protrusion; and the resist mask and the element isolation layer And a step of forming a channel stopper layer by implanting a first conductivity type impurity into the silicon substrate immediately below the protrusion.

  Thus, according to the present invention, after the opening is formed in the element isolation region of the silicon nitride film, the protrusion can be formed in a self-aligned manner in the central portion of the element isolation region using the formed opening as a proof. The channel stopper layer can be selectively formed directly below the element isolation layer by using the protrusion and utilizing the difference in the range between the element isolation layer and the silicon substrate, and the channel stopper layer is formed. Therefore, it is possible to form the channel stopper layer in a self-aligned manner without considering the alignment margin of the resist mask, and the distance d between the low concentration diffusion layer and the channel stopper layer is separated by a predetermined distance and increased. There is an effect that the pressure resistance of the withstand voltage element can be stabilized.

  Embodiments of a semiconductor device and a method for manufacturing the same according to the present invention will be described below with reference to the drawings.

FIG. 1 is an explanatory view showing a cross section of the semiconductor element of Example 1, and FIGS. 2, 3, and 4 are explanatory views showing a method for manufacturing the semiconductor element of Example 1. FIG.
In FIG. 1, reference numeral 1 denotes a high breakdown voltage type nMOS (Metal Oxide Semiconductor) element as a semiconductor element.
Reference numeral 2 denotes a silicon substrate, which is a substrate made of silicon (Si) in which a P-type impurity such as boron (B), which is the first conductivity type impurity of this embodiment, is diffused at a relatively low concentration. An element isolation region 4 for forming an element isolation region 12 (described later) surrounding the periphery of the element formation region 3 is formed.

Reference numeral 5 denotes a gate insulating film, which is a relatively thin insulating film made of an insulating material such as silicon oxide (SiO ₂ ).
Reference numeral 6 denotes a gate electrode, which is an electrode made of polysilicon or the like, and is formed opposite to the silicon substrate 2 in the element formation region 3 with the gate insulating film 5 interposed in the center of the element formation region 3 in the gate length direction. On the side surfaces, sidewalls 7 made of an insulating material such as silicon nitride (Si ₃ N ₄ ) are formed.

  Between the element isolation regions 4 of the silicon substrate 2 on both sides of the gate electrode 6 in the element formation region 3, phosphorus (which is a second conductivity type impurity of the present embodiment, which is of a type opposite to the P type at a relatively high concentration, is used. A low concentration diffusion layer 8 is formed by diffusing N-type impurities such as P) and arsenic (As) at a relatively low concentration, and is formed on the surface layer between the sidewall 7 of the low concentration diffusion layer 8 and the element isolation region 4. The source layer 9 and drain layer 10 in which N-type impurities are diffused at a relatively high concentration are formed, and the surface layer of the silicon substrate 2 in which P-type impurities are diffused at a low concentration under the gate electrode 6 is It functions as a channel region of the nMOS element 1 of the embodiment.

An element isolation layer 12 is formed in the element isolation region 4 around the element formation region 3 where the nMOS element 1 is formed to electrically isolate and isolate adjacent element formation regions 3 by the STI method. ing.
The element isolation layer 12 of this embodiment is formed by embedding an insulating material such as silicon oxide in the isolation groove 13 formed in the element isolation region 4. A protrusion 14 made of the silicon substrate 2 with a height less than the depth of the groove 13 is formed, and is relatively far from the end of the low-concentration diffusion layer 8 immediately below the protrusion 14 at a distance d. A channel stopper layer 15 is formed in which a P-type impurity is diffused at a high concentration to suppress the operation of the parasitic transistor.

Impurity ion implantation into the channel stopper layer 15 of the present embodiment is performed utilizing the fact that the impurity ion range Rp in the silicon substrate 2 at the time of ion implantation is larger than the impurity ion range Rp of the silicon oxide film. Is called.
For this reason, the width W of the protrusion 14 of this embodiment is set to the width of the channel stopper layer 15, and its height H is lower than the groove depth D 1 of the isolation groove 13, that is, the element isolation layer 12. It is set to be buried inside

In this case, the groove depth D1 of the separation groove 13 is formed by embedding an insulating material in the separation groove 13 of impurity ions implanted into the channel stopper layer 15 under a predetermined implantation condition. The depth is set to be deeper than the range Rp in the element isolation layer 12 and shallower than the range Rp in the silicon substrate 2.
For example, when the insulating material is silicon oxide and the ion species is phosphorus, the range Rp in silicon oxide at an implantation energy of 1000 keV is 0.93 μm and the range Rp in silicon is 1.1 μm. The depth D1 of the groove 13 from the top surface of the silicon substrate 2 is set to be deeper than 0.93 μm and shallower than 1.1 μm, and the depth D2 from the top surface of the silicon substrate 2 at the top of the protrusion 14 is from 0.93 μm. Set to a shallow depth.

  After forming the element isolation layer 12 in which the projecting portion 14 made of the silicon substrate 2 is embedded by embedding silicon oxide in the isolation groove 13 formed to such a depth, if the impurity ions are implanted, the projecting portion 14 Impurity ions do not reach the bottom of the trench in the region where no impurity is formed, and the impurity ions reach the projection 14 through silicon oxide thinner than 0.93 μm. Since it passes through, it becomes possible to selectively implant impurity ions into the silicon substrate 2 immediately below the protrusions 14 using the difference in the range Rp using the element isolation layer 12 as a mask.

2 to 4, reference numeral 20 denotes a resist mask as a mask member, which exposes and develops a positive type or negative type resist applied by spin coating or the like on the upper surface side of the silicon substrate 2 by photolithography. The formed mask pattern functions as a mask in the etching process and ion implantation process of the present embodiment.
In the following, a method for manufacturing a semiconductor device of this example will be described according to a process indicated by P in FIGS.

P1 (FIG. 2), a P-type silicon substrate 2 in which an element formation region 3 and an element isolation region 4 are set is prepared, and a silicon oxide film 21 made of silicon oxide is formed on the silicon substrate 2 by thermal oxidation. A silicon nitride film 22 made of silicon nitride is deposited on the silicon oxide film 21 by a CVD (Chemical Vapor Deposition) method.
Then, a resist mask 20 in which the silicon nitride film 22 in the element isolation region 4 is exposed is formed on the silicon nitride film 22 by photolithography.

P2 (FIG. 2), using the resist mask 20 formed in step P1 as a mask, the silicon nitride film 22 is etched by anisotropic etching to reach the silicon oxide film 21 in the element isolation region 4 of the silicon nitride film 22 Opening 23 is formed.
After the removal of the resist mask 20, 4000 絶 縁 of an insulating material layer 24 made of an insulating material (silicon oxide in this embodiment) is deposited on the entire surface of the silicon substrate 2 by a CVD method to insulate the opening 23. Embed the material.

  Next, the insulating material layer 24 is etched by anisotropic etching to expose the silicon nitride film 22, and the same insulation as that of the sidewall 7 formed on the gate electrode 6 is formed on the side surface of the opening 23. The material layer 24 is left, and a groove 25 reaching the silicon oxide film 21 with a width larger than the width of the protrusion 14 is formed in the center of the element isolation region 4 in a self-aligned manner, and is formed on the silicon substrate 2 by CVD. A silicon material layer 26 made of a silicon material (polysilicon in this embodiment) is deposited on the entire surface of the substrate, and the silicon material is embedded in the trench 25.

The silicon material layer 26 was polished by P4 (FIG. 2), CMP (Chemical Mechanical Polishing) method to expose the silicon nitride film 22, and left on the side surface of the opening 23 by wet etching with hydrofluoric acid (HF). The insulating material layer 24 is removed, and a silicon material layer 26 protruding at the center of the element isolation region 4 is formed.
The silicon material layer 26 protruding to the center of the element isolation region 4 can change the height of the silicon layer with the silicon substrate 2 adjacent to both sides of the silicon material layer 26. By making a difference in depths D1 and D2 (see FIG. 1) from the upper surface of the later silicon substrate 2, it is possible to form the protrusions 14 at the portions where the silicon material layer 26 protrudes.

  P5 (FIG. 3), using the silicon nitride film 22 having the opening 23 formed as a mask, the silicon oxide film 21 and the protruding silicon material layer 26 and the silicon substrate 2 under each of them are etched by anisotropic etching. As shown in FIG. 5, an isolation groove 13 surrounding the periphery of the element formation region 3 is formed, and a width W and a height H lower than the groove depth D1 are formed at the center of the groove bottom of the isolation groove 13. The protrusion 14 is formed.

Then, an insulating material 27 made of silicon oxide is deposited on the silicon nitride film 22 and inside the isolation groove 13 by P6 (FIG. 3), and the insulating layer 27 is formed.
P7 (FIG. 3), the insulating layer 27 is polished by CMP to expose the silicon nitride film 22, and the silicon nitride film 22, the silicon oxide film 21 and the insulating layer 27 are removed by wet etching to form a silicon substrate. 2 is exposed, and an isolation layer 12 is formed in the isolation groove 13 with an insulating material made of silicon oxide and having a protrusion 14 embedded in the center.

  Next, a resist mask 20 having an opening 28 in which the element isolation layer 12 on the protrusion 14 is exposed with a width wider than the width W of the protrusion 14 is formed on the silicon substrate 2 by photolithography, and this is used as a mask. A channel stopper layer in which a P-type impurity (boron in this embodiment) is implanted, and the P-type impurity is diffused at a relatively high concentration in the silicon substrate 2 immediately below the protrusion 14 by utilizing the range Rp. 15 is formed.

In this way, the protrusion 14 formed in a self-aligned manner is used on the silicon substrate 2 directly below the element isolation layer 12 formed by the STI method, and the range Rp of the element isolation layer 12 and the silicon substrate 2 is reduced. Using the difference, the channel stopper layer 15 is selectively formed without considering misalignment of the resist mask 20.
P8 (FIG. 3), the resist mask 20 formed in the process P7 is removed, and the upper surface of the silicon substrate 2 in the element formation region 3 is oxidized by a thermal oxidation method to form a gate insulating film 5, and on the gate insulating film 5 and A polysilicon film for forming the gate electrode 6 is deposited on the element isolation layer 12 by the CVD method, and a resist mask that covers the formation region of the gate electrode 6 in the element formation region 3 is formed on the polysilicon film by photolithography. 20 (not shown) is formed, and the polysilicon film and the gate insulating film 5 exposed by anisotropic etching are etched to form the gate electrode 6 facing the silicon substrate 2 through the gate insulating film 5.

  P9 (FIG. 4), a resist mask 20 is formed by exposing a part of the element formation region 3 and the element isolation layer 12 adjacent to the periphery thereof, that is, covering the protrusion 14 by photolithography, and using this as a mask An element isolation layer in which an N-type impurity (phosphorus in this embodiment) is implanted and the N-type impurity is diffused at a relatively low concentration in the silicon substrate 2 between the gate electrode 6 and the element isolation layer 12. A low-concentration diffusion layer 8 having a depth shallower than the depth D1 of 12 groove bottoms is formed.

As a result, the low-concentration diffusion layer 8 having the end portion is reliably formed at a position (see FIG. 1) spaced from the end portion with the channel stopper layer 15 by the distance d.
The resist mask 20 formed in P10 (FIG. 4) and Step P9 is removed, and silicon nitride is deposited on the entire surface of the silicon substrate 2 such as on the gate electrode 6 by a CVD method to form a silicon nitride film. The silicon nitride film is etched by etching to expose the upper surface of the gate electrode 6 and the upper surface of the silicon substrate 2, and sidewalls 7 are formed on the side surfaces of the gate electrode 6.

  Then, using the gate electrode 6, the side wall 7 and the element isolation layer 12 as a mask, an N-type impurity (arsenic in this embodiment) is implanted into the exposed silicon substrate 2 in the element formation region 3. A source layer 9 and a drain layer 10 in which N-type impurities are diffused at a relatively high concentration are formed between the side wall 7 of the surface layer of the low-concentration diffusion layer 8 on both sides and the element isolation layer 12.

  In the nMOS device 1 of this embodiment formed as described above, an opening 23 is formed in the element isolation region 4 of the silicon nitride film 22 formed on the silicon substrate 2, and the insulation embedded in the opening 23 is formed. The material layer 24 is etched by anisotropic etching so that the insulating material layer 24 remains on the side surface of the opening 23 of the silicon nitride film 22 and a groove 25 reaching the silicon oxide film 21 is formed at the center of the element isolation region 4. Then, a silicon material is embedded in the groove 25 to project a silicon material layer 26 at the center of the element isolation region 4, and the silicon material layer 26 and silicon are formed by anisotropic etching using the silicon nitride film 22 as a mask. The substrate 2 is etched to form an isolation groove 13 in the element isolation region 4, and a protrusion 14 made of the silicon substrate 2 is formed at the center of the groove bottom to form the isolation groove 3 is formed by embedding an insulating material to form the element isolation layer 12 in which the protrusions 14 are embedded, and then a resist mask 20 exposing the element isolation layer 12 on the protrusions 14 is formed, and the element isolation layer 12 is masked. As a channel stopper layer 15 is formed by injecting a P-type impurity at a high concentration into the silicon substrate 2 immediately below the protrusion 14, the opening 23 is formed in the element isolation region 4 of the silicon nitride film 22 using the resist mask 20. After the formation, the protrusion 14 can be formed in the center of the element isolation region 4 in a self-aligned manner using the formed opening as a proof, and the element isolation layer 12 and silicon are formed using the protrusion 14. A channel stopper layer 15 can be selectively formed immediately below the element isolation layer 12 by utilizing the difference in the range Rp with the substrate 2, and a resist mask 20 for forming the channel stopper layer 15. The channel stopper layer 15 can be formed in a self-aligned manner without considering the alignment margin, and the distance d between the low concentration diffusion layer 8 and the channel stopper layer 15 is separated by a predetermined distance, thereby The pressure resistance can be stabilized.

  Also, the groove depth D1 of the isolation groove 13 is set to be deeper than the range Rp of the impurity ions in the element isolation layer 12 when the impurity ions are implanted into the channel stopper layer 15 under predetermined injection conditions. Since it is formed at a depth shallower than the range Rp, impurity ions are selectively applied to the silicon substrate 2 immediately below the protrusions 14 made of the silicon substrate 2 formed in a self-aligned manner using the element isolation layer 12 as a mask. The channel stopper layer 15 can be formed in a self-aligned manner without considering the alignment margin of the resist mask 20 for forming the channel stopper layer 15.

  Further, since the low concentration diffusion layer 8 is formed shallower than the element isolation layer 12, the distance d between the low concentration diffusion layer 8 and the channel stopper layer 15 is utilized by utilizing the perpendicularity of the side surface of the isolation groove 13 by anisotropic etching. Can be reliably separated by a predetermined distance, and the width of the element formation region 3 for forming the element isolation layer 12 can be reduced without considering the alignment margin of the resist mask 20 for forming the channel stopper layer 15. Thus, the high voltage element can be miniaturized.

  As described above, in this embodiment, a silicon oxide film and a silicon nitride film are stacked on a silicon substrate, and an opening in which the silicon oxide film is exposed is formed in an element isolation region of the silicon nitride film. An insulating material layer is formed on the entire surface of the silicon substrate including the inside of the opening of the silicon nitride film, the insulating material layer is etched by anisotropic etching, and the insulating material layer is formed on the side surface of the opening of the silicon nitride film. A trench reaching the silicon oxide film is formed in the central portion of the element isolation region, and a silicon material is embedded in the trench, and the remaining insulating material is removed, and a silicon material layer is formed in the central portion of the element isolation region. The silicon oxide film, the silicon material layer, and the silicon substrate are etched by anisotropic etching using the silicon nitride film with the opening formed as a mask, thereby isolating the element. An element isolation layer in which an isolation groove is formed in the region, a protrusion having a height lower than the groove depth of the isolation groove is formed at the center of the groove bottom, and the protrusion is embedded by embedding an insulating material in the isolation groove Then, a resist mask exposing the element isolation layer on the protrusion is formed, and using the resist mask and the element isolation layer as a mask, a P-type impurity is implanted into the silicon substrate immediately below the protrusion. By forming the channel stopper layer, after the opening is formed in the element isolation region of the silicon nitride film, the protrusion is formed in a self-aligned manner at the center of the element isolation region as a proof of the formed opening. The channel stopper layer can be selectively formed directly below the element isolation layer using the difference in the range Rp between the element isolation layer and the silicon substrate by using the protrusion. Stopper layer The channel stopper layer can be formed in a self-aligned manner without considering the alignment margin of the resist mask for forming, and the distance d between the low concentration diffusion layer and the channel stopper layer is separated by a predetermined distance. Thus, the breakdown voltage of the high breakdown voltage element can be stabilized.

In addition, since the low concentration diffusion layer is formed shallower than the element isolation layer, the distance d between the low concentration diffusion layer and the channel stopper layer is set by utilizing the perpendicularity of the side surface of the isolation groove by anisotropic etching. The element can be reliably separated by a predetermined distance, and the width of the element formation region for forming the element isolation layer can be reduced to reduce the size of the high breakdown voltage element.
In the above embodiments, the semiconductor element is described as an nMOS element, but it may be a pMOS element. In this case, an N-type impurity is used as the first conductivity type impurity, and a P-type impurity is used as the second conductivity type impurity.

Explanatory drawing which shows the cross section of the semiconductor element of Example 1. Explanatory drawing which shows the manufacturing method of the semiconductor element of Example 1. Explanatory drawing which shows the manufacturing method of the semiconductor element of Example 1. Explanatory drawing which shows the manufacturing method of the semiconductor element of Example 1. Explanatory drawing which shows the upper surface of the silicon substrate of process P5 of Example 1. Graph showing the relationship between junction breakdown voltage and distance d

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 nMOS element 2 Silicon substrate 3 Element formation area 4 Element isolation area 5 Gate insulating film 6 Gate electrode 7 Side wall 8 Low concentration diffusion layer (second diffusion layer)
DESCRIPTION OF SYMBOLS 9 Source layer 10 Drain layer 12 Element isolation layer 13 Separation groove 14 Protrusion 15 Channel stopper layer 20 Resist mask 21 Silicon oxide film 22 Silicon nitride film 23, 28 Opening 24 Insulating material layer 25 Groove 26 Silicon material layer 27 Insulating layer

Claims (5)

A silicon substrate in which an element formation region and an element isolation region surrounding the element formation region are set;
An isolation groove formed in an element isolation region of the silicon substrate;
A protrusion formed by the silicon substrate at the center of the groove bottom of the separation groove and having a height lower than the groove depth of the separation groove;
An element isolation layer having the protrusion embedded in an insulating material embedded in the isolation trench;
A semiconductor device comprising: a channel stopper layer formed by diffusing a first conductivity type impurity in a silicon substrate immediately below the protrusion. In claim 1,
The depth of the isolation trench is such that impurity ions implanted into the channel stopper layer are deeper than the range in the element isolation layer and shallower than the range in the silicon substrate. Semiconductor element. In claim 1 or claim 2,
A gate electrode facing the silicon substrate across a gate insulating film at a central portion of the element formation region of the silicon substrate;
Shallow than the element isolation layer formed by diffusing a second conductivity type impurity opposite to the first conductivity type impurity in the silicon substrate between both sides of the gate electrode and the element isolation layer. A semiconductor device comprising: a low-concentration diffusion layer having a depth. Preparing a silicon substrate in which an element formation region and an element isolation region surrounding the element formation region are set;
Forming a silicon oxide film on the silicon substrate;
Forming a silicon nitride film on the silicon oxide film;
Forming an opening exposing the silicon oxide film in the element isolation region of the silicon nitride film;
Forming an insulating material layer on the entire surface of the silicon substrate including the inside of the opening of the silicon nitride film;
The insulating material layer is etched by anisotropic etching so that the insulating material layer remains on the side surface of the opening of the silicon nitride film, and a groove reaching the silicon oxide film is formed at the center of the element isolation region And a process of
Embedding a silicon material in the trench, removing the remaining insulating material, and forming a silicon material layer in a central portion of the element isolation region;
Using the silicon nitride film having the opening as a mask, the silicon oxide film, the silicon material layer, and the silicon substrate are etched by anisotropic etching to form an isolation groove in the element isolation region, and the groove bottom Forming a protrusion having a height lower than the depth of the separation groove at the center of
Embedding an insulating material in the isolation trench to form an element isolation layer in which the protrusion is embedded;
Forming a resist mask exposing the element isolation layer on the protrusion; and
And a step of forming a channel stopper layer by implanting a first conductivity type impurity into a silicon substrate immediately below the protrusion using the resist mask and the element isolation layer as a mask. Production method. In claim 4,
Removing the resist mask after forming the channel stopper layer, and forming a gate electrode facing the silicon substrate with a gate insulating film in between at the center of the element formation region of the silicon substrate;
A second conductivity type impurity opposite to the first conductivity type impurity is diffused in the silicon substrate between both sides of the gate electrode and the element isolation layer so as to have a shallower depth than the element isolation layer. Forming a low-concentration diffusion layer having a semiconductor element manufacturing method.

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