JP5287112B2 - Data transfer control device and electronic device - Google Patents

Description

  The present invention relates to a data transfer control device, an electronic device, and the like.

  In recent years, USB serial interfaces standardized by USB 2.0 (Universal Serial Bus 2.0) have become widespread. For example, it is widely used as an interface for connecting electronic devices such as a connection between a personal computer and peripheral devices, a connection between a printer and a digital camera, and a connection between a car navigation system and portable audio.

  By the way, a hub is generally used to connect a USB host controller and a plurality of devices. That is, a host controller is connected to the upstream port circuit of the hub via USB, and a plurality of devices are connected to the downstream port circuit of the hub via USB. The hub interfaces with a plurality of devices.

However, in such a configuration, there is a problem that the connection target of the upstream port circuit is fixed to the host controller, and the connection target of the downstream port circuit is fixed to the device. For example, there is a problem that an electronic device that can operate as a host controller cannot be connected to a downstream port circuit, or the upstream port side cannot be operated as a device.
JP 2007-172574 A

  According to some aspects of the present invention, it is possible to provide a data transfer control device and an electronic device that can switch a port connection target.

  One aspect of the present invention includes an upstream port circuit, a plurality of downstream port circuits, and a hub logic circuit that performs data transfer control between the upstream port circuit and the plurality of downstream port circuits. , An upstream / downstream port circuit is provided as at least one of the plurality of downstream port circuits. In the hub mode, the upstream port circuit performs an upstream port operation, and the upstream / downstream port circuit is down In the device mode, the upstream port circuit performs interface processing with the physical layer circuit of the upstream / downstream port circuit, and the upstream / downstream port circuit is upstream. Relating to the data transfer control device and performs over preparative operation.

  According to one aspect of the present invention, in the hub mode, the upstream / downstream port circuit is switched to the downstream port circuit, and the hub logic circuit performs data transfer control between the upstream port circuit and the downstream port circuit. On the other hand, in the device mode, the upstream / downstream port circuit is switched to the upstream port circuit, and the upstream port circuit performs interface processing with the physical layer circuit of the upstream / downstream port circuit.

  As described above, in one embodiment of the present invention, the hub mode and the device mode can be switched. Specifically, the operation as the hub and the operation as the physical layer circuit on the device side can be switched. Thereby, it is possible to connect a connection target capable of switching between the host operation and the device operation to the upstream port circuit and the upstream / downstream port circuit. Data can be transferred even when the host operation and device operation to be connected are switched. Alternatively, data can be transferred even when the connection target of the upstream port circuit and the upstream / downstream port circuit is replaced from the host controller to the device, or from the device to the host controller.

  In one aspect of the present invention, the upstream port circuit is connected to a first host / device controller capable of switching between host operation and device operation, and the upstream port circuit is connected to the first host / device. Interface processing with the link layer circuit of the controller is performed. In the hub mode, interface processing between the link layer circuit of the first host / device controller that performs a host operation and the hub logic circuit is performed. Interface processing between the link layer circuit of the first host / device controller that performs the operation and the physical layer circuit of the upstream / downstream port circuit may be performed.

  According to an aspect of the present invention, the upstream port circuit performs interface processing with the link layer circuit of the first host / device controller without passing through the physical layer circuit. Thereby, the physical layer circuit on the first host / device controller side and the physical layer circuit of the upstream port circuit can be omitted. Therefore, in the device mode, the physical layer circuit of the upstream / downstream port circuit is interfaced with the link layer circuit of the first host / device controller without passing through the physical layer circuit. As a result, the upstream / downstream port circuit can operate as a physical layer circuit corresponding to the first host / device controller.

  In addition, since the physical layer circuit of the upstream port circuit can be omitted, the circuit scale can be reduced. Further, since the signal delay in the transceiver can be eliminated, the propagation delay of data transfer with the first host / device controller can be reduced.

  In one aspect of the present invention, the upstream / downstream port circuit is connected to a second host / device controller capable of switching between host operation and device operation, and the upstream / downstream port circuit is connected in the hub mode. Interface processing between the second host / device controller that performs device operation and the hub logic circuit, and in the device mode, the second host / device controller that performs host operation and the upstream port circuit Interface processing may be performed.

  Thus, data transfer can be performed by switching between the host operation and the device operation of the second host / device controller while the second host / device controller is connected to the upstream / downstream port circuit. Alternatively, data transfer can be performed by replacing the second host / device controller that performs the host operation with the upstream / downstream port circuit or by replacing the second host / device controller that performs the device operation.

  In one aspect of the present invention, in the hub mode, a device is connected to the upstream / downstream port circuit, the upstream / downstream port circuit performs an interface process between the device and the hub logic circuit, and In the device mode, a host controller may be connected to the upstream / downstream port circuit, and the upstream / downstream port circuit may perform an interface process between the host controller and the upstream port circuit.

  Thereby, a host controller can be connected to the upstream / downstream port circuit, or data can be transferred by connecting a device.

  In one aspect of the present invention, the upstream port circuit includes a first interface circuit that performs an interface process with a link layer circuit of the first host / device controller, and the first interface circuit includes: It may be connected to the first host / device controller via a bus of ULPI standard (UTMI + Low Pin Interface), and may perform ULPI interface processing with the link layer circuit of the first host / device controller.

  In this way, it is possible to connect the first host / device controller with the ULPI standard bus as a synchronous interface. Thereby, the bit loss by synchronization can be reduced.

  In the aspect of the invention, the upstream port circuit includes a wrapper circuit that performs a wrapper process between the ULPI standard bus of the first interface circuit and the bus of the upstream / downstream port circuit, One host / device controller may have a ULPI register for controlling a physical layer circuit of the upstream / downstream port circuit.

  In this way, it is possible to wrap between the upstream / downstream port circuit bus and the ULPI standard bus of the first host / device controller. Thereby, an operation as a physical layer circuit corresponding to the first host / device controller can be realized.

  Also, in one aspect of the present invention, the wrapper circuit is connected to the upstream / downstream port circuit by a UTMI standard (USB 2.0 Transceiver Macrocell Interface) bus, and the ULPI standard bus of the first interface circuit and the Wrapper processing may be performed between the UTMI standard bus of the upstream / downstream port circuit.

  In this way, it is possible to realize wrapper processing between the UTMI bus of the upstream / downstream port circuit and the ULPI standard bus of the first host / device controller.

  Further, according to an aspect of the present invention, a switching control circuit that performs switching control between the hub mode and the device mode based on a register value of the ULPI register may be included.

  In this way, switching between the hub mode and the device mode can be realized. For example, switching of the operation of the upstream port circuit and switching of the operation of the upstream / downstream port circuit can be realized.

  In one aspect of the present invention, the upstream port circuit includes a first interface circuit that performs an interface process with a link layer circuit of the first host / device controller, and the first interface circuit includes: It may be connected to the first host / device controller via a UTMI standard bus and perform UTMI interface processing.

  In this way, it is possible to connect to the first host / device controller via a UTMI standard bus that is a synchronous interface. Thereby, the bit loss by synchronization can be reduced.

  In one aspect of the present invention, the upstream port circuit performs an interface process between the first interface circuit that performs an interface process with the link layer circuit of the first host / device controller and the hub logic circuit. A second interface circuit, and a conversion circuit that performs conversion processing of the interface signal of the first interface circuit and the interface signal of the second interface circuit may be included.

  In this way, omission of the physical layer circuit can be realized. That is, the data transfer via the physical layer circuit between the first host / device controller and the hub logic circuit can be emulated by the conversion process of the conversion circuit. The upstream port circuit can perform the same interface processing as the case where there is a physical layer circuit for the first host / device controller and the hub logic circuit.

  In the aspect of the invention, the second interface circuit may be connected to the hub logic circuit through a UTMI standard bus and perform UTMI interface processing with the hub logic circuit.

  In this way, interface processing between the upstream port circuit and the hub logic circuit can be performed by interface processing standardized by UTMI.

  In one embodiment of the present invention, the second interface circuit may be connected to the hub logic circuit via a ULPI standard bus, and may perform ULPI interface processing with the hub logic circuit.

  Also, in one aspect of the present invention, the conversion circuit receives a reception circuit having a reception buffer for buffering reception data from the first host / device controller, and transmission data to the first host / device controller. A transmission circuit having a transmission buffer to be buffered, a bus state connecting the first interface circuit and the first host / device controller, and a bus connecting the second interface circuit and the hub logic circuit And a control circuit that controls the data transfer between the first host / device controller and the hub logic circuit.

  Thereby, the interface signal conversion processing can be realized. Specifically, reception data conversion processing can be realized by the reception circuit, and transmission data conversion processing can be realized by the transmission circuit. Further, the control circuit can control the data transfer in response to the interface signals of the first and second interface circuits. Alternatively, the control circuit can control the interface signal conversion processing by controlling the interface signals of the first and second interface circuits to control data transfer.

  In the aspect of the invention, the conversion circuit may include a register for performing emulation processing of control of the physical layer circuit by the first host / device controller.

  According to another aspect of the present invention, a control signal for controlling the physical layer circuit by the first host / device controller can be held as a register value. By using this register value, the interface process between the first host / device controller and the physical layer circuit can be emulated.

  In the device mode, the hub logic circuit may set the plurality of downstream port circuits to a suspended state in the device mode.

  In the aspect of the invention, the hub logic circuit may set the plurality of downstream port circuits to a disconnected state in the device mode.

  In this way, data transfer with a plurality of devices via a plurality of downstream port circuits can be stopped in the device mode.

  Another aspect of the invention relates to an electronic device including the data transfer control device according to any one of the above.

  Hereinafter, preferred embodiments of the present invention will be described in detail. The present embodiment described below does not unduly limit the contents of the present invention described in the claims, and all the configurations described in the present embodiment are indispensable as means for solving the present invention. Not necessarily.

1. Hub (data transfer control device)
1.1. Comparative Example of Hub In order to explain the present embodiment, first and second comparative examples will be described first. The first and second comparative examples are configuration comparative examples for connecting a host controller and a plurality of devices via a hub and performing data transfer by USB interface processing.

  FIG. 1A shows a first comparative example. The first comparative example is a configuration comparative example when a transceiver is built in the host controller.

  Specifically, the hub includes a transceiver PHY_HUB (physical layer circuit), a hub logic circuit HUB_LC, and downstream port circuits DP1 to DPn (n is a natural number). The transceiver PHY_HOST of the host controller is connected to the transceiver PHY_HUB via USB. A hub logic circuit HUB_LC is connected to the transceiver PHY_HUB through a UTMI standard bus. The downstream port circuits DP1 to DPn each include a transceiver and are connected to the devices DEV1 to DEVn via USB. The hub logic circuit HUB_LC controls data transfer between the host controller and the devices DEV1 to DEVn.

  FIG. 1B shows a second comparative example. The second comparative example is a configuration comparative example in the case where the host controller and the transceiver are configured on separate chips.

  Specifically, a host controller and another chip transceiver PHY_HOST are connected to the hub transceiver PHY_HUB via USB. A link controller LK_HOST (link layer circuit) is connected to the transceiver PHY_HOST via a ULPI standard bus. As in the first comparative example, the hub logic circuit HUB_LC controls data transfer between the host controller and the devices DEV1 to DEVn.

  As described above, in the first and second comparative examples, the host controller is connected to the upstream port circuit of the hub via the USB, and the device is connected to the downstream port circuit of the hub via the USB. Therefore, there is a problem that the connection target of the port is fixed to the host controller or the device. That is, there is a problem that it is not possible to switch between a device operation and a host operation to be connected to a port, or to replace a host controller and a device with a port.

  In the first comparative example, the hub includes a transceiver PHY_HUB, and the host controller includes a PHY_HOST. Therefore, there is a problem that the circuit scale of the hub and the host controller increases. On the other hand, in the second comparative example, a transceiver PHY_HUB is built in the hub, and a transceiver PHY_HOST of another chip is connected to the host controller. As a result, the circuit scale of the hub increases, and the mounting area of the wiring board increases.

1.2. 2. Configuration Example of Hub FIG. 2 shows a configuration example of a hub (data transfer control device in a broad sense) of the present embodiment that can solve the above problems. The present embodiment includes an upstream port circuit 10, a hub logic circuit 40, and first to nth downstream port circuits 60-1 to 60-n (a plurality of downstream port circuits, where n is a natural number).

  Further, the downstream port circuits 60-1 to 60-n include an upstream / downstream port circuit as at least one of them. Hereinafter, a case where one upstream / downstream port circuit 60-n is included as at least one upstream / downstream port circuit will be described as an example. However, in the present invention, a plurality of upstream / downstream port circuits may be included as at least one upstream / downstream port circuit.

  The data transfer control device of the present invention is not limited to this configuration, and various modifications may be made such as omitting some of these components or adding other components.

  The upstream port circuit 10 is connected to, for example, a first host / device controller HDC1 (for example, CPU: Central Processing Unit). The upstream port circuit 10 includes a first interface circuit 20, and the first interface circuit 20 performs an interface process with the link controller LK_HD of the host / device controller HDC1.

  Specifically, the first interface circuit 20 is directly connected to the link controller LK_HD without going through a transceiver (physical layer circuit). The upstream port circuit 10 performs data transmission / reception and interface signal conversion processing between the host / device controller HDC1 and the hub logic circuit 40. Alternatively, the upstream port circuit 10 performs a wrapper process between the link controller LK_HD and the transceiver of the upstream / downstream port circuit 60-n.

  For example, the upstream port circuit 10 is connected to the first host / device controller HDC1 by a bus of ULPI standard (UTMI + Low Pin Interface). Further, for example, the upstream port circuit 10 is connected to the hub logic circuit 40 and the upstream / downstream port circuit 60-n through a bus of the UTMI standard (USB 2.0 Transceiver Macrocell Interface, including the UTMI + standard). The upstream port circuit 10 performs a conversion process between the ULPI interface signal and the UTMI interface signal of the hub logic circuit 40. Also, wrapper processing is performed between the ULPI interface signal and the UTMI interface signal of the upstream / downstream port circuit 60-n.

  The upstream / downstream port circuit 60-n is connected to, for example, the second host / device controller HDC2 via a USB (Universal Serial Bus, for example, a bus compliant with USB 1.1 or USB 2.0), and is connected to the host / device controller. Performs USB interface processing with HDC2. For example, the upstream / downstream port circuit 60-n can be configured by a transceiver conforming to the UTMI standard. The hub logic circuit 40 and the upstream port circuit 10 are connected via a UTMI standard bus, and UTMI interface processing with the hub logic circuit 40 and the upstream port circuit 10 is performed.

  The downstream port circuits 60-1 to 60-n-1 are connected to the devices DEV1 to DEVn-1 (a plurality of devices) via USB, respectively, and the USB of the hub logic circuit 40 and the devices DEV1 to DEVn-1 are connected. Perform interface processing. For example, the downstream port circuits 60-1 to 60-n-1 can be configured by transceivers conforming to the UTMI standard. Then, it is connected to the hub logic circuit 40 via a UTMI standard bus, and performs UTMI interface processing with the hub logic circuit 40.

  The hub logic circuit 40 controls data transfer between the host / device controller HDC1 and the devices DEV1 to DEVn-1, and connects the host / device controller HDC1 and the upstream / downstream port circuit 60-n (for example, the host / device). Performs data transfer control with the controller HDC2). Specifically, the hub logic circuit 40 controls data transfer of the upstream port circuit 10 and performs data transmission / reception with the link controller LK_HD. The hub logic circuit 40 controls data transfer of the downstream port circuits 60-1 to 60-n-1, and performs data transmission / reception with the devices DEV1 to DEVn-1. Alternatively, the data transfer between the upstream / downstream port circuit 60-n and the connection target (for example, the host / device controller HDC2) of the upstream / downstream port circuit 60-n is controlled.

  For example, the hub logic circuit 40 performs processing for detecting connection / disconnection of a device, processing for connection / disconnection with a host / device controller, a host controller, and a device, processing for detecting a bus error (fault) Data transfer control is performed by performing recovery processing from a bus error. The hub shown in FIG. 2 is, for example, a data transfer speed in HS mode (High Speed Mode, 480 Mbps), FS mode (Full Speed Mode, 12 Mbps), and LS mode (Low speed Mode, 1.5 Mbps) compliant with the USB 2.0 standard. Can support. In this case, the hub logic circuit 40 translates, for example, an HS transaction from the host / device controller HDC1 into an FS transaction or an LS transaction, and transmits it to the downstream port circuit.

  Here, the host / device controllers HDC1 and HDC2 can switch between the host operation and the device operation, and can operate as both a host controller and a device. For example, as a host operation, control flow and data transfer flow with the hub are managed. On the other hand, as a device operation, for example, processing of a request from the host controller and enumeration processing are performed. For example, HDC1 and HDC2 may switch the host operation and the device operation in response to a signal from a mode switching switch provided in an electronic device or the like. Alternatively, the connection partner may be recognized by negotiation at the time of connection with the hub, and the host operation and the device operation may be switched based on the recognition result. Alternatively, HDC1 and HDC2 may conform to the OTG standard (On-The-Go), and the host operation and device operation may be switched by OTG.

1.3. Hub Mode, Device Mode The operation of this embodiment will be described with reference to FIGS. 3 (A) and 3 (B).

  FIG. 3A is a connection configuration example when the data transfer control device of this embodiment operates in the hub mode. As shown in FIG. 3A, the present embodiment operates as a hub in the hub mode. Specifically, the upstream port circuit 10 performs an upstream port operation. The upstream / downstream port circuit 60-n performs a downstream port operation.

  More specifically, the host / device controller HDC1 performs a host operation. The upstream port circuit 10 performs ULPI interface processing with the host / device controller HDC1 as an upstream port operation.

  The host / device controller HDC2 performs device operation. The upstream / downstream port circuit 60-n performs USB interface processing with the host / device controller HDC2 that performs the device operation as the downstream port operation.

  The hub logic circuit 40 performs data transfer between the host / device controller HDC1 and the host / device controller HDC2. The hub logic circuit 40 performs data transfer between the host / device controller HDC1 and the devices DEV1 to DEVn-1.

  FIG. 3B is a connection configuration example when the data transfer control device of this embodiment operates in the device mode. As shown in FIG. 3B, the data transfer control device of this embodiment operates as a transceiver having a ULPI standard bus in the device mode. The host / device controller HDC1 and the data transfer control device of this embodiment operate as a USB device.

  Specifically, the upstream port circuit 10 performs interface processing with the transceiver of the upstream / downstream port circuit 60-n. The upstream / downstream port circuit 60-n performs an upstream port operation.

  More specifically, the host / device controller HDC1 performs device operation. The upstream port circuit 10 performs the interface processing with the transceiver of the upstream / downstream port circuit 60-n, the ULPI bus of the host / device controller HDC1, and the UTMI bus of the transceiver of the upstream / downstream port circuit 60-n. Wrap the file.

  The host / device controller HDC2 performs host operation. The upstream / downstream port circuit 60-n performs USB interface processing with the host / device controller HDC2 as an upstream port operation.

  The downstream port circuits 60-1 to 60-n-1 are set to, for example, a suspended state or a disconnected state based on a control signal from the hub logic circuit 40 in the device mode.

  FIG. 4A and FIG. 4B show connection modifications of this embodiment.

  As shown in FIG. 4A, in the hub mode, the device DEVn is connected to the upstream / downstream port circuit 60-n. In this embodiment, the host / device controller HDC1 that performs the host operation and the hub that performs data transfer between the devices DEV1 to DEVn operate.

  As shown in FIG. 4B, in the device mode, the host controller HC is connected to the upstream / downstream port circuit 60-n. The present embodiment operates as a transceiver having a ULPI standard bus.

  In FIGS. 3B and 4B, the upstream port circuit 10 is directly connected to the upstream / downstream port circuit 60-n and performs interface processing with the upstream / downstream port circuit 60-n. Was described as an example. However, in the present invention, the upstream port circuit 10 may be connected to the upstream / downstream port circuit 60-n via the hub logic circuit 40 to perform interface processing with the upstream / downstream port circuit 60-n.

  By the way, as described with reference to FIGS. 1A and 1B, the first and second comparative examples have a problem that the port connection target is fixed to the host controller or the device.

  In this regard, according to the present embodiment, in the hub mode, the upstream / downstream port circuit 60-n is switched to the downstream port circuit, and the hub logic circuit 40 is connected to the upstream port circuit 10 and the downstream port circuits 60-1 to 60-. Data transfer control with n is performed. On the other hand, in the device mode, the upstream / downstream port circuit 60-n is switched to the upstream port circuit, and the upstream port circuit 10 performs interface processing with the transceiver of the upstream / downstream port 60-n.

  Thus, in this embodiment, the hub mode and the device mode can be switched. Specifically, the operation as a hub and the operation as a transceiver on the device side can be switched. Thereby, a host / device controller capable of switching between host operation and device operation is connected to the port, and data can be transferred even when the host operation and device operation are switched. Alternatively, data transfer can be performed even when the port connection target is changed from the host controller to the device, or from the device to the host controller.

  In the present embodiment, the upstream port circuit 10 is connected to the host / device controller HDC1, and the upstream port circuit 10 performs the interface processing with the link controller LK_HD of the host / device controller HDC1. 20 may be included.

  As described above, in the present embodiment, the first interface circuit 20 directly performs interface processing with the link controller LK_HD without using USB. Thereby, the device mode can be realized. Specifically, the transceiver of the upstream / downstream port circuit 60-n is interfaced to the link controller LK_HD without going through USB. As a result, the operation as a transceiver of the host / device controller HDC1 that performs device operation can be realized.

  Here, in the first and second comparative examples, since the hub and the host controller are connected via the transceiver, there is a problem that the circuit scale and the mounting area increase.

  In this regard, according to the present embodiment, the first interface circuit 20 directly performs interface processing with the link controller LK_HD. Therefore, the transceivers PHY_HOST and PHY_HUB can be omitted as compared with the first and second comparative examples. As a result, the circuit scale of the hub and the host / device controller HDC1 can be reduced, and the mounting area of the wiring board can be reduced. Further, by omitting the transceiver, signal delay in the transceiver can be eliminated. As a result, the propagation delay of data transfer between the hub and the host / device controller can be reduced.

  Further, when the hub and the host controller are connected via USB, there is a problem that the transfer data needs to be synchronized in order to absorb the clock frequency difference between the hub side and the host controller side.

  In this regard, according to the present embodiment, the first interface circuit 20 may be connected to the host / device controller HDC1 via a ULPI standard bus and perform ULPI interface processing between the link controller LK_HD. Therefore, the hub and the host / device controller HDC1 can be connected via the ULPI interface, which is a synchronous interface. Thereby, the bit loss by synchronization can be reduced. Further, the circuit scale can be reduced by omitting the elasticity buffer that performs buffering for absorbing the clock frequency difference.

  However, in the present invention, the first interface circuit 20 may be connected to the host controller HC by a UTMI standard bus and perform UTMI interface processing between the link controller LK_HOST of the host controller HC. As a result, the hub logic circuit 40 and the host controller HC can be connected by a UTMI interface that is a synchronous interface. Then, the bit loss due to the synchronization can be reduced, and the circuit scale can be reduced by omitting the elasticity buffer.

2. Upstream Port Circuit, Switching Control Circuit FIG. 5 shows a detailed configuration example of this embodiment. In the following, each component such as the hub logic circuit described with reference to FIG.

  The configuration example shown in FIG. 5 includes an upstream port circuit 10, a hub logic circuit 40, downstream port circuits 60-1 to 60-n-1, an upstream / downstream port circuit 60-n, a switching control circuit 320, and a selector 340. including.

  The upstream port circuit 10 further includes a first interface circuit 20, a second interface circuit 30, a conversion circuit 100, a wrapper circuit 300, a ULPI register 310, and a selector 330.

  The first interface circuit 20 performs ULPI interface processing. For example, the host / device controller HDC1 of FIG. 2 is connected to the first interface circuit 20 via a ULPI bus.

  A hub logic circuit 40 is connected to the second interface circuit 30 via a UTMI bus. The second interface circuit 30 performs UTMI interface processing with the hub logic circuit 40.

  The conversion circuit 100 is a circuit for emulating data transfer via a transceiver (for example, PHY_HOST and PHY_HUB in FIGS. 1A and 1B). Specifically, the ULPI interface signal of the first interface circuit 20 and the UTMI interface signal of the second interface circuit 30 are converted.

  The wrapper circuit 300 wraps the ULPI interface signal of the first interface circuit 20 and the UTMI interface signal of the upstream / downstream port circuit 60-n.

  The ULPI register 310 sets a register value for wrapper processing by the wrapper circuit 300. The ULPI register 310 sets a register value for the host / device controller HDC1 of FIG. 2 to control the transceiver of the upstream / downstream port circuit 60-n, for example.

  The selector 330 electrically connects the bus of the first interface circuit 20 and the bus of the conversion circuit 100 in the hub mode. On the other hand, in the device mode, the bus of the first interface circuit 20 and the bus of the wrapper circuit 300 are electrically connected. The selector 330 performs bus switching based on the switching control signal HD_Select from the switching control circuit 320.

  The selector 340 electrically connects the bus of the upstream / downstream port circuit 60-n and the bus of the hub logic circuit 40 in the hub mode. On the other hand, in the device mode, the bus of the upstream / downstream port circuit 60-n and the bus of the wrapper circuit 300 are electrically connected. The selector 340 performs bus switching based on the switching control signal HD_Select from the switching control circuit 320.

  The upstream / downstream port circuit 60-n switches between the upstream port operation and the downstream port operation based on the switching control signal HD_Select from the switching control circuit 320. The upstream / downstream port circuit 60-n can be realized by, for example, a transceiver to be described later with reference to FIGS. 13A and 13B.

  The switching control circuit 320 outputs a switching control signal HD_Select to switch between the hub mode and the device mode. Specifically, the switching control circuit 320 sets HD_Select to the first logic level (or the second logic level) and switches to the hub mode. On the other hand, HD_Select is set to the second logic level (or the first logic level) to switch to the device mode.

  For example, as shown in FIG. 5, the ULPI register 310 can include a switching register 312. The switching register 312 sets a register value for mode switching based on an interface signal from the host / device controller HDC1, for example. Then, the switching control circuit 320 outputs HD_Select based on the register value of the switching register 312.

  Note that the switching control circuit 320 may output HD_Select based on the register value of the switching register 312 as described above, or may output HD_Select based on the register value of a register 140 of the conversion circuit 100 described later. Alternatively, the hub of the present invention may be provided with a mode terminal, and the switching control circuit 320 may output HD_Select based on a signal from the mode terminal. For example, a mode switching signal may be input from the host / device controller HDC1 to the mode terminal, or a mode switching switch may be provided in the electronic device, and a signal may be input from the switch.

3. Conversion circuit 3.1. Configuration Example of Conversion Circuit FIG. 6 shows a configuration example of the conversion circuit 100. The conversion circuit 100 controls the first interface circuit 20 and the second interface circuit 30 to input / output interface signals. First, the first interface circuit 20 and the second interface circuit 30 will be described.

  The first interface circuit 20 inputs and outputs ULPI interface signals data [7: 0], dir, stp, and nxt. Specifically, the first interface circuit 20 receives, for example, signals data [7: 0] and stp from the host / device controller HDC1 in FIG. 3A and outputs them to the conversion circuit 100. Further, the signal data [7: 0] from the conversion circuit 100 is output to the HDC1, and signals dir and nxt are output to the HDC1 in response to a control signal from the control circuit 130 described later. For example, the first interface circuit 20 drives a ULPI bus and outputs signals data [7: 0], nxt, and dir, and receives signals data [7: 0] and stp from the ULPI bus. It can be configured by a receiver.

  The second interface circuit 30 inputs and outputs UTMI interface signals DataIn [7: 0], DataOut [7: 0], TXValid, TXReady, and the like. Specifically, the second interface circuit 30 receives the signals DataIn [7: 0], TXValid, XcvrSelect [1: 0], TermSelect, OpMode [1: 0], etc. from the hub logic circuit 40, and so on. 100 is output. Further, it receives the signal DataOut [7: 0] from the conversion circuit 100 and outputs it to the hub logic circuit 40, receives the control signal from the control circuit 130, and receives the signals TXReady, RXActive, RXValid, LineState [1: 0]. Are output to the hub logic circuit 40. For example, the second interface circuit 30 can be configured by a data driver or a data receiver, like the first interface circuit 20.

  The conversion circuit 100 includes a reception circuit 110, a transmission circuit 120, a control circuit 130 (bus state controller), and a register 140. Between the ULPI interface signal to the host / device controller HDC1 and the hub logic circuit 40, Performs conversion processing with UTMI interface signals.

  The receiving circuit 110 converts the received data from the HDC 1 and outputs it to the hub logic circuit 40. Specifically, the reception circuit 110 receives the ULPI reception data data [7: 0] from the HDC 1 and outputs the UTMI reception data DataOut [7: 0] to the hub logic circuit 40. More specifically, the reception circuit 110 includes a reception buffer 112 that buffers reception data from the HDC1. Then, the reception circuit 110 takes in the reception data into the reception buffer 112 and transfers the reception data to the hub logic circuit 40 based on the control signal from the control circuit 130.

  The transmission circuit 120 converts the transmission data from the hub logic circuit 40 and outputs it to the HDC1. Specifically, the transmission circuit 120 receives the transmission data DataIn [7: 0] of UTMI from the hub logic circuit 40 and outputs ULPI transmission data data [7: 0] to the HDC1. More specifically, the transmission circuit 120 includes a transmission buffer 122 that buffers transmission data from the hub logic circuit 40. Based on the control signal from the control circuit 130, the transmission circuit 120 captures transmission data into the transmission buffer 122 and transfers transmission data to the HDC1.

  The control circuit 130 controls the conversion process of the interface signal. Specifically, the bus state is monitored by detecting the reception state and transmission state of the bus. Alternatively, the bus state is monitored by detecting an interface signal for controlling data transfer. Based on the monitoring result, the conversion process is controlled. More specifically, the control circuit 130 receives ULPI signals stp, data [7: 0], UTMI signals TXValid, DataIn [7: 0], OpMode [1: 0], and the like. In addition, a signal indicating the buffering state of the reception buffer 112 is input from the reception circuit 110 to the control circuit 130. A signal indicating the buffering state of the transmission buffer 122 is input from the transmission circuit 120 to the control circuit 130. Based on these signals, the control circuit 130 recognizes whether the conversion circuit 100 is in the data reception state or the data transmission state. The control circuit 130 controls the reception circuit 110 and the transmission circuit 120 based on the recognition result. The first interface circuit 20 is controlled to output ULPI signals nxt and dir, and the second interface circuit 30 is controlled to output UTMI signals TXReady, RXActive, RXValid, and the like.

  The register 140 sets a register value for emulating the control of the transceiver (for example, PHY_HOST in FIG. 1B) by the host controller HC. Specifically, the register 140 sets, for example, an UTMI interface signal as a register value in order to compensate for the shortage of ULPI standard bus signals. For example, the host / device controller HDC1 writes the control signals OpMode [1: 0], XcvrSelect [1: 0], TermSelect, etc. of the transceiver to the register 140. Alternatively, the control circuit 130 emulates the signal from the transceiver PHY_HOST and writes the signal LineState [1: 0] and the like to the register 140. The HDC 1 recognizes as if the transceiver PHY_HOST exists by accessing the register 140. The control circuit 130 controls the ULPI interface signal with the HDC 1 with reference to the register 140.

  As described above, according to the present embodiment, the conversion circuit 100 performs the conversion process between the interface signal of the first interface circuit 20 and the interface signal of the second interface circuit 30.

  In this way, it is possible to omit the transceiver (for example, PHY_HOST and PHY_HUB in FIGS. 1A and 1B). That is, the conversion processing of the conversion circuit 100 can realize data transfer emulation processing via the transceiver. For example, between the host / device controller HDC1 and the conversion circuit 100, the same interface processing as when PHY_HOST exists can be realized. Further, interface processing similar to that in the case where PHY_HUB exists can be realized between the conversion circuit 100 and the hub logic circuit 40.

  According to the present embodiment, the conversion circuit 100 may include the reception circuit 110 and the transmission circuit 120. The reception circuit 110 may include a reception buffer 112 that buffers reception data from the host / device controller HDC1, and the transmission circuit 120 buffers a transmission data to the host / device controller HDC1. You may have.

  Thereby, transfer data conversion processing can be realized. Data transfer between the hub logic circuit 40 and the host / device controller HDC1 can be realized. Specifically, the reception circuit 110 can realize conversion processing of received data from the host / device controller HDC1. Further, the transmission circuit 120 can realize the conversion processing of transmission data to the host / device controller HDC1.

  Further, according to the present embodiment, the control circuit 130 may monitor the bus state of the first interface circuit 20 and the bus state of the second interface circuit 30. The data transfer between the host / device controller HDC1 and the hub logic circuit 40 may be controlled based on the monitoring result.

  In this way, data transfer can be controlled based on the state of the bus. That is, data transfer between the host / device controller HDC1 and the conversion circuit 100 can be controlled based on the state of the bus of the first interface circuit 20. Further, data transfer between the conversion circuit 100 and the hub logic circuit 40 can be controlled based on the state of the bus of the second interface circuit 30.

  Further, according to the present embodiment, even if the first interface circuit 20 is connected to the host / device controller HDC1 via a ULPI standard bus and performs ULPI interface processing between the link controller LK_HD of the host / device controller HDC1. Good. The conversion circuit 100 may include a register 140 for emulating control of the transceiver (for example, PHY_HOST in FIG. 1B) by the host / device controller HDC1.

  In this way, a signal for controlling the transceiver by the host / device controller HDC1 can be set as a register value. Then, the emulation processing can be realized by setting the register value in the register 140 or generating the interface signal from the register value in accordance with the register write or read from the host / device controller HDC1.

3.2. Signal waveform example of conversion process 3.2.1. Reception FIG. 7 shows a first signal waveform example of the conversion process. The first signal waveform example is a signal waveform example of conversion processing performed by the conversion circuit 100 when the hub logic circuit 40 receives reception data from the host / device controller HDC1 (host operation) in the hub mode.

  As shown at A1 in FIG. 7, HDC1 outputs the received data to bus data [7: 0]. When detecting this, the control circuit 130 controls the first interface circuit 20 to activate (assert, to the first logic level), as shown at A2. The reception buffer 112 starts buffering received data. Further, as shown at A3, the second interface circuit 30 is controlled to activate the signal RXActive.

  As indicated by A4, when the control circuit 130 detects that the reception data is buffered in the reception buffer 112, the control circuit 130 controls the second interface circuit 30 to activate the signal RXValid. As shown in A5, the received data is transferred to the hub logic circuit 40 during a period in which RXActive and RXValid are active.

  As shown in A6, when HDC1 finishes outputting the received data, as shown in A7, HDC1 activates signal stp, and then deactivates (negates it to the second logic level). As indicated by A8, when the control circuit 130 detects that the signal stp is active, the control circuit 130 controls the first interface circuit 20 to deactivate the signal nxt.

  As shown at A9, when the control circuit 130 detects that the transfer of the received data has been completed, as shown at A10 and A11, the second interface circuit 30 is controlled to deactivate the signals RXActive and RXValid.

  As indicated by A12, during data transfer, the control circuit 130 controls the second interface circuit 30 to set the signal LineState [1: 0] to the J state.

  Further, when the conversion circuit 100 performs data transfer in, for example, the HS mode, the conversion circuit 100 receives XcvrSelect [1: 0] = (0,0) and TermSelect = 0 (0 is L level) from the hub logic circuit 40. Or a second logic level). For example, when the conversion circuit 100 emulates the normal operation mode of the transceiver PHY_HUB, OpMode [1: 0] = (0, 0) is input from the hub logic circuit 40 to the conversion circuit 100.

3.2.2. Transmission FIG. 8 shows a second signal waveform example of the conversion process. The second signal waveform example is a signal waveform example of conversion processing performed by the conversion circuit 100 when the hub logic circuit 40 transmits transmission data to the host / device controller HDC1 (host operation) in the hub mode.

  As shown in B 1 and B 2 of FIG. 8, the hub logic circuit 40 activates the signal TXValid and outputs transmission data to the conversion circuit 100. As indicated by B3, in response to the signal TXValid becoming active, the control circuit 130 controls the second interface circuit 30 to activate the signal TXReady. The transmission buffer 122 starts buffering transmission data.

  As indicated by B4, in response to the signal TXValid becoming active, the control circuit 130 controls the first interface circuit 20 to activate the signal dir. As shown in B5, when the control circuit 130 detects that transmission data is buffered in the transmission buffer 122, the control circuit 130 controls the first interface circuit 20 to activate the signal nxt. Then, as indicated by B6, the transmission circuit 120 secures a turn around to the transmission data, adds an RX command (RX CMD), and outputs it to the HDC1. As indicated by B7, the control circuit 130 deactivates nxt during the period in which the RX command is output.

  For example, the transmission circuit 120 outputs data including the register values VbusState, LineState, and the like held in the register 140 as RX commands. The transmission circuit 120 ensures turnaround at the active and inactive change points of the signal dir.

  As shown in B8 and B9, the hub logic circuit 40 deactivates the signal TXValid when the output of the transmission data is completed. As indicated by B10, the control circuit 130 controls the second interface circuit 30 to deactivate the signal TXReady in response to the signal TXValid being deactivated.

  As indicated by B11, when the control circuit 130 detects the end of transmission of transmission data, the control circuit 130 controls the first interface circuit 20 to deactivate the signal dir. As shown in B12, when the control circuit 130 detects that the transfer of the transmission data has been completed, the control circuit 130 controls the first interface circuit 20 to inactivate the signal nxt, as shown in B13.

  As in FIG. 7, the signal LineState [1: 0] is set to the J state, and the conversion circuit 100 includes, for example, XcvrSelect [1: 0] = (0,0), TermSelect = 0, OpMode [1: 0] = (0,0) is input.

3.2.3. Reset Operation FIG. 9 shows a third signal waveform example of the conversion process. The third signal waveform example is a signal waveform example of conversion processing performed by the conversion circuit 100 when the transceiver reset operation is emulated in the hub mode.

  As shown at C 1 in FIG. 9, the host / device controller HDC 1 (host operation) transmits a register write command TX CMD (RegWr) to the conversion circuit 100. In response to the command TX CMD, a register value (for example, OpMode [1: 0] = (1,0)) corresponding to the reset operation mode is set in the register 140.

  As shown in C2, when the hub logic circuit 40 detects that SE0 (Single Ended Zero) is output to LineState [1: 0] for a predetermined time and SOF (Start-of-Frame) is not output, it is shown in C3. Thus, TermSelect = 1 (1 is H level or first logic level) corresponding to the termination of the FS mode is output.

  Then, as indicated by C4, the hub logic circuit 40 outputs OpMode [1: 0] = (1,0) to the conversion circuit 100. As shown in C5, the hub logic circuit 40 transmits a device chirp K to the conversion circuit 100, and the conversion circuit 100 sets LineState [1: 0] to the device chirp K. As shown at C6, the conversion circuit 100 transmits to the HDC1 a command RX CMD for notifying that the LineState [1: 0] has changed.

  As shown in C7, the conversion circuit 100 sets LineState [1: 0] to SE0 after the transmission of the device chirp K is completed. As shown in C8, the conversion circuit 100 transmits to the HDC1 a command RX CMD for notifying that the LineState [1: 0] has changed.

  As shown in C9, HDC1 transmits a command TX CMD (NOPID) and host chirp K / J to the conversion circuit 100. As shown in C10, the conversion circuit 100 transmits the host chirp K / J to the hub logic circuit 40.

  As shown in C11, the hub logic circuit 40 determines that the data transfer rate of the HDC1 is, for example, the HS mode, and outputs TermSelect = 0 corresponding to the termination of the HS mode. As shown in C12, the conversion circuit 100 receives TermSelect = 0 and sets LineState [1: 0] to the J state.

  As shown in C13, the conversion circuit 100 sets LineState [1: 0] to SE0 after completion of transmission of the host chirp K / J.

  As shown in C14, HDC1 transmits a register write command TX CMD (RegWr) to the conversion circuit 100. In response to the command TX CMD, a register value (for example, OpMode [1: 0] = (0,0)) corresponding to the normal operation mode is set in the register 140.

4). Wrapper circuit 4.1. Connection Configuration Example of Wrapper Circuit FIG. 10 shows a connection configuration example of the wrapper circuit 300. The wrapper circuit 300 controls the first interface circuit 20 to input / output interface signals. Interface signals are input / output to / from the upstream / downstream port circuit 60-n (transceiver). First, the first interface circuit 20 and the upstream / downstream port circuit 60-n will be described.

  The first interface circuit 20 inputs and outputs ULPI interface signals data [7: 0], dir, stp, and nxt. For example, it receives signals data [7: 0] and stp from the host / device controller HDC1, and outputs them to the wrapper circuit 300. Further, the signal data [7: 0] from the wrapper circuit 300 is output to the HDC1, and the signals dir and nxt are output to the HDC1 in response to the control signal from the wrapper circuit 300.

  The upstream / downstream port circuit 60-n is connected to, for example, the host / device controller HDC2 in FIG. 3B (or the host controller HC in FIG. 4B) via the USB, and transfers serial data to and from the HDC2. Do. Specifically, it receives serial data from HDC 2 and outputs UTMI interface signals DataOut [7: 0], TXReady, RXActive, RXValid, LineState [1: 0], etc. to wrapper circuit 300. In response to the UTMI interface signals DataIn [7: 0], TXValid, XcvrSelect [1: 0], TermSelect, OpMode [1: 0], etc. from the wrapper circuit 300, serial data is output to the HDC2.

  The wrapper circuit 300 performs a wrapper process on these ULPI interface signals and UTMI interface signals. Specifically, data [7: 0] and stp from the first interface circuit 20 are analyzed to generate DataIn [7: 0], TXValid, XcvrSelect [1: 0], etc., and upstream / downstream Output to the port circuit 60-n. DataOut [7: 0], TXReady, LineState [1: 0], etc. from the upstream / downstream port circuit 60-n are analyzed to generate data [7: 0], dir, nxt, and the first interface Output to the circuit 20. Further, the wrapper circuit 300 writes XcvrSelect [1: 0], TermSelect, OpMode [1: 0], etc. (or a part thereof) into the ULPI register 310 as a register value. Alternatively, the register value is read to generate data [7: 0], dir, and nxt. For example, the upstream / downstream port circuit 60-n can be configured with a UTMI + PHY core conforming to the UTMI standard, and the wrapper circuit 300 can be configured with a ULPI PHY wrapper conforming to the ULPI standard.

4.2. Example of signal waveform of wrapper processing FIG. 11 shows an example of a signal waveform of wrapper processing. The signal waveform example of FIG. 11 is a signal waveform example when the wrapper circuit 300 performs the wrapper process on the reset operation of the upstream / downstream port circuit 60-n in the device mode.

  As shown in D1 of FIG. 11, SE0 (Single Ended Zero) without SOF (Start-of-Frame) is transmitted from the host / device controller HDC2 (host operation) of FIG. LineState [1: 0] = SE0 is output from the port circuit 60-n.

  As shown in D2, when the host / device controller HDC1 (device operation) detects LineState [1: 0] = SE0 for a predetermined time or more, a register write command TX CMD (RegWr) is sent to the wrapper circuit 300. Is sent. As shown at D3, TermSelect = 1 (1 is H level or first logic level) corresponding to the termination of the FS mode is output from the wrapper circuit 300.

  As indicated by D4, a register write command TX CMD (RegWr) is transmitted from the HDC 1 to the wrapper circuit 300. As indicated by D5, the wrapper circuit 300 outputs OpMode [1: 0] = (1,0) (0 is the L level or the second logic level) corresponding to the reset operation mode.

  As shown at D6, TX CMD (NOPID) is transmitted from HDC2 to wrapper circuit 300, and as a result, chirp K is transmitted to HDC2. As indicated by D7, the device chirp K is output as LineState [1: 0] from the upstream / downstream port circuit 60-n. As shown in D8, when the transmission of the chirp K is completed, LineState [1: 0] = SE0 is output from the upstream / downstream port circuit 60-n. As shown at D9, the command RX CMD for notifying that the LineState [1: 0] has changed is transmitted from the wrapper circuit 300 to the HDC1.

  As shown in D10, for example, when HDC2 is in the HS mode, the host chirp K / J is transmitted from HDC2. The host chirp K / J is output as LineState [1: 0] from the upstream / downstream port circuit 60-n to the wrapper circuit 300. As shown in D11, the command RX CMD for notifying that the LineState [1: 0] has changed is transmitted from the wrapper circuit 300 to the HDC1.

  As shown in D12, the command RX CMD of D11 is received, and the register write command TX CMD (RegWr) is transmitted from HDC1. As shown in D13 and D14, TermSelect = 0 corresponding to the termination of the HS mode is output from the wrapper circuit 300, and the register value OpMode [1: 0] = (0,0) corresponding to the normal operation mode is output. The As shown in D15, the J state is output as LineState [1: 0] from the upstream / downstream port circuit 60-n.

  As shown in D16, when transmission of the host chirp K / J from the HDC2 is completed, LineState [1: 0] = SE0 is output from the upstream / downstream port circuit 60-n. As shown in D17, the command RX CMD for notifying that the LineState [1: 0] has changed is transmitted from the wrapper circuit 300 to the HDC1.

5. Hub Logic Circuit FIG. 12 shows a detailed configuration example of the hub logic circuit 40. The hub logic circuit 40 includes a transaction translator 200, a hub repeater logic circuit 210, a hub state machine 220, a hub controller 230, a routing logic circuit 240, and a frame timer 250. The hub logic circuit of the present invention is not limited to the configuration shown in FIG. 12, and various modifications such as omitting a part of the configuration or adding other components are possible.

  In the transaction translator 200, an upstream port circuit is connected to a host controller (or a host / device controller, and so on) in HS mode, and a downstream port circuit (or an upstream / downstream port circuit, and so on) is connected to a device (or a host). / Device controller, and so on), when connected in FS mode or LS mode, it converts the HS mode transaction on the upstream side and the FS mode or LS mode transaction on the downstream side.

  The hub repeater logic circuit 210 performs data transfer when the host controller connected to the upstream port circuit and the device connected to the downstream port circuit have the same data transfer rate mode.

  Hub state machine 220 controls the state of the hub. For example, connection processing and disconnection of a port and a device are detected. Alternatively, the reset, stop, and return of the port are controlled.

  The hub controller 230 controls communication between the hub and the host controller. For example, enumeration is performed, and hub resource information and settings are exchanged with the host controller. Further, for example, a request from the host controller is processed.

  The routing logic circuit 240 connects the transaction translator 200 and each downstream port circuit. Alternatively, the routing logic circuit 240 connects the hub repeater logic circuit 210 and each downstream port circuit.

  The frame timer 250 synchronizes the upstream frame and the downstream frame and controls the frame interval.

6). Up / Downstream Port Circuit FIGS. 13A and 13B show configuration examples of the upstream / downstream port circuit. This configuration example shows pull-up resistor Rpu, switch SW_Rpu, pull-down resistors Rpd1, Rpd2, switch SW_Rpd1, SW_Rpd2, switch SW_VBUS, HS (High Speed) current driver HSD, LS / FS (Low Speed / Full Speed) driver LSD, resistor Rs1, Rs2, HS differential data receiver HSR, transmission envelope detector SQL, LS / FS differential data receiver LSR, disconnection envelope detector DIS, single-ended receiver DP_SER, DM_SER.

  The switches SW_Rpu, SW_Rpd1, and SW_Rpd2 are ON / OFF controlled based on the signal HD_Select (for example, the switching control signal HD_Select from the switching control circuit 320 in FIG. 5). The switch SW_VBUS is switched between the VBUS supply state and the VBUS detection state based on the signal HD_Select. The disconnection envelope detector DIS is switched between an enable state and a disable state based on the signal HD_Select.

  FIG. 13A shows a connection configuration example in the case where the downstream port operation is performed in the hub mode. As shown in FIG. 13A, in the hub mode, the switches SW_Rpd1 and SW_Rpd2 are turned on and the switch SW_Rpu is turned off. Then, the DP line and DM line are pulled down via resistors Rpd1 and Rpd2. Further, the switch SW_VBUS is switched to the VBUS supply state, and VBUS is supplied from the upstream / downstream port circuit. The disconnection envelope detector DIS is switched to the enable state and detects the HS disconnect state.

  FIG. 13B shows a connection configuration example in the case where the upstream port operation is performed in the device mode. As shown in FIG. 13B, in the device mode, the switches SW_Rpd1 and SW_Rpd2 are turned off and the switch SW_Rpu is turned on. Then, the DP line is pulled up through the resistor Rpu. Further, the switch SW_VBUS is switched to the VBUS detection state, and VBUS is supplied to the upstream / downstream port circuit. The disconnection envelope detector DIS is switched to a disabled state.

  13A and 13B, the connection configuration example in which the DP line is pulled up in the device mode when the hub of this embodiment operates in the HS / FS mode has been described. However, in the present invention, when the hub operates in the LS mode, the DM line may be pulled up via the resistor Rpu and the switch SW_Rpu in the device mode.

7). Electronic Device FIG. 14 shows a configuration example of an electronic device to which the hub (data transfer control device) of this embodiment is applied. For example, the hub of this embodiment can be applied to electronic devices such as a personal computer (PC), a home game machine, a car navigation system, a printer, a television, a digital photo frame, and an AV recorder / player.

  14 includes a hub 500, a CPU 510 (for example, a first host / device controller capable of switching between host operation and device operation), devices 520-1 to 520-3, ROM 530 (Read Only Memory), RAM 540 ( Random Access Memory), a display unit 550, and an operation unit 560.

  The hub 500 and the CPU 510 communicate via a ULPI bus. The hub 500 and the devices 520-1 to 520-3 communicate with each other via USB. The CPU 510, the ROM 530, the RAM 540, the display unit 550, and the operation unit 560 communicate via a CPU bus. The display unit 550 is configured by, for example, a liquid crystal panel, an EL (Electro Luminescence) panel, or the like. The operation unit 560 includes, for example, a mouse, a keyboard, a touch panel, a game controller, an infrared receiving unit, and the like.

  For example, a built-in device such as an HDD (Hard Disk Drive), a DVD drive, or a CD drive may be connected to the hub 500 as devices 520-1 to 520-3. Alternatively, the operation unit 560 may be connected to the hub 500 via USB. Further, an external device such as a USB memory, a portable audio player, or a digital camera may be connected to the hub 500 via a USB port.

  The hub 500 has a device (eg, device 520-3) as a portable audio player, printer, digital video camera, AV recorder / player, etc. (eg, second host / device controller) that can switch between host operation and device operation. May be connected. Alternatively, a host controller (for example, the host controller HC in FIG. 4B) may be connected.

  Although the present embodiment has been described in detail as described above, it will be easily understood by those skilled in the art that many modifications can be made without departing from the novel matters and effects of the present invention. Accordingly, all such modifications are intended to be included in the scope of the present invention. For example, in the specification or drawings, terms (hub, bus state controller) described at least once together with different terms (data transfer control device, control circuit, host controller, link layer circuit, physical layer circuit, etc.) having a broader meaning or the same meaning , CPU, link controller, transceiver, etc.) may be replaced by their different terms anywhere in the specification or drawings. In addition, the configuration and operation of the conversion circuit, upstream port circuit, hub logic circuit, downstream port circuit, data transfer control device, electronic device, etc. are not limited to those described in this embodiment, and various modifications are made. Is possible. In the present embodiment, the application examples of the present invention to the ULPI, UTMI, and USB 2.0 standards have been described. However, the present invention is based on standards based on the same idea as these standards, or standards developed from these standards. Etc.

1A is a first configuration comparison example, and FIG. 1B is a second configuration comparison example. Configuration example of this embodiment 3A and 3B are connection configuration examples of the present embodiment. 4 (A) and 4 (B) are connection variations of this embodiment. Detailed configuration example of this embodiment Configuration example of conversion circuit First signal waveform example of conversion processing Second signal waveform example of conversion processing Third signal waveform example of conversion processing Wrapper circuit connection configuration example Wrapper signal waveform example Hub logic circuit configuration example 13A and 13B are configuration examples of the upstream / downstream port circuit. Electronic device configuration example

Explanation of symbols

10 upstream port circuit, 20 first interface circuit,
40 Hub logic circuit, 60-1 downstream port circuit,
60-n upstream / downstream port circuit,
100 conversion circuit, 110 reception circuit, 112 reception buffer, 120 transmission circuit,
122 transmission buffer, 130 control circuit, 140 registers,
200 transaction translators, 210 hub repeater logic circuits,
220 hub state machine, 230 hub controller,
240 routing logic circuit, 250 frame timer,
300 wrapper circuit, 310 ULPI register, 312 switching register,
320 switching control circuit, 330, 340 selector,
500 data transfer control device, 510 CPU, 520-1 to 520-3 device,
530 ROM, 540 RAM, 550 display unit, 560 operation unit,
PHY_HOST, PHY_HUB transceiver,
HDC1 first host / device controller, LK_HD link controller,
HDC2 second host / device controller

Claims (15)

An upstream port circuit;
Multiple downstream port circuits;
A hub logic circuit for controlling data transfer between the upstream port circuit and the plurality of downstream port circuits;
Including
An upstream / downstream port circuit is provided as at least one of the plurality of downstream port circuits;
In hub mode, the upstream port circuit performs upstream port operation, the upstream / downstream port circuit performs downstream port operation,
The device mode, the upstream port circuit performs interface processing between the physical layer circuit of the up / down stream port circuit, the up / down stream port circuits have line upstream port operation,
A first host / device controller capable of switching between host operation and device operation is connected to the upstream port circuit,
The upstream port circuit includes:
Interface processing with the link layer circuit of the first host / device controller is performed. In the hub mode, interface processing between the link layer circuit of the first host / device controller performing the host operation and the hub logic circuit is performed. In the device mode, data transfer control is characterized in that interface processing is performed between the link layer circuit of the first host / device controller that performs device operation and the physical layer circuit of the upstream / downstream port circuit. apparatus. In claim 1 ,
A second host / device controller capable of switching between host operation and device operation is connected to the upstream / downstream port circuit,
The upstream / downstream port circuit includes:
In the hub mode, interface processing between the second host / device controller that performs device operation and the hub logic circuit is performed,
In the device mode, an interface process between the second host / device controller that performs a host operation and the upstream port circuit is performed. In claim 1 ,
In the hub mode, a device is connected to the upstream / downstream port circuit, and the upstream / downstream port circuit performs an interface process between the device and the hub logic circuit,
In the device mode, a host controller is connected to the upstream / downstream port circuit, and the upstream / downstream port circuit performs interface processing between the host controller and the upstream port circuit. Transfer control device. In any one of Claims 1 thru | or 3 ,
The upstream port circuit includes:
A first interface circuit that performs an interface process with a link layer circuit of the first host / device controller;
The first interface circuit includes:
It is connected to the first host / device controller via a ULPI standard (UTMI + Low Pin Interface) bus, and performs ULPI interface processing with the link layer circuit of the first host / device controller. Data transfer control device. In claim 4 ,
The upstream port circuit includes:
A wrapper circuit that performs a wrapper process between the ULPI standard bus of the first interface circuit and the bus of the upstream / downstream port circuit;
A ULPI register for the first host / device controller to control a physical layer circuit of the upstream / downstream port circuit;
A data transfer control device comprising: In claim 5 ,
The wrapper circuit is
The upstream / downstream port circuit is connected to a UTMI standard (USB 2.0 Transceiver Macrocell Interface) bus, and the ULPI standard bus of the first interface circuit and the UTMI standard bus of the upstream / downstream port circuit are connected to each other. A data transfer control device that performs a wrapper process between. In claim 6 ,
A data transfer control device comprising: a switching control circuit that controls switching between the hub mode and the device mode based on a register value of the ULPI register. In any one of Claims 1 thru | or 3 ,
The upstream port circuit includes:
A first interface circuit that performs an interface process with a link layer circuit of the first host / device controller;
The first interface circuit includes:
A data transfer control device connected to a first host / device controller via a UTMI standard (USB 2.0 Transceiver Macrocell Interface) bus and performing UTMI interface processing. In any one of Claims 1 thru | or 8 .
The upstream port circuit includes:
A first interface circuit that performs an interface process with a link layer circuit of the first host / device controller;
A second interface circuit for performing an interface process with the hub logic circuit;
A conversion circuit that performs conversion processing of the interface signal of the first interface circuit and the interface signal of the second interface circuit;
A data transfer control device comprising: In claim 9 ,
The second interface circuit includes:
A data transfer control device which is connected to the hub logic circuit via a UTMI standard bus and performs UTMI interface processing with the hub logic circuit. In claim 9 or 10 ,
The conversion circuit includes:
A reception circuit having a reception buffer for buffering reception data from the first host / device controller;
A transmission circuit having a transmission buffer for buffering transmission data to the first host / device controller;
Monitoring the state of the bus connecting the first interface circuit and the first host / device controller and the state of the bus connecting the second interface circuit and the hub logic circuit; A data transfer control device comprising a control circuit for controlling data transfer between a host / device controller and the hub logic circuit. In any of claims 9 to 11 ,
The conversion circuit includes:
A data transfer control device comprising a register for performing emulation processing of control of a physical layer circuit by the first host / device controller. In any one of Claims 1 to 12 ,
In the device mode, the hub logic circuit sets the plurality of downstream port circuits to a suspended state. In any one of Claims 1 to 12 ,
In the device mode, the hub logic circuit sets the plurality of downstream port circuits to a disconnected state. An electronic apparatus comprising the data transfer control device according to any one of claims 1 to 14.

Images