JP5300248B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a charge storage layer on a side of a gate electrode and a manufacturing method thereof.

  In recent years, nonvolatile memories, which are semiconductor devices that can retain data even when the power is turned off, have been widely used. In a flash memory which is a typical non-volatile memory, a transistor constituting a memory cell has a floating gate or an insulating film called a charge storage layer. Data is stored by accumulating charges in the charge accumulation layer. As a flash memory using an insulating film as a charge storage layer, there is a flash memory having a SONOS (Silicon Oxide Nitride Oxide silicon) type structure that stores charges in a trap layer in an ONO (oxide film / nitride film / oxide film) film.

  Patent Documents 1 and 2 disclose flash memories having ONO films on both sides of a gate electrode and storing multiple bits of information in one memory cell. By forming the ONO films on both sides of the gate electrode, interference between two bits stored in one memory cell and charge loss can be suppressed.

  FIG. 1A to FIG. 1D are cross-sectional views of a manufacturing process of a semiconductor device described in Patent Document 1. With reference to FIG. 1A (a diagram corresponding to FIG. 7E of Patent Document 1), a gate electrode 54 is formed on a silicon substrate 50 with a gate insulating film 52 interposed therebetween. A silicon oxide film 56, a silicon nitride film 58, a silicon oxide film 60, and a polysilicon film 64 are formed so as to cover the gate electrode 54. An ONO film 62 is formed from the silicon oxide film 56, the silicon nitride film 58 and the silicon oxide film 60. Sidewall spacers 66 are formed so that the silicon oxide film 56 remains on the silicon substrate 50 and the gate electrode 54. Referring to FIG. 1B (a diagram corresponding to FIG. 9G of Patent Document 1), an impurity diffusion region 68 is formed in the silicon substrate 50 using the gate electrode 14 and the sidewall spacer 66 as a mask. The insulating layer 70 is formed by wet oxidation on the impurity diffusion region 68. With reference to FIG. 1C (a diagram corresponding to FIG. 9H of Patent Document 1), the silicon oxide film 60 on the gate electrode 54 is removed. With reference to FIG. 1D (a diagram corresponding to FIG. 3 of Patent Document 1), a gate line 72 is formed on the gate electrode 54, the sidewall spacer 66, and the insulating layer 70. Thereby, the gate line 72 is electrically connected to the gate electrode 54 and the polysilicon film 64, and is insulated from the impurity diffusion region 68 through the insulating film 28.

2A to 2D are cross-sectional views of the manufacturing process of the semiconductor device described in Patent Document 2. FIG. 2A (a diagram corresponding to FIG. 1 of Patent Document 2), a lower oxide layer 86, a memory layer 88, and an upper oxide layer 90 are sequentially stacked on a semiconductor substrate 80, and an ONO film 92 is formed. Form. An auxiliary layer 100 is formed on the ONO film 92. The memory layer 88 and the upper oxide layer 90 are removed using the auxiliary layer 100 as a mask. A source region and a drain region 96 are formed in the semiconductor substrate 80 using the auxiliary layer 100 as a mask. Referring to FIG. 2B (a diagram corresponding to FIG. 3 in Patent Document 2), an oxide layer 98 is formed on the source and drain regions 96 using the auxiliary layer 100 as a mask. An auxiliary layer 102 is formed on the oxide layer 98. With reference to FIG. 2C (a diagram corresponding to FIG. 4 of Patent Document 2), the spacer 104 is formed on the side surface of the auxiliary layer 102. With reference to FIG. 2D (a diagram corresponding to FIG. 6 of Patent Document 2), a dielectric layer 82 is formed on the side surface of the spacer 104 and the inner surface of the recess 105 on the semiconductor substrate 80. A gate electrode 84 is formed on the dielectric layer 82 in the recess 105. By polishing, the dielectric layer 82 and the gate electrode 84 embedded between the spacers 104 are formed. A word line 106 is formed on the gate electrode 84, the spacer 104, and the auxiliary layer 102. Thereby, the word line 106 is electrically connected to the gate electrode 84 and the spacer 104.
JP 2002-237540 A International Publication No. 2002/011145 Pamphlet

  In the semiconductor device described in Patent Document 2, the dielectric layer 82 that is a gate insulating film is formed in the recess as shown in FIG. For this reason, the dielectric layer 82 is formed using a method such as a CVD method. Therefore, a dielectric film having a good film quality such as a thermal oxide film cannot be used as the gate insulating film. On the other hand, in the semiconductor device described in Patent Document 1, a method of directly oxidizing the semiconductor substrate, such as a thermal oxidation method, is used to form the gate insulating film 52 on the semiconductor substrate 10 as shown in FIG. Can do.

  Referring to FIG. 1D, when writing in the memory cell of Patent Document 1, a positive voltage is applied to the gate line 72, and a high electric field is applied between the impurity diffusion regions 68 that are the bit line or the source region or the drain region. Apply. Thereby, hot electrons generated between the impurity diffusion regions 68 are injected into the region B in the silicon nitride film 58, and charges (electrons) are accumulated. As a result, the memory cell stores data. Further, a negative voltage is applied to the gate line 72 and a high electric field is applied between the impurity diffusion regions 68. Thereby, hot holes are injected into the region B in the silicon nitride film 58, and data is erased.

  The silicon nitride film 58 has an L shape extending from the side of the gate electrode 54 to above the silicon substrate 50. Since the silicon nitride film 58 is an insulator, the accumulated charges are difficult to move. However, when the silicon nitride film 58 and the gate line 72 which is a word line are in contact as in the region A, if a positive voltage is applied to the gate line 72 many times, the silicon nitride film 58 is accumulated. The charged charges may move toward the gate line 72. This makes it difficult to erase the charges accumulated in the silicon nitride film 58.

  In addition, in the region C of FIG. 1D, a so-called bird's beak occurs in which the insulating layer 70 penetrates under the ONO film 62. In the region where the bird's beak has occurred, the thickness of the insulating film between the silicon nitride film 58 and the silicon substrate 50 increases. For this reason, the electric field in the vertical direction becomes weak, and the writing and erasing characteristics deteriorate.

  The present invention has been made in view of the above problems, and an object thereof is to suppress direct contact between a charge storage layer and a word line, and to suppress bird's beaks below the charge storage layer.

  According to the present invention, a step of forming a gate electrode on a semiconductor substrate and a laminated film in which a tunnel insulating film, a charge storage layer made of an insulator, and a dummy insulating film are sequentially formed so as to cover the gate electrode are formed. A step of etching back the laminated film to form a sidewall made of the laminated film on a side surface of the gate electrode; and a step of forming a diffusion region in the semiconductor substrate using the gate electrode and the sidewall as a mask; Removing a dummy insulating film from the side wall; forming a top insulating film on the side wall, the gate electrode and the diffusion region; forming a conductive layer on the top insulating film; A semiconductor comprising: a step of polishing a conductive layer until the gate electrode is exposed; and a step of forming a word line on the gate electrode and the conductive layer It is a method of manufacturing location. According to the present invention, since the top insulating film is formed after the sidewalls are formed, it is possible to prevent the charge storage layer and the word line from being in direct contact with each other by the top insulating film. Further, since the top insulating film is formed on the diffusion region, the diffusion region and the word line can be electrically separated by the top insulating film. Therefore, bird's beaks under the charge storage layer can be suppressed.

  In the above structure, the step of forming the side wall may be a step of forming the side wall so that an upper surface of the charge storage layer in the side wall is lower than an upper surface of the gate electrode. According to this configuration, the diffusion region and the word line can be electrically separated.

  The above structure may include a step of lowering an upper surface of the charge storage layer in the side wall from an upper surface of the gate electrode between the step of forming the side wall and the step of forming the top insulating film. it can. According to this configuration, the diffusion region and the word line can be electrically separated.

  In the above structure, a step of oxidizing the upper surface of the charge storage layer in the side wall may be provided between the step of forming the side wall and the step of forming the top insulating film. According to this configuration, the diffusion region and the word line can be electrically separated.

  In the above structure, the step of oxidizing the upper surface of the charge storage layer may be configured to use a plasma oxidation method or a radical oxidation method. According to this configuration, the diffusion region and the word line can be electrically separated.

  In the above structure, the method may include a step of etching the upper surface of the charge storage layer in the side wall between the step of forming the side wall and the step of forming the top insulating film. According to this configuration, the diffusion region and the word line can be electrically separated.

  In the above configuration, the step of forming the side wall may include a step of etching back the stacked film so that at least a part of the tunnel insulating film remains on the semiconductor substrate. According to this configuration, the polishing of the gate electrode can be suppressed in the step of polishing the conductive layer until the gate electrode is exposed.

  The above structure may include a step of oxidizing the upper surface of the bit line using the gate electrode and the side wall as a mask. According to this configuration, the diffusion region and the word line can be electrically separated.

  The present invention provides a gate electrode provided on a semiconductor substrate, a side surface of the gate electrode, a tunnel insulating film, a charge storage layer made of an insulator, and a top insulating film in order from the gate electrode and the semiconductor substrate. A sidewall provided in a letter shape, a diffusion region provided in a semiconductor substrate beside the gate electrode and the region provided with the sidewall, and a conductive layer provided on the side of the gate electrode via the sidewall. A gate line and a word line provided on the conductive layer so that the top surface of the charge storage layer and the word line are separated from each other by the top insulating film. The semiconductor device is also provided over the diffusion region. According to the present invention, since the top surface of the charge storage layer and the word line are separated from each other by the top insulating film, it is possible to suppress the direct contact between the charge storage layer and the word line. Further, since the top insulating film is provided on the diffusion region, the diffusion region and the word line can be electrically separated by the top insulating film. Therefore, bird's beaks under the charge storage layer can be suppressed.

  In the above structure, an insulating layer may be provided between the diffusion region and the top insulating film. According to this configuration, the diffusion region and the word line can be electrically separated.

  In the above structure, the gate electrode, the side wall, and the upper surface of the conductive layer may be substantially flat.

  According to the present invention, since the top insulating film is formed after the sidewalls are formed, it is possible to prevent the charge storage layer and the word line from being in direct contact with each other by the top insulating film. Further, since the top insulating film is formed on the diffusion region, the diffusion region and the word line can be electrically separated by the top insulating film. Therefore, bird's beaks under the charge storage layer can be suppressed.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 3 is a plan view of the flash memory according to the first embodiment. A diffusion region which is a bit line is provided in the semiconductor substrate 10. A side wall made of the ONO film 32 is provided on the semiconductor substrate 10 next to the diffusion region 26. A word line 36 intersecting with the diffusion region 26 is provided on the semiconductor substrate 10 and the ONO film 32 which is a side wall.

  A method for manufacturing the semiconductor device according to the first embodiment will be described with reference to FIGS. 4 (a) to 6 (c) are cross-sectional views corresponding to the AA cross section of FIG. Referring to FIG. 4A, a gate insulating film 12 made of a silicon oxide film is formed on a p-type silicon semiconductor substrate (or a p-type region in the silicon semiconductor substrate) 10 by using, for example, a thermal oxidation method. A gate electrode 14 made of polysilicon is formed on the semiconductor substrate 10 via a gate insulating film 12. A predetermined region of the gate electrode 14 and the gate insulating film 12 is removed. Thus, the stripe-like gate electrode 14 and the gate insulating film 12 extending in the direction in which the diffusion region 26 in FIG. 3 extends are formed.

  Referring to FIG. 4B, a tunnel insulating film 16 made of a silicon oxide film is formed on the semiconductor substrate 10 and the gate electrode 14 by using, for example, a thermal oxidation method. A charge storage layer 18 made of a silicon nitride film is formed on the tunnel insulating film 16 by using, for example, a CVD (Chemical Vapor Deposition) method. A dummy insulating film 20 made of a silicon oxide film is formed on the charge storage layer 18 by using, for example, a CVD method. Thereby, the laminated film 22 is formed so as to cover the gate electrode 14. Referring to FIG. 4C, the entire surface of the laminated film 22 is etched back, so that side walls 24 made of the laminated film 22 are formed on both side surfaces of the gate electrode 14. At this time, for example, the tunnel insulating film 16 remains on the semiconductor substrate 10 and the gate electrode 14.

  Referring to FIG. 5A, for example, arsenic ions are implanted into the semiconductor substrate 10 using the gate electrode 14 and the side wall 24 as a mask. Thereafter, the n-type diffusion region 26 is formed in the semiconductor substrate 10 by heat treatment. At this time, the tunnel insulating film 16 formed on the semiconductor substrate 10 functions as a through film for ion implantation. Of the dummy insulating film 20 and the side wall 24 remaining on the semiconductor substrate 10 and the gate electrode 14, the dummy insulating film 20 is removed using, for example, a hydrofluoric acid chemical solution. Referring to FIG. 5B, the insulating layer 28 is formed by, for example, thermally oxidizing the surface of the diffusion region 26 using the gate electrode 14 and the sidewall 24 as a mask. As a result, the insulating layer 28 is formed in a self-aligned manner with the diffusion region 26. Referring to FIG. 5C, a top insulating film 30 made of a silicon oxide film is formed on the gate electrode 14, the side wall 24, and the diffusion region 26 through an insulating layer 28 by using, for example, a CVD method. As a result, the ONO film 32 including the L-shaped charge storage layer 18 is formed on the side surface of the gate electrode 14.

  With reference to FIG. 6A, a conductive layer 34 made of polysilicon is formed on the top insulating film 30. Referring to FIG. 6B, the conductive layer 34 is polished using a CMP (Chemical Mechanical Polish) method until the gate electrode 14 is exposed. As a result, the upper surfaces of the gate electrode 14, the sidewall 24, and the conductive layer 34 are substantially flat. Note that “substantially flat” means flat as polished. Referring to FIG. 6C, a polysilicon film is formed on the gate electrode 14 and the conductive layer 34. As shown in FIG. 3, the conductive polysilicon film, the conductive layer 34, and the gate electrode 14 are etched so that the word line 36 intersects the diffusion region 26 that is a bit line. As a result, the word line 36 is formed on the gate electrode 14 and the conductive layer 34. As described above, the gate electrode 14 and the conductive layer 34 are electrically connected to the word line 36. The word line 36 and the diffusion region 26 are separated by an insulating layer 28.

  The effect of the flash memory according to the first embodiment will be described with reference to FIGS. 7A and 7B. 7 (a) and 7 (b) are enlarged views of the vicinity of the side surface of the gate electrode 14 in FIGS. 4 (c) and 6 (c), respectively. However, in this example, the etch back is performed so that the tunnel insulating film 16 is removed and the semiconductor substrate 10 is exposed during the etch back of the stacked film of FIG. With reference to FIG. 7A, when the sidewall 24 is formed, the sidewall 24 is formed such that the upper surface of the charge storage layer 18 in the sidewall 24 is lower than the upper surface of the gate electrode 14 by a height H1. Thereafter, a top insulating film 30 is formed on the upper surface of the charge storage layer 18 as shown in FIG. As shown in FIG. 6B, the conductive layer 34 formed on the top insulating film 30 is polished so that the gate electrode 14 is exposed. At this time, since the gate electrode 14 is hardly polished, the height difference between the upper surface of the charge storage layer 18 and the upper surface of the gate electrode 14 remains substantially H1, as shown in FIG. 7B. . Therefore, the charge storage layer 18, the word line 36, and the conductive layer 34 are insulated by the top insulating film 30. Thereby, as in the region A of FIG. 1D, the contact between the gate line 72 as a word line and the silicon nitride film 58 as a charge storage layer can be suppressed. Therefore, it is possible to prevent the charge accumulated in the region B in FIG. 1D from moving toward the gate line 72 and making it difficult to erase the charge.

  FIG. 8 is an enlarged view of the vicinity of the side surface of the gate electrode 54 in FIG. An insulating layer 70 is formed to electrically isolate the impurity diffusion region 68 and the gate line 72. The film thickness Tox0 of the insulating layer 70 is a size required for electrically separating the impurity diffusion region 68 and the gate line 72 from each other. At this time, a bird's beak is generated between the ONO film 62 and the silicon substrate 50. The width W0 of the bird's beak increases as the film thickness Tox0 of the insulating layer 70 increases.

  With reference to FIG. 7B, in Example 1, the top insulating film 30 is formed on the insulating layer 28. That is, in FIG. 5C, the top insulating film 30 is also formed on the diffusion region 26. For this reason, as shown in FIG. 7B, the film thickness Tox of the insulating layer separating the diffusion region 26 and the conductive layer 34 is the sum of the film thickness Tox1 of the insulating layer 28 and the film thickness Tox2 of the top insulating film 30. Become. The film thickness Tox shown in FIG. 7B required for electrically separating the diffusion region 26 and the conductive layer 34, and FIG. 8 required for electrically separating the impurity diffusion region 68 and the gate line 72 from each other. Is substantially the same as the film thickness Tox0. Therefore, the film thickness Tox1 of the insulating layer 28 formed by thermal oxidation can be made smaller than the film thickness Tox0 in FIG. 8 by a film thickness corresponding to the film thickness Tox2. Therefore, the width W1 of the bird's beak in FIG. 7B can be made smaller than the width W0 of the bird's beak in FIG.

  In FIG. 7A, when the laminated film 22 is etched back, the tunnel insulating film 16 is etched back. However, as shown in FIG. 4C, the step of forming the sidewall 24 is performed on the semiconductor substrate 10. The laminated film 22 is preferably etched back so that at least a part of the tunnel insulating film 16 remains. Thereby, as shown in FIG. 6B, when the conductive layer 34 is polished, the end point can be detected using the tunnel insulating film 16. Thereby, polishing can be stopped on the upper surface of the gate electrode 14. Therefore, the height H1 between the upper surface of the charge storage layer 18 and the gate electrode 14 in FIG. 7B can be formed with high accuracy.

  The second embodiment is an example having a step of making the upper surface of the charge storage layer in the sidewall lower than the gate electrode 14. FIG. 9A and FIG. 9B are cross-sectional views illustrating the manufacturing process of the flash memory according to the second embodiment. The gate electrodes correspond to FIGS. 4C and 6C of the first embodiment, respectively. 14 is an enlarged view of the vicinity of 14 side surfaces. FIG. Referring to FIG. 9A, after FIG. 4C of the first embodiment, the charge storage layer 18 is oxidized using a plasma oxidation method, and the oxidized region 40a and the charge storage layer 18 are formed on the upper surface of the charge storage layer 18. An oxidized region 40b is formed on the side surface of the substrate. As a result, the upper surface of the charge storage layer 18 can be made lower than the gate electrode 14 by a height H2. Thereafter, the steps from FIG. 5A to FIG. 6C of Example 1 are performed. In FIG. 5A, when the tunnel insulating film 16 is removed, the oxidized region 40a and the oxidized region 40b are removed.

  According to the second embodiment, with reference to FIG. 9B, the top insulating film 30 can insulate and isolate the charge storage layer 18 from the word line 36 or the conductive layer 34. For the oxidation of the charge storage layer 18, for example, a method of sufficiently oxidizing a silicon nitride film is preferable, for example, a radical oxidation method can be used. Further, similarly to the first embodiment, the width W2 of the bird's beak when forming the insulating layer 28 can be made narrower than that of FIG.

  The third embodiment is another example having a step of lowering the upper surface of the charge storage layer in the side wall than the gate electrode 14. FIGS. 10A and 10B show the manufacturing process of the flash memory according to the third embodiment. FIG. 4 is an enlarged view of the vicinity of the side surface of the gate electrode 14 of FIGS. 4C and 6C of the first embodiment. Referring to FIG. 10A, after FIG. 4C of the first embodiment, the charge storage layer 18 is etched using, for example, hot phosphoric acid. The upper surface of the charge storage layer 18 and the side surface of the charge storage layer 18 are etched like the recesses 42a and 42b. As a result, the upper surface of the charge storage layer 18 can be made lower than the gate electrode 14 by a height H3. Thereafter, the steps from FIG. 5A to FIG. 6C of Example 1 are performed. In FIG. 5A, when the tunnel insulating film 16 is removed, the tunnel insulating film 16 corresponding to the recesses 42a and 42b is also removed.

  According to the third embodiment, with reference to FIG. 10B, the top insulating film 30 can reliably insulate and isolate the charge storage layer 18 from the word line 36 or the conductive layer 34. Further, the bird's beak when forming the insulating layer 28 can be reduced.

  As shown in FIG. 5B of the first to third embodiments, it is preferable to have a step of oxidizing the upper surface of the diffusion region 26 using the gate electrode 14 and the side wall 24 as a mask. When the insulating layer 28 is not formed, electrical isolation between the insulating layer 28 and the conductive layer 34 can be performed using the top oxide film 30. However, in this case, electrical separation may not be sufficient. By providing the insulating layer 28, the diffusion region 26 and the conductive layer 34 can be electrically separated.

  The preferred embodiments of the present invention have been described in detail above, but the present invention is not limited to such specific embodiments, and various modifications can be made within the scope of the gist of the present invention described in the claims.・ Change is possible.

FIG. 1A to FIG. 1D are cross-sectional views showing the manufacturing process of the semiconductor device described in Patent Document 1. 2A to 2D are cross-sectional views showing the manufacturing process of the semiconductor device described in Patent Document 2. FIG. FIG. 3 is a plan view of the flash memory according to the first embodiment. FIG. 4A to FIG. 4C are diagrams (part 1) illustrating the manufacturing process of the flash memory according to the first embodiment. FIG. 5A to FIG. 5C are diagrams (part 2) illustrating the manufacturing process of the flash memory according to the first embodiment. FIGS. 6A to 6C are views (No. 3) illustrating the manufacturing process of the flash memory according to the first embodiment. FIG. 7A and FIG. 7B are enlarged views showing the manufacturing process of the flash memory according to the first embodiment. FIG. 8 is an enlarged view of FIG. FIG. 9A and FIG. 9B are cross-sectional views illustrating the manufacturing process of the flash memory according to the second embodiment. FIG. 10A and FIG. 10B are cross-sectional views illustrating the manufacturing process of the flash memory according to the third embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Semiconductor substrate 14 Gate electrode 16 Tunnel insulating film 18 Charge storage layer 20 Dummy insulating layer 22 Laminated film 24 Side wall 26 Diffusion area 28 Insulating layer 30 Top insulating film 32 ONO film 34 Conductive layer 36 Word line

Claims (11)

Forming a gate electrode on the semiconductor substrate;
Forming a laminated film in which a tunnel insulating film, a charge storage layer made of an insulator, and a dummy insulating film are sequentially formed so as to cover the gate electrode;
Etching back the laminated film and forming a side wall made of the laminated film on a side surface of the gate electrode;
Forming a diffusion region in the semiconductor substrate using the gate electrode and the sidewall as a mask;
Removing the dummy insulating film from the side wall;
Forming a top insulating film on the sidewall, the gate electrode and the diffusion region;
Forming a conductive layer on the top insulating film;
Polishing the conductive layer until the gate electrode is exposed;
Forming a word line on the gate electrode and the conductive layer. A method for manufacturing a semiconductor device, comprising:   2. The semiconductor device according to claim 1, wherein the step of forming the side wall is a step of forming the side wall so that an upper surface of the charge storage layer in the side wall is lower than an upper surface of the gate electrode. Manufacturing method.   2. The method according to claim 1, further comprising a step of lowering an upper surface of the charge storage layer in the side wall from an upper surface of the gate electrode between the step of forming the side wall and the step of forming the top insulating film. Semiconductor device manufacturing method.   2. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of oxidizing an upper surface of the charge storage layer in the side wall between the step of forming the side wall and the step of forming the top insulating film. .   5. The method of manufacturing a semiconductor device according to claim 4, wherein the step of oxidizing the upper surface of the charge storage layer uses a plasma oxidation method or a radical oxidation method.   2. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of etching an upper surface of the charge storage layer in the side wall between the step of forming the side wall and the step of forming the top insulating film. .   The step of forming the side wall includes a step of etching back the laminated film so that at least a part of the tunnel insulating film remains on the semiconductor substrate. A method for manufacturing a semiconductor device according to item. 8. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of oxidizing an upper surface of the diffusion region using the gate electrode and the side wall as a mask. A gate electrode provided on a semiconductor substrate;
A side wall formed on a side surface of the gate electrode, a tunnel insulating film, a charge storage layer made of an insulator, a top insulating film provided in an L shape in order from the gate electrode and the semiconductor substrate;
A diffusion region provided in a semiconductor substrate next to the region provided with the gate electrode and the side wall;
A conductive layer provided on the side of the gate electrode via the side wall;
A word line provided on the gate electrode and the conductive layer so that the top surface of the charge storage layer and the word line are separated by the top insulating film;
Comprising
The semiconductor device according to claim 1, wherein the top insulating film is also provided on the diffusion region.   The semiconductor device according to claim 9, wherein an insulating layer is provided between the diffusion region and the top insulating film.   11. The semiconductor device according to claim 9, wherein upper surfaces of the gate electrode, the side wall, and the conductive layer are substantially flat.

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