JP5303488B2 - Amplitude suppression circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a reproduction sound with high quality as a sound regardless of a small dynamic range and to manufacture an excellent device for difficulty in hearing or an acoustic device capable of outputting a relatively high-volume sound even with small output. <P>SOLUTION: An amplitude suppressing circuit includes: a logarithmic compressor 4 for compressing the amplitude of an input signal; an OUTPUT circuit for outside outputting an output signal from the logarithmic compressor 4; a bias control circuit 2 for controlling an amplitude suppression amount and an output potential of the logarithmic compressor 4; and a control signal generating circuit for inputting a bias control signal to the bias control circuit 2. The bias control signal generating circuit includes operational amplifiers 5 and 6 each for inputting the output of the logarithmic compressor 4 to a positive output circuit. A negative feedback circuit is connected to a negative input circuit of the operational amplifier 5. An output of the operational amplifier 5 is connected to a negative input circuit of the operational amplifier 6, and an output of the operational amplifier 6 and the output signal from the input circuit are connected to the OUTPUT circuit. The output of the operational amplifier 6 and the output of the logarithmic compressor 4 are connected to a subtractor 3 that comparing these outputs with each other. <P>COPYRIGHT: (C)2011,JPO&amp;INPIT

Description

  The present invention relates to a circuit that suppresses the amplitude of an AC signal such as an audio signal.

As an amplitude suppression technique for an audio signal or the like, an AGC (automatic gain control) circuit in which the gain of an amplifier changes according to the magnitude of an input signal is known. However, in the case of an audio signal, the reproduced sound of the signal whose amplitude is suppressed by the AGC circuit is
(1) If a large signal and a small signal are present at the same time, it is difficult to hear the small signal.
(2) The playback volume may fluctuate unstable.
(3) Slow response to impact sound.
There are disadvantages such as.

  In addition, amplitude suppression by a non-linear amplifier often used in hearing aids or the like is capable of more stable amplitude suppression than AGC, but has a drawback that a small signal may be difficult to hear. Therefore, there has been a demand for an amplitude suppression circuit that does not feel quality degradation even when strong amplitude suppression is performed.

  From this point of view, proposals relating to amplitude suppression circuits have been conventionally made, for example, as shown in Patent Documents 1 to 3.

JP 2006-197580 A JP 2006-197525 A JP 2006-025382 A

  As is well known, when a capacitor is further connected in series to diode circuits connected in parallel in opposite directions, and an AC signal is applied to both ends thereof, an amplitude-limited signal can be taken out at both ends of the diode. However, when strong amplitude limitation is performed by such a circuit, a strong harmonic signal is generated in the output signal. In the case of an audio signal, this harmonic signal causes unpleasant playback sound. The reason why a strong harmonic signal is generated in such a circuit is that a sudden amplitude limit is performed at the amplitude limit level.

  In order to remove this harmonic signal, in the inventions described in Patent Documents 1 to 3, high frequency harmonic components generated by amplitude suppression are removed by an integrating circuit. Certainly, in terms of improving the quality of the reproduced sound, a considerable effect is recognized even with this conventional technique. However, since it does not prevent the generation of the harmonic signal itself during amplitude suppression, there is a limit to the removal of the harmonic component, and a proposal of a more effective method has been desired.

  The present invention has been proposed in order to solve the above-described problems of the prior art. The purpose of the present invention is to minimize the quality degradation even when strong amplitude suppression is performed on the AC signal, or to reduce the quality degradation. An object of the present invention is to provide an amplitude suppression circuit that does not make it feel.

  In order to achieve the above object, the amplitude suppression circuit of the present invention performs logarithmic compression of the amplitude value change amount in the same direction when the peak value of the input signal changes in the plus direction, and outputs the compressed signal. When the change direction of the input signal waveform is reversed and the amplitude value starts to decrease, the compression operation is canceled and the continuation of the input signal waveform is output starting from the output peak value when the compression operation is stopped. Logarithmic compression is performed on the amount of amplitude change in the direction. By repeating such an operation, the amplitude of the AC signal is suppressed.

  In the prior art, in order to reduce the harmonic component generated by the amplitude suppression circuit, the high frequency harmonic component generated by the amplitude suppression is removed by the integration circuit, whereas in the present invention, the harmonic component is removed by logarithmic compression. Since the occurrence of this is suppressed, the amplitude limiting operation is performed smoothly.

  That is, when the rectangular group is subjected to spectrum analysis (Fourier analysis), an infinite number of frequency signals appear on the basis of the lowest frequency signal. In this case, how many times the frequency is different depends on the duty of the rectangular wave. That is, it can be said that a complete rectangular wave is obtained by adding countless f to ∞f sine waveform signals. And if a high frequency component is removed from a rectangular wave through a high cut filter, the rectangular wave becomes a waveform with rounded corners. That is, it can be said that a rectangular wave with rounded corners does not contain a high frequency signal or has a low level. When the level of the audio signal is abruptly limited as in the prior art, the restricted portion is in the same state as the non-round corner of the rectangular wave, and the signal includes many harmonic signals. That is, if this corner is rounded and smoothed, the generation of harmonic signals can be prevented or reduced. Therefore, in the present invention, the generation of harmonic signals is prevented or reduced by using logarithmic compression in order to round the corners of the waveform when the amplitude is limited.

  If the present invention is used for suppressing the amplitude of an audio signal, it is possible to obtain a reproduced sound that is excellent in quality as a sound and is easier to hear than the original sound even though the dynamic range is small. For this reason, it is possible to manufacture excellent deafness devices and sound devices that can produce relatively loud sounds even with a small output.

1 is a block diagram showing the configuration of Embodiment 1 of the present invention. The figure which shows the waveform in each part of the circuit of FIG. The block diagram which shows the structure of Example 2 of this invention.

  A first embodiment of the present invention will be described below with reference to a block circuit diagram shown in FIG. In this circuit, when the potential of the OUTPUT circuit is positive, the potential of the OUTPUT circuit follows the change in the output potential of the logarithmic compressor 4 when the potential of the input signal rises, and when the potential of the OUTPUT circuit falls, the potential of the OUTPUT circuit is logarithmically changed. The output potential of the compressor 4 follows. On the other hand, when the potential of the OUTPUT circuit is in the negative range, the potential of the OUTPUT circuit follows the change in the potential of the logarithmic compressor 4 when the potential of the input signal drops, and when the potential rises, the logarithmic compressor responds to the change in the potential of the OUTPUT circuit. The output potential of 4 follows.

Hereinafter, the configuration and operation of the circuit of FIG. 1 will be described.
(1) The signal input to the INPUT circuit is input to the logarithmic compressor 4 via the buffer amplifier 1 and also transmitted to the OUTPUT circuit via the capacitor C1.

(2) The output signal of the logarithmic compressor 4 is applied to the positive input circuit of the operational amplifier 5 and the input circuit of the subtractor 3, and further to the positive input circuit of the operational amplifier 6.

(3) The operational amplifier 5 is an amplifier provided with a negative feedback circuit including a diode D1 and a diode D2. The resistor R1 is also a part of the negative feedback circuit.

(4) The voltage of the OUTPUT circuit is applied to one of the input circuits of the subtractor 3, and the output voltage of the logarithmic compressor 4 is applied to the other input circuit. The two voltages are subtracted by the subtracter 3, and the result is output from the subtractor 3.

(5) The output signal of the subtracter 3 is input to the bias control circuit 2. The bias control circuit 2 controls the bias of the logarithmic compressor 4 based on the output signal (bias control signal) of the subtractor 3. That is, the output potential of the logarithmic compressor 4 is controlled so that the levels of the two input signals of the subtracter 3 are equal. Operational amplifiers 5 and 6 produce the signals input to the subtracters 3 and each element such as a diode connected and resist these constitute a bias control signal generation circuit of the present invention.

(6) The output signal from the logarithmic compressor 4 is input to the positive input circuit of the operational amplifier 5, and the same signal as the positive input circuit of the operational amplifier 5 is input to the positive input circuit of the operational amplifier 6. The output signal of the operational amplifier 5 is applied to the negative input circuit of the operational amplifier 6 via the resistor R2. The resistance values of the resistors R2 and R3 are set equal. That is, the operational amplifier 6 viewed from the output side of the operational amplifier 5 is an inverting amplifier having an amplification factor of −1 using the output of the logarithmic compressor 4 as a bias potential.

(7) The output circuit and the OUTPUT circuit of the operational amplifier 6 are coupled by a diode D3 and a diode D4 connected in parallel in opposite directions.

(8) When a signal starting from the GND potential and going upward is input to the INPUT circuit, this signal is input to the logarithmic compressor 4 through the buffer amplifier 1 and logarithmically compressed therein.

(9) The output signal of the logarithmic compressor 4 logarithmically compressed is applied to the positive input circuit of the operational amplifier 5. The diode D1, the diode D2, and the resistor R1 form a negative feedback circuit of the operational amplifier 5. Since the input signal potential of the operational amplifier 5 is positive, a signal having a potential higher than the input signal potential (the output potential of the logarithmic compressor 4) by the forward voltage of the diode D2 appears in the output circuit of the operational amplifier 5. Since this signal is inverted by the operational amplifier 6 with reference to the potential of the positive input circuit, a potential lower than the output potential of the logarithmic compressor 4 by the forward voltage of the diode D2 appears in the output circuit of the operational amplifier 6.

(10) Since the output signal of the buffer amplifier 1 is transmitted to the OUTPUT circuit via the capacitor C1, the potential of the OUTPUT circuit tends to change in the same manner as the output signal of the buffer amplifier 1, but current flows through the diode D4. It is suppressed to the same as the output potential of the logarithmic compressor 4. In this case, the forward voltage of the diode D4 and the forward voltage of the diode D2 are the same. As a result, the capacitor C1 is charged and the bias of the OUTPUT circuit is shifted downward. This operation continues until the direction of change of the input signal voltage waveform starts to decrease.

(11) When the potential change direction of the input signal changes from rising to falling, the potential of the OUTPUT circuit drops by the same amount as that of the INPUT circuit. At this time, since the voltages across the diodes D3 and D4 are lower than the forward voltage of the diode, the OUTPUT circuit potential is not affected by the output potential of the operational amplifier 6. As a result, the bias of the logarithmic compressor 4 is controlled, and the output potential of the logarithmic compressor 4 follows the OUTPUT circuit potential and drops by the same amount. This operation continues until the change direction of the input signal potential is reversed or the output potential of the logarithmic compressor 4 becomes negative.

(12) When the drop of the input signal potential proceeds and the output potential of the logarithmic compressor 4 becomes negative, the output potential of the operational amplifier 6 becomes higher than the output potential of the logarithmic compressor 4 by the forward voltage of the diode D1. For this reason, even if the potential of the OUTPUT circuit is made lower than the output potential of the logarithmic compressor 4 due to the signal transmitted to the OUTPUT circuit via the capacitor C1, a current flows through the diode D3 and the same amount as the output potential of the logarithmic compressor 4. Can be suppressed by descent. At this time, the capacitor C1 is discharged, and the bias potential of the OUTPUT circuit is shifted to the higher side. This operation continues until the potential change direction of the input signal starts to rise.

(13) When the potential change of the input signal starts from falling to rising, the potential of the OUTPUT circuit increases by the same amount as that of the INPUT circuit. Therefore, the bias of the logarithmic compressor 4 is controlled, and the output potential of the logarithmic compressor 4 increases by the same amount following the change in the OUTPUT circuit potential. This operation continues until the change direction of the input signal potential is reversed or the output potential of the operational amplifier 4 becomes positive.

(14) The operations (8) to (13) are repeated, and a signal in which the amplitude of the input voltage signal is suppressed appears in the OUTPUT circuit. In this circuit, the higher the frequency signal, the easier the output voltage becomes, but correction is possible in the circuit.

  FIG. 2 is a waveform example of each part in the circuit shown in the block diagram of FIG. The portions indicated by (a) to (d) in FIG. 1 correspond to the waveform of the same character in FIG.

(a) is an output voltage waveform of the buffer amplifier 1, which is a form of the signal inputted to the INPUT circuit as it is.

(b) is an output voltage waveform of the logarithmic compressor 4, and the waveform of (a) is logarithmically compressed. The compression method is as follows: (a) T2 to T3 waveform is compressed to (b) T2 to T3 waveform, (a) T4 to T5 waveform is (b) T4 to T5 interval It is compressed into a waveform. The section from T1 to T2 and the section from T3 to T4 are not compressed for the convenience of the circuit, but there is no harm to the function of the present invention.

(c) is the output waveform of the operational amplifier 6, and its potential is normally lower than the potential by the forward voltage of the diode D2 when the waveform potential of (b) is positive, and the forward direction of the diode D1 when negative. High voltage.

(d) is the waveform of the OUTPUT circuit and is equivalent to the waveform of (b). Note that the small amplitude portion of the input signal is mostly contained in the section from T1 to T2 or the section where the compression amount is small, and therefore appears in the OUTPUT circuit without being compressed so much.

  According to the circuit of the first embodiment having such a configuration, an input signal with a low level is output as it is, and if the input signal is large (plus or minus), the level can be suppressed by logarithmic compression. is there. When the absolute value of the waveform value of the input signal starts from increasing to decreasing, the previous logarithmic compression operation is canceled, and the subsequent input signal is newly compressed starting from the compressed level at that time. It is the characteristic of the compression operation by the circuit of the present invention that is output at the same time.

  In particular, in the present invention, when the bias direction of the logarithmic compression circuit is biased and the change direction of the input signal waveform is reversed during logarithmic compression, the logarithmic compression is newly started from the level at which the change direction is reversed, although not necessarily the initial state. . If this is not done, normal compression operation cannot be performed after inversion. In this embodiment, however, the output circuit voltage and the logarithmic compressor output voltage are compared, and the change in the potential of the OUTPUT circuit and logarithmic compression are performed. By controlling each other so that the output voltage of the detector becomes the same value, it is possible to always change an appropriate bias value for a signal whose level fluctuates irregularly.

  As a result, in the present embodiment, the waveform of the small level change portion (although the small change portion is in any level portion of the original waveform) is output almost as it is with the bias change, and the large signal is below the limit level. Limited output. As a result, the distortion of the output signal is minimal for a small signal, and the high frequency has few harmonics even if the large signal is distorted.

  In general, when the amplitude is suppressed, the signal is distorted. However, in this embodiment, in the waveform diagram of FIG. 2, since the amplitude is not compressed at T1-T2 and T3-T4, the signal is not distorted in principle in this portion. Therefore, in this circuit, the waveform distortion of the small-level signal is minimal, and a preferable result can be obtained as audio signal processing.

  FIG. 3 is a block diagram showing a circuit according to the second embodiment of the present invention. The basic operation of this circuit is the same as that of FIG. 1, but the signal dividing circuit 11, the operational amplifier 12, the operational amplifier 13 and their peripheral circuits are different in configuration from those in FIG. Here, the same parts as those in FIG.

(1) The signal dividing circuit 11 divides the output signal of the logarithmic compressor 10 into a positive level portion and a negative level portion, and outputs them to two output circuits. That is, the operational amplifier 12 the signal of the positive portion, and outputs a signal of the negative part to the operational amplifier 1 3. If the input potentials of both the operational amplifier 12 and the operational amplifier 13 are at the GND level, these amplifiers in principle do not pass current through either the diode D7 or the diode D8, but a slight difference may occur. That is, there is a possibility that current flows from the output circuit of the operational amplifier 13 toward the output circuit of the operational amplifier 12. In order to avoid this, the circuit design should be such that the potential of the positive input circuit of the operational amplifier 12 is slightly higher than the GND level even if it is low, and the potential of the positive input circuit of the operational amplifier 13 is slightly lower than the GND level even if it is high. (A resistor may be provided between the diode D7 and the operational amplifier 12 and between the diode D8 and the operational amplifier 13). This consideration may also be necessary for the circuit to be activated.

(2) Although the negative input circuit of the operational amplifier 12 and the B + power supply circuit are connected by the resistor R4, the potential of the negative input circuit is pulled down to the same potential as that of the positive input circuit by the potential of the output circuit via the diode D5. . That is, the potential of the output circuit is lower than the potential of the positive input circuit by the forward voltage of the diode D5. Therefore, even if the output signal of the buffer amplifier 7 transmitted through the capacitor C2 path causes the potential of the output circuit to be higher than the potential of the positive input circuit, a current flows through the diode D7 and the potential increase of the OUTPUT circuit is the same as the positive input circuit potential. Can be suppressed.

(3) When the potential change direction of the output signal of the buffer amplifier 7 starts to decrease, the OUTPUT circuit potential also decreases by the same amount. At this time, since the difference between the output potential of the operational amplifier 12 and the OUTPUT circuit is smaller than the forward potential of the diode D7, the output signal of the operational amplifier 12 does not affect the OUTPUT circuit. Therefore, the change in the output signal of the buffer amplifier 7 appears in the OUTPUT circuit as it is.

(4) When the potential of the OUTPUT circuit drops, the output potential of the logarithmic compressor 10 similarly drops.
This is because the bias of the logarithmic compressor 10 is controlled by the subtractor 9 and the bias control circuit 8 so as to be so.

(5) When the potential drop of the signal advances and the output potential of the logarithmic compressor 10 becomes negative, the OUTPUT circuit potential change follows the change of the output potential of the logarithmic compressor 10. That is, if the output signal of the buffer amplifier 7 transmitted through the capacitor C2 path causes the potential of the OUTPUT circuit to become lower than the potential of the positive input circuit, a current flows through the diode D8, and the drop in the OUTPUT circuit potential is the same as the positive input potential. It can be suppressed. (The negative input circuit of the operational amplifier 13 and the B-power supply circuit are connected by a resistor R5, but the potential of the negative input circuit is raised to the same potential as the positive input circuit by the output circuit potential via the diode D6. The potential of the output circuit is higher than the potential of the positive input circuit by the forward voltage of the diode D6.) This operation continues until the signal potential change direction starts to rise.

(6) When the potential change direction of the output signal of the buffer amplifier 7 starts to rise, the OUTPUT circuit potential also rises by the same amount. At this time, since the difference between the output potential of the operational amplifier 13 and the OUTPUT circuit is smaller than the forward potential of the diode D8, the output potential of the operational amplifier 13 does not affect the OUTPUT circuit. Therefore, the change in the output signal of the buffer amplifier 7 appears in the OUTPUT circuit as it is.

(7) When the potential of the OUTPUT circuit rises, the output potential of the logarithmic compressor 10 rises similarly.
This is because the bias of the logarithmic compressor 10 is controlled by the subtractor 9 and the bias control circuit 8 so as to be so.

(8) (2) to (7) are repeated, and an amplitude-compressed signal is output to the OUTPUT circuit.

  Also in the second embodiment, the same effect as that of the first embodiment is exhibited. However, in the circuit of the first embodiment, the current flowing through the diode D1 or D2 and the current flowing through the diode D3 or D4 cannot be the same, and therefore the amplitude limit value tends to increase as the frequency increases (the effect increases as the frequency increases). . In addition, the output signal of the buffer amplifier 6 is slightly delayed compared to the output signal of the buffer amplifier 1, which may adversely affect the output signal. These drawbacks can be reduced by devising the circuit of the first embodiment, but the circuit of the second embodiment has an advantage that such a phenomenon can be extremely reduced in principle. However, the circuit of the first embodiment is easier to design.

  Note that the present invention is not limited to the illustrated circuit, and other embodiments may be employed. For example, by digitally processing the input signal waveform, logarithmic compression and its cancellation can be performed according to the direction of change in the level of the input signal waveform.

  The present invention is suitable for hearing aids and telephones that are easy to hear serious deafness and have little burden on the ear, or acoustic equipment that can produce a loud sound with a small output amplifier, and collect distant sounds without being disturbed by nearby loud sounds. Microphones that can be used for sound, recorders that require almost no recording level adjustment, and that do not have the disadvantages of AGC have great utility value. In addition, the development of products using a sound signal amplitude suppression circuit that operates in this way is almost untouched, and a very large market can be expected.

DESCRIPTION OF SYMBOLS 1 ... Buffer amplifier 2 ... Bias control circuit 3 ... Subtractor 4 ... Logarithmic compressor 5 ... Operational amplifier 6 ... Operational amplifier 7 ... Buffer amplifier 8 ... Bias control circuit 9 ... Subtractor 10 ... Logarithmic compressor 11 ... Signal division circuit 12 Operational amplifier 13 Operational amplifier B + Positive power supply B− Negative power supply C1 to C2 Capacitors D1 to D8 Diodes R1 to R5 Resistance INPUT Input circuit OUTPUT Output circuit + Positive input circuit − Negative input circuit

Claims (4)

Means for logarithmically compressing the input signal waveform with respect to the level change direction;
When the change direction of the input signal waveform level is inverted, the logarithmic compression operation so far is canceled, logarithmic compression is started in the inverted amplitude change direction, and the compressed signal is output. Amplitude suppression circuit. A logarithmic compressor for compressing the amplitude of the input signal; an output circuit for outputting an output signal from the logarithmic compressor to the outside; a bias control circuit for controlling the operation reference potential of the logarithmic compressor by bias shift; A control signal generation circuit for inputting a bias control signal to the bias control circuit is provided.
In the bias control signal generation circuit, when the potential of the output signal of the output circuit is positive, when the potential of the input signal rises, the potential of the output circuit follows the change in the output potential of the logarithmic compressor and falls. When the output potential of the logarithmic compressor follows the change in the potential of the output circuit, and when the potential of the output circuit falls in the negative range, the potential of the output circuit is the output of the logarithmic compressor The bias control circuit generates a signal for controlling the bias potential of the logarithmic compressor so that the output potential of the logarithmic compressor follows the potential change of the output circuit when rising. An amplitude suppression circuit. The bias control signal generation circuit includes two operational amplifiers that input the output of the logarithmic compressor to a positive input circuit;
A negative feedback circuit is connected to the negative input circuit of the first operational amplifier, an output of the first operational amplifier is connected to the negative input circuit of the second operational amplifier, the output of the second operational amplifier, The output signal from the input circuit is connected to the output circuit,
The amplitude suppression circuit according to claim 2, wherein the output of the second operational amplifier and the output of the logarithmic compressor are connected to a subtractor for comparing them. The bias control signal generation circuit includes a signal division circuit that divides the output of the logarithmic compressor into a positive level portion and a negative level portion, and a first operational amplifier that inputs a positive level signal divided by the signal division circuit; A second operational amplifier for inputting a negative level signal;
The outputs of these two operational amplifiers are connected to the output circuit together with the input signal,
The amplitude suppression circuit according to claim 2, wherein the output of the two operational amplifiers and the output of the logarithmic compressor are connected to a subtractor for comparing them.

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