JP5303845B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor element that requires processing of the back surface of a wafer, and more particularly to a method for manufacturing a power semiconductor element such as an insulated gate bipolar transistor (hereinafter referred to as IGBT).

  2. Description of the Related Art Conventionally, an integrated circuit (IC) in which a large number of transistors, resistors, and the like are connected to form an electric circuit and integrated on a single chip is often used as a main part of a computer or a communication device. Among such ICs, those including power semiconductor elements are called power ICs, and IGBTs are one of the power semiconductor elements.

  The IGBT is a power element in which a MOSFET (insulated gate field effect transistor) having high-speed switching characteristics and voltage driving characteristics and a bipolar transistor having low on-voltage characteristics are configured on a single chip. The range of applications has expanded from industrial fields such as general-purpose inverters, AC servos, uninterruptible power supplies (UPS), or switching power supplies to consumer equipment fields such as microwave ovens, rice cookers, and strobes. Further, IGBTs having a lower on-voltage using a new chip structure have been developed, and reductions in the loss and efficiency of application devices using the IGBT have been achieved.

  The IGBT has a punch-through (hereinafter referred to as PT) type, non-punch-through (hereinafter referred to as NPT) type, and field stop (hereinafter referred to as FS) type, and an n-channel vertical double type. A diffusion structure is the mainstream. Therefore, in this specification, an n-channel IGBT is described as an example, but the same applies to a p-channel IGBT.

  The PT-type IGBT is formed using an epitaxial wafer obtained by epitaxially growing an n + buffer layer and an n − active layer on a p + semiconductor substrate. Therefore, for example, in a device with a withstand voltage of 600 V, the thickness of the active layer is about 70 μm, but the total thickness including the p + semiconductor substrate is about 200 to 300 μm. In the PT type IGBT, the depletion layer in the n − active layer reaches the n + buffer layer.

  FIG. 12 is a cross-sectional view showing the configuration of a half cell of an NPT type IGBT having a shallow p + collector layer with a low dose. As shown in FIG. 12, an n − semiconductor substrate made of, for example, an FZ wafer is used as an active layer 101, and a p + base region 102 is selectively formed on the front surface side. An n + emitter region 103 is selectively formed on the surface layer of the base region 102. A gate electrode 105 is formed on the substrate surface via a gate oxide film 104.

  The emitter electrode 106 is in contact with the emitter region 103 and the base region 102 and is insulated from the gate electrode 105 by the interlayer insulating film 107. A p + collector layer 108 and a collector electrode 109 are formed on the back surface of the substrate. In the case of the NPT type, the thickness of the active layer 101 is thicker than that of the PT type, but the entire device is significantly thinner than the PT type device. Moreover, since the FZ substrate is used without using the epitaxial substrate, the cost is low.

  FIG. 13 is a cross-sectional view showing the configuration of a half cell of the FS type IGBT. As shown in FIG. 13, the element structure on the front side of the substrate is the same as the NPT type element shown in FIG. On the back side of the substrate, an n + buffer layer 110 is provided between the n − active layer 101 and the p + collector layer 108. In the case of the FS type, the thickness of the active layer 101 is about 70 μm (withstand voltage 600 V system), which is the same as the PT type, and the thickness of the entire element is about 100 to 200 μm.

  FIG. 14 is a cross-sectional view showing the configuration of 1/2 cell of a reverse blocking IGBT. As shown in FIG. 14, the reverse blocking IGBT has the same structure as the NPT type element shown in FIG. 12, except that the isolation layer 110 is formed so as to be in contact with the p + collector layer 108. The reverse blocking IGBT has a reverse breakdown voltage in addition to the basic performance of the conventional IGBT, and is used for a semiconductor switch of a matrix converter that performs AC-AC exchange without passing through DC.

  Unlike a conventional converter, the matrix converter does not require a capacitor, and power supply harmonics are reduced. On the other hand, since the input of the matrix converter is an alternating current, the semiconductor switch is required to have reverse breakdown voltage. For this reason, in the case of a semiconductor switch using a conventional IGBT, it is necessary to connect reverse blocking diodes in series. On the other hand, according to the semiconductor switch using the reverse blocking IGBT, since it is not necessary to connect the diodes in series, the conduction loss can be halved and the conversion efficiency of the matrix converter can be greatly improved. For manufacturing a reverse blocking IGBT, a technology for forming a deep junction having a thickness of 100 μm or more from the substrate surface and a technology for producing an ultrathin wafer having a thickness of 100 μm or less are indispensable.

  Recently, in order to further reduce the total loss, an attempt has been made to make the device as thin as possible by shaving the wafer thinly. For example, in the case of an element having a withstand voltage of 600 V, the thickness of the FS type IGBT is assumed to be about 70 μm. When the breakdown voltage class is lowered, the thickness of the element is further reduced. As a manufacturing method of the FS type IGBT having such a thickness or a device similar thereto, a method of polishing an FZ wafer is known as described below.

15 to 19 are diagrams showing a manufacturing process of an FS type IGBT using a conventional FZ wafer. As shown in FIG. 15, first, on the front surface side of an n ⁻ FZ wafer to be the active layer 101, a base region, an emitter region, a gate oxide film made of SiO ₂ , a gate electrode, an interlayer insulation made of BPSG, etc. A surface-side element structure portion 112 having a film, an emitter electrode made of an Al—Si film, etc., and an insulating protective film made of a polyimide film, etc. is produced (FIG. 15).

  Next, the back surface of the wafer is ground by means such as back grinding or etching, so that the wafer has a desired thickness, for example, 70 μm (FIG. 16). In the case of etching, although it is not strictly grinding, in this specification, since means for thinning the wafer is not questioned, grinding including etching is performed.

  Next, for example, phosphorus (P), which is an n-type impurity, and boron (B), which is a p-type impurity, are ion-implanted from the back surface of the wafer, and heat treatment (annealing) is performed at 350 to 500 ° C. in an electric furnace. Layer 110 and collector layer 108 are formed (FIG. 17). Next, a collector electrode 109 is formed on the back surface of the wafer, that is, on the surface of the collector layer 108 (FIG. 18).

  Finally, dicing tape 113 is attached to the collector electrode 109 side to perform dicing, and the wafer is cut into a plurality of chips 114 (FIG. 19). Then, the collector electrode 109 of each chip 114 is soldered to a fixing member, and an aluminum wire electrode is fixed to the electrode of the surface side element structure portion 112 by a wire bonding apparatus.

  However, if an attempt is made to produce a thin element having a thickness of, for example, about 70 μm by the conventional method described above, the thickness of the wafer after back grinding or back grinding by etching (see FIG. 16) is thin. Cracks are likely to occur on the wafer during electrode deposition.

  For this reason, a method has been proposed in which a glass substrate is bonded to a wafer thinned by backside grinding, and the backside process is performed in that state (for example, see Patent Document 1 below).

Japanese Patent Laying-Open No. 2005-129652 (see paragraph number 0034)

  However, according to the conventional manufacturing process described above, the outer periphery of the wafer is cracked or chipped depending on the handling and handling method for the thin wafer after back grinding. For example, when an impact from the radial direction is applied to a thin wafer after back grinding, the outer periphery of the wafer is easily chipped. As described above, there is a problem in that the yield is lowered when cracks or chips are generated on the wafer after the back surface grinding.

  The present invention provides a method for manufacturing a semiconductor device capable of improving the yield by preventing cracks and chips generated on the outer periphery of a semiconductor wafer after back surface grinding in order to eliminate the above-described problems caused by the prior art. With the goal.

In order to solve the above-described problems and achieve the object, a method of manufacturing a semiconductor device according to the present invention includes a step of manufacturing a surface-side element structure portion of a semiconductor device on a front surface of a semiconductor wafer, and the surface-side device The step of grinding the back surface of the semiconductor wafer on which the structure portion has been manufactured to 90 μm or less, and the surface on the side on which the surface-side element structure portion of the semiconductor wafer after the back surface grinding has been manufactured are smaller than the diameter of the semiconductor wafer. a step of bonding to a support member having a larger diameter, the and the outer peripheral side surface of the support the semiconductor wafer which is bonded to the member, the support member, the outer than the semiconductor wafer surface of the semiconductor wafer is bonded together the side a step of covering a portion with an adhesive member, a step of fabricating the back side structure the outer peripheral side surface to the back surface of the semiconductor wafer remain covered by the adhesive member, A step of peeling the support member and the adhesive member from the semiconductor wafer on which the back surface structure is fabricated, and a step of cutting the semiconductor wafer into chips after the support member and the adhesive member are peeled off. It is characterized by.

A method of manufacturing a semiconductor device according to this invention is the invention described above, the adhesive member may be a UV-curable resin. Further, in the semiconductor element manufacturing method according to the present invention, in the above-described invention, the semiconductor wafer is bonded to the support member via an adhesive layer, and the outer periphery of the semiconductor wafer is bonded with the adhesive member made of the same material as the adhesive layer. It is characterized by covering the side.

  According to this invention, the strength of the thinned semiconductor wafer is increased by bonding the support substrate to the semiconductor wafer after the back surface grinding and further covering the outer peripheral side surface with the adhesive member, and the semiconductor wafer is cracked in the process after the back surface grinding. Or chipping can be prevented.

  According to the method for manufacturing a semiconductor element according to the present invention, it is possible to prevent cracks and chips generated on the outer periphery of the semiconductor wafer after back grinding, and to improve the yield.

  Exemplary embodiments of a method for manufacturing a semiconductor device according to the present invention will be explained below in detail with reference to the accompanying drawings.

(Embodiment 1)
FIGS. 1-7 is a figure which shows the manufacturing process of the manufacturing method of the semiconductor element concerning Embodiment 1. FIGS. In the first to third embodiments described below, an example in which an FS type IGBT is manufactured using an n-doped epitaxial wafer will be described as an example, but the same applies to the case where an FS type IGBT is manufactured using an FZ wafer. The manufacturing process can be advanced in this process. In addition, the present invention can be similarly applied to the manufacture of NPT type IGBTs, reverse blocking type IGBTs, MOS-FETs, diodes, and the like.

First, the surface side element structure portion is fabricated on the front surface of the wafer as follows. First, a gate electrode made of a gate oxide film such as SiO ₂ and polysilicon is formed on the front side of an epitaxial wafer on which an epitaxial layer 2 is grown on an n ⁺ semiconductor substrate 1, that is, on the surface of the epitaxial layer 2. Are deposited and processed. An interlayer insulating film such as BPSG is deposited on the surface and processed to produce an insulating gate structure.

Subsequently, a p ⁺ base layer is formed, and an n ⁺ emitter layer is formed therein. Then, a surface electrode made of an aluminum / silicon film or the like, that is, an emitter electrode is formed, and heat treatment is performed at about 400 ° C. to 500 ° C. to make the aluminum / silicon film or the like a low resistance wiring having a stable bonding property. An insulating protective film such as polyimide is laminated on the entire surface.

Further, a lattice-shaped polyimide protective film is formed on the wafer surface along the outer periphery of each chip. Thus far, the surface-side element structure 3 is completed on the front surface of the wafer (FIG. 1). In the diffusion process when the surface-side element structure portion 3 is produced, n-type impurities are diffused into the epitaxial layer 2 and the epitaxial layer 2 becomes an active layer. Hereinafter, the surface on which the front side element structure portion 3 is manufactured is referred to as a wafer front surface, and the opposite surface (n ⁺ semiconductor substrate 1 side) is referred to as a wafer back surface.

  Next, the back surface of the wafer is ground by back grinding, etching, or the like so that the entire thickness of the wafer including the front surface side element structure portion 3 remains at a desired thickness, for example, 70 μm (FIG. 2). Next, a PET (polyethylene terephthalate) film 11 is bonded to the front surface of the wafer as a supporting substrate (FIG. 3). The PET film 11 is bonded to the wafer via the adhesive layer 12. The adhesive layer 12 is preferably made of, for example, a UV curable resin (for example, a UV resin) that is cured by UV irradiation. Further, the film to be bonded to the wafer may be a glass substrate instead of the PET film 11.

  Then, the outer peripheral side surface of the wafer is covered with an adhesive member 13 made of the same material as that used for the adhesive layer 12 (FIG. 4). Thus, by coating the outer peripheral side surface of the wafer with the adhesive member 13, it is possible to increase the strength of the wafer and prevent the wafer outer periphery from being cracked or chipped in the subsequent steps.

Subsequently, boron, which is a p-type impurity, is ion-implanted from the back surface of the wafer at a dose of, for example, 1 × 10 ¹³ cm ⁻² to 1 × 10 ¹⁴ cm ⁻² and an acceleration voltage of, for example, 20 keV to 100 keV. Thereafter, annealing is performed by irradiating the back surface of the wafer with a laser to form a p ⁺ layer 4 serving as a collector layer. Although not particularly limited, here, a XeCl pulse laser (wavelength: 308 nm, half width: 49 ns, frequency: 100 Hz) is used as the laser. For example, one irradiation area is about 1 mm square and irradiation is performed with 50% to 90% overlap. Since only the p ⁺ layer 4 on the back surface of the wafer can be activated by this laser annealing, the heat treatment can be performed regardless of the heat-resistant temperature of the PET film 11. In place of the XeCl laser, a YAG2ω laser, a YAG3ω laser, or a XeF laser may be used.

  Subsequently, a back surface electrode 5 is formed by depositing a metal film on the back surface of the wafer (FIG. 5). Thereafter, the PET film 11, the adhesive layer 12 and the adhesive member 13 are peeled off to peel the PET film 11, the adhesive layer 12 and the adhesive member 13 from the wafer (FIG. 6). When a glass substrate is used as the support substrate, the support substrate, the adhesive layer, and the adhesive member can be peeled by irradiating the adhesive layer with laser light such as a YAG laser from the glass substrate side.

  Then, the dicing tape 6 is bonded to the back surface of the wafer and cut into a plurality of chips 7 (FIG. 7). Each chip 7 is soldered to a fixing member such as a wiring board via the back surface electrode 5, and an aluminum wire electrode is fixed to the electrode on the wafer surface side of each chip 7 by an ultrasonic wire bonding apparatus.

  As described above, according to the manufacturing method according to the first embodiment, the support substrate is bonded to the wafer after the back surface grinding, and further, the outer peripheral side surface of the wafer is coated with the adhesive member to increase the strength of the wafer. Advance the backside process. As a result, it is possible to reduce the occurrence of cracks and chips on the outer periphery of the wafer in the process after thinning.

(Embodiment 2)
In the first embodiment, the method of performing the back surface process by bonding the support substrate to the wafer has been described. In the second embodiment, a method for performing a back surface process without using a support substrate will be described. First, as in the first embodiment, the surface side element structure portion 3 is formed on the front surface of the wafer (see FIG. 1).

  Next, the wafer back surface is ground to a desired thickness (see FIG. 2). FIG. 8 is a diagram schematically showing the wafer before and after grinding. In FIG. 8, a cross-sectional view 801 shows the wafer 20 before grinding, and its thickness is, for example, 500 μm. A sectional view 802 shows the wafer 20 after grinding, and its thickness is, for example, 70 μm.

  As shown in a cross-sectional view 802, the wafer 20 after grinding is thinner toward the outer peripheral side. Therefore, the outer peripheral portion of the wafer 20 after grinding is very easily chipped due to contact in a metallic cassette or contact with a transfer arm. If the outer peripheral portion of the wafer 20 is chipped, the chipped member may become a source of particles, or the chipped member may damage another wafer.

  For this reason, as shown in FIG. 9, a region from the outer peripheral side surface of the wafer 20 to the outer peripheral end of the surface of the wafer 20 (hereinafter referred to as “outer peripheral region”) is coated with an adhesive member such as an adhesive. FIG. 9 is a diagram schematically showing a wafer coated on the outer peripheral edge region. As shown in FIG. 9, the outer peripheral edge region of the thinned wafer 20 is coated with an adhesive member 21. The adhesive member 21 can alleviate the impact applied to the outer peripheral edge region of the wafer 20 and prevent the outer periphery of the wafer 20 from being chipped. Further, by coating the outer peripheral edge region of the wafer 20 with the adhesive member 21, the warpage of the wafer 20 can be corrected.

  FIG. 10 is a diagram illustrating an example of a method of attaching the adhesive member to the wafer outer peripheral end region. An adhesive member material 24 is placed in the container 23. Next, a part of the outer peripheral end region of the wafer 20 is immersed in the adhesive member material 24 in the container 23. Then, the wafer 20 is rotated to adhere the adhesive member material 24 to the entire outer peripheral end region.

  Here, as a material of the adhesive member 21, for example, a material mainly composed of acrylic silicon resin is desirable. A material mainly composed of acrylic silicon resin is composed mainly of a resin having acid resistance and alkali resistance, and has good adhesion to silicon. Since there is a process of heating to about 130 ° C. later, it is desirable that the material mainly composed of acrylic silicon resin has a heat resistance of about 140 ° C. Acrylic silicon resins having heat resistance up to, for example, 180 ° C. are provided.

After coating the outer peripheral edge region of the wafer, p-type impurities are ion-implanted from the back surface of the wafer, as in the first embodiment. Then, annealing is performed by irradiating the back surface of the wafer with a laser to form a p ⁺ layer 4 serving as a collector layer. At this time, the laser is prevented from hitting the adhesive member 21. Next, a back surface electrode is formed by vapor-depositing a metal film on the back surface of the wafer (see FIG. 5). Thereafter, the adhesive member 21 is peeled off. When an acrylic silicon resin is used as the adhesive member 21, it can be peeled off using, for example, sulfuric acid / hydrogen peroxide. Then, a dicing tape is bonded to the back surface of the wafer and cut into a plurality of chips (see FIG. 7).

  As described above, according to the manufacturing method according to the second embodiment, the outer peripheral edge region of the wafer after the back surface grinding is coated with the adhesive member, and the back surface process proceeds. Thereby, the strength of the wafer can be increased without using a support substrate, and the occurrence of cracks and chips on the outer periphery of the wafer can be reduced.

  FIG. 11 is an explanatory diagram showing the relationship between the cracking rate of the wafer after forming the back electrode and the thickness of the wafer after back grinding. In FIG. 11, the vertical axis represents the wafer cracking rate (%), and the horizontal axis represents the wafer thickness (μm) after back grinding. In FIG. 11, white triangles (。) indicate the relationship between the crack rate of the wafer and the thickness of the wafer after the formation of the back electrode when the manufacturing process proceeds as in the first embodiment. Also, the black squares (■) in FIG. 11 indicate the relationship between the cracking rate of the wafer after the formation of the back electrode and the thickness of the wafer when the manufacturing process proceeds as in the second embodiment.

  Also, the black circles (●) in FIG. 11 indicate the relationship between the wafer cracking rate and the wafer thickness after the back electrode is formed when the manufacturing process is performed without attaching a support member (see the background art). ("Conventional example" in FIG. 11).

  As shown in FIG. 11, when the manufacturing process is advanced as in the first embodiment, the crack rate after forming the back electrode is almost zero (even if the thickness of the wafer after the back grinding is reduced to 70 μm) 5% or less) and extremely small. Further, when the manufacturing process is advanced as in the second embodiment, since the support substrate is not used, the crack rate is larger than that in the case where the manufacturing process is advanced as in the first embodiment. The cracking rate when the thickness of the wafer after grinding is 70 μm can be about 20%.

  On the other hand, in the conventional example, when the thickness of the wafer after back grinding is 90 μm, 80 μm, and 70 μm, the cracking rate after forming the back electrode is as high as 40%, 80%, and 95%, respectively. End up.

  In the above-described embodiment, the thickness of the wafer after the back surface grinding is 70 μm, but the present invention can be similarly applied to a wafer having a thickness after grinding of more than 70 μm. Further, the present invention can be effectively applied to a wafer that is liable to be cracked or chipped on its outer periphery regardless of the wafer thickness.

  As described above, according to the present invention, the subsequent steps are performed after the outer peripheral side surface and the outer peripheral end region of the wafer after back surface grinding are coated with the adhesive member. Thereby, the radial force applied to the semiconductor wafer after back grinding can be relaxed. Therefore, cracks and chips generated on the outer periphery can be prevented and yield can be improved. In addition, a semiconductor element having a desired withstand voltage and a semiconductor element having a low on-resistance can be manufactured stably.

  As described above, the method for manufacturing a semiconductor device according to the present invention is useful for manufacturing a semiconductor device having a thin device thickness, and in particular, a general-purpose inverter, AC servo, uninterruptible power supply (UPS), switching power supply, etc. It is suitable for manufacturing power semiconductor elements such as IGBTs used in industrial fields and consumer equipment fields such as microwave ovens, rice cookers or strobes.

FIG. 3 is a diagram illustrating a manufacturing process of the method for manufacturing a semiconductor element according to the first embodiment; FIG. 3 is a diagram illustrating a manufacturing process of the method for manufacturing a semiconductor element according to the first embodiment; FIG. 3 is a diagram illustrating a manufacturing process of the method for manufacturing a semiconductor element according to the first embodiment; FIG. 3 is a diagram illustrating a manufacturing process of the method for manufacturing a semiconductor element according to the first embodiment; FIG. 3 is a diagram illustrating a manufacturing process of the method for manufacturing a semiconductor element according to the first embodiment; FIG. 3 is a diagram illustrating a manufacturing process of the method for manufacturing a semiconductor element according to the first embodiment; FIG. 3 is a diagram illustrating a manufacturing process of the method for manufacturing a semiconductor element according to the first embodiment; It is a figure which shows typically the wafer before and behind grinding. It is a figure which shows typically the wafer which coated the outer periphery edge area | region. It is a figure which shows an example of the adhesion method of the adhesive member to a wafer outer peripheral edge area | region. It is explanatory drawing which shows the relationship between the crack rate of the wafer after back surface electrode formation, and the thickness of the wafer after back surface grinding. It is sectional drawing which shows the structure for 1/2 cell of NPT type IGBT which has a shallow p <+> collector layer of a low dose amount. It is sectional drawing which shows the structure for 1/2 cell of FS type IGBT. It is sectional drawing which shows the structure for 1/2 cell of reverse blocking IGBT. It is a figure which shows the manufacturing process of FS type IGBT using the conventional FZ wafer. It is a figure which shows the manufacturing process of FS type IGBT using the conventional FZ wafer. It is a figure which shows the manufacturing process of FS type IGBT using the conventional FZ wafer. It is a figure which shows the manufacturing process of FS type IGBT using the conventional FZ wafer. It is a figure which shows the manufacturing process of FS type IGBT using the conventional FZ wafer.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 n + semiconductor substrate 2 Epitaxial layer 3 Surface side element structure part 4 P ⁺ layer 5 Back electrode 6 Dicing tape 7 Chip 11 PET film 12 Adhesive layer 13 Adhesive member

Claims (3)

Producing a surface element structure portion of the semiconductor element on the front surface of the semiconductor wafer;
Grinding the back surface of the semiconductor wafer on which the surface-side element structure is fabricated to 90 μm or less ;
Bonding the surface of the semiconductor wafer after the back surface grinding on which the surface side element structure is formed to a support member having a diameter larger than the diameter of the semiconductor wafer;
Covering the outer peripheral side surface of the semiconductor wafer bonded to the support member, and the portion of the support member on the side where the semiconductor wafer is bonded to the outer side of the semiconductor wafer with an adhesive member;
Producing a back surface structure on the back surface of the semiconductor wafer while the outer peripheral side surface is covered with the adhesive member;
Peeling the support member and the adhesive member from the semiconductor wafer on which the back surface structure is fabricated;
A step of cutting the semiconductor wafer into chips after the support member and the adhesive member are peeled;
The manufacturing method of the semiconductor element characterized by the above-mentioned.   The method for manufacturing a semiconductor element according to claim 1, wherein the adhesive member is a UV curable resin. The semiconductor wafer is bonded to the support member via an adhesive layer,
The method for manufacturing a semiconductor element according to claim 1, wherein an outer peripheral side surface of the semiconductor wafer is covered with the adhesive member made of the same material as the adhesive layer.

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