JP5442121B2 - Magnetic memory cell and magnetic random access memory - Google Patents

Description

  The present invention relates to a magnetic memory cell and a magnetic random access memory to which spin torque magnetization reversal is applied.

  In recent years, attention has been focused on a nonvolatile magnetic random access memory (MRAM) having a possibility of replacing a conventional volatile dynamic random access memory (DRAM). In DRAM, there was a problem that information disappears when the circuit power is turned off. However, in MRAM, information is not erased even if the circuit power is turned off, so the memory power is turned on only when necessary. This is because power consumption can be significantly reduced. In the first MRAM, for example, as described in US Pat. No. 5,734,605, one magnetic film of a tunnel magnetoresistive effect (TMR) element having a multilayer structure of magnetic film / nonmagnetic insulating film / magnetic film is used. A system is employed in which recording is performed by reversing the magnetization using a synthetic magnetic field generated by currents flowing in two metal wirings provided in directions perpendicular to each other above and below the TMR element. However, even in the MRAM, if the size of the TMR element is reduced to increase the capacity, the magnitude of the magnetic field required for magnetization reversal increases, and it is necessary to pass a large amount of current through the metal wiring. It has been pointed out that it will lead to the destruction.

  As a method of reversing magnetization without using a magnetic field, for example, as described in Journal of Magnetism and Magnetic Materials, 159, L1-6 (1996), a giant magnetoresistive effect (GMR) film used in a magnetic reproducing head It has been theoretically shown that magnetization reversal is possible only by passing a certain current or more through the tunnel magnetoresistive (TMR) film. Thereafter, for example, Physical Review Letters, Vol.84, No.14, pp.2149-2152 (2000) describes a diameter of 130 nm including a Co / Cu / Co multilayer film (GMR film) between two Cu electrodes. An example of a recording method has been reported in which a pillar is formed, a current is passed through the pillar, and the spin torque applied to the magnetization of the Co layer from the spin of the flowing current is used to reverse the magnetization of the Co layer. Furthermore, in recent years, spin torque magnetization reversal has been demonstrated using nanopillars using TMR films, as described in, for example, Applied Physics Letters, Vol. 84, pp. 2118-2120 (2004). In the MRAM (STT-MRAM) using spin torque magnetization reversal, the current required for writing decreases with the area of the TMR pillar, so the scalability that the write power can be reduced along with miniaturization is guaranteed. As a nonvolatile RAM, much attention has been paid.

  A schematic diagram of the spin torque magnetization reversal mentioned above is shown in FIG. In the memory cell shown in FIG. 1, a bit line 1 includes a first ferromagnetic layer (recording layer) 2 whose magnetization direction changes, an intermediate layer 3, and a second ferromagnetic layer (fixed layer) whose magnetization direction is fixed. ) 4 and the transistor 6 whose conduction is controlled by the gate electrode 5 are connected, and the other terminal of the transistor is connected to the source line 7. As shown in FIG. 1A, when the magnetization of the fixed layer 4 and the recording layer 2 is changed from the antiparallel (high resistance) state to the parallel (low resistance) state, the current 8 is changed from the bit line 1 to the source line 7. Shed. At this time, the electrons 9 flow from the source line 7 to the bit line 1. On the other hand, when the magnetizations of the fixed layer 4 and the recording layer 2 are changed from the parallel (low resistance) state to the antiparallel (high resistance) state as shown in FIG. What is necessary is just to flow in the direction of line 1. At this time, the electrons 9 flow from the bit line 1 to the source line 7.

  Thereafter, as described in, for example, Japanese Patent Application Laid-Open No. 2008-252018, spin using a vertical TMR pillar that directs the magnetization directions of the fixed layer 4 and the recording layer 2 in the direction perpendicular to the film surface of each magnetic layer. A torque magnetization reversal application MRAM (STT-MRAM) has been proposed (FIG. 2). In this perpendicular TMR type STT-MRAM, a material (hard magnetic material) having a large magnetic anisotropy inherent to the material can be used for the ferromagnetic layer, so that thermal stability can be maintained even if the area of the TMR pillar is reduced. There is a feature.

US Pat. No. 5,734,605 JP 2008-252018 A

Journal of Magnetism and Magnetic Materials, 159, L1-6 (1996) Physical Review Letters, Vol.84, No.14, pp.2149-2152 (2000) Applied Physics Letters, Vol.84, pp.2118-2120 (2004)

  However, the conventional STT-MRAM has the following problems.

In a magnetic memory using spin torque magnetization reversal, it is extremely important to reduce the rewrite current and ensure the thermal stability to ensure the non-volatility. It is known that the rewrite current for spin torque magnetization reversal is determined by the current density. For example, according to Physical Review B, Vol.62, No.1, pp.570-578, the in-plane magnetization as shown in FIG. It is known that the threshold current density J _c0 is given by the equation (1) for the TMR pillars facing.

_{J c0 α (αM s t /} g) (H k + M eff) (1)
Where α is the Gilbert damping constant, M _s is the saturation magnetization of the recording layer, t is the thickness of the recording layer, g is the efficiency of the spin torque, H _k is the anisotropic magnetic field of the recording layer, and M _eff is the film surface. The effective magnetization of the recording layer minus the effect of the demagnetizing field acting in the perpendicular direction.

  On the other hand, the energy barrier that characterizes the thermal stability, that is, the energy required for the magnetization reversal between two stable magnetization directions is given by equation (2).

E to (M _s H _k St) / 2 (2)
Here, S is a cross-sectional area of the TMR pillar.

As can be seen from equation (1) (2) is an amount which is proportional to J _c0, E both M _s t. Therefore, when M _s t is increased in order to ensure thermal stability, J _c0 increases and power consumption required for writing increases. On the other hand, reducing the M _s t in order to reduce the threshold current also decreases E, thermal stability is impaired. That is, J _c0 and E are in a trade-off relationship.

On the other hand, in the vertical TMR type STT-MRAM described in Japanese Patent Application Laid-Open No. 2008-252018, the threshold current density J _c0 is
J _c0 ∝ (αM _s t / g) (H _k −4πM _s ) (3)
On the other hand, the barrier energy E is
E to [M _s (H _k −4πM _s ) St] / 2 (4)
Can be written. Again, is proportional to J _c0, E both M _s t, it is possible to increase the vertical MTJ in anisotropy field as described above, no problem with respect to the size of the E. However, since J _c0 increases when H _k is increased, it is a problem to prevent J _c0 from increasing by taking measures such as reducing α.

  As described above, the perpendicular TMR-type STT-MRAM has an advantage that the thermal stability can be improved as compared with the in-plane magnetization TMR-type STT-MRAM, but has another problem as follows.

FIG. 3A and FIG. 3B are diagrams showing two typical magnetization arrangements of the vertical TMR. As shown in FIG. 3A, the first arrangement is a case where the magnetization of the recording layer 2 and the magnetization of the fixed layer 4 are parallel (parallel arrangement). At this time, the resistance of the TMR element is low. As shown in FIG. 3B, the second arrangement is a case where the magnetization of the recording layer 2 and the magnetization of the fixed layer 4 are antiparallel (antiparallel arrangement). At this time, the resistance of the TMR element is high. In the case of the parallel arrangement, a stable energy arrangement in which the magnetic flux flow is closed in a state where the N poles and S poles of the magnets of the magnetic films 2 and 4 are alternately arranged. For example, in the case of FIG. 3A, the magnetic flux 31 flows from the N pole of the fixed layer 4 toward the S pole of the recording layer 2, and a magnetic field H _s is generated accordingly. Although the magnitude depends on the value of M _s , it is usually a large value of 1000 to several thousand Oe. On the other hand, in the case of the antiparallel arrangement as shown in FIG. 3B, the N pole and the N pole (or the S pole and the S pole) are in a state where the corners are in contact with each other, and the magnetic flux 32 is generated. It becomes unstable. As a result, the current-resistance hysteresis curve of the spin torque magnetization reversal requires a larger current when rewriting from parallel to antiparallel because the parallel arrangement as shown in FIG. 3A is stable. In addition, the value of g in the expression (3) is smaller in the case of rewriting from parallel to anti-parallel arrangement than the case of rewriting from anti-parallel to parallel arrangement (usually about 1/2). There is a problem that the current required for rewriting from parallel to antiparallel arrangement is further increased than in the case of rewriting from antiparallel to parallel arrangement.

  On the other hand, in the in-plane magnetization TMR, the fixed layer is a laminated ferrimagnetic fixed layer in which the magnetization directions are antiparallel to each other, and the flow of magnetic flux is confined inside the fixed layer, so that The problem can be avoided.

  Therefore, in order to put the vertical TMR type STT-MRAM into practical use, it is important to improve the current value asymmetry required for the above-described parallel-> antiparallel rewrite and antiparallel-> parallel rewrite.

  The magnetic memory cell of the present invention is formed between a fixed layer having a magnetization perpendicular to the film surface, a fixed layer having magnetization fixed in one direction perpendicular to the film surface, and the fixed layer and the recording layer. A magnetoresistive effect element including a nonmagnetic barrier layer, a selection transistor connected in series to the magnetoresistive effect element, a mechanism for passing a current in a desired direction through the magnetoresistive effect element and the selection transistor, a fixed layer, and a recording layer The layer is provided with a magnetic field application mechanism that applies a magnetic field opposite to the magnetization direction of the fixed layer, and the magnetization of the recording layer is generated by a spin-polarized current that flows in a direction perpendicular to the film surface of the recording layer through the selection transistor. Information is recorded depending on whether the magnetization direction of the recording layer and the magnetization direction of the fixed layer are substantially parallel or anti-parallel.

The magnetic field application mechanism can be composed of permanent magnet layers having magnetization perpendicular to the film surfaces provided on the upper and lower sides of the magnetoresistive element. The anisotropic magnetic fields of the permanent magnet layers provided above and below the magnetoresistive effect element are _denoted as H _k 1 and H _k 2, respectively, and the anisotropic magnetic fields of the recording layer and the fixed layer are _denoted as H _k 3 and H _k 4, respectively. , H _k 1 and H _k 2 are larger than H _k 3 and H _k 4. Further, when the saturation magnetization value of the recording layer is M _s 3 and the saturation magnetization value of the fixed layer is M _s 4, H _k 3-4π · M _s 3 <H _k 4-4π · M _s 4 is there.

  A magnetic random access memory according to the present invention includes a plurality of bit lines arranged in parallel to each other, a plurality of source lines arranged in parallel to the bit lines, and a plurality of lines intersecting the bit lines and arranged in parallel to each other. It has a subarray composed of a word line and a plurality of magnetic memory cells arranged at a portion where the bit line and the word line intersect. The magnetic memory cell of the present invention is used as the magnetic memory cell.

  More specifically, the magnetic memory cell includes a recording layer having magnetization in a direction perpendicular to the film surface, a fixed layer having magnetization fixed in one direction perpendicular to the film surface, and a space between the fixed layer and the recording layer. A magnetoresistive effect element having a fixed layer side electrically connected to a bit line, a source electrode, a drain electrode, and a gate electrode, and the source electrode electrically connected to the source line A selection transistor in which the drain electrode is electrically connected to the recording layer side of the magnetoresistive effect element, the gate electrode is electrically connected to the word line, and the magnetoresistive effect element and the select transistor are arranged in a desired direction. A mechanism for supplying current, and a magnetic field applying mechanism for applying a magnetic field opposite to the magnetization direction of the fixed layer to the fixed layer and the recording layer, and through the selection transistor perpendicular to the film surface of the recording layer from the bit line to the source line In the direction of Switches the magnetization direction of the recording layer by a spin-polarized current flowing from the source line to the bit line, and the information depends on whether the magnetization direction of the recording layer and the magnetization direction of the fixed layer are substantially parallel or antiparallel. Record.

  The magnetic field application mechanism includes a first permanent magnet layer formed between the drain electrode of the selection transistor and the recording layer, and a second layer formed between the fixed layer and the bit line for each magnetic memory cell. It can be composed of a permanent magnet layer. At this time, the magnetization directions of the first permanent magnet layer and the second permanent magnet layer are set to be opposite to the magnetization direction of the fixed layer.

  In addition, the magnetic field application mechanism includes a first permanent magnet layer formed between the drain electrode of the selection transistor and the recording layer of each magnetic memory cell, and a position opposite to the magnetoresistive effect element with respect to the bit line. A second permanent magnet layer provided so as to cover the entire subarray. At this time, the magnetization directions of the first permanent magnet layer and the second permanent magnet layer are set to be opposite to the magnetization direction of the fixed layer.

  In addition, the magnetic field application mechanism includes a first permanent magnet layer electrically insulated at a position opposite to the fixed layer with respect to the recording layer of the magnetoresistive element, and between the fixed layer and the bit line. You may comprise with the formed 2nd permanent magnet layer. At this time, the magnetization directions of the first permanent magnet layer and the second permanent magnet layer are set to be opposite to the magnetization direction of the fixed layer.

  Further, the magnetic field application mechanism includes a first permanent magnet layer electrically insulated at a position opposite to the fixed layer with respect to the recording layer of the magnetoresistive effect element, and a magnetoresistive effect with respect to the bit line. You may comprise with the 2nd permanent magnet layer provided so that the whole subarray might be covered in the position on the opposite side to an element. At this time, the magnetization directions of the first permanent magnet layer and the second permanent magnet layer are set to be opposite to the magnetization direction of the fixed layer.

  According to the present invention, it is possible to provide a magnetic random access memory for spin torque magnetization reversal application using a perpendicular magnetization type tunnel magnetoresistive effect element that is thermally stable at the time of reading and has a reduced current at the time of writing. .

It is a figure which shows the principle of a spin torque magnetization reversal, (a) is a figure which shows the magnetization reversal from an antiparallel state to a parallel state, (b) is a figure which shows the magnetization reversal from a parallel state to an antiparallel state. Schematic diagram of a conventional vertical TMR-type STT-MRAM. The figure which shows the subject of vertical type STT-MRAM. FIG. 3 is a diagram illustrating an example of a memory array circuit in the present invention. FIG. 3 is a diagram showing a layout of a memory array circuit of the present invention. 1 is a schematic cross-sectional view showing an embodiment of a magnetic memory cell according to the present invention. The figure explaining the rewriting operation | movement of a vertical TMR element. The figure which shows the interface layer insertion for improving TMR ratio. 1 is a schematic cross-sectional view showing an embodiment of a magnetic memory cell according to the present invention. 1 is a schematic cross-sectional view showing an embodiment of a magnetic memory cell according to the present invention. 1 is a schematic cross-sectional view showing an embodiment of a magnetic memory cell according to the present invention.

  Embodiments of the present invention will be described below with reference to the drawings.

[Memory array structure]
FIG. 4 is a diagram showing an example of the memory array circuit of the present invention, and is a schematic diagram showing a part of the subarray. In FIG. 4, 41 is a bit line, 42 is a magnetoresistive element, 43 is a source line, 44 is a cell selection transistor, 45 is a word line, and 46 is one memory cell. Reference numerals 47 and 48 denote resistance change elements (for example, transistors) for controlling the magnitude of a current flowing through the bit line, and reference numeral 49 denotes a resistance control word line for controlling the conduction state of the resistance change elements 47 and 48.

  As shown in FIG. 4, the source electrode S of the cell selection transistor 44 is connected to the source line 43, and the drain electrode D is connected to the magnetoresistive effect element 42. The gate electrode G is connected to the word line 45. The bit lines 41 are arranged in parallel to each other, and the source lines 43 are arranged in a direction parallel to the bit lines. The word lines 45 are arranged in parallel to each other and in a direction intersecting with the bit lines 41 and the source lines 43.

  These subarrays are arranged as shown in FIG. For the writing in this configuration, for example, when writing to the cell 46, first, a signal for designating the address of the cell 46 to be written to the address controller is sent from the CPU. Next, the address controller sends a write enable signal to the write driver connected to the bit line 41 to which a current is desired to be sent to boost the voltage, and then controls the voltage of the resistance control driver to pass a predetermined current through the bit line 41. . Depending on the direction of the current, either the write driver connected to the resistance change element 47 or the write driver connected to the resistance change element 48 is dropped to the ground, and the potential difference is adjusted to control the current direction. Next, after a predetermined time elapses, a write enable signal is sent to the write driver connected to the word line 45 to boost the write driver and turn on the transistor 44. As a result, a current flows through the magnetoresistive effect element 42 and spin torque magnetization reversal is performed. After the transistor 44 is turned on for a predetermined time, the signal to the write driver is disconnected and the transistor 44 is turned off.

At the time of reading, a signal for designating the address of the cell 46 to be read is sent from the CPU to the address controller. Next, with the signal from the address controller, only the bit line 41 connected to the memory cell to be read is boosted to the read voltage V, only the source line 43 connected to the selection transistor 44 is selected by the other write driver, and the word line An enable signal is sent to 45 to turn on the transistor 44 and allow current to flow. Then, reading is performed by amplifying a voltage difference applied to both ends of the resistance of the magnetoresistive effect element 42 of the desired memory cell 46 with a sense amplifier. In this case, the current direction during reading is always in the direction from the source line 43 to the bit line 41. As a result, erroneous writing due to the read current can be reduced, a larger read current can be passed, and high-speed reading can be performed. Since this structure is the simplest arrangement of 1 transistor + 1 memory cell, the area occupied by the unit cell can be made highly integrated with 2F × 4F = 8F ² .

  Hereinafter, some specific magnetoresistive elements and cell structures will be described in detail by taking TMR elements as an example.

[Example 1]
FIG. 6 is a schematic cross-sectional view of a magnetic memory cell including a TMR pillar in the first embodiment of the present invention. In FIG. 6, 43 is a source line, 44 is a transistor for controlling the current supplied to the TMR pillar, 503 is a base film, 504 is a permanent magnet layer, 505 is a nonmagnetic intermediate layer, 506 is a recording layer, and 507 is nonmagnetic. A barrier layer, 508 is a fixed layer, 509 is a nonmagnetic intermediate layer, 510 is a permanent magnet layer, and 41 is a bit line. The permanent magnet layers 504 and 510 are both magnetized downward, and generate a large downward magnetic field _Hex therebetween. The fixed layer 508 is magnetized upward. The direction of magnetization of the recording layer 506 can be changed from downward to upward when a current is passed from the recording layer 506 to the fixed layer 508. That is, anti-parallel ⇒ parallel rewriting is performed. Further, when a current is passed from the fixed layer 508 to the recording layer 506, the direction is changed from upward to downward, and parallel → antiparallel rewriting is performed.

  FIG. 7 is a diagram for explaining the rewriting operation of the vertical TMR element. FIG. 7A shows the current-resistance hysteresis in the rewriting operation of the TMR element in the present invention. In this figure, when the current flows from the fixed layer to the recording layer in the memory cell of FIG. 6, that is, when the current flows from the bit line 41 to the source line 43 is defined as positive. A square box in the drawing represents a range of current values that can be supplied by the transistor 44.

  In general, when a CMOS transistor and a resistance type element such as a TMR element are connected in series as shown in FIG. 6, the source line 43 is grounded, and the current flows from the bit line 41 to the source line (positive current in FIG. 7A). Direction can be larger than when flowing in the opposite direction (negative current direction in FIG. 7A). This is because when a current is passed from the source line 43 toward the bit line 41, a large voltage drop occurs in the portion of the TMR element that is a resistor, so that the voltage applied between the source S of the transistor 44 and the word line 45 decreases. It is because it ends up.

In the present invention, since the magnetization directions of the recording layer 506 and the fixed layer 508 in the parallel arrangement are opposite to the direction of the magnetic field _Hex acting between the permanent magnet layers 504 and 510, the energy state of the recording layer 506 in the parallel arrangement is not good. It is stabilized. For this reason, the absolute value of the rewriting current at the time of parallel-> antiparallel rewriting is reduced. On the other hand, the absolute value of the rewrite current from antiparallel to parallel rewriting increases, but the current required for parallel to antiparallel rewrite is originally larger than the current value from antiparallel to parallel rewrite, so this is not a problem.

  Further, since the stacking order of the recording layer and the fixed layer is opposite to that of the typical vertical TMR film shown in FIG. 2, the source grounding (that is, the positive polarity of FIG. Since the parallel-to-antiparallel rewrite operation can be performed in the direction of the current in the direction, an STT-MRAM with a large current margin and a high yield can be provided.

  FIG. 7B shows current-resistance hysteresis when there is no magnetic field from the permanent magnet layer for comparison. In this case, it can be seen that the current necessary for parallel-to-antiparallel rewriting cannot be provided sufficiently.

Hereinafter, selection of materials for each magnetic layer will be described. Permanent magnet layers 504,510, and the recording layer 506, K _u 1 anisotropic magnetic field energy density of the fixed layer _{508, K u 2, K u} 3, K u 4, the saturation magnetization M _s 1, M _s 2, Assume that M _s 3 and M _s 4 and the anisotropic magnetic field are H _k 1, H _k 2, H _k 3 and H _k 4. Here the anisotropy field energy K _u i (i = 1~4) are each of the saturation magnetization _{M s i (i = 1~4)} , and the anisotropy field _{H k i (i = 1~4)} , K _u i = (M _s i · H _k i) / 2. The value of the anisotropic magnetic field energy needs to have a relationship of H _k 1, H _k 2> H _k 3, H _k 4. This is related to the heat treatment in a magnetic field for fixing the magnetization direction of each layer after forming the TMR pillar. That is, in FIG. 6, first, a downward magnetic field larger than H _k 1 and H _k 2 is applied to magnetize all layers downward. Next, when an upward magnetic field smaller than H _k 1 and H _k 2 and larger than H _k 3 and H _k 4 is applied, the magnetic fields of only the recording layer 506 and the fixed layer 508 are directed upward, and the magnetization arrangement as shown in FIG. Become. Further, as can be seen from the equations (3) and (4), it is desirable that H _k 3-4π · M _s 3 <H _k 4-4π · M _s 4. This is the rewrite current density of the recording layer 506 and the fixed layer 508,
It is necessary to make the rewriting current density of the recording layer <the rewriting current density of the fixed layer, and the coercive forces H _c 3 and H _c 4 of the recording layer 506 and the fixed layer 508 are anisotropic magnetic fields H _k 3 and H _k. Therefore, it is necessary to stabilize the magnetization of the fixed layer against the external magnetic field rather than the magnetization of the recording layer. In order to apply a large magnetic field H _ex to the recording layer 506, it is desirable to use a permanent magnet material having a large saturation magnetization M _s 1, M _s 2.

The selection of specific materials based on the above policy will be described in detail below. First, the base layer 503 and the nonmagnetic intermediate layers 505 and 509 are preferably nonmagnetic materials having high conductivity and good crystal orientation of the permanent magnet layer. Specifically, Ru, Ta or a laminated film thereof is used. As the permanent magnet layers 504 and 510, it is preferable to use FePt and CoPt which are L10 ordered alloys. In particular, FePt has a sufficiently large anisotropic magnetic field H _k 1 (or H _k 2) of 40 kOe or more and a saturation magnetization M _s 1 (or M _s 2) of 1100 emu / cm ³ or more. It is a suitable material for the layer.

As the material of the fixed layer 508, the anisotropic magnetic field H _k is not as large as FePt and CoPt, but as a substance exhibiting a sufficiently large anisotropic magnetic field H _k , FePd, Co and Pt, which are ordered alloys of L10, are used. A multilayer film of Pd or the like is preferable. For example, in the case of FePd, the anisotropic magnetic field H _k 4 is about 20 kOe, which is smaller than that of the FePt alloy, and the saturation magnetization M _s 4 is relatively large, about 800 emu / cm ^3. Stable with respect to. Next, as the material of the recording layer 506, since it is necessary to reduce the damping constant α in order to reduce the threshold current density J _c0 , Cr, V, Mn, Cu, Sn, Pb, Sb, Bi are added to FePd. A material to which elements such as these are added, or an alloy based on Co to which Cr, Pt, B or the like is added is preferable. For example, when about 10% of Cr or Mn was added to the FePd alloy, the anisotropic magnetic field H _k 3 was reduced to 15 kOe, but the saturation magnetization M _s 3 was not significantly reduced to about 700 emu / cm ³ . Since the condition of H _k 4> H _k 3 is satisfied, it can be seen that the recording layer is suitable. When the thickness of this layer is 3 nm and the TMR pillar is processed into a circle having a diameter of 40 nm, the thermal stability index calculated by dividing the energy E of Equation (4) by Boltzmann constant × absolute temperature (300 K) is Therefore, it was found that the present invention is sufficiently applicable to a vertical TMR type STT-MRAM having a fine TMR pillar.

  In order to further improve the TMR ratio, it is desirable to use a material based on MgO as the nonmagnetic barrier layer 507. However, in order to obtain a high TMR ratio, the MgO crystal structure has a body-centered cubic lattice (001). ) For this purpose, as shown in FIG. 8, a metal having a body-centered cubic lattice structure between the recording layer 506 and the nonmagnetic barrier layer 507 and between the nonmagnetic barrier layer 507 and the fixed layer 508 It is preferable to insert layers, for example, interface layers 701 and 702 such as Fe and CoFeB.

[Example 2]
FIG. 9 is a schematic cross-sectional view of a magnetic memory cell including a TMR pillar in the second embodiment of the present invention. In FIG. 9, 43 is a source line, 44 is a transistor for controlling the current supplied to the TMR pillar, 503 is a base film, 504 is a permanent magnet layer, 505 is a nonmagnetic intermediate layer, 506 is a recording layer, and 507 is nonmagnetic. A barrier layer, 508 is a fixed layer, 509 is a nonmagnetic intermediate layer, 41 is a bit line, and 801 is an unpatterned permanent magnet layer. The magnetization directions of the two permanent magnet layers 504 and 801 are opposite to the magnetization direction of the fixed layer 508. The non-patterned permanent magnet layer 801 is disposed in a state of being electrically insulated at a position opposite to the magnetic memory cell group with respect to the plane in which the bit lines 41 are arranged. It is sized to cover the entire subarray.

  In the present embodiment, since the distance between the two permanent magnet layers 504 and 801 is seemingly separated, the magnitude of the magnetic field acting between the permanent magnet layers is considered to be small, but on the other hand, the area of the upper permanent magnet layer 801 is small. Since the effect of collecting the magnetic flux is increased, the magnitude of the magnetic field acting between the two permanent magnet layers is practically hardly reduced as compared with the structure of the first embodiment. On the other hand, since the height of the TMR pillar itself can be reduced in the present embodiment, there is an effect that a TMR pillar manufacturing error can be suppressed small.

[Example 3]
FIG. 10A is a schematic cross-sectional view of a memory cell including a TMR pillar according to the third embodiment of the present invention, and FIG. 10B is a cross-sectional view taken along the line AB in FIG. 10A and 10B, the cross section of the CMOS transistor indicated by the symbol in FIG. 6 is drawn in detail.

  In FIG. 10A, 901 is a source portion of a transistor, 902 is a word line, 903 is a drain portion of the transistor, 904 is a metal via connecting the transistor and the TMR pillar, 905 is a lower permanent magnet layer, and 906 is a lower portion of the TMR pillar. An electrode, 503 is a base film, 506 is a recording layer, 507 is a nonmagnetic barrier layer, 508 is a fixed layer, 509 is a nonmagnetic intermediate layer, 510 is a permanent magnet layer, 41 is a bit line, and 43 is a source line. The lower permanent magnet layer 905 is provided to be electrically insulated from the TMR pillar and the CMOS transistor. The direction of magnetization of the permanent magnet layers 905 and 510 is opposite to the direction of magnetization of the fixed layer 508.

  As shown in FIG. 10B, the lower permanent magnet layer 905 and the source line 43 both extend in a direction perpendicular to the bit line 41. In this embodiment, the lower permanent magnet layer 905 is formed below the lower electrode layer 906 of the TMR pillar, and the distance between the two permanent magnet layers is slightly increased, but the height of the TMR pillar itself is reduced. Therefore, the TMR pillar manufacturing error can be suppressed to a small value.

  Although the lower permanent magnet layer 905 shown in FIG. 10 is provided as an elongated layer continuously extending below the lower electrode layer 906 of a plurality of adjacent TMR pillars, the lower electrode layer 906 of each TMR pillar is provided. Each of them may be discretely provided only on the lower side.

[Example 4]
FIG. 11 is a schematic cross-sectional view of a memory cell including a TMR pillar in the fourth embodiment of the present invention. In FIG. 11, reference numeral 901 denotes a source portion of a transistor, 902 denotes a word line, 903 denotes a drain portion of the transistor, 904 denotes a metal via connecting the transistor and the TMR pillar, 905 denotes a lower permanent magnet layer, 906 denotes a lower electrode of the TMR pillar, 503 Is a base film, 506 is a recording layer, 507 is a nonmagnetic barrier layer, 508 is a fixed layer, 509 is a nonmagnetic intermediate layer, 801 is an unpatterned permanent magnet layer, 41 is a bit line, and 43 is a source line. .

  The lower permanent magnet layer 905 is provided with electrical insulation at a position opposite to the fixed layer with respect to the recording layer of the TMR pillar. Further, the non-patterned permanent magnet layer 801 is formed at a position opposite to the TMR pillar with respect to the plane in which the bit lines are arranged, and is electrically insulated from other elements so as to cover the entire subarray. ing. The direction of magnetization of the permanent magnet layers 801 and 905 is opposite to the direction of magnetization of the fixed layer 508.

  In the present embodiment, the distance between the two permanent magnet layers is somewhat increased, but the height of the TMR pillar itself can be minimized, so that the TMR pillar manufacturing error can be minimized.

  Note that the lower permanent magnet layer 905 of this embodiment may be provided independently only on the lower side of the lower electrode layer 906 of each TMR pillar, or as shown in FIG. It may be provided as an elongate layer extending in parallel.

DESCRIPTION OF SYMBOLS 1 ... Bit line, 2 ... Recording layer, 3 ... Barrier layer, 4 ... Fixed layer, 5 ... Gate electrode, 6 ... Transistor, 7 ... Source line, 8 ... Current direction, 9 ... Direction where electron moves, 31, 32 ... Magnetic flux in the barrier layer, 41 ... Bit line, 42 ... Magnetoresistive element, 43 ... Source line, 44 ... Cell selection transistor, 45 ... Word line, 46 ... Memory cell, 47, 48 ... Current flowing through the bit line Resistance change element for controlling the size, 49 ... Word line for resistance control for controlling the conduction state of the resistance change element, 503 ... Base film, 504 ... Permanent magnet layer, 505 ... Nonmagnetic intermediate layer, 506 ... Recording layer 507: Nonmagnetic barrier layer, 508: Fixed layer, 509 ... Nonmagnetic intermediate layer, 510 ... Permanent magnet layer, 701, 702 ... Interface layer, 801 ... Unpatterned permanent magnet layer, 901 ... Source part of transistor , 90 ... word line, the drain of 903 ... transistors, 904 ... Metarubia connecting the transistor and TMR pillar, 905 ... lower permanent magnet layer, 906 ... TMR pillar lower electrode.

Claims (11)

A recording layer having magnetization in a direction perpendicular to the film surface; a fixed layer having magnetization fixed in one direction perpendicular to the film surface; and a nonmagnetic barrier layer formed between the fixed layer and the recording layer; A magnetoresistive effect element including:
A select transistor connected in series to the magnetoresistive element;
A mechanism for flowing a current in a desired direction through the magnetoresistive element and the selection transistor;
A magnetic field application mechanism that applies a magnetic field in a direction opposite to the magnetization direction of the fixed layer to the fixed layer and the recording layer;
The magnetic field application mechanism comprises a permanent magnet layer having magnetization in a direction perpendicular to the film surfaces provided on the upper and lower sides of the magnetoresistive element,
The direction of magnetization of the recording layer is switched by a spin-polarized current that flows in a direction perpendicular to the film surface of the recording layer through the selection transistor,
2. A magnetic memory cell according to claim 1, wherein information is recorded depending on whether the magnetization direction of the recording layer and the magnetization direction of the fixed layer are substantially parallel or substantially antiparallel. 2. The magnetic memory cell according to claim 1 , wherein the anisotropic magnetic fields of the permanent magnet layers provided above and below the magnetoresistive effect element are H _k 1 and H _k 2, respectively, and the recording layer and the fixed layer are anisotropic. A magnetic memory cell characterized in that H _k 1 and H _k 2 are larger than H _k 3 and H _k 4 when the magnetic fields are H _k 3 and H _k 4, respectively. 2. The magnetic memory cell according to claim 1 , wherein when the value of saturation magnetization of the recording layer is M _s 3 and the value of saturation magnetization of the fixed layer is M _s 4, H _k 3-4π · M _s 3 < A magnetic memory cell characterized by being H _k 4-4π · M _s 4. A plurality of bit lines arranged in parallel to each other, a plurality of source lines arranged in parallel to the bit lines, a plurality of word lines intersecting the bit lines and arranged in parallel to each other, and the bit lines And a magnetic random access memory having a subarray composed of a plurality of magnetic memory cells arranged at a portion where the word lines intersect with each other,
The magnetic memory cell is
A recording layer having magnetization in a direction perpendicular to the film surface; a fixed layer having magnetization fixed in one direction perpendicular to the film surface; and a nonmagnetic barrier layer formed between the fixed layer and the recording layer; A magnetoresistive element whose fixed layer side is electrically connected to the bit line; and
A source electrode, a drain electrode, and a gate electrode, the source electrode is electrically connected to the source line, the drain electrode is electrically connected to the recording layer side of the magnetoresistive element, and the gate electrode A select transistor electrically connected to the word line;
A mechanism for flowing a current in a desired direction through the magnetoresistive element and the selection transistor;
A magnetic field application mechanism that applies a magnetic field in a direction opposite to the magnetization direction of the fixed layer to the fixed layer and the recording layer;
The magnetic field applying mechanism is formed for each magnetic memory cell between a first permanent magnet layer formed between the drain electrode of the selection transistor and the recording layer, and between the fixed layer and the bit line. And a second permanent magnet layer,
The magnetization directions of the first permanent magnet layer and the second permanent magnet layer are opposite to the magnetization direction of the fixed layer,
The magnetization of the recording layer is caused by a spin-polarized current that flows in the direction from the bit line to the source line, or from the source line to the bit line, perpendicularly to the film surface of the recording layer through the selection transistor. Switching direction,
A magnetic random access memory, wherein information is recorded depending on whether the magnetization direction of the recording layer and the magnetization direction of the fixed layer are substantially parallel or substantially antiparallel. A plurality of bit lines arranged in parallel to each other, a plurality of source lines arranged in parallel to the bit lines, a plurality of word lines intersecting the bit lines and arranged in parallel to each other, and the bit lines And a magnetic random access memory having a subarray composed of a plurality of magnetic memory cells arranged at a portion where the word lines intersect with each other,
The magnetic memory cell is
A recording layer having magnetization in a direction perpendicular to the film surface; a fixed layer having magnetization fixed in one direction perpendicular to the film surface; and a nonmagnetic barrier layer formed between the fixed layer and the recording layer; A magnetoresistive element whose fixed layer side is electrically connected to the bit line; and
A source electrode, a drain electrode, and a gate electrode, the source electrode is electrically connected to the source line, the drain electrode is electrically connected to the recording layer side of the magnetoresistive element, and the gate electrode A select transistor electrically connected to the word line;
A mechanism for flowing a current in a desired direction through the magnetoresistive element and the selection transistor;
A magnetic field application mechanism that applies a magnetic field in a direction opposite to the magnetization direction of the fixed layer to the fixed layer and the recording layer;
The magnetic field application mechanism includes: a first permanent magnet layer formed between a drain electrode of the selection transistor of each magnetic memory cell and the recording layer; and the bit line opposite to the magnetoresistive element. A second permanent magnet layer provided at a position so as to cover the entire sub-array,
The magnetization directions of the first permanent magnet layer and the second permanent magnet layer are opposite to the magnetization direction of the fixed layer ,
The magnetization of the recording layer is caused by a spin-polarized current that flows in the direction from the bit line to the source line, or from the source line to the bit line, perpendicularly to the film surface of the recording layer through the selection transistor. Switching direction,
A magnetic random access memory, wherein information is recorded depending on whether the magnetization direction of the recording layer and the magnetization direction of the fixed layer are substantially parallel or substantially antiparallel. A plurality of bit lines arranged in parallel to each other, a plurality of source lines arranged in parallel to the bit lines, a plurality of word lines intersecting the bit lines and arranged in parallel to each other, and the bit lines And a magnetic random access memory having a subarray composed of a plurality of magnetic memory cells arranged at a portion where the word lines intersect with each other,
The magnetic memory cell is
A recording layer having magnetization in a direction perpendicular to the film surface; a fixed layer having magnetization fixed in one direction perpendicular to the film surface; and a nonmagnetic barrier layer formed between the fixed layer and the recording layer; A magnetoresistive element whose fixed layer side is electrically connected to the bit line; and
A source electrode, a drain electrode, and a gate electrode, the source electrode is electrically connected to the source line, the drain electrode is electrically connected to the recording layer side of the magnetoresistive element, and the gate electrode A select transistor electrically connected to the word line;
A mechanism for flowing a current in a desired direction through the magnetoresistive element and the selection transistor;
A magnetic field application mechanism that applies a magnetic field in a direction opposite to the magnetization direction of the fixed layer to the fixed layer and the recording layer;
The magnetic field application mechanism includes a first permanent magnet layer provided in a position electrically opposite to the fixed layer with respect to the recording layer of the magnetoresistive element, the fixed layer, and the bit. A second permanent magnet layer formed between the wires,
The magnetization directions of the first permanent magnet layer and the second permanent magnet layer are opposite to the magnetization direction of the fixed layer ,
The magnetization of the recording layer is caused by a spin-polarized current that flows in the direction from the bit line to the source line, or from the source line to the bit line, perpendicularly to the film surface of the recording layer through the selection transistor. Switching direction,
A magnetic random access memory, wherein information is recorded depending on whether the magnetization direction of the recording layer and the magnetization direction of the fixed layer are substantially parallel or substantially antiparallel. 7. The magnetic random access memory according to claim 6 , wherein the first permanent magnet layer has an elongated shape and is arranged in parallel with the source line. A plurality of bit lines arranged in parallel to each other, a plurality of source lines arranged in parallel to the bit lines, a plurality of word lines intersecting the bit lines and arranged in parallel to each other, and the bit lines And a magnetic random access memory having a subarray composed of a plurality of magnetic memory cells arranged at a portion where the word lines intersect with each other,
The magnetic memory cell is
A recording layer having magnetization in a direction perpendicular to the film surface; a fixed layer having magnetization fixed in one direction perpendicular to the film surface; and a nonmagnetic barrier layer formed between the fixed layer and the recording layer; A magnetoresistive element whose fixed layer side is electrically connected to the bit line; and
A source electrode, a drain electrode, and a gate electrode, the source electrode is electrically connected to the source line, the drain electrode is electrically connected to the recording layer side of the magnetoresistive element, and the gate electrode A select transistor electrically connected to the word line;
A mechanism for flowing a current in a desired direction through the magnetoresistive element and the selection transistor;
A magnetic field application mechanism that applies a magnetic field in a direction opposite to the magnetization direction of the fixed layer to the fixed layer and the recording layer;
The magnetic field application mechanism includes a first permanent magnet layer that is electrically insulated from the recording layer of the magnetoresistive element at a position opposite to the fixed layer, and the bit line. A second permanent magnet layer provided so as to cover the entire subarray at a position opposite to the magnetoresistive element,
The magnetization directions of the first permanent magnet layer and the second permanent magnet layer are opposite to the magnetization direction of the fixed layer ,
The magnetization of the recording layer is caused by a spin-polarized current that flows in the direction from the bit line to the source line, or from the source line to the bit line, perpendicularly to the film surface of the recording layer through the selection transistor. Switching direction,
A magnetic random access memory, wherein information is recorded depending on whether the magnetization direction of the recording layer and the magnetization direction of the fixed layer are substantially parallel or substantially antiparallel. 9. The magnetic random access memory according to claim 8 , wherein the first permanent magnet layer has an elongated shape and is arranged in parallel with the source line. The magnetic random access memory according to any one of claims 4 to 9, and the anisotropic magnetic field of the first permanent magnet layer and the second permanent magnet layer and H _k 1, H _k 2, respectively, wherein Magnetic random access memory characterized in that H _k 1 and H _k 2 are larger than H _k 3 and H _k 4 when the anisotropic magnetic fields of the recording layer and the fixed layer are H _k 3 and H _k 4, respectively. . 11. The magnetic random access memory according to claim 10 , wherein when the saturation magnetization value of the recording layer is M _s 3 and the saturation magnetization value of the fixed layer is M _s 4, H _k 3-4π · M _s 3 <Magnetic random access memory, wherein H _k 4-4π · M _s 4

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