JP5475820B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor device having a wiring structure covered with a barrier film formed in a self-aligning manner.

  As a conventional semiconductor device manufacturing method, a semiconductor device having a wiring structure in which a barrier film for preventing diffusion of Cu is formed in a self-aligned manner between a wiring main body layer mainly composed of Cu and an interlayer insulating film (For example, refer to Patent Document 1).

  This barrier film is mainly composed of a compound of a predetermined metal element such as Mn and a constituent element of the interlayer insulating film. Since this predetermined metal element is easy to form an oxide and the oxide is rich in wettability with the interlayer insulating film, this semiconductor device has a uniform and ultrathin wall between the wiring body layer and the interlayer insulating film. A stable barrier film.

  According to this method for manufacturing a semiconductor device, an alloy film of, for example, Mn and Cu is formed in a wiring groove formed in an interlayer insulating film, and a Cu film as a wiring material is deposited thereon. Accordingly, by performing heat treatment, the barrier film is formed, and at the same time, Mn diffuses and moves in the Cu film and is deposited on the surface of the Cu film as an insulating film containing Mn oxide as a main component. By removing this insulating film, Mn can be removed from the Cu film.

  However, according to the manufacturing method of the semiconductor device, since the Cu film is deposited with a thickness of 0.8 to 1.0 μm, when the insulating film mainly composed of Mn oxide is deposited on the Cu film surface, There is a possibility that Mn may not move to the surface of the Cu film and remain in the Cu film. The remaining Mn becomes a cause of increasing the specific resistance of the wiring as an impurity metal.

Further, according to this method of manufacturing a semiconductor device, a method of forming a barrier film by performing a heat treatment before depositing a Cu film on an alloy film of Mn and Cu can be used. However, according to this method, when the barrier film is formed, the Cu film formed on the surface of the barrier film may be aggregated, and the Cu film deposited thereon may be peeled off.
JP 2005-277390 A

  One embodiment of the present invention provides a method for manufacturing a semiconductor device in which the concentration of impurity metal remaining in a wiring is low.

According to the present embodiment, the step of forming an insulating film on the semiconductor substrate;
Forming a recess in the insulating film;
Forming a precursor film containing a predetermined metal element on the surface of the insulating film in which the recess is formed;
Depositing a wiring formation film on the precursor film;
By performing a heat treatment, the precursor film and the insulating film are reacted to form a self-forming barrier film containing as a main component a compound containing the predetermined metal element and the constituent element of the insulating film at the interface. Diffusing the unreacted predetermined metal element into the wiring formation film;
After the step of forming the self-forming barrier film and diffusing the unreacted predetermined metal element into the wiring formation film, the step of flattening the wiring formation film until the insulating film outside the recess is exposed When,
After the step of planarizing the wiring formation film, by performing a heat treatment in an oxidizing atmosphere, the predetermined metal element diffused in the wiring formation film is reacted with oxygen in the atmosphere on the surface of the wiring formation film, By advancing the reaction into the self-forming barrier film, an unreacted metal oxide film is deposited on the upper surface of the wiring forming film and a side surface near the upper surface, and the upper end of the wiring forming film is rounded to form a wiring structure. Forming, and
A method for manufacturing a semiconductor device is provided.

  In each of the embodiments of the present invention described below, a semiconductor device having a dual damascene wiring structure in which wirings and vias are coated with a self-forming barrier film will be described.

The wiring is made of a material whose main component is Cu (50 atomic% or more), and the self-forming barrier film is made of αSi _x O _y , αC _x O _y , and αF _x O _y (a predetermined metal element α). x and y are real materials). Here, the predetermined metal element α is any one of Mn, Mn, V, Zn, Nb, Zr, Cr, Y, Tc, and Re.

  A film containing a predetermined metal α is used as a precursor film for forming the self-forming barrier film.

The predetermined metal element α is preferably Mn, the self-forming barrier film is MnSi _x O _y , and the precursor film is preferably a CuMn alloy.

[First Embodiment]

  1A (a) to 1 (c), FIG. 1B (d) to (e), FIG. 1C (f) to (g), and FIG. 1D (h) show the semiconductor device according to the first embodiment of the present invention. It is sectional drawing which shows the manufacturing process of this wiring structure.

  First, as shown in FIG. 1A (a), on the first interlayer insulating film 2 and the cap layer 3 on which the first wiring 11 whose side and bottom surfaces are covered with the self-forming barrier film 12 is formed. A first barrier film 4, a second interlayer insulating film 5, a second barrier film 6, a first interlayer insulating film 2, and a cap layer 3 are sequentially stacked.

  Here, an organic insulating film having a low dielectric constant such as PAr (polyarylene ether) can be used for the first interlayer insulating film 2. The first interlayer insulating film 2 on the second barrier film 6 has a thickness of 50 nm, for example.

For the cap layer 3, for example, an inorganic insulating film such as SiO ₂ having a thickness of 50 to 80 nm can be used.

  As the first barrier film 4, for example, an inorganic insulating film such as SiCN or SiC having a thickness of 10 to 30 nm can be used. The first barrier film 4 prevents Cu diffusion of the first wiring 11 and also functions as an etching stopper when forming the wiring.

  As the second interlayer insulating film 5, for example, an inorganic insulating film such as SiOC having a thickness of 50 nm can be used.

  As the second barrier film 6, for example, an inorganic insulating film such as SiOC having a thickness of 10 nm can be used. Note that the second barrier film 6 functions as an etching stopper at the time of wiring formation.

The first barrier film 4, the second interlayer insulating film 5, the second barrier film 6, the first interlayer insulating film 2, and the cap layer 3 are formed when the self-formed barrier film 12 is αSi _x O _y. Each may be an insulating film containing Si, and may be an insulating film containing C or F when the self-forming barrier film 12 is αC _x O _y or αF _x O _y .

  Next, as shown in FIG. 1A (b), wiring grooves (concave portions) 13 for forming second wirings 17 and vias 18 to be described later are formed by etching.

  Next, as shown in FIG. 1A (c), the first barrier film 4, the second interlayer insulating film 5, the second barrier film 6, the first interlayer insulating film 2, and the wiring groove 13 of the cap layer 3. The precursor film 14 is formed by sputtering, a CVD (Chemical Vapor Deposition) method or the like so as to cover the exposed portion by the above.

  Here, the precursor film 14 is, for example, a CuMn alloy having a thickness of 20 to 90 nm (Mn concentration is 4 to 10 atomic%).

  Next, as shown in FIG. 1B (d), a wiring formation film 15 is deposited on the precursor film 14 by plating using the precursor film 14 as a seed layer, CVD, or the like.

  Here, the wiring formation film 15 is, for example, Cu having a thickness of 10 to 110 nm from the surface of the precursor film 14 on the cap layer 3.

  Next, as shown in FIG. 1B (e), heat treatment is performed in an oxidizing atmosphere at, for example, 200 to 400 ° C. for 5 to 60 minutes, whereby the precursor film 14 becomes the first barrier film 4 and the second interlayer insulation. The self-forming barrier film 12 is formed in a self-aligned manner by reacting with the film 5, the second barrier film 6, the first interlayer insulating film 2, and the cap layer 3. At this time, when the thickness of the wiring formation film 15 from the surface of the precursor film 14 on the cap layer 3 is 10 nm or more, the aggregation of the wiring formation film 15 due to the heat treatment hardly occurs.

  On the other hand, the unreacted predetermined metal element α in the precursor film 14 diffuses and moves in the wiring forming film 15 and is deposited on the surface as an unreacted metal oxide film 16. At this time, if the thickness of the wiring formation film 15 from the surface of the precursor film 14 on the cap layer 3 exceeds 110 nm, the movement distance of the unreacted predetermined metal element α to the surface of the wiring formation film 15 increases. There is a possibility that the deposition does not proceed and a large amount remains in the wiring forming film 15.

When the precursor film 14 is a CuMn alloy and the self-forming barrier film 12 is MnSi _x O _y , the Mn contained in the precursor film 14, the second interlayer insulating film 5, the second barrier film 6, and the cap layer MnSi _x O _y having a thickness of about 2 to 10 nm is formed as the self-forming barrier film 12 by Si and O contained in 3 and the like. Note that Cu in the precursor film 14 diffuses into the wiring formation film 15.

Further, the unreacted metal oxide film 16 is a film in which unreacted Mn in the precursor film 14 diffuses and moves in the wiring forming film 15 and is deposited on the surface as MnO _x (x is a real number). In this case, the wiring forming film 15 to be the Cu wiring contains about 0.04 atomic% of Mn, and the specific resistance increases by about 0.14 μΩ / cm as compared with the case where no Mn is contained. . This increase in specific resistance is not a problem in practical use. In addition, when Mn of about 0.05 atomic% or less is contained, an increase in specific resistance is not a problem. On the other hand, since Mn hinders the movement of Cu, high reliability against electromigration and stress voids can be obtained.

  Next, as shown in FIG. 1C (f), the unreacted metal oxide film 16 is removed using an acid such as hydrochloric acid, and a sufficient thickness for performing CMP (Chemical Mechanical Polishing) in the subsequent process, for example, 0. The wiring formation film 15 is increased by plating, CVD method, etc. to 8 to 1.5 μm.

  Next, as shown in FIG. 1C (g), CMP is performed using the cap layer 3 as a stopper to flatten the wiring formation film 15 until the cap layer 3 is exposed, and the second wiring 17 and the first wiring A via 18 that connects the wiring 11 and the second wiring 17 is formed. Further, the self-formed barrier film 12 on the cap layer 3 is removed by CMP.

  Next, as shown in FIG. 1D (h), the first barrier film 4 is formed on the second wiring 17 and the cap layer 3. Further, although not shown, the semiconductor device 1 is formed by forming an insulating film or the like on the upper layer.

(Effects of the first embodiment)
According to the first embodiment, after forming the wiring forming film 15 so that the thickness from the surface of the precursor film 14 on the cap layer 3 is 10 to 110 nm, the unreacted metal oxide film 16 is deposited. As a result, the residual amount of the unreacted predetermined metal element α in the wiring forming film 15 is kept low, the specific resistance of the second wiring 17 is hardly increased, and high reliability against electromigration and stress voids is achieved. Can be obtained.

  Needless to say, the first wiring 11 can be formed in the same manner as the second wiring 17.

[Second Embodiment]
The second embodiment of the present invention is different from the first embodiment in that the unreacted metal oxide film 16 is deposited after the wiring forming film 15 is planarized by CMP. Note that the description of the same points as in the first embodiment, such as the configuration of other parts, is omitted.

  2A (a) to 2 (b), FIGS. 2B (c) to (d), and FIGS. 2C (e) to (f) show a manufacturing process of a wiring structure of a semiconductor device according to the second embodiment of the present invention. FIG.

  First, the steps up to forming the precursor film 14 shown in FIG. 1A (c) in the first embodiment are performed.

  Next, as shown in FIG. 2A (a), a wiring formation film 15 is deposited on the precursor film 14 by plating using the precursor film 14 as a seed layer, CVD, or the like. Here, the wiring forming film 15 is formed so that a sufficient thickness for performing CMP in the subsequent process, for example, a thickness from the surface of the precursor film 14 on the cap layer 3 is 1 to 1.5 μm.

  Next, as shown in FIG. 2A (b), the precursor film 14 is formed into the first barrier film 4 and the second barrier film preferably by performing heat treatment in a reducing atmosphere at, for example, 200 to 400 ° C. for 5 to 60 minutes. It reacts with the interlayer insulating film 5, the second barrier film 6, the first interlayer insulating film 2, and the cap layer 3 to become a self-formed barrier film 12. At this time, the unreacted predetermined metal element α in the precursor film 14 is in a state of diffusing into the wiring forming film 15 and has not yet been deposited as the unreacted metal oxide film 16.

  Next, as shown in FIG. 2B (c), the wiring formation film 15 is retracted to a thickness in the middle by CMP. For example, the thickness is removed until the thickness from the surface of the self-formed barrier film 12 on the cap layer 3 becomes 10 to 110 nm.

  Next, as shown in FIG. 2B (d), an unreacted metal oxide film 16 is deposited on the surface of the wiring formation film 15 by performing a heat treatment in an oxidizing atmosphere at, for example, 200 to 400 ° C. for 5 to 60 minutes.

  Next, as shown in FIG. 2C (e), after removing the unreacted metal oxide film 16 using an acid such as hydrochloric acid, CMP is performed using the cap layer 3 as a stopper until the cap layer 3 is exposed. The wiring forming film 15 is flattened, and the second wiring 17 and the via 18 that connects the first wiring 11 and the second wiring 17 are formed. Further, the self-formed barrier film 12 on the cap layer 3 is removed by CMP.

  At this time, by using an acidic CMP slurry, the removal of the unreacted metal oxide film 16 and the planarization of the wiring formation film 15 can be continuously performed by CMP.

  Next, as shown in FIG. 2C (f), the first barrier film 4 is formed on the second wiring 17 and the cap layer 3. Further, although not shown, the semiconductor device 1 is formed by forming an insulating film or the like on the upper layer.

(Effect of the second embodiment)
According to the second embodiment, the same effects as in the first embodiment can be obtained by different manufacturing methods.

[Third Embodiment]
The third embodiment of the present invention is different from the second embodiment in that an unreacted metal oxide film 16 is deposited after CMP is performed on the wiring formation film 15 to the height of the surface of the cap layer 3.
Note that the description of the same points as in the second embodiment, such as the configuration of other parts, is omitted.

  3A (a) to 3 (b) and FIGS. 3B (c) to (d) are cross-sectional views illustrating the manufacturing process of the wiring structure of the semiconductor device according to the third embodiment of the present invention.

  First, the process of forming the self-formed barrier film 12 and diffusing the unreacted predetermined metal element α into the wiring forming film 15 shown in FIG. 2A (b) in the second embodiment is performed.

  Next, as shown in FIG. 3A (a), CMP is performed using the cap layer 3 as a stopper, and the wiring formation film 15 is planarized until the cap layer 3 is exposed. Further, the self-formed barrier film 12 on the cap layer 3 is removed by CMP.

  Next, as shown in FIG. 3A (b), the unreacted metal oxide film 16 is deposited on the surface of the wiring formation film 15 by performing a heat treatment in an oxidizing atmosphere at, for example, 200 to 400 ° C. for 5 to 60 minutes. At this time, since the self-forming barrier film 12 contains the predetermined metal α and oxygen, the formation reaction of the unreacted metal oxide film 16 proceeds to the self-formed barrier film 12, and the outer edge of the unreacted metal oxide film 16 is the cap layer. 3, the shape extends downward.

When the unreacted metal oxide film 16 is MnO _x and the self-forming barrier film 12 is MnSi _x O _y , Mn and O are contained in the self-forming barrier film 12, so that the formation reaction of MnO _x occurs in the self-forming barrier film 12. Proceed to. As a result, the second wiring 17 having a shape whose upper end is rounded, and the via 18 connecting the first wiring 11 and the second wiring 17 are formed.

  Next, as shown in FIG. 3B (c), the unreacted metal oxide film 16 is removed using an acid such as hydrochloric acid.

  Next, as shown in FIG. 3B (d), the first barrier film 4 is formed on the second wiring 17 and the cap layer 3. Further, although not shown, the semiconductor device 1 is formed by forming an insulating film or the like on the upper layer.

  Since the unreacted metal oxide film 16 is an insulating film, it need not be removed. In that case, the first barrier film 4 is formed on the unreacted metal oxide film 16.

(Effect of the third embodiment)
According to the third embodiment, electric field concentration can be suppressed by making the upper end portion of the second wiring 17 round. Further, by changing the height of the upper surface of the second wiring 17 and the upper surface of the cap layer 3, the leakage current can be reduced.

  Needless to say, the first wiring 11 can be formed in the same manner as the second wiring 17.

  FIG. 4 is a graph showing the leakage current characteristics of the wiring structure according to the third embodiment of the present invention. In the figure, the lower curve represents the characteristics of the wiring with the upper surface end rounded according to the third embodiment, and the upper curve represents the characteristics of the wiring with the conventional upper surface edge not rounded. . Each represents the magnitude of the leakage current (vertical axis in FIG. 4) generated when an electric field of a predetermined magnitude (horizontal axis in FIG. 4) is generated between two adjacent wirings.

  As can be seen from FIG. 4, in the conventional wiring in which the upper end portion is not rounded, dielectric breakdown occurs when the electric field exceeds about 3.8 MV / cm, and the magnitude of the leakage current jumps up. On the other hand, it can be seen that the wiring having a rounded upper end according to the third embodiment has a smaller overall leakage current than the conventional wiring structure and does not cause dielectric breakdown within the measurement range.

[Fourth Embodiment]
The fourth embodiment of the present invention is different from the third embodiment in that an unreacted metal oxide film 16 is deposited after the first barrier film 4 is formed on the wiring forming film 15. Note that the description of the same points as in the third embodiment, such as the configuration of other parts, is omitted.

  5A to 5B are cross-sectional views showing a manufacturing process of a wiring structure of a semiconductor device according to the fourth embodiment of the present invention.

  First, steps until CMP is performed on the wiring forming film 15 using the cap layer 3 as a stopper, as shown in FIG. 3A in the third embodiment, are performed.

  Next, as shown in FIG. 5A, the first barrier film 4 is formed on the wiring formation film 15 and the cap layer 3.

  Next, as shown in FIG. 5 (b), an unreacted metal oxide film 16 is deposited on the upper surface of the wiring forming film 15 by performing a heat treatment in an oxidizing atmosphere at, for example, 200 to 400 ° C. for 5 to 60 minutes. At this time, since the self-forming barrier film 12 contains the metal and oxygen constituting the unreacted metal oxide film 16, the formation reaction of the unreacted metal oxide film 16 proceeds to the self-formed barrier film 12, and the unreacted metal oxide film 16. The outer edge portion of this has a shape extending downward along the cap layer 3. Further, although not shown, the semiconductor device 1 is formed by forming an insulating film or the like on the upper layer.

(Effect of the fourth embodiment)
According to the fourth embodiment, the same effects as those of the third embodiment can be obtained by different manufacturing methods.

[Fifth Embodiment]
The fifth embodiment of the present invention is different from the first or second embodiment in that the self-formed barrier film 12 is also formed on the upper surface of the second wiring 17. In addition, description is abbreviate | omitted about the point similar to 1st or 2nd Embodiment, such as a structure of another part.

  FIG. 6 is a cross-sectional view showing a manufacturing process of a wiring structure of a semiconductor device according to the fifth embodiment of the present invention.

  First, the first barrier film 4 on the second wiring 17 and the cap layer 3 shown in FIG. 1D (h) in the first embodiment or FIG. 2C (f) in the second embodiment. The process until forming is performed. However, in the present embodiment, it is assumed that the predetermined metal α that can form the self-formed barrier film 12 on the upper surface of the second wiring 17 remains in the second wiring 17.

  Next, as illustrated in FIG. 6, the second wiring 17 and the first barrier on the second wiring 17 are desirably performed by performing heat treatment in a reducing atmosphere at, for example, 200 to 400 ° C. for 5 to 60 minutes. Reaction occurs between the film 4 and the self-formed barrier film 12 is formed on the upper surface of the second wiring 17.

If self-formed barrier film 12 is MnSi _x O _y has a Mn which have remained in the second wiring 17, its upper surface of the first barrier film 4 on the second wiring 17 due Si contained A formation barrier film 12 is formed.

  Further, although not shown, the semiconductor device 1 is formed by forming an insulating film or the like on the upper layer.

(Effect of 5th Embodiment)
According to the fifth embodiment, by forming the self-formed barrier film 12 also on the upper surface of the second wiring 17, the leakage current can be further reduced as compared with the first or second embodiment. Can do.

  Needless to say, the first wiring 11 can be formed in the same manner as the second wiring 17.

[Sixth Embodiment]
The sixth embodiment of the present invention is different from the third embodiment in that the self-formed barrier film 12 is also formed on the upper surface of the second wiring 17. Note that the description of the same points as in the third embodiment, such as the configuration of other parts, is omitted.

  FIG. 7 is a cross-sectional view showing a manufacturing process of a wiring structure of a semiconductor device according to the sixth embodiment of the present invention.

  First, steps until the first barrier film 4 is formed on the second wiring 17 and the cap layer 3 shown in FIG. 3B (d) in the third embodiment are performed. However, in the present embodiment, it is assumed that the predetermined metal α that can form the self-formed barrier film 12 on the upper surface of the second wiring 17 remains in the second wiring 17.

  Next, as shown in FIG. 7, the second wiring 17 and the first barrier on the second wiring 17 are desirably performed by performing heat treatment in a reducing atmosphere, for example, at 200 to 400 ° C. for 5 to 60 minutes. Reaction occurs between the film 4 and the self-formed barrier film 12 is formed on the upper surface of the second wiring 17.

If self-formed barrier film 12 is MnSi _x O _y has a Mn which have remained in the second wiring 17, its upper surface of the first barrier film 4 on the second wiring 17 due Si contained A formation barrier film 12 is formed.

  Further, although not shown, the semiconductor device 1 is formed by forming an insulating film or the like on the upper layer.

(Effect of 6th Embodiment)
According to the sixth embodiment, by forming the self-formed barrier film 12 also on the upper surface of the second wiring 17, it is possible to further reduce the leakage current as compared with the third embodiment.

  Needless to say, the first wiring 11 can be formed in the same manner as the second wiring 17.

[Seventh Embodiment]
The seventh embodiment of the present invention is different from the first or second embodiment in that the self-formed barrier film 12 is also formed on the upper surface of the second wiring 17. In addition, description is abbreviate | omitted about the point similar to 1st or 2nd Embodiment, such as a structure of another part.

  8A to 8B are cross-sectional views showing a manufacturing process of a wiring structure of a semiconductor device according to the seventh embodiment of the present invention.

  First, as shown in FIG. 1C (g) in the first embodiment or FIG. 2C (e) in the second embodiment, the cap layer 3 is exposed by performing CMP using the cap layer 3 as a stopper. Steps until the wiring forming film 15 is flattened are performed. However, in the present embodiment, it is assumed that the predetermined metal α that can form the self-formed barrier film 12 on the upper surface of the second wiring 17 remains in the second wiring 17.

  Next, as shown in FIG. 8A, plasma treatment using ammonia or the like is performed under reduced pressure to remove the Cu oxide film (not shown) on the upper surface of the second wiring 17, and then the second wiring. 17 The upper surface is exposed to reducing gas and silane gas. Thereby, Si enters only the pole surface on the upper surface of the second wiring 17. Therefore, the self-forming barrier film 12 is formed on the upper surface of the second wiring 17 by performing heat treatment in an oxidizing atmosphere at, for example, 200 to 400 ° C. for 5 to 60 minutes.

When the self-forming barrier film 12 is MnSi _x O _y , the self-forming barrier film 12 on the upper surface of the second wiring 17 is formed by Mn and Si contained in the second wiring 17 and O contained in the atmosphere. It is formed.

  Next, as shown in FIG. 8B, the first barrier film 4 is formed on the second wiring 17 and the cap layer 3. Further, although not shown, the semiconductor device 1 is formed by forming an insulating film or the like on the upper layer.

(Effect of 7th Embodiment)
According to the seventh embodiment, by forming the self-formed barrier film 12 also on the upper surface of the second wiring 17, the leakage current can be further reduced than in the first or second embodiment. Can do.

  Needless to say, the first wiring 11 can be formed in the same manner as the second wiring 17.

[Eighth Embodiment]
The eighth embodiment of the present invention is different from the third embodiment in that the self-formed barrier film 12 is also formed on the upper surface of the second wiring 17. Note that the description of the same points as in the third embodiment, such as the configuration of other parts, is omitted.

  FIGS. 9A to 9B are cross-sectional views showing a manufacturing process of a wiring structure of a semiconductor device according to the eighth embodiment of the present invention.

  First, steps until the unreacted metal oxide film 16 is removed shown in FIG. 3B (c) in the third embodiment are performed. However, in the present embodiment, it is assumed that the predetermined metal α that can form the self-formed barrier film 12 on the upper surface of the second wiring 17 remains in the second wiring 17.

  Next, as shown in FIG. 9A, plasma treatment using ammonia or the like is performed under reduced pressure to remove the Cu oxide film (not shown) on the upper surface of the second wiring 17, and then the second wiring. 17 The upper surface is exposed to reducing gas and silane gas. Thereby, Si enters only the pole surface on the upper surface of the second wiring 17. Therefore, the self-forming barrier film 12 is formed on the upper surface of the second wiring 17 by performing heat treatment in an oxidizing atmosphere at, for example, 200 to 400 ° C. for 5 to 60 minutes.

When the self-forming barrier film 12 is MnSi _x O _y , the self-forming barrier film 12 on the upper surface of the second wiring 17 is formed by Mn and Si contained in the second wiring 17 and O contained in the atmosphere. It is formed.

  Next, as shown in FIG. 9B, the first barrier film 4 is formed on the second wiring 17 and the cap layer 3. Further, although not shown, the semiconductor device 1 is formed by forming an insulating film or the like on the upper layer.

(Effect of 8th Embodiment)
According to the eighth embodiment, by forming the self-formed barrier film 12 also on the upper surface of the second wiring 17, it is possible to further reduce the leakage current as compared with the third embodiment.

  Needless to say, the first wiring 11 can be formed in the same manner as the second wiring 17.

[Other Embodiments]
The present invention is not limited to the above embodiments, and various modifications can be made without departing from the spirit of the invention. For example, the present invention can be applied to a wiring structure other than the dual damascene structure as shown in each of the above embodiments. For example, a wiring structure composed of a wiring / via coated with a self-forming barrier film is individually provided. It may be applied when forming.

  In addition, the constituent elements of the above embodiments can be arbitrarily combined without departing from the spirit of the invention.

(A)-(c) is sectional drawing which shows the manufacturing process of the wiring structure of the semiconductor device which concerns on the 1st Embodiment of this invention. (D)-(e) is sectional drawing which shows the manufacturing process of the wiring structure of the semiconductor device which concerns on the 1st Embodiment of this invention. (F)-(g) is sectional drawing which shows the manufacturing process of the wiring structure of the semiconductor device which concerns on the 1st Embodiment of this invention. (H) is sectional drawing which shows the manufacturing process of the wiring structure of the semiconductor device which concerns on the 1st Embodiment of this invention. (A)-(b) is sectional drawing which shows the manufacturing process of the wiring structure of the semiconductor device which concerns on the 2nd Embodiment of this invention. (C)-(d) is sectional drawing which shows the manufacturing process of the wiring structure of the semiconductor device which concerns on the 2nd Embodiment of this invention. (E)-(f) is sectional drawing which shows the manufacturing process of the wiring structure of the semiconductor device which concerns on the 2nd Embodiment of this invention. (A)-(b) is sectional drawing which shows the manufacturing process of the wiring structure of the semiconductor device which concerns on the 3rd Embodiment of this invention. (C)-(d) is sectional drawing which shows the manufacturing process of the wiring structure of the semiconductor device which concerns on the 3rd Embodiment of this invention. It is a graph showing the leakage current characteristic of the wiring structure which concerns on the 3rd Embodiment of this invention. (A)-(b) is sectional drawing which shows the manufacturing process of the wiring structure of the semiconductor device which concerns on the 4th Embodiment of this invention. It is sectional drawing which shows the manufacturing process of the wiring structure of the semiconductor device which concerns on the 5th Embodiment of this invention. It is sectional drawing which shows the manufacturing process of the wiring structure of the semiconductor device which concerns on the 6th Embodiment of this invention. (A)-(b) is sectional drawing which shows the manufacturing process of the wiring structure of the semiconductor device which concerns on the 7th Embodiment of this invention. (A)-(b) is sectional drawing which shows the manufacturing process of the wiring structure of the semiconductor device which concerns on the 8th Embodiment of this invention.

DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 1st interlayer insulation film 3 Cap layer 4 1st barrier film 5 2nd interlayer insulation film 6 2nd barrier film 11 1st wiring 12 Self-forming barrier film 13 Wiring groove 14 Precursor film 15 Wiring forming film 16 Unreacted metal oxide film 17 Second wiring

Claims (3)

Forming an insulating film on the semiconductor substrate;
Forming a recess in the insulating film;
Forming a precursor film containing a predetermined metal element on the surface of the insulating film in which the recess is formed;
Depositing a wiring formation film on the precursor film;
By performing a heat treatment, the precursor film and the insulating film are reacted to form a self-forming barrier film containing as a main component a compound containing the predetermined metal element and the constituent element of the insulating film at the interface. Diffusing the unreacted predetermined metal element into the wiring formation film;
After the step of forming the self-forming barrier film and diffusing the unreacted predetermined metal element into the wiring formation film, the step of flattening the wiring formation film until the insulating film outside the recess is exposed When,
After the step of planarizing the wiring formation film, by performing a heat treatment in an oxidizing atmosphere, the predetermined metal element diffused in the wiring formation film is reacted with oxygen in the atmosphere on the surface of the wiring formation film, By advancing the reaction into the self-forming barrier film, an unreacted metal oxide film is deposited on the upper surface of the wiring forming film and a side surface near the upper surface, and the upper end of the wiring forming film is rounded to form a wiring structure. Forming, and
A method for manufacturing a semiconductor device, comprising: After the step of forming the wiring structure, a step of forming a barrier film on the wiring formation film;
By performing a heat treatment, the barrier film and the wiring forming film are reacted to form a self-forming barrier film containing as a main component a compound containing the predetermined metal element and the constituent element of the barrier film at the boundary surface. Process,
The method of manufacturing a semiconductor device according to claim 1, further comprising: After the step of forming the wiring structure, exposing the wiring forming film to at least silane gas;
By performing heat treatment in an oxidizing atmosphere, the wiring formation film exposed to the silane gas is reacted with oxygen in the atmosphere, and the upper surface of the wiring formation film is mainly composed of a compound containing the predetermined metal element and Si. Forming a self-forming barrier film;
The method of manufacturing a semiconductor device according to claim 1, further comprising:

Images