JP5483207B2 - Logic circuit - Google Patents

Description

  The present invention relates to a logic circuit using an in-plane double gate transistor having a thin active region (electrically conductive region) extending in two dimensions.

  Basic elements of the semiconductor logic circuit are a NAND circuit, a NOR circuit, a NOT circuit (inverter), and the like. An LSI is designed by a combination of these circuits. A logic circuit that has been generally used conventionally is a combination of CMOSs. For example, the simplest NOT circuit (inverter) can be realized by a single CMOS configuration, that is, a combination of an n-MOS transistor and a p-MOS transistor. A configuration example of the NOT circuit is shown in FIG.

  The NOT circuit includes a p-MOS transistor 100 and an n-MOS transistor 101. This NOT circuit can operate as an inverter by using the gates of the p-MOS transistor 100 and the n-MOS transistor 101 as the input terminal 102 and the drains of the p-MOS transistor 100 and the n-MOS transistor 101 as the output terminal 103. It is.

  On the other hand, a configuration example of a NAND circuit realized by a combination of CMOSs is shown in FIG. This NAND circuit is composed of a set of CMOSs composed of a p-MOS transistor 200 and an n-MOS transistor 201 and another set of CMOSs composed of a p-MOS transistor 202 and an n-MOS transistor 203. Yes. With this configuration, when (1, 1) is input as the input signal (A, B) to the input terminals 204 and 205, 0 is output from the output terminal 206 as the output signal OUT. On the other hand, when any of (1, 0), (0, 1), (0, 0) is input as the input signal (A, B), 1 is output as the output signal OUT.

  FIG. 14 shows a configuration example of a NOR circuit realized by a combination of CMOSs. This NOR circuit is composed of one set of CMOS composed of a p-MOS transistor 300 and an n-MOS transistor 301, and another set of CMOS composed of a p-MOS transistor 302 and an n-MOS transistor 303. Yes. Due to such a configuration, when any of (1, 0), (0, 1), (1, 1) is input to the input terminals 304 and 305 as the input signal (A, B), the output is performed. 0 is output from the terminal 306 as the output signal OUT. On the other hand, when (0, 0) is input as the input signal (A, B), 1 is output as the output signal OUT.

In both the NAND circuit and the NOR circuit, two sets of CMOSs, that is, four transistors are required. Further, in the CMOS manufacturing process, a plurality of ion implantation processes are indispensable, and the manufacturing cost is high.
As described above, the logic circuit in the prior art has a problem that the number of elements is large and the process requires many steps and costs.

As a logic circuit element capable of solving such a problem, an in-plane gate type element having an extremely thin active region (electric conduction region) extending in two dimensions is known (see, for example, Non-Patent Document 1). The structure of the in-plane gate type device is composed of GaAs / AlGaAs, InGaAs / InAlAs, InSb / InAlGaSb, InAs / AlGaSb, SiGe / Si, Si / SiO _2, etc. Realization with various semiconductors such as semiconductors is possible.

  Here, description will be made using an InGaAs / InAlAs system. FIG. 15 is a sectional view showing a semiconductor wafer structure of an in-plane gate type device. The wafer includes an InP substrate 400, an InAlAs buffer layer 401 formed on the InP substrate 400, an InGaAs layer 402 formed on the InAlAs buffer layer 401, an InAlAs layer 403 formed on the InGaAs layer 402, Si-doped InAlAs layer 404 formed on InAlAs layer 403, InAlAs layer 405 formed on Si-doped InAlAs layer 404, InP layer 406 formed on InAlAs layer 405, and InP layer 406 InGaAs layer 407. The thicknesses of the InAlAs buffer layer 401, InGaAs layer 402, InAlAs layer 403, Si-doped InAlAs layer 404, InAlAs layer 405, InP layer 406, and InGaAs layer 407 are 200 nm, 20 nm, 3 nm, 5 nm, 4 nm, 5 nm, and 2 nm, respectively. is there.

  In this semiconductor wafer structure, a two-dimensional electron conduction layer 408 having a high electron mobility is generated in the InGaAs layer 402 at the interface between the InGaAs layer 402 and the InAlAs layer 403. The thickness of the conductive layer 408 is extremely thin, about several nm. A thin groove is formed in the semiconductor wafer by ion etching from the surface, a channel structure is formed, and an in-plane double gate transistor is manufactured. By increasing the accuracy of ion etching, it is possible to form a very thin groove having a small aspect ratio with an etching width of 40 nm or less with little etching damage.

  16 is a plan view of the in-plane double gate transistor formed on the semiconductor wafer of FIG. 15 as viewed from above. FIG. 17 is a cross-sectional view of the in-plane double gate transistor of FIG. is there. 16 and 17, reference numeral 501 denotes an etching groove, 502 and 503 denote gates, 504 denotes a channel, 505 denotes a drain, and 506 denotes a source. The gates 502 and 503 are separated from the channel 504, the drain 505, and the source 506 by the etching groove 501. One end of the channel 504 is connected to the drain 505, and the other end of the channel 504 is connected to the source 506. The width W1 of the etching groove 501 is 40 nm, and the depth of the etching groove 501 is 33 nm. The width W2 of the channel 504 is 120 nm, and the length L1 of the channel 504 is 1.1 μm. This in-plane double gate transistor 500 has a double gate structure in which gates 502 and 503 are arranged on both sides of a channel 504.

  In the structure of the in-plane double gate transistor 500 shown in FIGS. 16 and 17, there is a concern that the gate efficiency (gm) is low. However, when two-dimensional electrons are used, sufficient controllability can be obtained. FIG. 18 is a diagram illustrating output characteristics of the in-plane double gate transistor 500 illustrated in FIGS. 16 and 17. FIG. 18 shows output characteristics when gate voltages of 0 V, 0.2 V, 0.4 V, 0.6 V, 0.8 V, and 1.0 V are applied to both gates 502 and 503.

  As a NAND circuit using the in-plane double gate transistor 500 shown in FIGS. 16 and 17, for example, a configuration as shown in FIG. 19 is known (see, for example, Non-Patent Document 2). This NAND circuit includes an in-plane double gate transistor 500 and a fixed load resistor 507 connected in series with the in-plane double gate transistor 500.

When 1 V is applied as the input voltages V _In1 and V _In2 to the two input terminals 508 and 509, the channel of the in-plane double gate transistor 500 is turned on, and the channel is reduced in resistance. 0V appears. On the other hand, if 1V is applied to one of the two input terminals 508 and 509 and 0V is applied to the other input terminal, or 0V is applied to the two input terminals 508 and 509, the Since the channel of the plane double gate transistor 500 is turned off and the resistance of the channel increases, 1V appears at the output terminal 510. Such channel ON / OFF can be realized by adjusting the channel width.

A.D.Wieck and K.Ploog, “In-plane-gated quantum wire transistor fabricated with directly written focused ion beams”, Appl. Phys. Lett., Vol. 56, No. 10, p. 928-930, March 1990 S. Reitzenstein, L. Worschech, CRMuller and A. Forchel, “Compact Logic NAND-Gate Based on a Single In-Plane Quantum-Wire Transistor”, IEEE ELECTRON DEVICE LETTERS, VOL.26, NO.3, p.142 -144, March 2005

  In the logic circuit shown in FIG. 19, the number of elements can be remarkably reduced as compared with the circuits shown in FIGS. 13 and 14. However, since a fixed load resistor is used, the contrast between the ON state and the OFF state (High) / Low ratio) cannot be made sufficiently large. In the logic circuit shown in FIG. 19, when the channel of the in-plane double gate transistor is in the ON state, a current always flows through the circuit, and there is a problem that power consumption increases.

  SUMMARY An advantage of some aspects of the invention is that it provides a logic circuit with high contrast (High / Low ratio) between an ON state and an OFF state and low power consumption.

  In the logic circuit of the present invention, the first and second gates are respectively connected to the first and second input terminals, the drain is connected to the output terminal, and the source is connected to the ground terminal. A gate transistor; and a second in-plane double gate transistor having first and second gates and a source connected to a drain of the first in-plane double-gate transistor and a drain connected to a bias terminal. It is a feature.

  In the logic circuit of the present invention, the first and second gates are connected to the first and second input terminals, the drain is connected to the output terminal, and the source is connected to the ground terminal. The transistor, the first and second gates and the source are integrally formed, the first and second gates and the source are connected to the drain of the in-plane double gate transistor, and the drain is connected to the bias terminal. And a self-biased in-plane transistor.

  In the logic circuit of the present invention, the second gate and the source of the first and second gates are integrally formed, the first gate is connected to the input terminal, and the drain is connected to the output terminal. The in-plane double gate transistor having the second gate and source connected to the ground terminal, and the first and second gates and source are formed as a single structure, and the first and second gates and source are connected to the in-plane structure. And a self-biased in-plane transistor having a drain connected to a drain of the plain double gate transistor and having a drain connected to a bias terminal.

In one configuration example of the logic circuit of the present invention, the drain of the first in-plane double gate transistor and the source of the second in-plane double gate transistor are connected via a wiring. To do.
In one configuration example of the logic circuit of the present invention, the first and second in-plane double gate transistors are formed in the same semiconductor stacked structure and share a conductive layer embedded in the semiconductor stacked structure. It is characterized by.
In one configuration example of the logic circuit of the present invention, the dimensions of the first and second in-plane double gate transistors are set so that a difference occurs in conductance between the first and second in-plane double gate transistors. It is characterized by being.

In one configuration example of the logic circuit of the present invention, the drain of the in-plane double gate transistor and the first and second gates and the source of the self-biased in-plane transistor are connected via a wiring. It is characterized by.
In one configuration example of the logic circuit of the present invention, the in-plane double gate transistor and the self-biased in-plane transistor are formed in the same semiconductor stacked structure, and a conductive layer embedded in the semiconductor stacked structure is formed. It is characterized by sharing.
Also, one configuration example of the logic circuit according to the present invention is configured so that a difference occurs between the conductance of the in-plane double gate transistor and the conductance of the self-biased in-plane transistor. The dimensions of the plain transistor are set.

  According to the present invention, by using an in-plane double gate transistor having a thin conductive layer (active region) that spreads in two dimensions as an element of a logic circuit, a logic circuit can be realized with a smaller number of elements than when using a CMOS. And wiring between elements can be reduced. Therefore, the present invention can greatly contribute to the high integration of circuits, the simplification of the manufacturing process, and the reduction of the manufacturing cost. Furthermore, in the present invention, the two in-plane double gate transistors are connected in series, so that the ON state is compared with the conventional logic circuit in which the in-plane double gate transistor and the fixed load resistor are connected in series. The contrast in the OFF state (High / Low ratio) can be made sufficiently large, and the power consumption can be reduced.

  Further, according to the present invention, a conventional logic circuit in which an in-plane double gate transistor and a fixed load resistor are connected in series by configuring the in-plane double gate transistor and the self-biased in-plane transistor in series. In comparison, the contrast (High / Low ratio) between the ON state and the OFF state can be made sufficiently large, and the power consumption can be reduced.

  In the present invention, an in-plane double gate transistor in which the second gate and the source of the first and second gates are integrally formed and a self-biased in-plane transistor are connected in series. Thus, a NOT circuit can be realized. In the present invention, the contrast (High / Low ratio) between the ON state and the OFF state can be sufficiently large as compared with a conventional logic circuit in which an in-plane double gate transistor and a fixed load resistor are connected in series. Power consumption can be reduced.

  In the present invention, the first and second in-plane double gate transistors are formed in the same semiconductor stacked structure, and the conductive layer embedded in the semiconductor stacked structure is shared by the first and second in-plane double gate transistors. By doing so, the input / output characteristics of the logic circuit can be improved, and the cost for designing and manufacturing can be reduced.

  In the present invention, the in-plane double gate transistor and the self-biased in-plane transistor are formed in the same semiconductor stacked structure, and the conductive layer embedded in the semiconductor stacked structure is formed in the in-plane double-gate transistor and the self-biased in-plane. By sharing the transistors, the input / output characteristics of the logic circuit can be improved, and the cost for designing and manufacturing can be reduced.

  In the present invention, the logic circuit is configured as a NAND circuit by setting the dimensions of the first and second in-plane double gate transistors so that a difference occurs in conductance between the first and second in-plane double gate transistors. Alternatively, it can be operated as a NOR circuit.

  In the present invention, the dimensions of the in-plane double gate transistor and the self-biased in-plane transistor are set so that a difference occurs between the conductance of the in-plane double-gate transistor and the self-biased in-plane transistor. The circuit can be operated as a NAND circuit or a NOR circuit.

1 is a circuit diagram showing a configuration of a logic circuit according to a first embodiment of the present invention. It is a figure which shows the input / output characteristic of the logic circuit based on the 1st Embodiment of this invention. It is a circuit diagram which shows the structure of the logic circuit based on the 2nd Embodiment of this invention. It is a circuit diagram which shows the structure of the logic circuit based on the 3rd Embodiment of this invention. It is a top view of the self-bias type in-plane transistor in the 3rd Embodiment of this invention. It is a figure which shows the input / output characteristic of the logic circuit based on the 3rd Embodiment of this invention. It is a figure which shows another input / output characteristic of the logic circuit based on the 3rd Embodiment of this invention. It is a circuit diagram which shows the structure of the logic circuit based on the 4th Embodiment of this invention. It is a circuit diagram which shows the structure of the logic circuit based on the 5th Embodiment of this invention. It is a circuit diagram which shows the structure of the logic circuit based on the 6th Embodiment of this invention. It is the photograph which image | photographed the logic circuit based on the 6th Embodiment of this invention from the top. It is a circuit diagram which shows the structural example of the conventional NOT circuit. It is a circuit diagram which shows the structural example of the conventional NAND circuit. It is a circuit diagram which shows the structural example of the conventional NOR circuit. It is sectional drawing which shows the semiconductor wafer structure of the conventional in-plane gate type | mold element. It is a top view of the conventional in-plane double gate transistor. It is sectional drawing of the in-plane double gate transistor of FIG. It is a figure which shows the output characteristic of an in-plane double gate transistor. It is a circuit diagram which shows the structural example of the NAND circuit using an in-plane double gate transistor.

[First Embodiment]
Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram showing a configuration of a logic circuit according to the first embodiment of the present invention. The logic circuit according to the present embodiment includes a first in-plane double gate transistor 1 and a second in-plane double gate transistor 2 connected in series with the first in-plane double gate transistor 1. . The structures of the in-plane double gate transistors 1 and 2 are the same as those of the transistors shown in FIGS. 16 and 17, and the channel width is about 120 nm and the channel length is about 1.1 μm.

  The gate 10 of the in-plane double gate transistor 1 is connected to the input terminal 3, the gate 11 is connected to the input terminal 4, the drain 12 is connected to the output terminal 5, and the source 13 is connected to the ground terminal (low potential terminal) 8. Has been. Gold wires are connected between the input terminal 3 and the gate 10, between the input terminal 4 and the gate 11, and between the ground terminal 8 and the source 13.

  The gates 20 and 21 of the in-plane double gate transistor 2 are connected to the output terminal 5 and the drain 12 of the in-plane double gate transistor 1, the drain 22 is connected to the bias terminal 6, and the source 23 is connected to the output terminal 5 and the in-plane double gate. It is connected to the drain 12 of the transistor 1. Gold wires are connected between the output terminal 5 and the gates 20 and 21, between the bias terminal 6 and the drain 22, and between the source 23 and the drain 12 of the in-plane double gate transistor 1.

Logic operation is possible by applying 1 V to the bias terminal 6 of this logic circuit and inputting voltages V _In1 and V _In2 to the two input terminals (double gate terminals) 3 and 4 of the in-plane double gate transistor 1.
FIG. 2 is a diagram showing input / output characteristics of the logic circuit of this embodiment. The input / output characteristics shown in FIG. 2 are measurement results in a configuration in which two in-plane double gate transistors 1 and 2 are connected in series with gold wiring. The bias voltage V _DD applied to the bias terminal 6 is 1V, and the voltage of the ground terminal 8 is 0V.

When 0V is applied to the two input terminals 3 and 4 as the input voltages V _In1 and V _In2 , the channel of the in-plane double gate transistor 1 is turned off and the resistance of the channel is increased. The voltage of 12 rises. Since this drain voltage is input to the two gates 20 and 21 of the in-plane double gate transistor 2, the channel of the in-plane double gate transistor 2 is turned on, and the resistance of the channel is reduced. As a result, the voltage _Vout of the output terminal 5 rises to a high level close to 1V (0.9V in the example of FIG. 2).

On the other hand, when 1V is applied to one input terminal of the two input terminals 3 and 4, and 0V is applied to the other input terminal, or 1V is applied to the two input terminals 3 and 4, Since the channel of the plane double gate transistor 1 is turned on and the resistance of the channel is lowered, the voltage of the drain 12 of the inplane double gate transistor 1 is lowered. Since this drain voltage is input to the two gates 20 and 21 of the in-plane double gate transistor 2, the channel of the in-plane double gate transistor 2 is turned off, and the resistance of the channel is increased. As a result, most of the bias voltage is applied to the in-plane double gate transistor 2, so that the voltage _Vout of the output terminal 5 becomes a low level close to 0V (0.03 to 0.05V in the example of FIG. 2). As described above, the logic circuit of this embodiment operates as a NOR circuit.

  In this embodiment, a semiconductor stacked structure having a thin active region extending two-dimensionally is used as a starting material. Since a specific logic circuit is realized by digging extremely fine grooves in the semiconductor laminated structure, connection between elements can be freely realized by designing a groove pattern. For this reason, the connection terminals, wiring, etc. between elements can be omitted significantly. As described above, in this embodiment, by using the in-plane double gate transistors 1 and 2 as the elements of the logic circuit, a logic circuit can be realized with a smaller number of elements compared to the case of using the CMOS, and Wiring between elements can be reduced. Therefore, this embodiment can greatly contribute to the high integration of circuits, the simplification of the manufacturing process, and the reduction of the manufacturing cost.

  Furthermore, in the present embodiment, the two in-plane double gate transistors 1 and 2 are connected in series, so that the contrast between the ON state and the OFF state (High / OFF) is compared with the logic circuit shown in FIG. (Low ratio) can be made sufficiently large. In the present embodiment, when the channel of the in-plane double gate transistor 1 is in the OFF state, the channel of the in-plane double gate transistor 2 is in the ON state, and when the channel of the in-plane double gate transistor 1 is in the ON state, The channel of the plane double gate transistor 2 is turned off. Therefore, in the present embodiment, almost no current flows from the bias terminal 6 to the ground, so that power consumption can be reduced as compared with the logic circuit shown in FIG. In this embodiment mode, a more complicated circuit configuration can be dealt with by combining logic circuits.

Although the logic circuit of this embodiment operates as a NOR circuit, 1 V is applied to only one gate of the in-plane double gate transistor 1 by adjusting the channel widths of the two in-plane double gate transistors 1 and 2. If the channel is not turned on even when it is applied, it can be operated as a NAND circuit. That is, a NAND circuit can be realized by using as the load an in-plane gate transistor 2 having a channel width wider than the channel width of the in-plane double gate transistor 1 to which the input voltages V _In1 and V _In2 are applied. The details of setting the channel width and channel length according to the desired circuit operation will be described later.

[Second Embodiment]
Next, a second embodiment of the present invention will be described. FIG. 3 is a circuit diagram showing a configuration of a logic circuit according to the second embodiment of the present invention. The same components as those in FIG. 1 are denoted by the same reference numerals. In the logic circuit of this embodiment, two in-plane double gate transistors 1 and 2 are formed on the same semiconductor wafer structure, and the active region (the conductive layer 408 in FIGS. 15 and 17) is formed by two in-plane double gate transistors. 1 and 2 are shared.

  Since there is a conductive layer in a portion other than the etching groove, it is not necessary to connect the transistors by wiring. As a result, the drain 12 of the in-plane double gate transistor 1 and the source 23 of the in-plane double gate transistor 2 are directly connected without using wiring. This connection is possible because the drains 12 and 22, the sources 13 and 23, and the gates 10, 11, 20, and 21 of the in-plane double gate transistors 1 and 2 are all formed in the same layer.

As described in the first embodiment, the logic circuit of this embodiment can be operated as a NOR circuit or a NAND circuit.
In the first embodiment, two in-plane double gate transistors 1 and 2 are connected in series with gold wiring. On the other hand, in this embodiment, such wiring is not necessary, and a terminal formed on the drain 12 and a terminal formed on the source 23 are not necessary, so that the input / output characteristics of the logic circuit are improved. Can be expected. In addition, since the design and manufacture of the circuit are facilitated as compared with the first embodiment, the cost for design and manufacture can be reduced.

[Third Embodiment]
Next, a third embodiment of the present invention will be described. FIG. 4 is a circuit diagram showing a configuration of a logic circuit according to the third embodiment of the present invention. The same components as those in FIG. 1 are denoted by the same reference numerals. The logic circuit of the present embodiment includes an in-plane double gate transistor 1 and a self-biased in-plane transistor 7 connected in series with the in-plane double gate transistor 1. The structure of the in-plane double gate transistor 1 is the same as that of the transistor shown in FIGS. 16 and 17, and the channel width is about 120 nm and the channel length is about 1.1 μm.

  The gate 10 of the in-plane double gate transistor 1 is connected to the input terminal 3, the gate 11 is connected to the input terminal 4, the drain 12 is connected to the output terminal 5, and the source 13 is connected to the ground terminal 8. Gold wires are connected between the input terminal 3 and the gate 10, between the input terminal 4 and the gate 11, and between the ground terminal 8 and the source 13.

  The gates 70 and 71 and the source 73 of the self-bias type in-plane transistor 7 are connected to the output terminal 5 and the drain 12 of the in-plane double gate transistor 1, and the drain 72 is connected to the bias terminal 6. Gold wires are connected between the output terminal 5 and the gates 70 and 71 and the source 73, and between the gates 70 and 71 and the source 73 and the drain 12 of the in-plane double gate transistor 1.

  FIG. 5 is a plan view of the self-biased in-plane transistor 7 as viewed from above. Since the cross section of the self-bias type in-plane transistor 7 taken along the line II in FIG. 5 is the same as that in FIG. 17, the description of the cross section is omitted. In FIG. 5, 74 is an etching groove, and 75 is a channel. One end of the channel 75 is connected to the drain 72. On the other hand, the gates 70 and 71 and the channel 75 are not separated by the etching groove 74, and the other end of the channel 75 is connected to the gates 70 and 71 and the source 73 as they are. The width W3 of the etching groove 74 is 40 nm, and the depth of the etching groove 74 is 33 nm. The width W4 of the channel 75 is 100 nm, and the length L2 of the channel 75 is 1.1 μm.

FIG. 6 is a diagram showing input / output characteristics of the logic circuit of this embodiment. The input / output characteristics shown in FIG. 6 are measurement results in a configuration in which the in-plane double gate transistor 1 and the self-biased in-plane transistor 7 are connected in series with a gold wiring. The bias voltage V _DD applied to the bias terminal 6 is 1V.

When 0V is applied to the two input terminals 3 and 4 as the input voltages V _In1 and V _In2 , the channel of the in-plane double gate transistor 1 is turned off and the resistance of the channel is increased. The voltage of 12 rises. Since this drain voltage is input to the two gates 70 and 71 of the self-biased in-plane transistor 7, the channel of the self-biased in-plane transistor 7 is turned on, and the resistance of the channel is reduced. As a result, the voltage _Vout of the output terminal 5 rises to a high level close to 1V (0.95V in the example of FIG. 6).

On the other hand, when 1V is applied to one input terminal of the two input terminals 3 and 4, and 0V is applied to the other input terminal, or 1V is applied to the two input terminals 3 and 4, Since the channel of the plane double gate transistor 1 is turned on and the resistance of the channel is lowered, the voltage of the drain 12 of the inplane double gate transistor 1 is lowered. Since this drain voltage is input to the two gates 70 and 71 of the self-biased in-plane transistor 7, the channel of the self-biased in-plane transistor 7 is turned off, and the resistance of the channel is increased. As a result, most of the bias voltage is applied to the self-bias type in-plane transistor 7, so that the voltage _Vout of the output terminal 5 becomes a low level close to 0V (0.02 to 0.05V in the example of FIG. 6). As described above, when the channel width of the self-bias type in-plane transistor 7 is 100 nm and the channel length is 1.1 μm, the logic circuit of this embodiment operates as a NOR circuit.

  On the other hand, FIG. 7 shows input / output characteristics of the logic circuit when the channel width of the self-biased in-plane transistor 7 is 120 nm and the channel length is 1.1 μm. Similar to FIG. 6, the input / output characteristics shown in FIG. 7 are measurement results in a configuration in which the in-plane double gate transistor 1 and the self-biased in-plane transistor 7 are connected in series with a gold wiring.

When the channel width is increased to 120 nm, the self-biased in-plane transistor 7 is not turned off unless a strong voltage is applied to the gates 70 and 71. When voltage application to the gates 10 and 11 of the in-plane double-gate transistor 1 is performed only on one gate, the drain voltage of the in-plane double-gate transistor 1 leads the self-biased in-plane transistor 7 to the OFF state. It does n’t drop as well. Therefore, when 0 V is applied as the input voltages V _In1 and V _In2 to the two input terminals 3 and 4, or 1 V is applied to one of the two input terminals 3 and 4, and 0 V is applied to the other input terminal. Is applied, the channel of the in-plane double gate transistor 1 is turned off and the voltage of the drain 12 rises. As the drain voltage rises, the channel of the self-biased in-plane transistor 7 is turned on. As a result, the voltage _Vout of the output terminal 5 rises to a high level close to 1V (0.9 to 0.98V in the example of FIG. 7).

On the other hand, when 1 V is applied as the input voltages V _In1 and V _In2 to the two input terminals 3 and 4, the channel of the in-plane double gate transistor 1 is turned on, and the voltage of the drain 12 is lowered. Due to the drop of the drain voltage, the channel of the self-biased in-plane transistor 7 is turned off. As a result, the voltage _Vout of the output terminal 5 becomes a low level close to 0V (0.09V in the example of FIG. 7). Thus, when the channel width of the self-biased in-plane transistor 7 is 120 nm and the channel length is 1.1 μm, the logic circuit of this embodiment operates as a NAND circuit.

  As described above, in the present embodiment, the inplane double gate transistor 1 and the self-biased inplane transistor 7 are connected in series to obtain the same effect as the first embodiment. Can do.

[Fourth Embodiment]
Next, a fourth embodiment of the present invention will be described. FIG. 8 is a circuit diagram showing a configuration of a logic circuit according to the fourth embodiment of the present invention. The same components as those in FIG. 4 are denoted by the same reference numerals. In the logic circuit of this embodiment, an in-plane double gate transistor 1 and a self-biased in-plane transistor 7 are fabricated on the same semiconductor wafer structure, and an active region (the conductive layer 408 in FIGS. 15 and 17) is formed in-plane. The double gate transistor 1 and the self-biased in-plane transistor 7 are shared.

  As in the second embodiment, since there is a conductive layer in a portion other than the etching groove, it is not necessary to connect the transistors with wiring. As a result, the drain 12 of the in-plane double gate transistor 1 and the gates 70 and 71 and the source 73 of the self-biased in-plane transistor 7 are directly connected without using wiring. This connection is because the drain 12, source 13 and gates 10 and 11 of the in-plane double gate transistor 1 and the drain 72, source 73 and gates 70 and 71 of the self-biased in-plane transistor 7 are all formed in the same layer. It becomes possible.

As described in the third embodiment, the logic circuit of this embodiment can be operated as a NOR circuit or a NAND circuit.
In the third embodiment, the in-plane double gate transistor 1 and the self-biased in-plane transistor 7 are connected in series with a gold wiring. On the other hand, in this embodiment, such wiring is not necessary, and terminals formed on the drain 12 and terminals formed on the gates 70 and 71 are not necessary. Improvement can be expected. In addition, since the design and manufacture of the circuit are facilitated as compared with the third embodiment, the cost for design and manufacture can be reduced.

[Fifth Embodiment]
Next, a fifth embodiment of the present invention will be described. FIG. 9 is a circuit diagram showing a configuration of a logic circuit according to the fifth embodiment of the present invention. The same components as those in FIGS. 4 and 8 are denoted by the same reference numerals. In this embodiment, in the logic circuit of the fourth embodiment, the gates 10 and 11 of the in-plane double gate transistor 1 are short-circuited by wiring. That is, the gates 10 and 11 are connected to the same input terminal 9.

The conditions of the channel width and the channel length of the in-plane double gate transistor 1 and the conditions of the channel width and the channel length of the self-biased in-plane transistor 7 may be the conditions for the NOR circuit described in the third embodiment. However, the conditions for a NAND circuit may be used. The bias voltage V _DD applied to the bias terminal 6 is 1V, and the voltage of the ground terminal 8 is 0V.

When 1V is applied to the input terminal 9 as the input voltage V _In , the channel of the in-plane double gate transistor 1 is turned on and the resistance of the channel is lowered, so that the voltage of the drain 12 of the in-plane double gate transistor 1 is lowered. Due to the drop in the drain voltage, the channel of the self-biased in-plane transistor 7 is turned off, and the resistance of the channel is increased. As a result, the voltage _Vout of the output terminal 5 becomes a low level close to 0V.

On the other hand, when 0 V is applied to the input terminal 9 as the input voltage V _In , the channel of the in-plane double gate transistor 1 is turned off and the resistance of the channel increases, so that the voltage of the drain 12 of the in-plane double gate transistor 1 increases. To do. As the drain voltage rises, the channel of the self-biased in-plane transistor 7 is turned on, and the resistance of the channel is reduced. As a result, the voltage _{Vout at} the output terminal 5 rises to a high level close to 1V. As described above, the logic circuit of this embodiment operates as a NOT circuit (inverter).

  As described above, in the present embodiment, the inplane double gate transistor 1 and the self-biased inplane transistor 7 are connected in series to obtain the same effect as the first embodiment. Can do. Further, in the present embodiment, a wiring for connecting the in-plane double gate transistor 1 and the self-biased in-plane transistor 7 is not necessary, and a terminal formed on the drain 12 and a terminal formed on the gates 70 and 71. Therefore, the same effect as in the fourth embodiment can be obtained.

[Sixth Embodiment]
Next, a sixth embodiment of the present invention will be described. FIG. 10 is a circuit diagram showing a configuration of a logic circuit according to the sixth embodiment of the present invention, and FIG. 11 is a photograph of the logic circuit taken from above, which has the same configuration as that of FIGS. Are given the same reference numerals. The logic circuit of the present embodiment includes an in-plane double gate transistor 1a and a self-biased in-plane transistor 7 connected in series with the in-plane double gate transistor 1a. In FIG. 11, 30 is an etching groove, and 31 is an element isolation groove formed to separate a circuit portion from a semiconductor wafer after the logic circuit is manufactured.

  Similar to the fourth and fifth embodiments, the in-plane double gate transistor 1a and the self-biased in-plane transistor 7 are formed in the same semiconductor wafer structure and share an active region.

The in-plane double gate transistor 1a includes the gate 11 (the gate 503 in FIGS. 16 and 17) and the source 13 (the source 506 in FIGS. 16 and 17) in the in-plane double gate transistor 1 of the fifth embodiment. The etching groove which has been separated is eliminated, and the gate 11 and the source 13 are short-circuited. Other configurations are the same as those of the in-plane double gate transistor 1. The gate 10 of the in-plane double gate transistor 1 a is connected to the input terminal 9, and the gate 11 and the source 13 are connected to the ground terminal 8.
The gates 70 and 71 and the source 73 of the self-bias type in-plane transistor 7 are connected to the output terminal 5 and the drain 12 of the in-plane double gate transistor 1 a, and the drain 72 is connected to the bias terminal 6.

When 1V is applied to the input terminal 9 as the input voltage V _In , the channel of the in-plane double gate transistor 1a is turned on and the resistance of the channel is reduced, so that the voltage of the drain 12 of the in-plane double gate transistor 1a is lowered. Due to the drop in the drain voltage, the channel of the self-biased in-plane transistor 7 is turned off, and the resistance of the channel is increased. As a result, the voltage _Vout of the output terminal 5 becomes a low level close to 0V.

On the other hand, when 0 V is applied to the input terminal 9 as the input voltage V _In , the channel of the in-plane double gate transistor 1a is turned off and the channel becomes highly resistive, so that the voltage of the drain 12 of the in-plane double gate transistor 1a increases. To do. As the drain voltage rises, the channel of the self-biased in-plane transistor 7 is turned on, and the resistance of the channel is reduced. As a result, the voltage _{Vout at} the output terminal 5 rises to a high level close to 1V. As described above, the logic circuit of this embodiment operates as a NOT circuit (inverter).

  However, the NOT circuit of the present embodiment can be considered that the input of the gate on one side is always zero. Therefore, in order to operate as a NOT circuit, the channel width and channel length conditions of the in-plane double gate transistor 1a and the channel width and channel length conditions of the self-biased in-plane transistor 7 are the same as those in the NOR circuit. It is necessary to make it a condition.

  The feature of this embodiment is that no wiring other than the input terminal 9, the output terminal 5, the bias terminal 6, and the ground terminal 8 is required. According to the present embodiment, the number of wirings and terminals can be reduced as compared with the fifth embodiment, so that the cost for designing and manufacturing can be further reduced.

  Finally, conditions for operating the logic circuit as a NAND circuit or a NOR circuit will be described. In any one of the logic circuits of the first to sixth embodiments, whether to operate as a NAND circuit or a NOR circuit depends on the transistors 1 and 1a to which an input signal is applied and the transistors 2 and 7 that operate as a load. Is determined by using the channel length and the channel width under appropriate conditions.

The condition for operating the logic circuit as a NAND circuit is that the conductance of the transistors 2 and 7 on the load side is higher than that of the transistors 1 and 1a on the input side when the input is (V _In1 , V _In2 ) = (0V, 1V). It is expensive. In other words, when the channel lengths of the transistors 1 and 1a on the input side and the channel lengths of the transistors 2 and 7 on the load side are the same, the channel width of the transistors 2 and 7 on the load side is the channel width of the transistors 1 and 1a on the input side. It is a condition that it is wider.

On the other hand, the condition for operating the logic circuit as a NOR circuit is that when the input is (V _In1 , V _In2 ) = (0V, 1V), the conductance of the transistors 1 and 1a on the load side is higher than that of the transistors 1 and 1a on the input side. The conductance is low. In other words, when the channel lengths of the transistors 1 and 1a on the input side and the channel lengths of the transistors 2 and 7 on the load side are the same, the channel width of the transistors 2 and 7 on the load side is the channel width of the transistors 1 and 1a on the input side. It is a condition that is equal to or narrower.

Here, the reason why the channel widths may be equal is that when (V _In1 , V _In2 ) = (0V, 1V) is input, the conductance of the transistors 1 and 1a on the input side is (V _In1 , V _In2 ) = (0V, 0V), which is higher than that at the time of (0V, 0V), the load-side transistors 2 and 7 and the input-side transistors 1 and 1a have the same channel width, but the load-side transistors 2 and 7 are relatively This is because the conductance is lowered.

  To summarize the above conditions, when the channel length of the input-side transistors 1 and 1a is the same as that of the load-side transistors 2 and 7, the channel width of the input-side transistors 1 and 1a and the load-side transistors 2 and 7 are the same. The relative relationship of the channel widths is opposite between the NAND circuit and the NOR circuit. In addition, it is important that the condition for operating the logic circuit as a NAND circuit or a NOR circuit has a difference in conductance rather than setting the channel width.

  The NOT circuit can be realized only by short-circuiting the two gates of the input-side transistor as described in the fifth embodiment, regardless of the conditions of the NAND circuit or the NOR circuit. However, in the case of the sixth embodiment, it is necessary to set the conditions for the dimensions of the NOR circuit to operate.

  The present invention can be applied to a semiconductor logic circuit.

  DESCRIPTION OF SYMBOLS 1, 1a, 2 ... In-plane double gate transistor, 3, 4, 9 ... Input terminal, 5 ... Output terminal, 6 ... Bias terminal, 7 ... Self-bias type in-plane transistor, 8 ... Ground terminal, 10, 11, 20 , 21, 70, 71 ... gate, 12, 22, 72 ... drain, 13, 23, 73 ... source.

Claims (9)

A first in-plane double gate transistor having first and second gates connected to the first and second input terminals, a drain connected to the output terminal, and a source connected to the ground terminal;
And a second in-plane double gate transistor having a first and a second gate and a source connected to a drain of the first in-plane double-gate transistor and a drain connected to a bias terminal. circuit. An in-plane double-gate transistor having first and second gates connected to the first and second input terminals, a drain connected to the output terminal, and a source connected to the ground terminal;
Self-bias type in which first and second gates and sources are integrally formed, the first and second gates and sources are connected to the drain of the in-plane double gate transistor, and the drain is connected to a bias terminal. A logic circuit comprising an in-plane transistor. Of the first and second gates, the second gate and the source are integrally formed, the first gate is connected to the input terminal, the drain is connected to the output terminal, and the second gate and source are grounded. An in-plane double gate transistor connected to the terminal;
Self-bias type in which first and second gates and sources are integrally formed, the first and second gates and sources are connected to the drain of the in-plane double gate transistor, and the drain is connected to a bias terminal. A logic circuit comprising an in-plane transistor. The logic circuit according to claim 1, wherein
The logic circuit, wherein a drain of the first in-plane double gate transistor and a source of the second in-plane double gate transistor are connected via a wiring. The logic circuit according to claim 1, wherein
The logic circuit characterized in that the first and second in-plane double gate transistors are formed in the same semiconductor stacked structure and share a conductive layer embedded in the semiconductor stacked structure. The logic circuit according to any one of claims 1, 4, and 5,
A logic circuit characterized in that dimensions of the first and second in-plane double gate transistors are set such that a difference occurs in conductance between the first and second in-plane double gate transistors. The logic circuit according to claim 2 or 3,
A logic circuit, wherein the drain of the in-plane double gate transistor and the first and second gates and the source of the self-biased in-plane transistor are connected through a wiring. The logic circuit according to claim 2 or 3,
The in-plane double gate transistor and the self-biased in-plane transistor are formed in the same semiconductor stacked structure, and share a conductive layer embedded in the semiconductor stacked structure. The logic circuit according to any one of claims 2, 3, 7, and 8,
The dimensions of the in-plane double gate transistor and the self-biased in-plane transistor are set so that a difference occurs between the conductance of the in-plane double-gate transistor and the conductance of the self-biased in-plane transistor. Logic circuit.

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