JP5428824B2 - Secondary battery protection device and semiconductor device manufacturing method - Google Patents

Description

  The present invention relates to a semiconductor device and a secondary battery protection device using a trench gate type MOSFET.

Since the trench gate type MOSFET has a channel region formed in the vertical direction, it has an advantage that the device area can be greatly reduced particularly in a power MOSFET requiring a large area.
The bidirectional trench lateral MOSFET disclosed in Patent Documents 1 and 2 will be described below.

  FIG. 21 is a plan view showing a charge / discharge control circuit of a conventional bidirectional trench lateral MOSFET and secondary battery protection device. FIG. 22 is a cross-sectional view of a principal part taken along line X1-X1 in FIG. FIG. 23 is a detailed view of an example of the B part of FIG. 21, where FIG. 23A is a plan view of the main part, and FIG. 23B is a cross-sectional view of the main part taken along line X2-X2 of FIG. . FIG. 24 is a detailed view of another example of the B part in FIG. 21. FIG. 24A is a plan view of the main part, and FIG. 24B is a cross-sectional view of the main part taken along line X3-X3 of FIG. It is.

In FIG. 21, the bidirectional trench lateral MOSFET 90 is mainly described, and the configuration of the charge / discharge control circuit 95 is omitted. In FIG. 21, the first n ⁺ source region 7, the second n ⁺ source region 8, the first p ⁺ base pickup region 41, and the second p ⁺ base pickup region 51 are omitted. 22, 23 (a) and 24 (a), the plug 13, the first source electrode wiring 14, and the second source electrode wiring 15 are omitted, and in FIG. 22, the interlayer filling the first trench 3. The insulating film 200, the first p ⁺ base pickup region 41, and the second p ⁺ base pickup region 51 are not shown.

  This bidirectional trench lateral MOSFET 90 includes an n-well region 2 formed in the surface layer of the p-type semiconductor substrate 1, and a first trench 3 having a closed loop-shaped meandering portion formed inside from the surface of the n-well region 2. Have The meandering portion is composed of an arc portion 300 and a straight portion 310. The second trench 25 is formed simultaneously with the first trench 3 and has a closed loop shape surrounding the first trench 3. The second trench 25 may be formed as necessary.

In addition, the first p base region 4 surrounded by the first trench 3 and the second trench 25 and formed in the surface layer of the n well region 2, and the first p base region 4 formed in the surface layer of the n well region 2 and surrounded by the first trench 3. 2 p base region 5, first n ⁺ source region 7 formed in the surface layer of first p base region 4 and in contact with the side wall of first trench 3, and side wall of first trench 3 formed in the surface layer of second p base region 5 A second n ⁺ source region 8 in contact with the first p base region 4, a first p ⁺ base pickup region 41 formed in the surface layer of the first p base region 4, and a second p ⁺ base pickup region 51 formed in the surface layer of the second p base region 5. And have.

  In addition, a first gate electrode 11 made of polysilicon is formed on the side wall of the first trench 3 via the gate insulating film 10 on the first p base region 4 side, and a gate insulating film 10 is formed on the side wall of the first trench 3. And a second gate electrode 12 made of polysilicon formed on the second p base region 5 side. In a region surrounded by the first trenches 3, there is a third trench 72 that connects the first trenches 3 to each other. The third trench 72 may be cut under the second polysilicon gate wiring 20. In the case of cutting, it is formed as shown in FIG. FIG. 31A is a main-portion cross-sectional view taken along the line Y1-Y1 of FIG. 21 when the third trench 72 is cut. FIG. 31B is a cross-sectional view of the main part taken along the line Y2-Y2 of FIG. 21 when the third trench 72 is cut. FIG. 31C is a mask layout view around the third trench 72 and the second polysilicon gate wiring 20. When the contact hole 21 on the second polysilicon gate wiring 20 is formed, the gate insulating film 10 below the second polysilicon gate wiring 20 may be damaged by contact etching. LOCOS, which is a thermal oxide film, may be formed. This LOCOS needs to be formed at a predetermined distance from the third trench 72. In the case of miniaturization, the third trench 72 is cut to separate it from LOCOS. Such a configuration can be the same in the fourth trench 71. Further, one end of the third trench 72 is formed so as to protrude from the arc portion 300. The second gate electrode 12 is formed on both side walls of the third trench 72 via the gate insulating film 10. The second gate electrode 12 is connected to the second gate electrode 12 in the first trench 3. The third trench 72 may be narrower than the first trench 3. In this case, the interlayer insulating film may be formed so as to be buried with the second gate electrode 12 and not be formed between the second gate electrodes 12.

  Further, a polysilicon film 28 (first gate electrode 11, second gate electrode 12 formed on the side of the first p base region 4 through an insulating film 27 formed simultaneously with the gate insulating film 10 on the side wall of the second trench 25. And a polysilicon film 29 (formed simultaneously with the first gate electrode 11 and the second gate electrode 12) formed on the n-well region 2 side. Further, a fourth trench 71 connecting the second trench 25 and the first trench 3 is provided. The fourth trench 71 may be cut under the first polysilicon gate wiring 19. One end of the fourth trench 71 is formed so as to protrude from the arc portion 300. A first gate electrode 11 is formed on both side walls of the fourth trench 71 via a gate insulating film 10. The first gate electrode 11 is connected to the first gate electrode 11 in the first trench 3 and the polysilicon film 28 in the second trench 25. The fourth trench 71 may be narrower than the first trench 3 and may be buried with the first gate electrode 11 so that no interlayer insulating film is formed between the first gate electrodes 11.

A plug 13 formed of tungsten or the like is disposed in the contact hole 16 opened in the interlayer insulating film 200 as necessary, and is in contact with the first n ⁺ source region 7 and the first p ⁺ base pickup region 41 via the plug 13. The first source electrode wiring 14 and the second source electrode wiring 15 in contact with the second n ⁺ source region 8 and the second p ⁺ base pickup region 51 through the plug 13 are provided.

  The first polysilicon gate wiring 19 in contact with the first gate electrode 11 in the fourth trench 71, the second polysilicon gate wiring 20 in contact with the second gate electrode 12 in the third trench 72, and the first polysilicon A first gate metal line 17 in contact with the gate line 19 through the contact hole 21, a second gate metal line 18 in contact with the second polysilicon gate line 20 through the contact hole 21, and a first gate line connected to the first source electrode line 14. 1 source terminal S1, 2nd source terminal S2 connected to the 2nd source electrode wiring 15, 1st gate terminal G1 connected to the 1st gate metal wiring 17, and 2nd gate connected to the 2nd gate metal wiring 18 Terminal G2. It should be noted that the polysilicon film 29 is not connected to other portions but is in a floating potential state or connected to the n-well region 2.

In FIG. 23A, a first p ⁺ base pickup region 41 and a second p ⁺ base pickup region 51 are formed in parallel with the longitudinal direction of the straight portion of the arc portion. On the other hand, in FIG. 24A, in order to reduce the device area (device pitch) compared to FIG. 23A, the first n ⁺ source region 7 and the first p ⁺ base are arranged in the longitudinal direction of the straight portion 310. Pickup regions 41, second n ⁺ source regions 8 and second p ⁺ base pickup regions 51 are alternately formed.

A LOCOS film 37 serving as an isolation region is formed so as to surround the bidirectional trench lateral MOSFET 90. The isolation region may not be the LOCOS film 37 but may be STI (Shallow Trench Isolation) or the like. The charge / discharge control circuit 95 includes planar MOSFETs such as a PMOS 333 and an NMOS 334. PMOS333 is gate formed through a gate insulating film on the surface of the n-well region 31 between the p formed in the n-well region 31 ⁺ source drain regions 32, 33 and p ⁺ source and drain regions 32, 33 An electrode 38 is provided. The NMOS 334 is a p-type semiconductor substrate 1 or a p-type semiconductor substrate between n ⁺ source / drain regions 35 and 36 and n ⁺ source / drain regions 35 and 36 formed in a p-well region (not shown) if necessary. 1 is provided with a gate electrode 39 formed on the surface of 1 via a gate insulating film. The gate electrode 38 and the gate electrode 39 can be formed simultaneously with the first gate electrode 11, the second gate electrode 12 and the polysilicon films 28 and 29 of the bidirectional trench lateral MOSFET 90. Between the charge / discharge control circuit 95 and the bidirectional trench lateral MOSFET, a p ⁺ region 34 is provided on the surface layer of the p-type semiconductor substrate 1, and the p ⁺ region 34 is grounded. The parasitic operation is suppressed by flowing the leakage current generated in the bidirectional trench lateral MOSFET 90 to the ground.

Thus, in the conventional bidirectional trench lateral MOSFET 90, the first trench 3 having the closed loop meandering portion has the first gate electrode 11 and the second gate electrode 12 formed on the side wall thereof, and the linear portion 310 of the meandering portion is formed. The trench remaining portions on both sides are the first n ⁺ source region 7 and the second n ⁺ source region 8 of the bidirectional MOSFET.

  In the case of forming the closed-loop second trench 25 on the outermost periphery, the first p base region 4 and the n-well region 2 are separated by the second trench 25. By forming the second trench 25, the pn junction between the n-well region 2 and the first p base region 4 is not the surface, so that the inactive region can be narrowed. Further, when the chip size is not changed, the active region can be expanded, so that the on-resistance can be reduced.

Hereinafter, the case where the above-described bidirectional trench lateral MOSFET 90 is applied to the secondary battery protection device and the secondary battery protection device described in Patent Document 3 will be described.
FIG. 25A is a block diagram showing a circuit configuration of a conventional secondary battery protection device housed in a battery pack housing a secondary battery such as a lithium ion battery. The battery pack 98 is connected to the charger 99. Shows the state. FIG. 25B is a diagram showing the charge / discharge control operation of FIG. FIG. 26 is a diagram showing a current path in the charge / discharge control operation of the secondary battery protection device, and shows a path of current flowing through the discharge FET 91 and the charge FET 92. (A) of the figure shows the charging / discharging current path at the normal time, (b) shows the discharging current path at the time of overcharge protection, and (c) shows the charging current path at the time of overdischarge protection.

  The battery pack 98 includes a charge / discharge control circuit that controls on / off of a discharge FET 91 that is a semiconductor device for discharge control of the secondary battery 96 and a charge FET 92 that is a semiconductor device for charge control. 95 is provided. The charge / discharge control circuit 95 detects an overdischarge detection circuit that detects overdischarge of the secondary battery 96, an overcharge detection circuit that detects overcharge of the secondary battery, and a discharge overcurrent of the secondary battery 96 in a normal state. A discharge overcurrent detection circuit is provided. 93 and 94 are parasitic diodes of the discharge FET 91 and the charge FET 92.

  Further, the battery pack 98 is provided with positive (+) side and negative (−) side output terminals of the secondary battery 96, and these output terminals are connected to the charger 99 when the secondary battery 96 is charged. It becomes an input terminal to which the charging current from the charging circuit 97 is input.

  During normal charging / discharging, both the discharge FET 91 and the charge FET 92 are controlled to be in the ON state. When overcharging is detected during normal charging, the discharge FET 91 is controlled to be in an OFF state, and the charging current is cut off. The charge FET 92 remains in the ON state. When a load device (not shown) is connected to the battery pack 98, the secondary battery 96 is in a discharged state to supply power to the load. When overdischarge is detected during normal discharge, the charge FET 92 is controlled to be in an OFF state, and the discharge current is cut off. The discharge FET 91 remains in the ON state. Also, in order to protect the secondary battery 96 from overcurrent due to abnormal load or load short circuit during discharge, the discharge overcurrent detection circuit is provided. When the overcurrent is detected in the discharge overcurrent detection circuit, the discharge FET 91 is The discharge current is cut off in the OFF state.

The bidirectional trench lateral MOSFET 90 shown in FIG. 21 includes a discharge FET 91, a charge FET 92, and parasitic diodes 93 and 94.
Specifically, a discharge FET 91 using the n well region 2 as a drain and the first n ⁺ source region 7 as a source, and a charge FET 92 using the n well region 2 as a drain and the second n ⁺ source region 8 as a source include an n well region. 2 and the n-well region 2 is not connected to any terminal. Further, the discharge FET 91 and the charge FET 92 are connected in antiparallel. Further, a parasitic diode 93 formed by a pn junction between the first p base region 4 and the n well region 2 and a parasitic diode 94 formed by a pn junction between the second p base region 5 and the n well region 2 are respectively antiparallel. It is connected.

A method for manufacturing the bidirectional trench lateral MOSFET 90 shown in FIGS. 21, 22 and 24 will be described below.
First, an impurity such as phosphorus is selectively introduced into the surface of the p-type semiconductor substrate 1, and the n-well region 2 is formed by thermal diffusion. At this time, the n-well region 31 of the charge / discharge control circuit may be formed at the same time. Next, impurities such as B (boron) are selectively introduced into the surface of the n-well region 2 and the first p base region 4 and the second p base region 5 are simultaneously formed by thermal diffusion. Next, a first trench 3 having a depth deeper than the final depth of the first p base region 4 and the second p base region 5 from the surface of the n well region 2 and shallower than the n well region 2 by dry etching or the like, The second trench 25, the third trench 72, and the fourth trench 71 are formed simultaneously. Next, an isolation region for isolating the bidirectional trench lateral MOSFET 90 from the charge / discharge control circuit 95 and the like is formed. Specifically, the element formation region (bidirectional trench lateral MOSFET 90 and charge / discharge control circuit 95) is masked with a nitride film, and the LOCOS film 37 is formed by thermal oxidation. Next, after removing the nitride film, a silicon oxide film is formed as the gate insulating film 10 by thermal oxidation or CVD. At this time, the gate insulating films of the PMOS 333 and the NMOS 334 formed in the charge / discharge control circuit 95 can be formed simultaneously. Next, polysilicon doped with impurities is deposited and etched by anisotropic etching, leaving polysilicon on both side walls of the first trench 3, the second trench 25, the third trench 72, and the fourth trench 71, A first gate electrode 11, a second gate electrode 12, a polysilicon film 28, and a polysilicon film 29 are formed. At this time, the gate electrode 38 of the PMOS 333 and the gate electrode 39 of the NMOS 334 can be formed simultaneously. Specifically, a step of forming a mask in a region for forming the gate electrodes 38 and 39 after depositing polysilicon may be added. The first p base region 4 and the second p base region 5 may be formed after the first gate electrode 11 and the second gate electrode 12 are formed. When the trench is not a closed loop but a trench having an end, the gate electrode needs to be divided into first and second. For example, the first and second gate electrodes can be formed by partially removing polysilicon on the trench sidewalls by CDE etching or the like using a resist as a mask. The step of dividing the gate electrode into two can be performed in any step from immediately after the gate formation to the trench filling.

Next, the first n ⁺ source region 7 and the second n ⁺ source region 8 are formed. 27 is a cross-sectional view of the main part in the manufacturing process. FIGS. 27 (a) and (c) are cross-sectional views taken along line X3-X3 in FIG. 24. FIG. 27 (b) is a cross-sectional view of FIG. The principal part sectional drawing cut | disconnected by the X4-X4 line is shown.

First, a resist is applied to the entire surface, a resist mask 61 is formed by patterning, and arsenic ions are implanted (FIGS. 27A and 27B). Next, the resist mask 61 is removed (FIG. 27C). At this time, ion implantation for forming the n ⁺ source / drain regions 35 and 36 may be performed simultaneously. The first n ⁺ source region 7 and the second n ⁺ source region 8 are activated by reflow described later. When the first p base region 4 and the second p base region 5 are formed after the first gate electrode 11 and the second gate electrode 12 are formed, impurities of the first n ⁺ source region 7 and the second n ⁺ source region 8 are formed. Before ion implantation, ion implantation and thermal diffusion (activation) of BF ₂ may be performed using the resist mask 61 as a mask.

Next, a first p ⁺ base pickup region 41 and a second p ⁺ base pickup region 51 are formed. 28 is a cross-sectional view of the main part in the manufacturing process. FIG. 28 (a) shows a cross-sectional view of the main part taken along line X3-X3 in FIG. 24. FIGS. 28 (b) and (c) are X4 in FIG. The principal part sectional drawing cut | disconnected by -X4 line is shown.

A resist is applied to the entire surface, a resist mask 62 is formed by patterning, and BF ₂ is ion-implanted (FIGS. 28A and 28B). Next, the resist mask 62 is removed (FIG. 28C). At this time, ion implantation for forming the p ⁺ source / drain regions 32 and 33 and the p ⁺ region 34 may be performed simultaneously. The first p ⁺ base pickup region 41 and the second p ⁺ base pickup region 51 are activated by reflow described later.

FIG. 29 is a fragmentary cross-sectional view during the manufacturing process, and shows a fragmentary cross-sectional view taken along line X3-X3 of FIG.
After forming the first p ⁺ base pickup region 41 and the second p ⁺ base pickup region 51, an interlayer insulating film 200 is formed. The interlayer insulating film 200 is reflowed after depositing BPSG (boro-phospho silicate glass film) by a CVD method. By this reflow, the first n ⁺ source region 7, the second n ⁺ source region 8, the first p ⁺ base pickup region 41, and the second p ⁺ base pickup region 51 are activated (FIG. 29A). Then, contact holes are formed in the interlayer insulating film 200, and the plugs 13 that are in contact with the first n ⁺ source region 7 and the second n ⁺ source region 8, the first p ⁺ base pickup region 41 and the second p ⁺ base pickup region 51 are formed. (FIG. 29 (b)). Thereafter, by forming the first source electrode wiring 14 and the second source electrode wiring 15 connected to the plug 13, the bidirectional trench lateral MOSFET 90 shown in FIGS. 21, 22 and 24 is completed.

JP 2004-274039 A JP 2008-172006 A JP 2008-42964 A

The bidirectional trench lateral MOSFET 90 shown in FIG. 24 includes a first parasitic transistor having an n well region 2 as an emitter, a first p base region 4 as a base, and a first n ⁺ source region 7 as a collector, and an n well region 2 as an emitter. And a second parasitic transistor having the second p base region 5 as a base and the second n ⁺ source region 8 as a collector. In order to increase the latch-up resistance so that these parasitic transistors are not turned on and the element is not destroyed, the interval between the first p ⁺ base pickup region 41 and the second p ⁺ base pickup region 51 is narrowed and the p base resistance is lowered. Is effective. However, the areas of the first n ⁺ source region 7 and the second n ⁺ source region 8 are reduced correspondingly, and the case where both the discharge FET 91 and the charge FET 92 are in the on state during the normal charge and discharge shown in FIG. On-resistance increases.

FIG. 30 is a diagram showing the mask displacement corresponding to FIG. In the step of forming the resist mask 62, if the alignment accuracy or processing accuracy is poor, the resist exposure area increases, and the resist mask 62 may be formed in a state where the resist has been removed to the bottom of the trench. In this case, ions are also implanted into the bottom surface of the trench, forming a p ⁺ region and lowering the breakdown voltage. The same problem occurs when the first n ⁺ source region 7 and the second n ⁺ source region 8 are formed.

A mask alignment margin in the patterning process of the resist mask 62 is only a thickness H1 obtained by adding the thickness of the first gate electrode 11 or the second gate electrode 12 and the thickness of the gate insulating film 10 (hereinafter referred to as a margin H1). If the first gate electrode 11 and the second gate electrode 12 are thickened to increase the margin, the device pitch increases and the on-resistance increases. Further, when the gate electrodes 38 and 39 of the PMOS 333 and the NMOS 334 are formed simultaneously with the first gate electrode 11 and the second gate electrode 12, a difference in level between the PMOS 333 and the NMOS 334 becomes large, which affects other processes. Further, when the gate insulating film 10 is thickened, the characteristics of the MOSFET are deteriorated. Therefore, in order to manufacture the bidirectional trench lateral MOSFET 90 excellent in cost and performance, the first n ⁺ source region 7 and the second n ⁺ source region 8 are formed, and the first p ⁺ base pickup region 41 and the second p ⁺ base pickup region. High alignment accuracy and processing accuracy in the forming step 51 are required.

  Since high alignment accuracy and processing accuracy are required in this way, it is necessary to add an inspection process and, in some cases, to perform a patterning process again, resulting in poor productivity. It can be said that such a problem occurs not only in the bidirectional trench lateral MOSFET but also in a trench gate type semiconductor device in which a gate electrode is formed on each side wall of the trench via an insulating film.

  An object of the present invention is to provide a semiconductor device and a secondary battery protection device with improved characteristics by solving the above-described problems. Another object of the present invention is to provide a method for manufacturing a semiconductor device which is low in cost and has improved productivity.

In order to achieve the above object, according to the first aspect of the present invention, the second conductivity type well region located in the surface layer of the first conductivity type semiconductor substrate,
A trench located in the well region;
A first base region and a second base region of a first conductivity type located on a surface layer of the well region and separated from each other by the trench and in contact with the trench;
A first source region of a second conductivity type located in a surface layer of the first base region and in contact with the trench;
A second source region of a second conductivity type located in a surface layer of the second base region and in contact with the trench;
A first pickup region of a first conductivity type located in a surface layer of the first base region;
A second pickup region of a first conductivity type located in a surface layer of the second base region;
A first gate electrode located on the first base region between the well region and the first source region on the sidewall of the trench via a gate insulating film;
A second gate electrode located on the second base region between the well region and the second source region on the sidewall of the trench via a gate insulating film;
A first main electrode in electrical contact with the first source region and the first pickup region;
A semiconductor device comprising: a second main electrode in electrical contact with the second source region and the second pickup region;
The first source region and the first pick-up region are arranged alternately in the longitudinal direction of the trench, the second pick-up region and the second source region are alternately arranged in the longitudinal direction of the trench, the first A secondary battery protection device in which one main electrode is connected to a low potential side of a secondary battery, and the second main electrode is connected to a charging circuit or a load for charging the secondary battery,
The length of the first source region between the first pickup regions in the length direction of the trench is shorter than the length of the second source region between the second pickup regions in the length direction of the trench.

According to the invention of claim 2 , the second conductivity type well region selectively formed in the surface layer of the first conductivity type semiconductor substrate;
A trench located in the well region;
A first base region and a second base region of a first conductivity type located on a surface layer of the well region and separated from each other by the trench and in contact with the trench;
A first source region of a second conductivity type located in a surface layer of the first base region and in contact with the trench;
A second source region of a second conductivity type located in a surface layer of the second base region and in contact with the trench;
A first pickup region of a first conductivity type located in a surface layer of the first base region;
A second pickup region of a first conductivity type located in a surface layer of the second base region;
A first gate electrode located on the first base region between the well region and the first source region on the sidewall of the trench via a gate insulating film;
A second gate electrode located on the second base region between the well region and the second source region on the sidewall of the trench via the gate insulating film;
A first main electrode in electrical contact with the first source region and the first pickup region;
A second main electrode in electrical contact with the second source region and the second pickup region,
A semiconductor device in which the first source region and the first pickup region are alternately arranged in the length direction of the trench, and the second source region and the second pickup region are alternately arranged in the length direction of the trench. In the manufacturing method of
After forming the well region, the first base region, the second base region, the trench, the gate insulating film, the first gate electrode, and the second gate electrode,
Forming a first resist mask that covers the bottom of the trench between the first gate electrode and the second gate electrode and has an opening that reaches the first base region and the second base region adjacent to the trench; When,
Performing ion implantation of impurities for forming the first source region and the second source region using the first resist mask;
Covering the trench bottom between the first gate electrode and the second gate electrode and a part of the first base region and the second base region adjacent to the trench, the first base region and the second base region Forming a second resist mask having an opening that reaches
Performing ion implantation of impurities for forming the first pickup region and the second pickup region using the second resist mask;
Forming a first main electrode in electrical contact with the first source region and the first pickup region;
Forming a second main electrode in electrical contact with the second source region and the second pickup region;
Suppose that

According to the invention described in claim 3 , the method for manufacturing a semiconductor device according to claim 2 ,
Selectively forming the well region in the semiconductor substrate;
Forming a first conductivity type region to be the first base region and the second base region in the well region;
Forming the trench in the well region at a depth deeper than the first conductivity type region so as to separate the first conductivity type region into the first base region and the second base region;
Forming a gate insulating film on the inner surface of the trench;
Forming the first gate electrode and the second gate electrode on both side walls of the trench.

According to the invention as set forth in claim 4 , in the method for manufacturing a semiconductor device according to claim 2 ,
Selectively forming the well region in the semiconductor substrate;
Forming the trench in the well region;
Forming a gate insulating film on the inner surface of the trench;
Forming the first gate electrode and the second gate electrode on both side walls of the trench;
Forming a third resist mask that covers the bottom of the trench between the first gate electrode and the second gate electrode, and has an opening reaching the portion of the first base region and the second base region adjacent to the trench. When,
And a step of performing ion implantation of impurities to form the first base region and the second base region in the well region using the third resist mask.

According to the invention of claim 5 , the second conductivity type well region selectively formed in the surface layer of the first conductivity type semiconductor substrate;
A trench located in the well region;
A base region of a first conductivity type located in a surface layer of the well region and in contact with one side wall of the trench;
A source region of a second conductivity type located in a surface layer of the base region and in contact with the trench;
A base pickup region of a first conductivity type located in a surface layer of the base region;
A drain region of a second conductivity type located in the surface layer of the well region and in contact with the other side wall of the trench;
A gate electrode located on the base region between the well region and the source region on one side wall of the trench via a gate insulating film;
A first main electrode in electrical contact with the source region and the base pickup region;
A second main electrode in electrical contact with the drain region,
In the method of manufacturing a semiconductor device in which the source region and the pickup region are alternately arranged in the length direction of the trench,
After forming the well region, the base region, the trench, the gate insulating film and the gate electrode,
Forming a first resist mask that covers the bottom of the trench and has an opening reaching a portion of the base region adjacent to the trench;
Performing impurity ion implantation for forming the source region and the drain region using the first resist mask;
Forming a second resist mask that covers a portion of the trench bottom and the base region adjacent to one side wall of the trench and has an opening reaching the base region;
Performing impurity ion implantation for forming the base pickup region using the second resist mask;
Forming a first main electrode in electrical contact with the source region and the base pickup region;
Forming a second main electrode in electrical contact with the drain region;
Suppose that

According to the invention described in claim 6 of the claims, in the method of manufacturing a semiconductor device according to claim 5 ,
Selectively forming the well region in the semiconductor substrate;
Forming the base region in the well region;
Forming a trench in the well region at a depth deeper than the base region;
Forming a gate insulating film on the inner surface of the trench;
Forming the gate electrode on one side wall of the trench.

According to the invention of claim 7 of the scope of claims, in the method of manufacturing a semiconductor device of claim 5 ,
Selectively forming the well region in the semiconductor substrate;
Forming the trench in the well region;
Forming a gate insulating film on the inner surface of the trench;
Forming the gate electrode on one side wall of the trench;
Forming a third resist mask covering the surface adjacent to the trench bottom and the other sidewall of the trench and having an opening reaching a location adjacent to the sidewall of the trench;
And a step of performing ion implantation of impurities for forming the base region in the well region using the third resist mask.

  According to the present invention, a semiconductor device and a secondary battery protection device with improved characteristics can be provided. Further, it is possible to provide a method for manufacturing a semiconductor device with low cost and improved productivity.

BRIEF DESCRIPTION OF THE DRAWINGS It is a block diagram of the semiconductor device of 1st Example of this invention, FIG. 1 (a) is a principal part top view, The same figure (b) is principal part sectional drawing cut | disconnected by the Z1-Z1 line | wire of the same figure (a). It is. It is a mask layout figure used for manufacture. It is a mask layout figure used for manufacture. It is principal part sectional drawing in a manufacturing process. It is principal part sectional drawing in a manufacturing process. It is principal part sectional drawing in a manufacturing process. It is principal part sectional drawing in a manufacturing process. It is principal part sectional drawing in a manufacturing process. It is principal part sectional drawing in a manufacturing process. It is principal part sectional drawing in a manufacturing process. It is a principal part top view of the semiconductor device of 3rd Example of this invention. FIG. 11A is a detailed view of a portion C in FIG. 11, in which FIG. 11A is a plan view of the main portion, and FIG. 11B is a cross-sectional view of the main portion cut along the Z4-Z4 line of FIG. It is principal part sectional drawing cut | disconnected by the Z3-Z3 line | wire of FIG. It is a mask layout figure used for manufacture. It is principal part sectional drawing in a manufacturing process. It is principal part sectional drawing in a manufacturing process. It is principal part sectional drawing in a manufacturing process. It is principal part sectional drawing in a manufacturing process. It is principal part sectional drawing of a manufacturing process. It is principal part sectional drawing of a manufacturing process. It is a top view which shows the conventional bidirectional trench lateral MOSFET and a secondary battery protection apparatus. It is principal part sectional drawing cut | disconnected by the X1-X1 line | wire of FIG. FIG. 21A is a detailed view of an example of a portion B in FIG. 21, in which FIG. 21A is a plan view of the main portion, and FIG. 21B is a cross-sectional view of the main portion cut along line X2-X2 in FIG. FIG. 21B is a detailed view of another example of the B part in FIG. 21, in which FIG. 21A is a plan view of the main part, and FIG. 21B is a cross-sectional view of the main part taken along line X3-X3 of FIG. FIG. 25A is a block diagram showing a circuit configuration of a conventional secondary battery protection device housed in a battery pack housing a secondary battery such as a lithium ion battery. FIG. 25B is a diagram showing the charge / discharge control operation of FIG. It is a figure which shows the current pathway in the charge / discharge control operation | movement of a secondary battery protection apparatus, and has shown the path | route of the electric current which flows into discharge FET91 and charge FET92. (A) of the figure shows the charging / discharging current path at the normal time, (b) shows the discharging current path at the time of overcharge protection, and (c) shows the charging current path at the time of overdischarge protection. FIG. 25 is a cross-sectional view of a main part in the manufacturing process, in which FIGS. (A) and (c) show a cross-sectional view of the main part taken along line X3-X3 in FIG. 24, and (b) in FIG. The principal part sectional drawing cut | disconnected by the line is shown. It is principal part sectional drawing cut | disconnected by the X1-X1 line | wire of FIG. It is principal part sectional drawing in a manufacturing process, and is principal part sectional drawing cut | disconnected by the X3-X3 line | wire of FIG. It is a figure which shows the mask shift | offset | difference corresponding to FIG.28 (b). (A) is principal part sectional drawing cut | disconnected by the Y1-Y1 line | wire of FIG. 21 when the 3rd trench 72 is cut | disconnected, (b) is Y2 of FIG. 21 when the 3rd trench 72 is cut | disconnected. FIG. 31C is a cross-sectional view of a main part cut at -Y2, and FIG. 31C is a mask layout diagram around the third trench 72 and the second polysilicon gate wiring 20. FIG.

  Embodiments will be described in the following examples. The same parts as those of the conventional structure are denoted by the same reference numerals.

  FIGS. 1 and 2 are configuration diagrams of a semiconductor device according to a first embodiment of the present invention. FIG. 1A is a plan view of a main part, and FIG. 1B is a Z1-Z1 line in FIG. The principal part sectional drawing cut | disconnected by is shown. FIG. 2 is a mask layout diagram used for manufacturing and corresponds to part A of FIG.

1 corresponds to FIG. 24, and is an enlarged view of a portion B in FIG. The first p ⁺ base pickup regions 41 and the first n ⁺ source regions 7 are alternately formed in the length direction of the first trench 3, and the second p ⁺ base pickup regions 51 are similarly formed in the length direction of the first trench 3. Second n ⁺ source regions 8 are alternately formed. In the configuration of the first embodiment, the difference from FIG. 24 is the arrangement position of the first p ⁺ base pickup region 41 and the second p ⁺ base pickup region 51, and the other points are the same as those in FIG. In FIG. 1, the length in the length direction of the first trench 3 of the second n ⁺ source region 8 between the second p ⁺ base pickup region 51 is the length of the first n ⁺ source region 7 between the first p ⁺ base pickup region 41. The first trench 3 is longer than the length in the length direction.

  The first trench 3 may be a simple closed loop having a mesh shape or a track shape as a planar shape of the trench. Moreover, it is good also as a stripe form which has not only a closed loop but a termination | terminus. Further, the arc portion 300 may be bent at a right angle.

2 and the mask layout diagram of FIG. 3 to be described later, a mask for forming the first trench 3, a mask for forming the first n ⁺ source region 7 and the second n ⁺ source region 8, and the first p ⁺ base pickup FIG. 5 is a diagram showing a mask for forming a region 41 and a second p ⁺ base pickup region 51. The opening 161 is a portion that becomes a mask opening for forming the contact hole 16. The opening 311 is a mask opening for forming the first trench 3. The opening 451 is a portion serving as a mask opening for forming the first p ⁺ base pickup region 41 and the second p ⁺ base pickup region 51. The opening 781 is a portion serving as a mask opening for forming the first n ⁺ source region 7 and the second n ⁺ source region 8.

This is because, in the case of the battery pack 98 as shown in FIG. 25, the first source terminal S1 is grounded and the second source terminal S2 is connected to a load (not shown) such as a charging circuit 97 or a mobile phone. The current and voltage applied to the second source terminal S2 are higher than the current and voltage applied to the first source terminal S1. In the case where a charging circuit is connected to the secondary battery protection device, when a charging voltage is applied from the charging circuit 97 to the second source terminal S2, the voltage of the n-well region 2 is also applied to the second source terminal S2. The voltage is close to the applied voltage. In this case, the first parasitic transistor having the n well region 2 as an emitter, the first p base region 4 as a base, and the first n ⁺ source region 7 as a collector is easily latched up.

Therefore, the discharge FET 91 requires a higher latch-up resistance than the charge FET 92.
In this way, in the bidirectional trench lateral MOSFET in which the required latch-up resistance of the two MOSFETs formed on the both side walls of the trench is not the same, a MOSFET having a low latch-up resistance and a MOSFET having a high latch-up resistance are formed. The on-resistance can be minimized while securing the required latch-up resistance.

As shown in FIGS. 1 and 2, the interval between the second p ⁺ base pickup regions 51 of the charge FET 92 is made wider than the interval between the first p ⁺ base pickup regions 41 of the discharge FET 91.
By widening the interval at which the second p ⁺ base pickup region 51 is arranged, the region of the second n ⁺ source region 8 is increased, and the on-resistance of the charge FET 92 is reduced.

  Therefore, the on-resistance of the bidirectional trench lateral MOSFET 90 when both the discharge FET 91 and the charge FET 92 are in the on state can be reduced.

FIG. 3 shows a mask layout used for manufacturing and corresponds to part A of FIG.
FIG. 3 differs from FIG. 2 of the first embodiment in that the mask opening width L2 for performing ion implantation for forming the first p ⁺ base pickup region 41 and the second p ⁺ base pickup region 51 is the mask opening width L1 in FIG. It is narrow compared to.

Hereinafter, the manufacturing method will be described mainly with reference to FIGS. 4 to 10 are cross-sectional views taken along the line Z1-Z1 or Z2-Z2 in FIG.
First, as shown in FIG. 22, impurities such as phosphorus are introduced on the surface of the p-type semiconductor substrate 1 by masking a region other than the bidirectional trench lateral MOSFET formation region with a resist (not shown), and the n-well region 2 by thermal diffusion. (FIG. 4A). Next, an impurity such as B (boron) is selectively introduced into the surface of the n-well region 2 to form a p region 225 that becomes the first p base region 4 and the second p base region 5 by thermal diffusion (FIG. 4B). )). Next, using the mask 211 made of a silicon oxide film as a mask, the surface of the n well region 2 is deeper than the first p base region 4 and the second p base region 5 from the surface of the n well region 2 by anisotropic dry etching or the like. A first trench 3 having a shallow depth is formed (FIG. 4C). Next, an isolation region for isolating the bidirectional trench lateral MOSFET from the charge / discharge control circuit 95 is formed. Specifically, the element formation region (bidirectional trench lateral MOSFET 90 and charge / discharge control circuit 95) is masked with a nitride film, and the LOCOS film 37 shown in FIG. 22 is formed by thermal oxidation. Next, after removing the nitride film, a silicon oxide film is formed as the gate insulating film 10 by thermal oxidation or CVD, and then polysilicon doped with impurities is deposited (FIG. 5A). Next, etching is performed by anisotropic etching to leave polysilicon on both side walls of the first trench 3 to form the first gate electrode 11 and the second gate electrode 12 (FIG. 5B).

  The first p base region 4 and the second p base region 5 may be formed after the first gate electrode 11 and the second gate electrode 12 are formed. Specifically, as shown in FIG. 6A, after the n-well region 2 is formed, the first trench 3 is formed, and further, the first gate electrode 11 and the second gate electrode 12 are formed. As in a), a resist mask 264 is formed so as to cover the bottom of the first trench 3, and boron is ion-implanted using the resist mask 264 as a mask. Thereafter, the resist mask 264 is removed and thermal diffusion is performed (FIG. 6B).

Next, the first n ⁺ source region 7 and the second n ⁺ source region 8 are formed. 7 is a cross-sectional view of the main part in the manufacturing process. FIGS. 7A and 7C are cross-sectional views of the main part taken along the line Z1-Z1 in FIG. 1, and FIG. The principal part sectional drawing cut | disconnected by the Z2-Z2 line is shown.

First, a resist is applied to the entire surface, a resist mask 261 is formed by patterning, and arsenic ions are implanted (FIGS. 7A and 7B). Next, the resist mask 261 is removed (FIG. 7C). At this time, ion implantation for forming the n ⁺ source / drain regions 35 and 36 may be performed simultaneously. The first n ⁺ source region 7 and the second n ⁺ source region 8 are activated by reflow described later.

  8 and 9 are cross-sectional views of the main part during the manufacturing process, and FIG. 8A is a cross-sectional view of the main part taken along the line Z1-Z1 in FIG. 1, and FIGS. FIG. 2 is a cross-sectional view of a main part taken along line Z2-Z2 in FIG. FIGS. 9A and 9B are cross-sectional views taken along the line Z2-Z2 in FIG.

After applying the resist, the resist is patterned using a mask for forming the first p ⁺ base pickup region 41 and the second p ⁺ base pickup region 51 to form a resist mask 63 (FIGS. 8A and 8B). . The width L3 of the resist mask 63 is wider than the width of the first trench 3, and the resist mask 63 is formed so as to cover the first p base region 4 and the second p base region 5. Thereafter, heat treatment is performed to activate the first p ⁺ base pickup region 41 and the second p ⁺ base pickup region 51 (FIG. 8C). In FIG. 8C, the first p ⁺ base pickup region 41 and the second p ⁺ base pickup region 51 are formed adjacent to the first trench 3 for lateral diffusion. However, as shown in FIG. 9, mask displacement occurs in the direction of arrow Y in the patterning process of the resist mask 63, and the first p ⁺ base pickup region 41 and the second p ⁺ base pickup region 51 are adjacent to the first trench 3. Of course, it does not matter if it is not formed. As shown in FIG. 9, a portion adjacent to one first trench 3 of the p base region 504 sandwiched between the first trenches 3 is covered with a resist mask 63 and a portion adjacent to the other first trench 3 is exposed. There is a case. However, the resist mask 63 is formed so as to cover a part of the surface adjacent to the first trench 3 of the first p base region 4.

FIG. 10 is a cross-sectional view of a main part in the manufacturing process, and shows a cross-sectional view of the main part taken along line Z1-Z1 in FIG.
After forming the first p ⁺ base pickup region 41 and the second p ⁺ base pickup region 51, an interlayer insulating film 200 is formed. The interlayer insulating film 200 is reflowed after depositing BPSG by the CVD method. By this reflow, the first n ⁺ source region 7, the second n ⁺ source region 8, the first p ⁺ base pickup region 41, and the second p ⁺ base pickup region 51 are activated (FIG. 10A). Then, contact holes are formed in the interlayer insulating film 200, and the plugs 13 that are in contact with the first n ⁺ source region 7 and the second n ⁺ source region 8, the first p ⁺ base pickup region 41 and the second p ⁺ base pickup region 51 are formed. (FIG. 10 (b)). Thereafter, by forming the first source electrode wiring 14 and the second source electrode wiring 15 connected to the plug 13, the bidirectional trench lateral MOSFET 90 shown in FIGS. 21, 22 and 1 is completed.

In the prior art, as described with reference to FIG. 30, the first n ⁺ source region 7, the second n ⁺ source region 8, the first p ⁺ base pickup region 41 and the second p ⁺ base pickup region 51 are adjacent to the first trench 3. When forming, productivity is not good. The first n ⁺ source region 7 and the second n ⁺ source region 8 must be formed adjacent to the first trench 3, while the first p ⁺ base pickup region 41 and the second p ⁺ base pickup region 51 are formed in the first trench. It is not necessary to form adjacent to 3. Therefore, in the process of forming the first p ⁺ base pickup region 41 and the second p ⁺ base pickup region 51, the margin H2 shown in FIG. 3 is further added to the margin H1 shown in FIG. 30 to increase the margin. Thereby, since high alignment accuracy and processing accuracy are not required, the first p ⁺ base pickup region 41 and the second p ⁺ base pickup region 51 can be formed with the same alignment accuracy and processing accuracy as other regions. As a result, the redoing of the inspection process and the patterning process can be omitted, and the productivity can be improved.

  11 is a plan view of an essential part of a semiconductor device according to a third embodiment of the present invention. FIG. 12 is a detailed view of a C part in FIG. 11, and FIG. 11 (a) is a plan view of the essential part, and FIG. FIG. 13 is a fragmentary sectional view taken along line Z4-Z4 in FIG. 11A, and FIG. 13 is a fragmentary sectional view cut along line Z3-Z3 in FIG. 11. This semiconductor device is a unidirectional trench lateral MOSFET. It is an example.

In FIG. 11, the n ⁺ source region 507, the n ⁺ drain region 508 and the p ⁺ base pickup region 541 shown in FIG. 12 are omitted. 12A and 13, the drain electrode wiring 515, the source electrode wiring 514, the polysilicon gate wiring 519, and the polysilicon wiring 520 described in FIG. 11 are omitted.

  A configuration of the unidirectional trench lateral MOSFET 500 will be described. The unidirectional trench lateral MOSFET 500 includes an n-well region 502 formed in the surface layer of the p-type semiconductor substrate 501, a closed-loop first trench 503 formed from the surface of the n-well region 502, and a first trench. And a closed-loop second trench 525 that is formed at the same time as 503 and surrounds the first trench 503. The first trench 503 includes a meandering portion having an arc portion 700 and a straight portion 710.

Further, a p base region 504 surrounded by the first trench 503 and the second trench 525 and formed in the surface layer of the n well region 502, and an n region formed in the surface layer of the n well region 502 and surrounded by the first trench 503. 505, an n ⁺ source region 507 formed in the surface layer of the p base region 504 and in contact with the sidewall of the first trench 503, and an n ⁺ drain region 508 formed in the surface layer of the n region 505 and in contact with the sidewall of the first trench 503. And a p ⁺ base pickup region 541 formed in the surface layer of the p base region 504 in contact with the n ⁺ source region 507. The p base region 504, the n region 505, the n ⁺ source region 507 and the n ⁺ drain region 508 are formed along the straight portion 710 of the first trench 503.

The gate electrode 511 is formed on the side of the first trench 503 on the p base region 504 side with the gate insulating film 510 interposed therebetween.
In addition, a field plate electrode 512 formed simultaneously with the gate electrode 511 is formed on the side of the first trench 503 on the n region 505 side through the gate insulating film 510. A polysilicon film 528 (formed at the same time as the gate electrode 511) formed on the side of the second trench 525 on the p base region 504 side through an insulating film 531 formed at the same time as the gate insulating film 510 on the side wall of the second trench 525, and an n well region 502 side And a polysilicon film 529 (formed simultaneously with the gate electrode 511).

In addition, a contact hole 516 opened in the interlayer insulating film 600, a source electrode wiring 514 contacting the n ⁺ source region 507 and the p ⁺ base pickup region 541 via a plug 513, a gate electrode 511 and a poly on the third trench 571 A polysilicon gate wiring 519 in contact with the silicon film 528, a polysilicon wiring 520 in contact with the field plate electrode 512 at a portion protruding from the arc portion of the first trench 503, and a gate metal in contact with the polysilicon gate wiring 519 through the contact hole 521 The wiring 517 has a drain electrode wiring 515 in contact with the polysilicon wiring 520 through the contact hole 521 and in contact with the n ⁺ drain region 508 through the plug 513. Note that the trench width of the first trench 503 protruding from the arc portion 700 may be narrower than the other width of the first trench 503. In this case, the trench width is formed so that the interlayer insulating film 600 is not formed between the gate electrodes 511. The third trench 571 may be cut like the third trench 72 shown in FIG.

  Further, it has a source terminal S connected to the source electrode wiring 514, a drain terminal D connected to the drain electrode wiring 515, and a gate terminal G connected to the gate metal wiring 517. Note that the polysilicon film 529 is in a floating potential state or connected to the n-well region 502.

A LOCOS film 537 is formed so as to surround the n-well region 502, and has a p ⁺ region 534 for drawing out a leakage current generated in the unidirectional trench lateral MOSFET 500.

Also in such a unidirectional trench lateral MOSFET 500, the manufacturing method described in the second embodiment can be applied.
FIG. 14 is a mask layout diagram used for manufacturing, and corresponds to part C of FIG.

The mask layout diagram of FIG. 14 is a mask for forming the first trench 503, a mask for forming the n ⁺ source region 507 and the n ⁺ drain region 508, and a mask for forming the p ⁺ base pickup region 541. It is the figure shown about. The opening of the mask for forming the first trench 503 is the opening 5311, and the opening of the mask for forming the n ⁺ source region 507 and the n ⁺ drain region 508 is the opening 5781 and the opening 5161, p ⁺ base. An opening of the mask for forming the pickup region 541 is an opening 5451.

  Next, a manufacturing method will be described. 15 to 17 are cross-sectional views showing the main part during the manufacturing process, FIG. 17B is a cross-sectional view taken along the line Z5-Z5 in FIG. 12, and the others are cut along the line Z4-Z4 in FIG. A cross section is shown.

  First, a mask such as a resist mask (not shown) is formed, impurities such as phosphorus are selectively introduced into the surface of the p-type semiconductor substrate 501, and an n-well region 502 is formed by thermal diffusion (FIG. 15A). Next, after forming the resist mask 65, an impurity such as boron (B) is selectively introduced into the surface of the n-well region 502 in order to form the p base region 504 (FIG. 15B). Next, after removing the resist mask 65 and forming the resist mask 66, impurities such as phosphorus are selectively introduced into the surface of the n-well region 502 in order to form the n-region 505 (FIG. 15C). Next, a first trench 503, a second trench 525, and a third trench 571 are simultaneously formed in the n-well region 2 from the surface of the n-well region 2 by dry etching or the like (FIG. 16A). Next, although not shown, an isolation region for isolating the unidirectional trench lateral MOSFET 500 from other regions is formed. Specifically, the element formation region (unidirectional trench lateral MOSFET 500) is masked with a nitride film (not shown), and a LOCOS film 537 is formed by thermal oxidation. Next, after removing the nitride film, a silicon oxide film is formed as a gate insulating film 510 by thermal oxidation or CVD (FIG. 16B). Next, polysilicon 5111 into which impurities are introduced is deposited (FIG. 16B). Next, the polysilicon 5111 is etched by anisotropic etching to leave the polysilicon 5111 on both side walls of the first trench 503, the second trench 525, and the third trench 571, and the gate electrode 511, the field plate electrode 512, the polysilicon A film 528 and a polysilicon film 529 are formed (FIG. 16C). Although the n region 505 is formed in FIG. 15C, the n region 505 is not formed in FIG. 15C, and a mask is formed so as to cover the first trench 503 and the p base region 504 after FIG. May be formed by ion implantation and thermal diffusion.

Next, an n ⁺ source region 507 and an n ⁺ drain region 508 are formed. First, a resist is applied on the entire surface, and a resist mask 67 is formed by patterning. The resist mask 67 covers the bottoms of the first trench 503, the second trench 525, and the third trench 571, and has an opening 5781 and an opening that open the surfaces adjacent to the first trench 503 in the p base region 504 and the n region 505. A portion 5161 is formed (FIG. 17A). This mask formation requires high alignment accuracy and processing accuracy. Then, arsenic ions are implanted into the mask opening. Thereafter, the resist mask is removed. The n ⁺ source region 507 and the n ⁺ drain region 508 are activated by reflow described later.

Next, a p ⁺ base pickup region 541 is formed.
18 is a cross-sectional view of the main part of the manufacturing process, FIG. 18 (a) is a cross-sectional view of the main part taken along the line Z4-Z4 of FIG. 12, and FIG. 18 (b) and FIG. It is principal part sectional drawing cut | disconnected by the Z5-Z5 line.

A resist is applied to the entire surface, a resist mask 68 having an opening 5451 is formed by patterning, and BF ₂ is ion-implanted using the resist mask 68 as a mask (FIGS. 18A and 18B). Since this resist mask 68 has an opening 5451, the mask shift margin is obtained by adding H1 (the width of the gate insulating film and the gate electrode) shown in FIG. 30 and the margin H3 shown in FIG. Become. As shown in FIG. 19, even if mask displacement occurs, it is possible to suppress the bottom of the first trench 503 from being exposed. In this embodiment, as shown in FIG. 19, the p base region 504 and the n region 505 have a cross-sectional shape sandwiched between a plurality of first trenches 503. In such a case, a portion adjacent to one first trench 503 of the p base region 504 sandwiched between the first trenches 503 may be covered with the resist mask 68 and a portion adjacent to the other first trench 503 may be exposed. is there. However, the resist mask 68 is formed so as to cover a part of the surface adjacent to the first trench 503 of the p base region 504. The resist mask 68 is removed. The p ⁺ base pickup region 541 is diffused by activation described later. Thereafter, BPSG is deposited and reflowed to form an interlayer insulating film 600. During this reflow, n ⁺ source region 507, n ⁺ drain region 508 and p ⁺ base pickup region 541 are activated. The p ⁺ base pickup region 541 is formed adjacent to the first trench 503 (FIG. 20A). Then, a contact hole 516 is formed in the interlayer insulating film 600, and a plug 513 in contact with the n ⁺ source region 507, the n ⁺ drain region 508, and the p ⁺ base pickup region 541 is formed (FIG. 20B). Thereafter, the source electrode wiring 514 and the drain electrode wiring 515 connected to the plug 513 are formed (FIG. 20C), whereby the unidirectional trench lateral MOSFET 500 is completed.

By such a manufacturing method, formation of the p ⁺ base pickup region 541 does not require high alignment accuracy and processing accuracy, and therefore can be formed with alignment accuracy and processing accuracy equivalent to other regions. As a result, the redoing of the inspection process and the patterning process can be omitted, and the productivity can be improved.

  In this embodiment, the second trench 525 may be formed as necessary and may not be formed. Further, although the field plate electrode 512 has been described, the field plate electrode 512 may be removed. Specifically, after the gate electrode 511 and the field plate electrode 512 are formed, the gate electrode 511 may be masked and the field plate electrode 512 may be removed by etching. When the field plate electrode 512 is removed, the n region 505 for reducing the on-resistance by the field plate electrode 512 is not necessary, and thus the n region 505 may not be formed.

  Further, the p base region 504 may be formed after the gate electrode 511 is formed as in the second embodiment.

1, 501 p-type semiconductor substrate 2, 502 n-well region 3, 503 first trench 4 first p base region 5 second p base region 7 first n ⁺ source region 8 second n ⁺ source region 10, 510 gate insulating film 11 first Gate electrode 12 Second gate electrode 13, 513 Plug 14 First source electrode wiring 15 Second source electrode wiring 16 Contact hole 17 First gate metal wiring 18 Second gate metal wiring 19 First polysilicon gate wiring 20 Second polysilicon Gate wiring 21 Contact hole 25, 525 Second trench 27, 531 Insulating film 28, 29, 528, 529 Polysilicon film 31 N well region 32, 33 p ⁺ source / drain region 34 p ⁺ region 35, 36 n ⁺ source / drain region 37, 537 LOCOS film 38, 39 Gate electrode 41 First p ⁺ base pickup region 51 Second p ⁺ base pickup region 61, 62, 63, 65, 66, 67, 68 Resist mask 71 Fourth trench 72, 571 Third trench 90 Bidirectional trench lateral MOSFET
91 Discharge FET
92 Charge FET
93, 94 Parasitic diode 95 Charge / discharge control circuit 96 Secondary battery 97 Charging circuit 98 Battery pack 99 Battery charger 200, 600 Interlayer insulating film 261, 264 Resist mask 300, 700 Arc portion 310, 710 Linear portion 333 PMOS
334 NMOS
500 Unidirectional trench lateral MOSFET
504 p base region 505 n region 507 n ⁺ source region 508 n ⁺ drain region 511 gate electrode 512 field plate electrode 514 source electrode wiring 515 drain electrode wiring 516 contact hole 517 gate metal wiring 519 polysilicon gate wiring 520 polysilicon wiring 521 contact Hole 534 p ⁺ region 541 p ⁺ base pickup region 161, 311, 451, 781 opening 5161, 5311, 5451, 5781 opening H1, H2, H3 margin L1, L2 mask opening width L3 width

Claims (7)

A second conductivity type well region located in the surface layer of the first conductivity type semiconductor substrate;
A trench located in the well region;
A first base region and a second base region of a first conductivity type located on a surface layer of the well region and separated from each other by the trench and in contact with the trench;
A first source region of a second conductivity type located in a surface layer of the first base region and in contact with the trench;
A second source region of a second conductivity type located in a surface layer of the first base region and in contact with the trench;
A first pickup region of a first conductivity type located in a surface layer of the first base region;
A second pickup region of a first conductivity type located in a surface layer of the second base region;
A first gate electrode located on the first base region between the well region and the first source region on the sidewall of the trench via a gate insulating film;
A second gate electrode located on the second base region between the well region and the second source region on the sidewall of the trench via a gate insulating film;
A first main electrode in electrical contact with the first source region and the first pickup region;
A semiconductor device comprising: a second main electrode in electrical contact with the second source region and the second pickup region;
The first source regions and the first pickup regions are alternately arranged in the length direction of the trench, the second source regions and the second pickup regions are alternately arranged in the length direction of the trench,
The first main electrode is connected to a low potential side of a secondary battery, and the second main electrode is a secondary battery protection device connected to a charging circuit or a load for charging the secondary battery,
The length of the first source region between the first pickup regions in the length direction of the trench is shorter than the length of the second source region between the two pickup regions in the length direction of the trench. Secondary battery protection device. A second conductivity type well region selectively formed in the surface layer of the first conductivity type semiconductor substrate;
  A trench located in the well region;
  A first base region and a second base region of a first conductivity type located on a surface layer of the well region and separated from each other by the trench and in contact with the trench;
  A first source region of a second conductivity type located in a surface layer of the first base region and in contact with the trench;
  A second source region of a second conductivity type located in a surface layer of the second base region and in contact with the trench;
  A first pickup region of a first conductivity type located in a surface layer of the first base region;
  A second pickup region of a first conductivity type located in a surface layer of the second base region;
  A first gate electrode located on the first base region between the well region and the first source region on the sidewall of the trench via a gate insulating film;
  A second gate electrode located on the second base region between the well region and the second source region on the sidewall of the trench via the gate insulating film;
  A first main electrode in electrical contact with the first source region and the first pickup region;
  A second main electrode in electrical contact with the second source region and the second pickup region;
With
  A semiconductor device in which the first source region and the first pickup region are alternately arranged in the length direction of the trench, and the second source region and the second pickup region are alternately arranged in the length direction of the trench. In the manufacturing method of
  After forming the well region, the first base region, the second base region, the trench, the gate insulating film, the first gate electrode, and the second gate electrode,
  Forming a first resist mask that covers the bottom of the trench between the first gate electrode and the second gate electrode and has an opening that reaches the first base region and the second base region adjacent to the trench; When,
  Performing ion implantation of impurities for forming the first source region and the second source region using the first resist mask;
  Covering the trench bottom between the first gate electrode and the second gate electrode and a part of the first base region and the second base region adjacent to the trench, the first base region and the second base region Forming a second resist mask having an opening that reaches
  Performing ion implantation of impurities for forming the first pickup region and the second pickup region using the second resist mask;
  Forming a first main electrode in electrical contact with the first source region and the first pickup region;
  Forming a second main electrode in electrical contact with the second source region and the second pickup region. A method for manufacturing a semiconductor device, comprising:   Selectively forming the well region in the semiconductor substrate;
  Forming a first conductivity type region to be the first base region and the second base region in the well region;
  Forming the trench in the well region at a depth deeper than the first conductivity type region so as to separate the first conductivity type region into the first base region and the second base region;
  Forming a gate insulating film on the inner surface of the trench;
  The method for manufacturing a semiconductor device according to claim 2, further comprising: forming the first gate electrode and the second gate electrode on both side walls of the trench.   Selectively forming the well region in the semiconductor substrate;
  Forming the trench in the well region;
  Forming a gate insulating film on the inner surface of the trench;
  Forming the first gate electrode and the second gate electrode on both side walls of the trench;
  Forming a third resist mask that covers the bottom of the trench between the first gate electrode and the second gate electrode, and has an opening reaching the portion of the first base region and the second base region adjacent to the trench. When,
  3. The step of ion-implanting impurities for forming the first base region and the second base region in the well region using the third resist mask is provided. The manufacturing method of the semiconductor device of description. A second conductivity type well region selectively formed in the surface layer of the first conductivity type semiconductor substrate;
  A trench located in the well region;
  A base region of a first conductivity type located in a surface layer of the well region and in contact with one side wall of the trench;
  A source region of a second conductivity type located in a surface layer of the base region and in contact with the trench;
  A base pickup region of a first conductivity type located in a surface layer of the base region;
  A second conductivity type located on the surface layer of the well region and in contact with the other side wall of the trench;
A drain region;
  A gate electrode located on the base region between the well region and the source region on one side wall of the trench via a gate insulating film;
  A first main electrode in electrical contact with the source region and the base pickup region;
  A second main electrode in electrical contact with the drain region,
  In the method of manufacturing a semiconductor device in which the source region and the pickup region are alternately arranged in the length direction of the trench,
  After forming the well region, the base region, the trench, the gate insulating film and the gate electrode,
  Forming a first resist mask that covers the bottom of the trench and has an opening reaching a portion of the base region adjacent to the trench;
  Performing impurity ion implantation for forming the source region and the drain region using the first resist mask;
  Forming a second resist mask that covers a portion of the trench bottom and the base region adjacent to one side wall of the trench and has an opening reaching the base region;
  Performing impurity ion implantation for forming the base pickup region using the second resist mask;
  Forming a first main electrode in electrical contact with the source region and the base pickup region;
  Forming a second main electrode that is in electrical contact with the drain region. Selectively forming the well region in the semiconductor substrate;
  Forming the base region in the well region;
  Forming a trench in the well region at a depth deeper than the base region;
  Forming a gate insulating film on the inner surface of the trench;
  The method of manufacturing a semiconductor device according to claim 5, further comprising: forming the gate electrode on one side wall of the trench.   Selectively forming the well region in the semiconductor substrate;
  Forming the trench in the well region;
  Forming a gate insulating film on the inner surface of the trench;
  Forming the gate electrode on one side wall of the trench;
  Forming a third resist mask covering the surface adjacent to the trench bottom and the other sidewall of the trench and having an opening reaching a location adjacent to the sidewall of the trench;
  6. A method of manufacturing a semiconductor device according to claim 5, further comprising the step of ion-implanting impurities for forming the base region in the well region using the third resist mask.