JP5554293B2 - Semiconductor device and manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

  As a conventional technique, there is a semiconductor device having an alignment mark (see, for example, Patent Document 1).

This semiconductor device includes an arbitrary circuit formed on a semiconductor substrate, an oxide film such as SiO ₂ formed as a protective film on the circuit, and a high reflectance pattern by an aluminum layer formed on the oxide film. The alignment mark is formed in a substantially cross shape in the X direction and the Y direction with the high reflectance pattern and the low reflectance pattern with the underlying oxide film layer exposed.

  According to this semiconductor device, since the high reflection pattern and the low reflection pattern having different reflectivities are used for the alignment mark, the contrast is improved as compared with the case where the alignment mark is formed only by the high reflection pattern, and the alignment is ensured. can do.

Japanese Patent Laid-Open No. 7-221166

  However, in the semiconductor device disclosed in Patent Document 1, since the irradiated light reaches the substrate by using the oxide film layer as the low reflectance pattern, the reflectance of the low reflectance pattern also depends on the reflectance of the substrate. In the case where there is a variation in the reflectance of the substrate on the wafer, a high-reflectance pattern and a low-reflectance pattern with insufficient contrast may be manufactured, and discrimination may not be ensured.

  Accordingly, it is an object of the present invention to provide a semiconductor device and a method for manufacturing the semiconductor device that can ensure the identification of the alignment mark without depending on the reflectance of the substrate.

One embodiment of the present invention includes a semiconductor substrate, a circuit portion formed including at least a first layer and a second layer on the semiconductor substrate, and the first portion of the circuit portion formed on the semiconductor substrate. a low-reflection pattern formed as a layer in the layer and the step is formed in the low reflective pattern, possess a high reflection pattern formed as a layer in the second layer in the same step of the circuit portion, Provided is a semiconductor device in which an alignment mark is formed on the semiconductor substrate by the low reflection pattern and the high reflection pattern .

  The first layer of the semiconductor device may be a magnetoresistive film, and the second layer may be an electrode electrically connected to the magnetoresistive film.

According to one embodiment of the present invention, a step of forming a first layer including a circuit portion pattern and a low-reflection pattern over a semiconductor substrate, and a step of forming the circuit portion pattern and the height over the first layer are performed. There is provided a method for manufacturing a semiconductor device , comprising: a step of forming a second layer including a reflection pattern; and a step of forming an alignment mark on the semiconductor substrate by the low reflection pattern and the high reflection pattern .

  According to the present invention, it is possible to ensure the identification of the alignment mark without depending on the reflectance of the substrate.

FIG. 1A is a schematic plan view illustrating an example of the configuration of the semiconductor device according to the embodiment. FIG. 1B is a schematic cross-sectional view illustrating an example of the configuration of the semiconductor device according to the embodiment. FIG. 2 is a schematic plan view showing an example of the configuration of the semiconductor device according to the embodiment of the present invention. 3A is an enlarged cross-sectional view of the vicinity of the alignment mark of the semiconductor device according to the present embodiment, and FIG. 3B is an enlarged cross-sectional view of the vicinity of the alignment mark of a conventionally used semiconductor device. It is. 4A and 4B are graphs showing the reflection intensity when the entire alignment mark of the semiconductor device according to the present embodiment and the conventional semiconductor device is scanned (measurement L). FIGS. 5A and 5B are graphs showing the reflection intensity when the aluminum pattern of the semiconductor device according to the present embodiment and the conventional semiconductor device is scanned (measurement M). 6 (a) and 6 (b) are graphs showing the reflection intensity when scanning a portion other than the aluminum pattern of the semiconductor device according to the present embodiment and the conventional semiconductor device (measurement N). 7A to 7E are cross-sectional views illustrating an example of the manufacturing process of the semiconductor device according to the present embodiment.

(Configuration of semiconductor device)
FIG. 1A is a schematic plan view illustrating an example of the configuration of the semiconductor device according to the embodiment. FIG. 1B is a schematic cross-sectional view illustrating an example of the configuration of the semiconductor device according to the embodiment.

  The semiconductor device 1 includes an alignment mark 2 for alignment, which is manufactured by a semiconductor process, and a circuit unit 3 including a magnetoresistive element 3A and a bipolar transistor 3B.

  The alignment mark 2 includes an oxide film 23 formed on the silicon substrate 24, a NiCo pattern 22 as a low reflection pattern formed on the oxide film 23, a nitride film 21 formed on the NiCo pattern 22, and a nitride film And an aluminum pattern 20 as a highly reflective pattern formed on the film 21.

  The magnetoresistive element 3A includes an oxide film 23 formed on the silicon substrate 24, a NiCo pattern 31 as a magnetoresistive film formed on the oxide film 23, a nitride film 21 formed on the NiCo pattern 31, The nitride film 21 is provided with an opening and an aluminum electrode 30 formed on the NiCo pattern 31.

  The bipolar transistor 3B includes a collector 35, an emitter 36 and a base 37 formed on the silicon substrate 24, an oxide film 23 formed on the silicon substrate 24, a nitride film 21 formed on the oxide film 23, and an oxide film. 23 and the nitride film 21 are provided with an aluminum electrode 32 formed on the collector 35, an aluminum electrode 33 formed on the emitter 36, and an aluminum electrode 34 formed on the base 37.

  FIG. 2 is a schematic plan view showing an example of the configuration of the semiconductor device according to the embodiment of the present invention.

  A plurality of semiconductor devices 1 are manufactured on a silicon wafer 10 having a diameter of 4 inches. Here, since the roughness of the back surface of the silicon wafer 10 is not uniform in each region, the reflectance of the silicon wafer 10 itself is different in each region due to the roughness of the back surface before the alignment mark 2 is produced. It becomes.

As an example, when the area of the silicon wafer 10 is divided into “CENTER”, “LEFT”, “RIGHT”, “TOP”, and “BOTTOM”, the semiconductor device 1 in each area as shown in FIG. The reflectance of _Center , 1 _Left , 1 _Right , 1 _Top , and 1 _Bottom varies.

(Measurement of reflectance)
In order to measure the reflectance of the alignment mark, two examples shown in FIGS. 3A and 3B were compared.

  3A is an enlarged cross-sectional view of the vicinity of the alignment mark of the semiconductor device according to the present embodiment, and FIG. 3B is an enlarged cross-sectional view of the vicinity of the alignment mark of a conventionally used semiconductor device. It is.

  As shown in FIG. 3A, the measurement L is the case where the entire alignment mark 2 is scanned from above the semiconductor device 1, the measurement M is the case where the aluminum pattern 20 is scanned, and the measurement N is the case where the NiCo pattern 22 is scanned. To do. Each measurement is performed by irradiating a laser beam having a wavelength of 1300 nm, measuring the intensity of the reflected light, and calculating the reflectance from the intensity ratio of the irradiated light and the reflected light.

  Further, as shown in FIG. 3B, when the entire conventional alignment mark 4 is scanned, the measurement L, when the aluminum pattern 20 is scanned, the measurement M, and when the low reflection pattern other than the aluminum pattern 20 is scanned. Let it be measurement N.

  4A and 4B are graphs showing the reflection intensity when the entire alignment mark of the semiconductor device according to the present embodiment and the conventional semiconductor device is scanned (measurement L). 5A and 5B are graphs showing the reflection intensity when the aluminum pattern of the semiconductor device according to the present embodiment and the conventional semiconductor device is scanned (measurement M). 6 (a) and 6 (b) are graphs showing the reflection intensity when scanning a region other than the aluminum pattern of the semiconductor device according to the present embodiment and the conventional semiconductor device (measurement N).

In any of the semiconductor devices 1 _Center , 1 _Left , 1 _Right , 1 _Top , and _Bottom in each region of the silicon wafer 10, there is little variation in the reflectance of the aluminum pattern 20 as shown in FIG. Further, as shown in FIG. 6A, the variation in the reflectance of the NiCo pattern 22 is small. Further, as shown in FIG. 4A, the difference between the reflectance of the aluminum pattern 20 and the reflectance of the NiCo pattern 22 is about 25%.

On the other hand, in the conventional semiconductor devices 1 _Center , 1 _Left , 1 _Right , 1 _Top , and 1 _Bottom in each region of the silicon wafer 10, the reflectivity of the aluminum pattern 20 varies somewhat as shown in FIG. The reflectance is inferior compared to the case of FIG. Further, as shown in FIG. 6B, the reflectance of the region other than the aluminum pattern 20 varies, and there is a difference of about 10% at the maximum. Further, as shown in FIG. 4B, the difference between the reflectance of the aluminum pattern 20 and the reflectance of the region other than the aluminum pattern 20 is about 10% at the maximum and several% at the minimum. The contrast is lower than that of the semiconductor device 1.

(Manufacturing process)
7A to 7E are cross-sectional views showing an example of the manufacturing process of the semiconductor device according to the present embodiment.

  First, as shown in FIG. 7A, the collector 35, the emitter 36, and the base 37 of the bipolar transistor 3B are formed on the silicon substrate 24.

Next, as shown in FIG. 7B, an oxide film 23 such as SiO _{2 is formed} on the silicon substrate 24 by a plasma CVD method or a thermal oxidation method. Note that an opening is provided in the oxide film 23 by appropriately forming a mask, etching, or the like.

  Next, as shown in FIG. 7C, a NiCo pattern 22 and a NiCo pattern 31 are simultaneously formed on the oxide film 23 by plasma CVD or sputtering.

Next, as shown in FIG. 7D, a nitride film 21 is formed on the NiCo patterns 22 and 31 and the oxide film 23 by plasma CVD using SiN _x or the like.

  Next, as shown in FIG. 7E, an aluminum pattern 20 and aluminum electrodes 30, 32, and 33 are simultaneously formed by sputtering or the like.

(Effect of embodiment)
According to the above-described embodiment, since the NiCo pattern 22 is used for the low reflection pattern of the alignment mark 2, the reflectance of the low reflection pattern is not affected by the roughness of the back surface of the silicon substrate 24, and any region of the silicon wafer 10 is used. Even if the semiconductor device 1 is manufactured from the above, the variation in the reflectance of the low reflection pattern is reduced. Thereby, the dispersion | variation in the difference of the reflectance of the aluminum pattern 20 which is a high reflection pattern, and the NiCo pattern 22 which is a low reflection pattern also decreases, and the identification property of the alignment mark 2 can be ensured.

  Further, since the NiCo pattern 22 is simultaneously formed in the manufacturing process of the NiCo pattern 31 of the magnetoresistive element 3A, and the aluminum pattern 20 is simultaneously manufactured in the manufacturing process of the aluminum electrodes 30, 32, 33, and 34, the semiconductor device 1 The manufacturing process is not increased.

  The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from or adjusting the technical idea of the present invention. For example, the material of the low-reflection pattern and the high-reflection pattern is not limited to NiCo and Al, and other materials may be used as long as the difference in reflectance between the low-reflection pattern and the high-reflection pattern is within the identification ability of the apparatus or user that identifies the alignment mark. Materials can be used.

DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Alignment mark 3 Circuit part 3A Magnetoresistive element 3B Bipolar transistor 4 Alignment mark 10 Silicon wafer 20 Aluminum pattern 21 Nitride film 22 NiCo pattern 23 Oxide film 24 Silicon substrates 30, 32, 33, 34 Aluminum electrode 31 NiCo pattern 35 Collector 36 Emitter 37 Base

Claims (3)

A semiconductor substrate;
A circuit unit formed on the semiconductor substrate including at least a first layer and a second layer;
A low reflection pattern formed as a layer in the same step as the first layer of the circuit portion on the semiconductor substrate;
Wherein formed on the low-reflection pattern, it possesses a high reflection pattern formed as a layer in the second layer in the same step of the circuit portion,
A semiconductor device in which an alignment mark is formed on the semiconductor substrate by the low reflection pattern and the high reflection pattern . The first layer is a magnetoresistive film;
The semiconductor device according to claim 1, wherein the second layer is an electrode electrically connected to the magnetoresistive film. Forming a first layer including a circuit portion pattern and a low reflection pattern on a semiconductor substrate;
Forming a second layer comprising a pattern and a highly reflective pattern for the circuit portion on said first layer,
Forming an alignment mark on the semiconductor substrate by the low reflection pattern and the high reflection pattern .

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