JP5510639B2 - AD converter - Google Patents

Description

  The present invention relates to an AD converter that converts an analog signal into a digital signal.

  A basic configuration of a flash AD converter having a resolution of 3 bits is shown in FIG. The flash-type AD converter includes a comparator unit 102 including a plurality of comparators, a divided resistor array 101 including a plurality of divided resistors for generating a plurality of reference potentials used for signal comparison, and a temperature based on a plurality of comparison results of the comparator unit 102. It comprises a logic unit 103 composed of a plurality of logic gates for generating a total code, and an encoder unit 105 for converting the plurality of outputs into binary data. The reference potential Vref is divided into a minimum step voltage by resistance division and connected to each comparator as a reference signal. Each comparator compares the input signal Vin with a reference signal having a different weight, and outputs a comparison result in synchronization with the clock Clock. When the input signal Vin is gradually changed from −Vref / 2 to + Vref / 2, the output is inverted in order from the comparator below the comparator unit 102 in FIG. In the following description, the AD converter is composed of two AD conversion elements, and the AD conversion element in such a case may be referred to as ADC in order to distinguish it from the entire AD converter.

  A characteristic A in FIG. 2 shows a relationship (input / output characteristics) between an input value and a converted output in the case of a 7-bit ideal AD converter. In the ideal AD converter, the output changes stepwise at equal intervals corresponding to each reference signal.

  However, the relationship between the input / output characteristics of the actual AD converter does not match the ideal AD converter as shown by the characteristic B in FIG. The major reason why the input / output characteristics of the actual AD converter greatly differ from the input / output characteristics of the ideal AD converter is that there is an offset in the judgment threshold value of the comparator in the comparator unit 102, which is different for each comparator. I know. For example, the comparison part of comparators used in high-speed AD converters is often composed of differential input transistor pairs, but there are always variations in the thresholds of transistor pairs, and these variations are comparators. Will appear as an offset.

  Conversely, the offset of the comparator is adjusted by some method to reduce the amount of offset, and the difference in offset between the plurality of comparators is reduced to approximate the input / output characteristics of the ideal AD converter, thereby improving the performance as an AD converter. It is considered possible.

  Several methods for adjusting the offset of the comparator have been proposed, but the calibration AD converter of Non-Patent Document 1 is composed of two ADCs, and the signals simultaneously sampled by these two ADCs are the same value. On the premise of this, a method of automatically adjusting the offset of the comparator circuit in each ADC is adopted. The configuration is shown in FIG. Hereinafter, this method is referred to as a 2 ADC mutual offset calibration AD converter.

  As shown in FIG. 4, assuming that two ADC1 and ADC2 acquire data with master clocks Master CLK1 and Master2 having the same timing, ADC1 and ADC2 are the same if they are made of comparators having exactly the same offset characteristics. A signal is output. Actually, since there is an offset, it becomes a different value in the initial state, but by adjusting the offset amount of each comparator from the difference of the comparison circuit 301 that outputs the difference between the two outputs, the converted output has the same waveform, Furthermore, by incorporating signal processing, it is possible to approximate the input / output characteristics of an ideal AD converter (Non-Patent Document 1). As a result, the characteristics of the AD converter can be improved.

2009 Symposium on VLSI Circuit Digest of Technical Papers, p. 266

  However, according to the method of Non-Patent Document 1, after the offset adjustment is completed, one of the two ADCs 1 and ADC 2 having the same characteristics becomes unnecessary and is wasted. For example, in a radio system, there are many cases where it is necessary to sample two systems of signals such as an I channel signal and a Q channel signal at the same time. However, when this AD converter is used, four ADCs are required. In this operation, two ADCs are unnecessary. Although the current consumption can be suppressed by electrically stopping the ADC on one side, the area is wasted when the IC is made into an IC.

  Accordingly, an object of the present invention is to enable two ADCs (AD conversion elements) constituting an AD converter to be effectively used even after the offset adjustment is completed.

  According to the first aspect of the present invention, two AD conversion elements operating with the same clock signal are included, and the same input signal is input to the AD conversion element when the AD conversion element is calibrated. An AD converter comprising switching means on the input side of the two AD conversion elements, wherein the switching means inputs the same input signal to the two AD conversion elements when performing calibration, while the calibration An AD converter is provided, characterized in that after completion, two different input signals are input to the respective AD conversion elements.

  In the above AD converter, the switching means inputs one of the two different input signals to the two AD conversion elements as the same input signal when the calibration is executed. In this case, the switching unit includes a switch connected to an input side of one of the two AD conversion elements, and the switch receives an input signal to the other AD conversion element when the calibration is performed. When input is made to the one AD conversion element and the calibration is completed, an input signal to the one AD conversion element is inputted to the one AD conversion element.

  In the AD converter, a calibration signal independent of the two different input signals may be used when the calibration is performed. In this case, the switching means includes two switches connected to the respective input sides of the two AD conversion elements, and these two switches respectively correspond to the independent calibration signals corresponding to the AD signals when the calibration is performed. When input to the conversion element and the calibration is completed, an input signal to each AD conversion element is input to the corresponding AD conversion element.

  In the above-described AD converter, the missing sampling data generated at the time of executing the calibration may be interpolated using the sampling data before and after switching by the switching means.

  According to a second aspect of the present invention, there is provided an AD converter that includes two AD conversion elements and inputs the same input signal to the AD conversion element when the AD conversion element is calibrated. The phase of the operation clock of the two AD conversion elements is 180 degrees different, and a track and hold switch is connected to the input side of the two AD conversion elements, and the AD conversion element is used when the track and hold switch performs calibration. When the track and hold switch is in the hold state, the two AD elements are calibrated, and the track and hold switch is in the track state. In addition, the two AD conversion elements operate in a time interval. AD converter is provided that.

  According to the present invention, two AD conversion elements built in a mutual offset calibration type AD converter using two AD conversion elements can always be used, and an area for mounting an integrated circuit is not wasted.

It is the figure which showed the basic circuit structure of the flash type AD converter of 3 bit resolution. It is a characteristic diagram for comparing and explaining the ideal input / output characteristic (A) of the 7-bit AD converter and the input / output characteristic (B) of the actual AD converter. It is the figure which showed the basic composition of the conventional mutual offset calibration AD converter by two ADCs. It is a figure for demonstrating operation | movement of each ADC of the conventional mutual offset calibration AD converter by two ADCs. It is the figure which showed the basic composition of the mutual offset calibration AD converter by the 1st Example of this invention. It is the figure which showed some examples of the switch used for the AD converter by this invention. FIG. 6 is a signal waveform diagram for explaining the operation of the AD converter shown in FIG. 5. It is another signal waveform diagram for demonstrating operation | movement of the AD converter shown by FIG. It is the figure which showed the basic composition of the mutual offset calibration AD converter by the 2nd Example of this invention. It is the figure which showed the example of the waveform of the calibration signal source used for the 2nd Example of this invention. It is the figure which showed the basic composition of the conventional time interval type AD converter. It is a signal waveform diagram for demonstrating operation | movement of the time interval type AD converter shown by FIG. It is a signal waveform diagram for demonstrating operation | movement of the past mutual offset calibration time interval type | mold AD converter which implement | achieved calibration by changing the phase of the master clock of two ADCs. It is the figure which showed the basic composition of the mutual offset calibration time interval type AD converter by the 3rd Example of this invention. It is the figure which showed the circuit structural example of the switch used for the 3rd Example of this invention. It is a signal waveform diagram for demonstrating a normal operation state by operation | movement of the mutual offset calibration time interval type AD converter by the 3rd Example of this invention. It is a signal waveform diagram for demonstrating the production | generation method of the control signal required for operation | movement of the mutual offset calibration time interval type AD converter by the 3rd Example of this invention. It is a signal waveform diagram for demonstrating the operation state when acquiring offset adjustment data by operation | movement of the mutual offset calibration time interval type AD converter by the 3rd Example of this invention. It is a signal waveform diagram for demonstrating the general operation state of the mutual offset calibration time interval type AD converter by the 3rd Example of this invention. It is a figure for demonstrating the example in the case of applying the mutual offset calibration time interval type AD converter by the 3rd Example of this invention to a burst signal.

  FIG. 5 shows a first embodiment of a mutual offset calibration AD converter according to the present invention, and shows an application example to two systems (I channel and Q channel) often used in a radio system.

  In FIG. 5, this mutual offset calibration AD converter uses, as described in Non-Patent Document 1, sampling data of two ADCs (AD conversion elements) 1 and 2 for the same input signal, using a comparison preparation circuit 502. And has a function of adjusting the offset of each ADC so that the same output is obtained. The input of the ADC 1 is connected to an I channel signal (input I). The input of the ADC 2 is a Q channel signal (input Q) and an I channel signal connected via a switch (switching means) 501, and either a Q channel signal or an I channel signal is determined by a calibration data acquisition CLK signal (clock signal). Is entered.

  When the switch 501 distributes the I channel signal to the ADC 2 by the calibration data acquisition CLK signal, the same I channel signal is input to the ADC 1 and ADC 2. At this time, calibration data for offset adjustment is acquired. Calibration Data Acquisition CLK is supplied to ADC1 and ADC2, and is output as a discrimination signal, that is, a converted output in synchronization with offset adjustment data. The comparison adjustment circuit 502 determines whether the input is data for offset adjustment. If the data is for offset adjustment, an offset adjustment signal is output to an offset adjustment circuit (not shown) in the ADCs 1 and 2, thereby reducing the offset. Adjusted.

  As shown in FIG. 6 (a), the switch 501 is composed of two n-channel MOSFETs (hereinafter abbreviated as nMOSFETs). When the calibration data acquisition clock signal is at a high level, the n-channel MOSFET on the I-channel side The n-channel MOSFET on the Q-channel side is cut off and the I-channel signal is connected to the ADC.

  FIGS. 6B and 6C show another example in which the same switch function is realized using a p-channel MOSFET (hereinafter abbreviated as pMOSFET).

  FIG. 7 shows the timing relationship between the I channel and Q channel input signals, the Master CLK signal, and the Calibration Data Acquisition CLK signal in order to explain the operation in detail.

  FIG. 7A shows the operation state of normal AD conversion. Since Calibration Data Acquisition CLK is always at a low level, different signals are input to the I channel and Q channel, and ADC 1 and ADC 2 continue to acquire data at the same timing in synchronization with Master CLK.

  On the other hand, FIG. 7B shows a case where the calibration data acquisition CLK is at a high level during the first three clocks (Master CLK), and an I channel signal is input to the ADC 2 during the first three clocks. Therefore, the same signal as ADC1 is converted. The conversion data during the period when the calibration data acquisition CLK is at a high level is used as data for adjusting the offset amount of the ADC. Further, after the fourth clock from the beginning, ADC1 and ADC2 perform normal operations for sampling the I channel and Q channel, respectively.

  FIG. 8 shows an operation when a signal obtained by dividing the master CLK by 1/2 is used as the calibration data acquisition CLK. In this case, data for offset adjustment is acquired for every two clocks of Master CLK. If the data acquired for offset adjustment is removed from the ADC1 and ADC2 conversion outputs, the sampling frequency will be half that of Master CLK. Apparently, real-time offset adjustment can be performed by AD conversion simultaneously with offset adjustment. .

  In the first embodiment described above, the ½ frequency division signal of the Master CLK is the calibration data acquisition CLK. However, for example, the calibration data acquisition CLK that is high for only one clock with respect to 10 clocks of the master CLK is generated. By setting the offset adjustment to be performed once every 10 clocks, and generating the data missing by the offset adjustment (missing sampling data) by interpolating from the previous and subsequent data, Data conversion function can be implemented.

  FIG. 9 shows a second embodiment of a mutual offset calibration AD converter with two ADCs.

  9, the same switches (switching means) 901 and 902 as the switch 501 shown in FIG. 5 described in FIG. 6 are provided between the I channel and the ADC 1 and between the Q channel and the ADC 2, respectively, and the calibration signal source and the I channel signal, Q Switch between channel signals. That is, in the second embodiment, calibration is performed by providing a calibration signal source and inputting a signal independent of two different input signals (input I, input Q) as a calibration signal. The configurations (calibration on the downstream side) and functions after ADC1 and ADC2 are the same as those in FIG. 5 described above, and are the same as the mutual offset calibration AD converter using two ADCs.

  In the normal operation of the second embodiment, the I channel signal (input I) is converted by the ADC 1 and the Q channel signal (input Q) is converted by the ADC 2 as in FIG. On the other hand, when Calibration Data Acquisition CLK becomes high level, both ADC1 and ADC2 are connected to the calibration signal source, and the same signal is input. In this case, ADC1 and ADC2 recognize the input signals as data for offset adjustment with each other, and execute an offset adjustment function.

  An example of the waveform of the calibration signal source connected to the switches 901 and 902 is shown in FIG. By adopting a signal that covers the full scale of ADC1 and ADC2 as a calibration signal source, it is possible to calibrate the input operation range of ADC1 and ADC2 evenly, and the performance of the ADC can always be set to a constant accuracy.

  Further, as described with reference to FIG. 8, if the relationship between Master CLK and Calibration Data Acquisition CLK is set (divided by 1/2), the second embodiment also uses the same Master CLK as in the first embodiment. It is possible to operate as an AD converter that performs a calibration operation in real time using a half of the sampling frequency as a sampling frequency.

  Next, an application example to a time interleave type AD converter will be described.

  FIG. 11 shows the configuration of a basic AD converter that time-interleaves two ADCs to double the sampling frequency. At this time, ADC 1 'and ADC 2' need to have exactly the same characteristics. These ADC1 'and ADC2' are driven by Master CLK1 and Master CLK2 that are 180 degrees different in phase.

  FIG. 12 shows the relationship between Master CLK1 / Master CLK2 of ADC 1 'and ADC 2', the input signal waveform, and the waveform after sampling. As can be seen from the comparison between the sampling waveform of the ADC 1 ′ and the sampling waveform of the ADC 2 ′, data is acquired so as to fill the middle of each sampling time. After encoding, the data is multiplexed with a clock with a frequency twice that of Master CLK1 / Master CLK2, and the results of ADC1 'and ADC2' are combined and the sampling frequency is twice that of Master CLK1 / Master CLK2. An operating AD converter can be realized.

  The above operation can be realized as it is if the relationship between Master CLK1 and Master CLK2 is set to the relationship having a phase difference of 180 degrees as described above in the AD converter ADC using the two ADC of FIG. is there. However, since the sampling time is different, the offset adjustment function cannot be operated as it is. For example, when the offset adjustment function is desired, a function for making both Master CLK1 and Master CLK2 have the same phase is required.

  As shown in FIG. 13, a signal called Calibration Data Acquisition CLKB is prepared, and when this signal is at a low level, a function of switching so that the phases of Master CLK1 and Master CLK2 are in phase may be implemented.

  When Master CLK1 / CLK2 operates in phase, the same signal is sampled and calibration data can be acquired. On the other hand, when Calibration Data Acquisition CLKB is at a high level, the phase difference between Master CLK1 and Master CLK2 is switched to 180 degrees and operates as an AD converter that samples at a frequency twice that of Master CLK1 / Master CLK2. This makes it possible to realize an AD converter that can be calibrated.

  In this second embodiment, the phase of Master CLK1 / CLK2 must be instantaneously switched to a 180 degree difference, so that the ADC whose clock phase changes must change its internal state all at once within one clock. Become. However, it is difficult to design so that the entire operation of the ADC can be switched instantaneously. As a method for solving this problem, the configuration of the third embodiment shown in FIG. 14 is preferable.

  In the third embodiment shown in FIG. 14, as described above, a mutual offset calibration AD converter is constituted by two ADCs 1 and 2 having a calibration function for adjusting the offset to each other based on the data of the same input signal. doing. However, Master CLK1 / CLK2 are supplied with clocks that are 180 degrees out of phase with each other. The signal input unit of ADC1 and ADC2 has a T / H switch 1401 for tracking and holding the input signal, and the offset is adjusted for the signal T / H Signal for driving the T / H switch 1401 and ADC1 and ADC2. The calibration data acquisition CLKB signal is input to distinguish whether the data acquisition is for acquisition or normal AD conversion data acquisition.

  The T / H switch 1401 is realized by, for example, the circuit shown in FIG. 15, and when the drive signal T / H Signal is at a high level, the channel of the nMOSFET 1501 becomes conductive and the voltage value of the input signal is charged to the terminal of the capacitor 1502 ( Track). When the drive signal T / H Signal becomes low level, the channel of the nMOSFET 1501 becomes high resistance, the terminal of the capacitor 1502 is separated from the signal source, and the next time the drive signal T / H Signal becomes high level, Hold state. The T / H switch 1401 in FIG. 15 has a simple configuration for the sake of explanation, but any T / H switch that is generally used can be applied.

  The T / H switch 1401 is placed in front of the input signals of the ADC1 and ADC2, but if the drive signal T / H Signal is always set to a high level, the input signal is always input to the ADC1 and ADC2 as it is. Therefore, as shown in FIG. 16, when Master CLK1 and Master CLK2 are input with a phase difference of 180 degrees, the signal waveform is the same as that shown in FIG. 12, and the sampling frequency is twice that of Master CLK1 / CLK2. Works as an operating AD converter.

  Next, FIG. 18 shows the operation signal waveform in the case where the drive signal T / H Signal is a 1/2 frequency divided signal of Master CLK1. The input signal is first tracked and held by the T / H switch 1401, but since it operates just for two clocks of Master CLK1, the timing of both Master CLK1 and Master CLK2 is set during the hold state of the second clock. Can bring. That is, the input signal value to ADC1 and ADC2 can be set to the same value by being tracked and held by the T / H switch 1401. Calibration can be performed with the data at the time of holding.

  In order to determine whether to acquire calibration data or normal data, a signal called Calibration Data Acquisition CLK is added, and when this signal is high, the drive signal T / H Signal corresponds to Master CLK1 as shown in FIG. When the calibration data acquisition CLKB is at low level, the processing signal is added so that the drive signal T / H signal becomes a signal that continues to output high level as shown in FIG. In addition, the ADC 1 and the ADC 2 may have a function of processing only the data whose calibration data acquisition CLKB is at the low level and the drive signal T / H Signal is at the low level as the calibration data. In addition, although the clock of the signal T / H Signal for driving Track and Hold has been described with a ½ cycle, it may be divided into a frequency of ½ or less.

  Next, the relationship among Master CLK1, Master CLK2, Calibration Data Acquisition CLKB, and T / H Signal will be described with reference to FIG. Master CLK1 and Master CLK2 are given from the beginning as clocks that are 180 degrees out of phase with each other. A clock CLK3 having a ½ frequency division of Master CLK1 is generated, and the calibration data acquisition CLKB signal is set to a low level in correspondence with a predetermined calibration data acquisition time and time in synchronization with the rising edge of the clock CLK3.

  In FIG. 17A, it is assumed that the calibration data acquisition CLKB for one clock of CLK3 is set to a low level from a certain time. At this time, it is only necessary to generate a signal so that the drive signal T / H Signal is at a low level only in the half clock of the second half of one clock of CLK3.

  FIG. 17B shows a case where two clocks are generated counting with CLK3.

  FIG. 19 shows an example of an operation signal waveform when the calibration data acquisition CLKB is inserted by thinning out the low level state. Since Master CLK1 and CLK2 of ADC1 and ADC2 only supply the clock in a constant state, it is only necessary to be able to follow the input signal even when the state of Calibration Data Acquisition CLKB basically changes.

  On the other hand, even if the signal of CLK3 for one clock, that is, the minimum time Calibration Data Acquisition CLKB, becomes low level, the original data for four clocks is lost. It is easier to apply a separate dedicated time region for the offset adjustment data acquisition mode and the normal data acquisition mode.

  However, if the measurement target signal 2001 is a burst-type signal as shown in FIG. 20, pseudo real-time calibration AD conversion can be performed by mixing the calibration signal with the rest time of the burst signal. Specifically, a synchronization signal 2004 for the burst signal is generated, and the measurement target signal 2001 and the calibration signal source 2002 are switched by the synchronization signal 2004 via the switch 2003 to generate an input signal waveform to the ADC, and the synchronization signal 2004 is supported. Then, calibration data acquisition CLKB may be generated. In synchronization with the input timing of the calibration signal, the ADC 1 and ADC 2 enter a mode in which the offsets are calibrated with each other, and a pseudo real-time calibration operation is possible.

[Effect of Example]
As described above, in the first and second embodiments, by applying to a two-signal system of I channel and Q channel often used in a radio system, it is built in a mutual offset calibration type AD converter using two ADCs. The two ADCs can always be used, and the area when the integrated circuit is mounted does not have to be wasted.

  On the other hand, in the third embodiment, the two ADCs of the mutual offset calibration AD converter by two ADCs are configured in a time interleave type, but by introducing a circuit for making both input signals identical, The ADC is always used, and the effect of increasing the sampling frequency by a factor of 2 can be obtained without impairing the mutual offset calibration function.

101 resistor array 102 comparator unit 103 logic unit 501, 901, 902 switch 1401 T / H switch 1501 nMOSFET
1502 capacitor

Claims (5)

When two AD conversion elements that operate with the same clock signal are included, and the offset adjustment of the two AD conversion elements is performed as calibration based on the result of comparison of the outputs of the two AD conversion elements by the comparison adjustment means An AD converter for inputting the same input signal to the AD conversion element,
One switching means is provided on the input side of the two AD conversion elements, and the switching means inputs the same input signal to the two AD conversion elements at the time of calibration execution. An AD converter, wherein different input signals are input to respective AD conversion elements.   2. The AD converter according to claim 1, wherein the switching unit inputs one of the two different input signals to the two AD conversion elements as the same input signal when the calibration is performed. 3. A featured AD converter.   3. The AD converter according to claim 2, wherein the switching unit includes a switch connected to an input side of one of the two AD conversion elements, and the switch is connected to the other when performing the calibration. An input signal to an AD conversion element is input to the one AD conversion element, and when the calibration is completed, an input signal to the one AD conversion element is input to the one AD conversion element. converter.   2. The AD converter according to claim 1, wherein a calibration signal independent of the two different input signals is used when the calibration is performed. In the AD converter according to any one of claims. 1 to 4, AD converter, characterized in that the interpolation using the before and after sampling the data of switching by said switching means missing sampling data generated during the calibration run vessel.

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