JP5685215B2 - Packet communication method and packet communication apparatus - Google Patents

Description

  The present invention relates to a packet communication method and a packet communication device, for example, a relief method when a memory hard error occurs in a packet communication device.

  In a packet communication device having a packet buffer, a hard error occurs in the memory device due to a soft error or external noise for SRAM (Static Random Access Memory) used as a packet buffer, resulting in a packet loss. There are things to do. A typical example of a hard error is single event latch-up.

  A soft error is an event that occurs accidentally when radiation existing in outer space affects a semiconductor device and cannot be suppressed by a mechanism / circuit configuration. Such a soft error can be normally used thereafter by overwriting the memory, that is, the write process.

  However, a memory hardware error, in particular, a latch-up event is not recovered by a write process or a normal reset process, but is recovered only by turning the power off / on. Such memory hard errors occur at a frequency of about once per month per device (package).

Therefore, in the past, for the occurrence of trouble events such as packet loss in SRAM latch-up, etc.,
Switching process (for example, refer to Patent Document 1) due to the duplexing of the device (package)
Device (package) replacement, or
Device (package) power OFF / ON (for example, see Patent Document 2)
We have dealt with such as.

JP 2007-208396 A Japanese Patent Laid-Open No. 06-318107

  However, as a countermeasure when a memory hardware error event occurs, there is a problem that if a countermeasure by duplication is implemented, a device having a plurality of slots cannot be used simultaneously when a multi-package malfunction event occurs. In addition, normally, even when a hard error event occurs, the SRAM device remains powered on, so there is a possibility that a large current flows. Therefore, there is a problem that the device failure may occur if it is left as it is. is there.

  In addition, if the device (package) replacement is used in a remote place such as a station building, it is necessary for the administrator to go to the site to recover this event, and it is difficult to respond quickly and it takes time to recover. There is a problem.

  Further, in response to the power supply OFF / ON of the device (package), communication disconnection occurs during that time. Therefore, in the multi-line accommodating device, communication disconnection also occurs in other lines that are normally communicating.

  Therefore, an object of the present invention is to continue packet communication in response to a memory hardware error quickly without increasing the size of the apparatus.

In order to solve the above problems, (1) in the packet communication method, when a memory hard error occurs in an operation static random access memory used as a packet buffer in the packet communication method, the operation static A packet communication method characterized by turning off only the random access memory and switching to a spare static random access memory to continue the communication when the memory hard error occurs. If it is necessary to identify the cause of the failure, the packet communication device operator is notified of error detection information, and the packet communication device operator switches / operates to the spare static random access memory. Remote switch back to static random access memory And performing manually.

  Thus, by providing a spare static random access memory, it is possible to communicate in response to packet loss without duplicating the package, without exchanging the package, and without turning the power off / on. Can continue. In addition, even when the package is duplicated, it is possible to use a duplicated package for other package failure.

In addition, since only the static random access memory for operation in which a memory hard error has occurred is turned off, a large current does not flow and device failure can be prevented. In particular, it is possible to identify the cause of the failure of the memory hardware error event by manually performing switching / switching back by remote operation of the packet communication apparatus operator. That is, since a package in which a memory hardware error has occurred often recovers from an event when the power is turned OFF / ON, the cause of the failure cannot often be specified even if it is returned as a faulty product. However, by enabling manual switching / switchback processing when an event occurs, it is possible to maintain the status at the time of a hard error without switching back, making it easier to isolate the cause of the failure. . In addition, by performing manual switching, it is possible to perform switching at a timing intended by the apparatus operator (such as a period of quiet operation of the apparatus).

  (2) In the present invention, in (1) above, after switching to the spare static random access memory, the operation static random access memory in which the memory hard error has occurred is turned on. Then, a parity error is checked, and if no parity error is detected, the spare static random access memory is switched back to the operational static random access memory.

  By switching back in this way, even if a memory hard error occurs again in the operational static random access memory, the communication is continued again by switching to the spare static random access memory. be able to.

(3) Further, the present invention is Oite above (1) or (2), in the preliminary static random access memory at all times, static random access to be used as a packet buffer for the operation and The same writing as the memory is performed.

  By performing such writing duplication, when a memory hardware error event occurs, packet communication can be continued without causing packet loss, that is, switching without interruption is possible.

( 4 ) Further, according to the present invention, in a package communication apparatus, an operational static random access memory used as a packet buffer and the operational static random access memory via a switching means Spare static random access memory connected in parallel, static random access memory for operation, and memory for controlling on / off of power to spare static random access memory A power control unit , a mechanism for notifying the packet communication device operator of error detection information when the memory hard error occurs, and the packet communication device operator to the spare static random access memory Static / random for switching / operation Characterized in that it comprises a mechanism for manually by switching back the remote control to access memory.

  By adopting such a device configuration, even if a memory hardware error event occurs, a communication device that can continue packet communication with a simple package configuration and without causing a package failure is constructed. Can do.

( 5 ) Further, according to the present invention, in the above ( 4 ), the spare static random access memory is connected to the operational static random access memory connected to the upper line and the lower line. It is connected to be used for a static random access memory for operation.

  In this way, one spare static random access memory is used as an operational static random access memory connected to the upper line and an operational static random access memory connected to the lower line. By connecting in such a way, the number of parts can be reduced.

( 6 ) Further, according to the present invention, in the above ( 4 ), the spare static random access memory is connected to the operation static random access memory connected to the upper line and the operation connected to the lower line. It is individually connected to the static random access memory.

  In this way, the spare static random access memory is divided into a static random access memory for operation connected to the upper line and a static random access memory for operation connected to the lower line. By connecting to, it becomes possible to always write to the spare static random access memory and to eliminate packet loss when a memory hard error occurs.

  According to the disclosed packet communication method and packet communication apparatus, it is possible to continue packet communication in response to a memory hardware error quickly without increasing the apparatus configuration.

It is a principle block diagram of the switching mechanism of the packet communication apparatus of the switching system with an instantaneous interruption of embodiment of this invention. It is a memory switching flowchart when a memory hard error event occurs. It is a principle block diagram of the switching mechanism of the packet communication apparatus of the non-instantaneous switching system of the embodiment of the present invention. It is a memory switching flowchart when a memory hard error event occurs. It is a notional block diagram of the packet communication apparatus of Example 1 of this invention. FIG. 3 is a memory switching flowchart when a memory hard error event occurs in the first embodiment of the present invention. It is a notional block diagram of the packet communication apparatus of Example 2 of this invention. It is a memory switching flowchart at the time of memory hard error event occurrence in Example 2 of the present invention.

Here, with reference to FIG.1 and FIG.2, the packet communication apparatus of embodiment of this invention is demonstrated. FIG. 1 is a principle configuration diagram of a switching mechanism of a packet communication device of a switching method with instantaneous interruption according to an embodiment of the present invention. The device package unit 1 constituting the packet communication device is provided with a memory function unit 2 ₁ having a power input unit 3 ₁ and a spare memory function unit 2 ₂ having a power input unit 3 ₂ , and switch units 4 ₁ , 4. ₂ to the parity detection unit 5. The output of the parity detection unit 5 is output to the power OFF / ON determination unit 6, the output from the power OFF / ON control unit 7 through the memory functional unit _{2 1} and spare memory functional unit _{2 2} Power OFF / Control ON. Further, the memory used in the packet communication is selected via the selector unit 8 based on the output of the parity detection unit 5.

If necessary provided the remote device notifying unit 9, the output of the power supply OFF / ON determination unit 6 Problem the power state of the memory functional unit 2 ₁ and spare memory functional unit 2 ₂ to the remote monitoring control device 11, necessary An abnormal warning is issued according to the situation. Note that the memory functional unit _{2 1} and spare memory functional unit _{2 2} eg, SRAM of 128Mbit is mounted.

FIG. 2 is a memory switching flowchart when a memory hardware error event occurs.
S _1: to detect a parity error whenever performing the memory functional unit _{2 1} write / read.
S _2: If a parity error is detected, then the power of the spare memory functional unit 2 ₂ to ON, switching to the spare memory function section 2 _2.
S _3: starting the write / read processing to the spare memory function unit _{2 2.}
S _4: perform write / read process to all the addresses address the memory function section 2 ₁ of event occurrence, performed again parity error detection, it is determined whether a hardware error or a soft error.
S _5: If there is no parity error, switches back to the original memory functional unit 2 ₁ determines that the soft error, and the power of the spare memory functional unit 2 ₂ to OFF, to continue communication.
S _6: if a parity error is detected, to turn OFF the power supply of the memory functional unit 2 ₁ determines that the hard errors, continue to operate in the pre-memory function section 2 _2.

In this case, since the packet at the time of occurrence of the event is lost, a notification to that effect is generated. Thereafter, or to restore the latch-up, etc. performing power OFF / ON of the hard error and the determined memory functional unit 2 ₁ optionally Alternatively, for elucidation of failure causes, to turn ON the power Collect the device package at an appropriate time. The power supply for latch-up recovery may be programmed to be turned off / on automatically, or may be remotely operated by the device operation manager based on a report from the remote device report unit.

Next, a non-instantaneous switching type packet communication apparatus according to an embodiment of the present invention will be described with reference to FIGS. FIG. 3 is a principle configuration diagram of the switching mechanism of the packet communication device of the non-instantaneous switching method according to the embodiment of this invention. The basic configuration is the same with the above embodiment, by inserting a buffer 10 between the parity detecting unit 5 and a switch unit 4 _1, 4 _2, write operation the memory functional unit 2 ₁ and the spare memory operation unit writes always packet to 2 _2, reading of the normal operation is performed from the memory functional unit 2 _1.

FIG. 4 is a memory switching flowchart when a memory hardware error event occurs.
S _1: the memory functional unit _{2 1} and spare memory functional unit _{2 2} performs write, to detect a parity error from the memory functional unit _{2 1} each time to perform read.
S _2: If a parity error is detected, switch it to the spare memory functional unit 2 _2.
S _3: starting the write / read processing to the spare memory function unit _{2 2.}
S _4: perform write / read process to all the addresses address the memory function section 2 ₁ of event occurrence, performed again parity error detection, it is determined whether a hardware error or a soft error.
S _5: If there is no parity error, switches back to the original memory functional unit 2 ₁ determines that the soft error, and continues the communication with read from the memory functional unit 2 _1.
S _6: if a parity error is detected, to turn OFF the power supply of the memory functional unit 2 ₁ determines that the hard errors, continue to operate in the pre-memory function section 2 _2.

In this case, since the spare memory functional unit 2 ₂ even when an event occurs is the same packet are written, packet loss does not occur. Thereafter, or to restore the latch-up, etc. performing power OFF / ON of the hard error and the determined memory functional unit 2 ₁ optionally Alternatively, for failure cause elucidation, without turning ON the power supply Collect the device package at the appropriate time. The power supply for latch-up recovery may be programmed to be turned off / on automatically, or may be remotely operated by the device operation manager based on a report from the remote device report unit.

Thus, in the embodiment of the present invention, only by providing the spare memory mechanism 2 _2, without having to duplicate equipment package, it is possible to correspond to the memory hard errors without interrupting communications.

Also, when the memory hardware error occurred also because the power of only the memory function section 2 ₁ of event occurrence is only to OFF, when the multi-line accommodating device, the communication other lines that are communicating properly No interruption occurs.

Since the power of only the memory function section 2 ₁ event occurred to OFF, no a large current flows through the memory functional unit 2 _1, therefore, never device package 1 with the memory hard error is destroyed .

  Next, the packet communication apparatus according to the first embodiment of the present invention will be described with reference to FIGS. FIG. 5 is a conceptual configuration diagram of the packet communication apparatus according to the first embodiment of the present invention, in which a common package 40 including a plurality of line packages 20 having multiple lines in one package and a package multiplexing / separating unit 41 is back-wired. It is mounted on the board 50 and the lower line and the upper line are connected via the common package 40.

  Each line package 20 includes a line multiplexer / demultiplexer 21 and is connected to a lower line via a number of interface converters 22. An upper direction SRAM 23 and a lower direction SRAM 24, which are packet buffers, are connected to the line multiplexing / demultiplexing unit 21 via relay switches 25 and 26 connected to a communication line in the upstream direction and the downstream direction, respectively.

  Further, one common spare SRAM 27 is provided for the upper direction SRAM 23 and the lower direction SRAM 24. As shown in FIG. 1, the power source 28 is a power OFF / ON control unit connected to the power supply line. The relays 29 and 30 are connected to the upper direction SRAM 23, the lower direction SRAM 24 and the spare SRAM 27.

  Although not shown, the parity error detection unit, the power OFF / ON determination unit, the selector unit, and the remote device notification unit shown in FIG. 1 are provided. When a memory hardware error occurs, a remote device notification is provided. Is notified to the remote monitoring and control device 60.

FIG. 6 is a memory switching flowchart when a memory hard error event occurs in the first embodiment of the present invention. First,
S ₁ : Parity error is detected each time write / read is performed to the upper direction SRAM 23 and the lower direction SRAM 24.
S ₂ : When a parity error is detected, the spare SRAM 27 is powered on and switched to the spare SRAM. The SRAM on the side where no event has occurred continues to operate as it is.
S ₃ : The write / read process to the spare SRAM 27 is started.
S ₄ : Write / read processing to all address addresses is performed on the event occurrence SRAM, parity error detection is performed again, and it is determined whether it is a hardware error or a software error.
S ₅ : If there is no parity error, it is determined as a soft error and switched back to the original SRAM, the spare SRAM 27 is turned off, and communication is continued.
S ₆ : When a parity error is detected, it is determined as a hard error, the power of the event occurrence SRAM is turned off, and the operation in the spare SRAM 27 is continued.
S _7: For SRAM of event occurrence when the power is ON attempt to recover the memory hard errors.
S ₈ : Write / read processing to all address addresses is performed on the SRAM that has attempted to recover from the memory hard error, and parity error detection is performed again to determine whether the error is a hard error or a soft error.
S ₉ : If no parity error is detected, switch back to the restored SRAM and turn off the power of the spare SRAM 27.
S ₁₀ : If a parity error is detected, the power of the SRAM is turned off again, and the operation with the spare SRAM 27 is continued.

  The attempt to recover the memory hard error for the event-occurring SRAM may be programmed to be performed automatically, or may be performed manually by the device manager by the remote monitoring control device 60 by remote operation.

  In addition, the remote supervisory control device 1 may prevent the device administrator from trying to recover the memory hardware error for the event-occurring SRAM. The cause of the failure may be investigated.

  As described above, in the first embodiment of the present invention, the line package can be duplicated or the entire line package can be configured with a simple configuration in which only one common spare SRAM is provided for the upstream and downstream packet buffers. It becomes possible to cope with a memory hardware error without turning off the power and interrupting communication.

  In addition, if the hard memory error is not recovered by the power recovery after the occurrence of the event, the power of the SRAM remains off, so that a large current does not flow through the SRAM, and the memory hard error As a result, the line package 20 is not destroyed.

  Next, the packet communication apparatus according to the second embodiment of the present invention will be described with reference to FIG. 7 and FIG. 8. In this embodiment, separate spare SRAMs are provided in both the upper direction SRAM and the lower direction SRAM. The other basic configuration is the same as that of the first embodiment.

  FIG. 7 is a conceptual configuration diagram of the packet communication apparatus according to the second embodiment of the present invention, and includes a plurality of line packages 20 having multiple lines in one package and a package multiplexing / separating unit 41 as in the first embodiment. The common package 40 is mounted on the back wiring board 50, and the lower line and the upper line are connected via the common package 40.

  Each line package 20 includes a line multiplexing / separating unit 21 and is connected to a lower line via an interface conversion unit 22. An upper direction SRAM 23 and a lower direction SRAM 24, which are packet buffers, are connected to the line multiplexing / demultiplexing unit 21 via relay switches 25 and 26 connected to a communication line in the upstream direction and the downstream direction, respectively.

  In the second embodiment of the present invention, the spare SRAM 31 is connected in parallel to the upper direction SRAM 23, and the spare SRAM 32 is also connected in parallel to the lower direction SRAM 24. In this case, as shown in FIG. 3, packets are always written to the spare SRAM 31 and the spare SRAM 32 via a buffer (not shown). The power supply 28 is connected to the upper direction SRAM 23, the lower direction SRAM 24, and the spare SRAMs 31 and 32 via relay switches 29 and 30 serving as a power OFF / ON control unit connected to the power supply line.

  Although not shown, the parity error detection unit, the power OFF / ON determination unit, the selector unit, and the remote device notification unit shown in FIG. 3 are also provided in this case, and a memory hardware error occurs. Then, the remote device notification unit notifies the remote monitoring control device 60 to that effect.

FIG. 8 is a memory switching flowchart when a memory hard error event occurs in the second embodiment of the present invention. First,
S ₁ : Write to the upper direction SRAM 23 and the spare SRAM 31, the lower direction SRAM 24 and the spare SRAM 32, and write a parity error each time read is performed from the upper direction SRAM 23 and the lower direction SRAM 24.
S ₂ : When a parity error is detected, the corresponding spare SRAM 31 (32) is turned on and switched to the spare SRAM 31 (32). The SRAM on the side where no event has occurred continues to operate as it is.
S _3: starting the write / read processing to the spare SRAM31 (32).
S ₄ : Write / read processing to all address addresses is performed on the event occurrence SRAM, parity error detection is performed again, and it is determined whether it is a hardware error or a software error.
S _5: If there is no parity error, switching back to the original SRAM it is determined that the soft error, to continue the communication. The write to the corresponding SRAM 31 (32) is continued as it is.
S ₆ : When a parity error is detected, it is determined as a hard error, the power of the event occurrence SRAM is turned off, and the operation in the spare SRAM 31 (32) is continued.
S _7: For SRAM of event occurrence when the power is ON attempt to recover the memory hard errors.
S ₈ : Write / read processing to all address addresses is performed on the SRAM event occurrence SRAM that attempted to recover from the memory hard error, and a parity error is detected again to determine whether it is a hard error or a soft error.
S ₉ : If no parity error is detected, switch back to the restored SRAM and continue operation. The write to the corresponding SRAM 31 (32) is continued as it is.
S ₁₀ : When a parity error is detected, the power of the SRAM is turned off again, and the operation with the spare SRAM 31 (32) is continued.

  In this case as well, an attempt to recover the memory hard error for the event-occurring SRAM may be programmed to be performed automatically, or may be performed manually by the device manager by the remote monitoring control device 60 by remote operation. Also good.

  Further, the attempt to recover the memory hard error for the SRAM in which the event has occurred may be made so that the remote manager / control device 11 does not attempt the recovery by the device manager. May be collected to determine the cause of the failure.

  As described above, in the second embodiment of the present invention, separate spare SRAMs are provided for the upstream and downstream packet buffers, and packets are always written to the spare SRAM. Even in the case of occurrence of an error, switching without interruption can be performed without causing packet loss.

DESCRIPTION OF SYMBOLS 1 Device package part 2 ₁ Memory function part 2 ₂ Spare memory function part 3 ₁ , 3 ₂ Power supply input part 4 ₁ , 4 ₂ Switch part 5 Parity detection part 6 Power supply OFF / ON determination part 7 Power supply OFF / ON control part 8 Selector Unit 9 Remote device notification unit 10 Buffer 11 Remote monitoring and control device 20 Line package 21 Line multiplexing / separation unit 22 Interface conversion unit 23 Upper direction SRAM
24 Lower direction SRAM
25, 26, 29, 30 Relay switches 27, 31, 32 Spare SRAM
28 Power supply 40 Common package 41 Package multiplexing / separating unit 50 Back wiring board 60 Remote monitoring and control device

Claims (6)

When a memory hard error occurs in the static random access memory for operation used as a packet buffer, only the static random access memory for the operation is turned off and a spare static random access memory is used. A packet communication method characterized by switching to a memory and continuing communication ,
When the memory hardware error has occurred and it is necessary to identify the cause of the failure, the packet communication device operator is notified of error detection information, and the packet communication device operator A packet communication method characterized in that switching to an access memory / switching back to a static random access memory for operation is performed manually by remote control.   After switching to the spare static random access memory, turn on the static random access memory for operation where the memory hard error occurred, check the parity error, and detect the parity error 2. The packet communication method according to claim 1, wherein, if not, switching back from the spare static random access memory to the operational static random access memory. 3. The spare static random access memory at all times, according to claim 1 or claim 2, characterized in that the same write as the static random access memory used as a packet buffer for the operation Packet communication method. Static random access memory for use as a packet buffer,
A spare static random access memory connected in parallel via switching means to the operational static random access memory;
A memory power control unit for controlling on / off of power to the operational static random access memory and the spare static random access memory;
A mechanism for notifying the packet communication device operator of error detection information when the memory hard error occurs;
A mechanism in which an operator of the packet communication apparatus manually switches to the spare static random access memory / switches back to the static random access memory for operation manually by remote operation. A packet communication device. The spare static random access memory is used for the operational static random access memory connected to the upper line and the operational static random access memory connected to the lower line. The packet communication device according to claim 4 , wherein the packet communication device is connected to the packet communication device. The spare static random access memory is separately provided for the operational static random access memory connected to the upper line and the operational static random access memory connected to the lower line. The packet communication device according to claim 4 , wherein the packet communication device is connected.

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