JP5700649B2 - Manufacturing method of semiconductor device - Google Patents

Description

The present invention relates to a method of manufacturing a semi-conductor device, in particular a method of manufacturing a semi-conductor device engaging Ru on DMOS transistor having a high breakdown voltage.

  Currently, there is a DMOS (Double-Diffused MOS) transistor as a high breakdown voltage MOS transistor. A high breakdown voltage DMOS transistor is used as a power source for supplying power in a semiconductor integrated circuit. Patent document 1 is mentioned as a prior art of a DMOS transistor. 13A and 13B are diagrams for explaining the DMOS transistor described in Patent Document 1. FIG. 13A is a top view of the DMOS transistor, and FIG. 13B is shown in FIG. It is sectional drawing in alignment with line segment AA '.

As shown in FIGS. 13A and 13B, the DMOS transistor described in Patent Document 1 includes a P-type body 2 formed in an N-type well (NW), and an N ⁺ layer functioning as a drain ( (Hereinafter referred to as a drain) 4. In the P-type body 2, an N ⁺ layer (hereinafter referred to as a source) 8 functioning as a source and a P ⁺ layer (hereinafter referred to as a take-out region) 7 serving as a take-out region of the P-type body 2 are formed. ing.

  A gate 3 is provided on part of the P-type body 2 and the source 8, and when a voltage is applied to the gate 3, a channel is formed in the P-type body 2 below the gate 3. By forming the channel, the DMOS transistor is turned on and a current flows between the source 8 and the drain 4. A contact hole 6 c is provided on the drain 4 via an insulating layer (not shown), and a contact hole 6 a is provided on the source 8. A contact hole 6 b is provided on the extraction region 7.

Incidentally, the semiconductor device is generally required to further reduce the occupied area, and the DMOS transistor shown in FIG. 13 is required to be further downsized. In order to meet the demand for miniaturization, Patent Document 2 discloses an invention for shortening the cell pitch P1 shown in FIG.
14A and 14B are diagrams for explaining the DMOS transistor described in Patent Document 2. FIG. 14A is a top view, and FIG. 14B is a line segment B shown in FIG. FIG. 14C is a cross-sectional view taken along the line CC ′ shown in FIG. 14A. In addition, the same code | symbol is attached | subjected about the structure similar to the structure shown in FIG. 13 in FIG. 14, and the description is partially abbreviate | omitted.

In the DMOS transistor shown in FIG. 14, the source 8 and the extraction region 7 shown in FIG. 13 are arranged in the vertical direction in the figure. In FIG. 14, a member denoted by reference numeral 70 indicates a take-out area (take-out area 70), and a member indicated by reference numeral 80 indicates a source (source 80). The whole including the extraction region 70 and the source 80 is referred to as an impurity layer 90. According to the DMOS transistor shown in FIG. 14, the cell pitch P1 shown in FIG. 13 can be set to a shorter cell pitch P2. Specifically, the cell pitch P1 of the DMOS transistor of the cited document 1 is 3.8 μm, whereas the cell pitch P2 of the DMOS transistor of the patent document 2 is 3.0 μm, and the invention of the cited document 2 realizes a cell pitch reduction of 21%. doing.

JP 11-354793 A JP 2007-250780 A

However, the DMOS transistor of Patent Document 2 has a drawback that the on-resistance of the DMOS transistor is increased. Hereinafter, this reason will be described.
FIG. 15 is a schematic diagram for explaining that the on-resistance of the DMOS transistor of Patent Document 2 is increased. When a voltage is applied to the gate 3 shown in FIG. 14 and a channel is formed under the gate 3, electrons flow from the source 80 toward the drain 4 as shown in FIG. A current Id flows. However, in the DMOS transistor shown in FIG. 14, since no channel is formed in the extraction region 70, no current Id is generated between the extraction region 70 and the drain 4. Such a phenomenon acts as if the source region is substantially reduced as compared with the prior art shown in FIG.

FIG. 16 is a schematic diagram for explaining the relationship between the current Id and the on-resistance of the DMOS transistor. A straight line q shown in FIG. 16 indicates the Id-Vd characteristic between the source 8 and the drain 4 of the DMOS transistor when a voltage of 5 V is applied to the gate 3 of the DMOS transistor shown in FIG. A straight line r indicates the Id-Vd characteristic between the impurity layer 90 and the drain 4 shown in FIG. 14 of the DMOS transistor when a voltage of 5 V is applied to the gate 3 of the DMOS transistor shown in FIG.
That is, in the DMOS transistor shown in FIG. 14, the current Id does not flow between the extraction region 70 and the drain 4 as shown in FIG. 15, so that the DMOS transistor shown in FIG. When the voltages Vd are equal, the on-resistance increases and the amount of current Id decreases.

In general, the ability of a MOS transistor to flow current is represented by the product of the on-resistance value Ron of the transistor and the transistor area A (hereinafter referred to as Ron × A), and the cell pitch of the transistor is reduced and the transistor area A is reduced. However, if Ron increases and Ron × A does not decrease, the advantage of downsizing the transistor cannot be obtained.
The present invention was made in view of the above, there is no possibility to increase the also on-resistance while reducing the cell pitch of the DMOS transistor, the capacity high have semi conductor device to flow a current with a small An object is to provide a manufacturing method.

In addition, according to the method of manufacturing a semiconductor device of the present invention, the gate dielectric film (for example, shown in FIG. 4-2) is formed on the surface of the semiconductor layer having the first conductivity type (for example, the N-type well 202 shown in FIG. A gate forming step (for example, the step shown in FIG. 4E) of forming a gate through the gate oxide film 101c), an impurity is implanted using the gate as a mask, and an impurity is formed using the gate as a mask. Body forming step (for example, the step shown in FIG. 4-2 (f)) for forming a body impurity region of the second conductivity type, and the body impurity region formed in the body forming step in the body impurity region. A low-resistance impurity region forming step (for example, the step shown in FIG. 4-2 (f)) in which impurities are implanted using the gate as a mask to form a low-resistance impurity region having the first conductivity type in the body impurity region. ) and, before After the low-resistance impurity region forming step, a spacer forming step of forming a spacer on a peripheral surface of said gate (e.g., the step shown in FIG. 4-2 (g)) and, in a predetermined area of the low-resistance impurity region A source region forming step (for example, the steps shown in FIGS. 5 and 6) in which impurities are implanted to form a first conductivity type source region and a first conductivity type drain, and the source region adjacent to the source region. Impurities are implanted into the low-resistance impurity region, and the periphery is surrounded by the low-conductivity impurity region of the first conductivity type and the source region of the first conductivity type, and is electrically connected to the body impurity region. conductivity type and the impurity region forming step of forming an impurity region (e.g., the step shown in FIG. 7) viewed it contains a, a, the source region formation step, in the impurity region forming step is to the spacer as a mask impurities Characterized in that it is injected.

According to the semiconductor device of the present invention, since the source region and the impurity region are alternately arranged along one direction, the cell pitch of the DMOS transistor can be shortened. The source region includes an impurity region of the second conductivity type, and the second conductivity type impurity region is surrounded by the first conductivity type source region and is electrically connected to the body impurity region. Therefore, current flows between the drain and the low-resistance impurity region, and current does not flow in part of the channel region, so that the on-resistance of the transistor can be prevented from increasing. Therefore, the semiconductor device of the present invention can provide a semiconductor device that does not increase the on-resistance value while shortening the cell pitch of the DMOS transistor.
According to the method for manufacturing a semiconductor device of the present invention, it is possible to provide a method for manufacturing a semiconductor device that does not increase the on-resistance value while shortening the cell pitch of the DMOS transistor. Further, according to the method for manufacturing a semiconductor device of the present invention, the source region and the impurity region can be formed in a self-aligning manner using the spacer as a mask.

It is a figure for demonstrating the semiconductor device of one Embodiment of this invention. It is the schematic diagram which showed the cross section shown in FIG. 1 in detail. It is a figure for demonstrating the effect by the structure of the semiconductor device of one Embodiment of this invention. It is a figure for demonstrating the manufacturing method of the semiconductor device of one Embodiment of this invention. It is a figure for demonstrating the manufacturing method of the semiconductor device of one Embodiment of this invention, Comprising: It is a figure for demonstrating the process performed after the process shown to FIGS. 4-1. FIG. 4D is a diagram for explaining a process performed subsequent to FIG. 4B by dividing the process into a P ⁺ -type impurity region and an N ⁺ -type source. FIG. 6 is a diagram for explaining a semiconductor device manufacturing process performed subsequent to FIG. 5 for an N ⁺ type source. FIG. 6 is a diagram for describing a semiconductor device manufacturing process performed subsequent to FIG. 5 for a P ⁺ -type impurity region. FIG. 8 is a diagram for explaining a state of an N ⁺ type source during the manufacturing process of the semiconductor device shown in FIG. 7. FIG. 8 is a diagram for explaining a semiconductor device manufacturing process performed subsequent to FIG. 7 for a P ⁺ -type impurity region. FIG. 9 is a diagram for explaining a semiconductor device manufacturing process performed subsequent to FIG. 8 for an N ⁺ type source; It is a figure for demonstrating the process of forming wiring in the manufacturing method of the semiconductor device of one Embodiment of this invention about a P ⁺ type impurity region. It is a figure for demonstrating the process of forming wiring in the manufacturing method of the semiconductor device of one Embodiment of this invention about N ^<+> type | mold source. It is a figure for demonstrating the invention equivalent to the prior art of this invention. It is a figure for demonstrating the other invention which is the prior art of this invention. It is a figure for demonstrating the problem of a prior art. It is another figure for demonstrating the problem of a prior art.

Hereinafter, a semiconductor device according to an embodiment of the present invention and a method for manufacturing the semiconductor device will be described.
(Semiconductor device)
1A to 1C are diagrams for explaining the semiconductor device according to the present embodiment. FIG. 1A is a top view of the semiconductor device according to the present embodiment, and FIG. 1A is a cross-sectional view taken along line DD ′ shown in FIG. 1A, and FIG. 1C is a cross-sectional view taken along line EE ′ shown in FIG. The semiconductor device of this embodiment is configured as a DMOS transistor formed on an N-well (denoted as NW in FIG. 1) of a P-type substrate.

  As shown in FIGS. 1A to 1C, the semiconductor device of this embodiment includes a P-type body impurity region 105 formed in an N-Well, and the body impurity region 105 and the N-Well. A source electrode 102 formed between the two gates 101, an N-type drain 104 provided on each side of the gate 101, Is included. According to such a layout, the source 102 is located inside (between) the two gates 101, and the drain 104 is located outside each of the two gates 101. The source 102 is longer in one direction (vertical direction in FIG. 1) than the other direction, and the longitudinal direction of the source 102 is referred to as the “length” of the source. A direction perpendicular to the length direction of the source 102 is referred to as a “width” of the source 102. Body impurity region 105 is formed so as to sandwich both sides of source 102 from the width direction of source 102.

The source 102 includes a P ⁺ -type impurity region 102a and an N ⁺ -type source 102b. The P ⁺ -type impurity region 102a is surrounded by the N ⁺ -type source 102b and electrically connected to the P-type body impurity region 105. Connected to. In this embodiment, the P ⁺ -type impurity regions 102a and the N ⁺ -type sources 102b are alternately arranged in the vertical direction in FIG. In this embodiment, the N ⁺ type source low resistance region 110 is provided between the P ⁺ type impurity region 102 a and the gate 101 and between the N ⁺ type source 102 b and the gate 101. According to such a layout of this embodiment, the cell pitch P3 of the DMOS transistor can be reduced to the same extent as the cell pitch P2 of the DMOS transistor disclosed in the cited document 2.

The source 102 is not limited to the layout shown in FIG. That is, the source 102 is not limited to the N ⁺ type source 102b as shown in FIG. 1 in which sandwich the P ⁺ -type impurity regions 102a, sandwiching the P ⁺ -type impurity regions 102a by N ⁺ -type source 102b It may be formed as follows. Further, the number and pitch of the contact holes 106a are not limited to those shown in FIG. 1, and can be arbitrarily set to any number and pitch.

Further, FIG. 1A is not limited to the whole semiconductor device of the present embodiment, and may show a part of the semiconductor device. In the case where FIG. 1A shows a part of a semiconductor device, it is preferable that the source 102 and the drain 104 are formed longer in the length direction of the source 102 and the width of the source 102 is not changed. At this time, the source 102 may be configured by alternately arranging more N ⁺ type sources 102b and P ⁺ type impurity regions 102a.

FIG. 2 is a schematic diagram showing the cross section shown in FIG. 1B in more detail. FIG. 2A shows an N ⁺ type source 102b, and FIG. 2B shows a P ⁺ type impurity region 102a. Shows about. As shown in FIGS. 2A and 2B, the gate 101 includes a gate electrode 101a, an oxide spacer 101b, and a gate oxide film 101c. An N ⁺ type source low resistance region 110 is formed under the oxide spacer 101b. A wiring 201 is in contact with the P ⁺ -type impurity region 102a and the N ⁺ -type source 102b.

FIG. 3 is a diagram for explaining the effect of the structure described above. That is, according to the present embodiment, as shown in FIG. 2B, when a voltage is applied to the gate 101 and the P-type body impurity region 105 is inverted to form a channel, the N ⁺ -type source 102b Then, electrons are supplied to the channel from the N ⁺ type source low resistance region 110 (arrow f in FIG. 3 indicates the flow of electrons). For this reason, since the current Id flows in substantially the entire region of the channel, the change in the drain current with respect to the change in the drain voltage is increased, and the on-resistance of the DMOS transistor can be reduced.

(Method for manufacturing semiconductor device)
Next, a method for manufacturing the semiconductor device of this embodiment will be described.
4A and 4B are cross-sectional views for explaining the method for manufacturing the semiconductor device of this embodiment. A method for manufacturing the semiconductor device of this embodiment will be described with reference to FIGS.
In this embodiment, first, as shown in FIG. 4A, an oxide film (SiO ₂ film) 301 having a thickness of 30 to 100 nm is formed on the surface of a P-type substrate 203 having a resistivity of about 5 to 10 Ω · cm. It is formed by steam oxidation at about 900 to 1000 ° C. A photoresist layer (not shown) is formed on the SiO ₂ film 301. This photoresist layer is patterned by a known photolithography technique so as to have an opening in a region where an N-type well is formed.

Next, ion implantation is performed using the photoresist layer (not shown) as a mask. About 1 × 10 ¹² to 1 × 10 ¹³ / cm ^{2 of} phosphorus (P) is introduced into the P-type substrate 203 by ion implantation. After removal of the photoresist layer, a photoresist layer 303 is formed. The photoresist layer 303 is patterned by a known photolithography technique so as to have an opening in a region where a P-type well is formed. By performing ion implantation using the photoresist layer 303 as a mask, boron (B) is introduced into the P-type substrate 203 at about 1 × 10 ¹² to 1 × 10 ¹³ / cm ² . As a result, as shown in FIG. 4A, an N-type well impurity implantation region 202 ′ and a P-type well impurity implantation region 302 ′ are formed.

After the removal of the photoresist layer 303, heat treatment at about 1100 to 1300 ° C. is performed. The heat treatment diffuses impurities in the N-type well impurity implantation region 202 ′ and the P-type well impurity implantation region 302 ′, and the N-type well 202 and the P-type well 302 shown in FIG. 4B are formed.
Next, the SiO ₂ film 301 on the P-type substrate 203 is removed with a hydrofluoric acid (HF) chemical solution. Subsequently, a 10 to 30 nm SiO ₂ film 304 is formed by steam oxidation at about 800 to 900 ° C. Further, a Si ₃ N ₄ film 305 having a film thickness of about 110 to 120 nm is formed on the entire surface of the P-type substrate 203 by a low pressure CVD method. On the SiO ₂ film 304 and the Si ₃ N ₄ film 305, a photoresist layer 306 patterned to have an opening in an element isolation layer (LOCOS) formation region by a known photolithography technique is formed.

By etching using the photoresist layer 306 as a mask, the SiO ₂ film 304 and the Si ₃ N ₄ film 305 remain only on the active region. The state after etching is shown in FIG. This etching can be performed by a known etching method, for example, reactive ion etching (RIE). In this embodiment, after removing the photoresist layer 306, steam oxidation at about 950 to 1000 ° C. is performed to form a LOCOS 307 of an oxide film of about 400 to 600 nm. Subsequently, the Si ₃ N ₄ film 305 is removed by hot phosphoric acid, and the SiO ₂ film 304 is removed using a hydrofluoric acid (HF) chemical solution. Through the above steps, the structure shown in FIG.

  Next, in this embodiment, the gate oxide film 101c is formed on the surface of the N-type well 202 by performing thermal oxidation at 800 to 900 ° C. on the structure shown in FIG. Next, a conductive polysilicon layer (not shown) having a thickness of about 350 to 400 nm is formed on the entire surface of the P-type substrate 203 by the CVD method. Thereafter, a photoresist layer 310 is formed in the gate region by a known photolithography technique. When the conductive polysilicon layer other than the gate region is removed by a known etching method using the photoresist layer 310 as a mask, the gate electrode 101a is formed. FIG. 4E is a diagram illustrating the state of the semiconductor device of the present embodiment after the formation of the gate electrode 101a.

Next, in this embodiment, after the removal of the photoresist layer 310, a photoresist layer 311 having an opening in the P-type body impurity implantation region is formed by a known photolithography technique. In the P-type body impurity implantation region, boron (B) is about 1 × 10 ¹³ to 1 × 10 ¹⁴ / cm ^{2 and is} inclined at 45 ° or 30 ° with respect to a plane perpendicular to the P-type substrate 203. Ion implanted. P type body impurity region 105 shown in FIG. 4B is formed by ion implantation.

Further, in this embodiment, arsenic (As) is ion-implanted by about 1 × 10 ¹³ to 1 × 10 ¹⁴ / cm ² using the photoresist layer 311 as a mask, and an N ⁺ type source low resistance impurity implantation region 321 is formed. The In this ion implantation, the P-type body impurity region 105 and the N ⁺ -type source low resistance impurity implanted region 321 are formed in a self-aligned manner using the gate electrode 101a as a mask. According to the present embodiment, high-precision processing can be performed without being affected by mask misalignment that occurs in a photolithography process performed by mask patterning for ion implantation.

After the removal of the photoresist layer 311, a compliant oxide is deposited on the upper side of the gate electrode 101a and its periphery. As this oxide, for example, tetraethyl-orthosilicate (TEOS) or TEOS / O ₃ oxide is used. Next, the deposited oxide is anisotropically etched by RIE, and oxide spacers 101b are formed on the side surfaces of the gate electrode 101a. Through the above steps, the structure shown in FIG.

FIGS. 5 to 12 are diagrams for explaining the process executed subsequent to FIG. 4-2 (g) separately for the P ⁺ -type impurity region 102a and the N ⁺ -type source 102b shown in FIG. is there. 5 to 12, (a) is a top view of the completed semiconductor device of this embodiment, and (b) is a line segment DD ′ or a line segment EE ′ shown in (a). It is sectional drawing of the semiconductor device of the manufacturing process in alignment. Line segment DD ′ and line segment EE ′ indicate the positions of the cross-sectional views of the manufacturing process on the completed semiconductor device. Line segment DD ′ and line segment E shown in FIG. Matches -E '.

In this embodiment, as shown in FIG. 5B, a photoresist layer 401 having openings in the formation regions of the N ⁺ -type source 102b and the drain 104 shown in FIG. 5A by a known photolithography technique. Is formed. Note that FIG. 5B is a cross-sectional view taken along the line EE ′ on the P ⁺ -type impurity region 102a, and therefore the opening on the N ⁺ -type source 102b is not shown.

Arsenic (As) of about 1 × 10 ¹⁵ to 1 × 10 ¹⁶ / cm ² is ion-implanted into a region where the N ⁺ -type source 102 b is formed and a region where the drain 104 is formed. FIG. 5B shows a state in which an N ⁺ -type drain impurity implantation region 322 is formed in the drain 104 formation region by ion implantation.
FIG. 6 is a cross-sectional view along the line DD ′ in the same process as FIG. As shown in FIG. 6 (b), in the section taken along the line D-D ', together with the N ⁺ -type drain impurity implantation region 322 by ion implantation, the N ⁺ type source impurity implanted region 323 is formed.

In the present embodiment, as shown in FIG. 7B, a photoresist layer 601 having an opening in the P ⁺ -type impurity region 102a is formed by a known photolithography technique. Then, boron (B) of about 1 × 10 ¹⁵ to 1 × 10 ¹⁶ / cm ² is ion-implanted using the photoresist layer 601 as a mask. A P + type impurity implantation region 324 is formed by ion implantation.

Boron ions (P-type impurities) for forming the P ⁺ -type impurity implantation region 324 are implanted into the N ⁺ -type source low resistance impurity implantation region 321. Dose of P-type impurity, N ⁺ for type 10 to 100 times the N-type impurity of the source resistance impurity implanted region 321, P ⁺ -type P ⁺ region within the N ⁺ type source resistance impurity implanted region 321 An impurity implantation region 324 can be formed.

Further, since the oxide spacer 101b shown in FIG. 7B serves as a mask for the P-type impurity, the region under the oxide spacer 101b becomes an N ⁺ region without being affected by the P-type impurity. Thus, in this embodiment, the N ⁺ type source low resistance impurity implanted region 321 is formed between the P ⁺ type impurity implanted region 324 and the P type body impurity region 105 under the gate 101 where the channel is formed. Can do.

FIG. 8B is a cross-sectional view taken along the line DD ′ of the semiconductor device in the same process as FIG. As shown in FIG. 8B, the photoresist layer 601 does not have an opening on the P ⁺ -type impurity region 102a. For this reason, in this embodiment, boron ions are not implanted into the N ⁺ -type source impurity implantation region 21.
Next, the photoresist 601 shown in FIGS. 7B and 8B is removed, and then a heat treatment at about 800 to 900 ° C. is performed on the structure shown in FIGS. By the heat treatment, arsenic in the N ⁺ -type source low resistance impurity implantation region 321, the N ⁺ -type drain impurity implantation region 322, and the N ⁺ -type source impurity implantation region 323 and boron in the P ⁺ -type impurity implantation region 324 are diffused.

Due to impurity diffusion, the N ⁺ type source low resistance impurity implantation region 321 is an N ⁺ type source low resistance region 110, the N ⁺ type drain impurity implantation region 322 is a drain 104, and the N ⁺ type source impurity implantation region 323 is an N ⁺ type source. 102b. Also, the P ⁺ -type impurity implantation region 324 becomes the P ⁺ -type impurity region 102a. Through the above steps, the structure shown in FIGS. 9 and 10 is manufactured.
11 and 12 are diagrams for explaining a process of forming a wiring in the semiconductor device manufactured by the process described above. As shown in FIGS. 11B and 12B, in this embodiment, an interlayer insulating film (SiO ₂ film) of about 600 to 700 nm is formed after the formation of the P ⁺ -type impurity region 102a and the N ⁺ -type source 102b. 100 is deposited on the entire surface. The interlayer insulating film 100 can be deposited by, for example, a CVD method.

Next, in this embodiment, a photoresist layer (not shown) having an opening on the P ⁺ -type impurity region 102a, the N ⁺ -type source 102b, and the drain 104 is formed on the interlayer insulating film 100 by a known photolithography technique. Formed by. The interlayer insulating film 100 is etched by a known etching method, for example, RIE, using the photoresist layer as a mask. After the removal of the photoresist layer, a wiring metal layer including a barrier metal layer, such as Ti / TiN or AL, is deposited in the electrode forming opening formed in the interlayer insulating film 100.
Further, the wiring 201 is formed by patterning the wiring metal layer by a known photolithography technique and RIE. Through the above steps, the semiconductor device of this embodiment shown in FIGS. 11 and 12 can be obtained.

  The present invention can be applied to a DMOS transistor and a method for manufacturing a DMOS transistor, and is particularly suitable for a method for manufacturing a DMOS transistor and a DMOS transistor in which a cell pitch is desirably short.

100 Interlayer insulation film 101 Gate 101a Gate electrode 101b Oxide spacer 101c Gate oxide film 102 Source 102a P ⁺ type impurity region 102b N ⁺ type source 104 Drain 105 P type body impurity region 110 N ⁺ type source low resistance region 201 Wiring 202 ′ P-type well impurity implantation region 202 N-type well 203 P-type substrate 301, 304 SiO ₂ film 302 ′ P-type well impurity implantation region 302 P-type wells 303, 306, 310, 311, 401, 601 Photoresist layer 305 Si ₃ N ₄ films 321 N ⁺ type source low resistance impurity implantation region 322 N ⁺ type drain impurity implantation region 323 N ⁺ type source impurity implantation region 324 P ⁺ type impurity implantation region

Claims (1)

A gate forming step of forming a gate on the surface of the semiconductor layer of the first conductivity type via a gate dielectric film;
A body forming step of implanting impurities using the gate as a mask to form a body impurity region of a second conductivity type;
A low-resistance impurity region forming step of implanting impurities into the body impurity region formed in the body forming step using the gate as a mask to form a low-resistance impurity region of a first conductivity type in the body impurity region; ,
After the low resistance impurity region forming step, a spacer forming step of forming a spacer on the peripheral surface of the gate;
A source region forming step of forming a first conductivity type source region and a first conductivity type drain by implanting impurities into a predetermined region in the low resistance impurity region;
Impurities are implanted into the low-resistance impurity region adjacent to the source region, the periphery is surrounded by the low-conductivity impurity region of the first conductivity type and the source region of the first conductivity type, and the body impurity region and the impurity region forming step of forming an impurity region of the second conductivity type which electrically connects, only including,
In the source region forming step and the impurity region forming step, impurities are implanted using the spacer as a mask .

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