JP5857869B2 - Level conversion circuit - Google Patents

Description

  The present invention relates to a level conversion circuit that converts a signal level.

  In recent years, highly integrated semiconductor devices often have a low operating voltage of a logic circuit and are connected to an external circuit via a level conversion circuit provided in an interface unit. For example, when the operating voltage of the logic circuit in the semiconductor device is 1.2 V and the operating voltage of the external circuit connected to the semiconductor device is 3.3 V, a 1.2 V signal is converted into a 3.3 V signal. A level conversion circuit is used.

  This type of level conversion circuit is generally formed using a transistor having a breakdown voltage of 3.3 V or higher. However, if a transistor with a high withstand voltage is used, the degree of integration of the semiconductor device is reduced. Therefore, a level conversion circuit may be formed by using a transistor with a withstand voltage lower than 3.3V.

WO2004 / 077674 JP 2000-269432 A

  It is an object of the present invention to provide a level conversion circuit in which destruction of elements is avoided regardless of the order in which voltages are supplied to each power supply line.

According to an aspect of the disclosed technology, a first power supply line to which a first voltage is supplied, a second power supply line to which a second voltage higher than the first voltage is supplied, and the first power supply line The level of the input signal connected to the third power line, the fourth power line, the first power line, and the second power line to which a third voltage higher than the voltage 2 is supplied. A first level shifter that converts the level of a signal that is connected to the third power line and the fourth power line and that is output from the first level shifter; and And a protection circuit connected to the first power supply line, the second power supply line, the third power supply line, and the fourth power supply line, and the protection circuit includes the third power supply line and the third power supply line. 2 connected in series between two power lines A transistor and a first resistor; and a second resistor and a third resistor connected in series between the third power supply line and the second power supply line; Level conversion wherein a gate is connected to a connection between the second resistor and the third resistor, and a connection between the transistor and the first resistor is connected to the fourth power supply line A circuit is provided.

  According to the level conversion circuit according to the above aspect, the voltage difference between the third power supply line and the fourth power supply line is an element connected between the third power supply line and the fourth power supply line. A protection circuit which prevents the voltage from exceeding the withstand voltage. Thereby, destruction of the element can be avoided regardless of the order in which the voltage is supplied to each power supply line.

FIG. 1 is a block diagram illustrating an example of a level conversion circuit. FIG. 2 is a diagram (part 1) illustrating a voltage change of a node indicated by N1 in FIG. FIG. 3 is a diagram (part 2) illustrating a voltage change of a node indicated by N1 in FIG. FIG. 4 is a block diagram of the level conversion circuit according to the embodiment. FIG. 5 is a circuit diagram illustrating a specific example of the level conversion circuit according to the embodiment. FIG. 6 is a circuit diagram showing an example of a bias voltage generation circuit. FIG. 7 is a diagram (part 1) showing the result of simulation calculation of the voltage change of each power supply line and the node N1. FIG. 8 is a diagram (part 2) illustrating the result of simulation calculation of the voltage change of each power supply line and the node N1.

  Hereinafter, before describing the embodiment, a preliminary matter for facilitating understanding of the embodiment will be described.

  FIG. 1 is a block diagram illustrating an example of a level conversion circuit.

  The level conversion circuit 10 illustrated in FIG. 1 includes a first level shifter 11, a second level shifter 12, a first driver circuit 13, a second driver circuit 14, a bias voltage generation circuit 19, and an output transistor. Q1-Q4.

  The first level shifter 11 and the first driver circuit 13 are connected to the first power supply line 16 and the second power supply line 17, and the second level shifter 12 and the second driver circuit 14 are connected to the second power supply line 17 and the second power supply line 17. The third power line 18 is connected. Here, it is assumed that the voltage of the first power supply line 16 is 0V, the voltage of the second power supply line 17 is 1.8V, and the voltage of the third power supply line 18 is 3.3V.

  The output transistors Q1 and Q2 are p-type MOS transistors and are connected in series between the third power supply line 18 and the output terminal OUT. The output transistors Q3 and Q4 are n-type MOS transistors and are connected in series between the output terminal OUT and the first power supply line 16. The gate of the output transistor Q1 is connected to the output of the second driver circuit 14, the gates of the output transistors Q2 and Q3 are connected to the second power supply line 17, and the gate of the output transistor Q4 is the output of the first driver circuit 13. It is connected to the.

  The first level shifter 11 receives the signal A and its inverted signal AX from the internal circuit. Here, the signals A and AX are digital signals having an “L” level of 0V and an “H” level of 1.2V.

  The first level shifter 11 converts the “L” level of the signals A and AX to 0V and the “H” level to 1.8V, and outputs them as signals A1 and AX1. The signal AX1 output from the first level shifter 11 is transmitted to the gate of the output transistor Q4 via the first driver circuit 13.

  The second level shifter 12 receives the signals A1 and AX1 from the first level shifter 11, and converts the "L" level to 1.8V and the "H" level to 3.3V. Then, the “H” level or “L” level signal output from the second level shifter 12 is transmitted to the gate of the output transistor Q 1 via the second driver circuit 14.

  The bias voltage generation circuit 19 generates a bias voltage for turning on and off the transistors in the second level shifter 12.

  In the level conversion circuit 10 described above, one of the output transistors Q1 and Q2 and the output transistors Q3 and Q4 is turned on and the other is turned off according to the signals A and AX. When the transistors Q1 and Q2 are on, the voltage at the output terminal OUT is 3.3V, and when the transistors Q3 and Q4 are on, the voltage at the output terminal OUT is 0V. In this case, in any of the first level shifter 11, the second level shifter 12, the first driver circuit 13, the second driver circuit 14, and the output transistors Q1 to Q4, the maximum value of the applied voltage is 1.8V or less. Become. Therefore, the level conversion circuit 10 shown in FIG. 1 can be formed with a transistor having a breakdown voltage of about 2V.

  By the way, in the level conversion circuit 10 described above, the order of rising of the voltages supplied to the second power supply line 17 and the third power supply line 18 is important. The reason will be described below.

  FIG. 2 is a diagram showing a change in the voltage of the node indicated by N1 in FIG. 1, that is, a change in the gate voltage of the output transistor Q1, with time on the horizontal axis and voltage on the vertical axis. 2, the voltage of 1.8V supplied to the second power supply line 17 rises 2 ns after the first power supply line 16 becomes 0V, and is supplied to the third power supply line 18 after 6 ns. The voltage change of the node N1 when the voltage of 3V rises is shown.

  In this case, the voltage difference between the node N1 and the second power supply line 17 and the third power supply line 18 is less than 2V, which is lower than the withstand voltage of the output transistor Q1. Therefore, when the voltage rises in the order of the first power supply line 16, the second power supply line 17, and the third power supply line 18, the output transistor Q1 is not destroyed.

  FIG. 3 is a diagram showing a voltage change of the node N1 with time on the horizontal axis and voltage on the vertical axis. However, in FIG. 3, the voltage of 3.3 V supplied to the third power supply line 19 rises 2 ns after the first power supply line 16 becomes 0 V, and is supplied to the second power supply line 17 after 6 ns. The voltage change of the node N1 when the voltage of 1.8V rises is shown.

  In this case, as shown in FIG. 3, the voltage at the node N1 rises simultaneously with the rise of the voltage of the third power supply line 18, but the voltage difference between the node N1 and the third power supply line 19 is about 3 thereafter. .3V. For this reason, the output transistor Q1 having a breakdown voltage of about 2V is destroyed.

  In the following embodiments, a level conversion circuit that prevents destruction of elements regardless of the order in which the voltages are supplied to the respective power supply lines will be described.

(Embodiment)
FIG. 4 is a block diagram of the level conversion circuit according to the embodiment, and FIG. 5 is a circuit diagram showing a specific example of the level conversion circuit. In the present embodiment, a level conversion circuit applied to an interface unit of a semiconductor device (LSI) is described.

  The level conversion circuit 20 illustrated in FIGS. 4 and 5 includes a first level shifter 21, a second level shifter 22, a first driver circuit 23, a second driver circuit 24, a protection circuit 25, and a bias. A voltage generation circuit 29 and output transistors Q1 to Q4 are provided.

  The first level shifter 21 and the first driver circuit 23 are connected to the first power supply line 26 and the second power supply line 27, and power is supplied from these power supply lines 26 and 27. The protection circuit 25 is connected to the first power supply line 26, the second power supply line 27, the third power supply line 28, and the fourth power supply line 31, and has substantially the same voltage as the second power supply line 27. Is supplied to the fourth power supply line 31.

  The second level shifter 22 and the second driver circuit 24 are connected to the fourth power supply line 31 and the third power supply line 28, and power is supplied from these power supply lines 31 and 28. Here, the voltage of the first power supply line 26 is 0V, the voltage of the second power supply line 27 is 1.8V, the voltage of the third power supply line 28 is 3.3V, and the voltage of the fourth power supply line 31 is 1. Suppose that it is 8V.

  The output transistors Q1 and Q2 are p-type MOS transistors and are connected in series between the third power supply line 28 and the output terminal OUT. The gate of the output transistor Q 1 is connected to the output of the second driver circuit 24, and the gate of the output transistor Q 2 is connected to the fourth power supply line 31.

  The output transistors Q3 and Q4 are n-type MOS transistors and are connected in series between the output terminal OUT and the first power supply line 26. The gate of the output transistor Q3 is connected to the second power supply line 27, and the gate of the output transistor Q4 is connected to the output of the first driver circuit 23.

  As shown in FIG. 5, the first level shifter 21 is formed of n-type MOS transistors Q11 and Q13 and p-type MOS transistors Q12 and Q14. The source of the transistor Q11 is connected to the first power supply line 26, and the drain is connected to the drain of the transistor Q12 and the gate of the transistor Q14. The gate of the transistor Q11 is connected to a terminal to which the inverted signal AX is input.

  The source of the transistor Q12 is connected to the second power supply line 27, and the gate is connected to the drains of the transistors Q13 and Q14. The source of the transistor Q13 is connected to the first power supply line 26, and the gate is connected to a terminal to which the signal A is input. Further, the source of the transistor Q14 is connected to the second power supply line 27.

  A connection portion between the drain of the transistor Q11 and the drain of the transistor Q12 is connected to the second level shifter 24 as one output of the first level shifter 21. Further, a connection portion between the drain of the transistor Q13 and the drain of the transistor Q14 is connected to the first driver circuit 23 and the second level shifter 24 as the other output of the first level shifter 21.

  The second level shifter 22 is formed by p-type MOS transistors Q21, Q23, Q24, Q26 and n-type MOS transistors Q22, Q25.

  The source of the transistor Q23 is connected to the third power supply line 28, and the transistor Q22 and the transistor Q23 are connected in series between the drain of the transistor Q23 and the fourth power supply line 31. The source of the transistor Q26 is connected to the third power supply line 28, and the transistor Q25 and the transistor Q24 are connected in series between the drain of the transistor Q26 and the fourth power supply line 31.

  One output of the first level shifter 21 is transmitted to the gate of the transistor Q21, and the other output of the first level shifter 21 is transmitted to the gate of the transistor Q24. The gates of the transistors Q22 and Q25 are connected to the bias voltage generating circuit 29. Further, the gate of the transistor Q23 is connected to the drain of the transistor Q26. The gate of the transistor Q26 is connected to the drain of the transistor Q23, and is further connected to the second driver circuit 24 as the output of the second level shifter 22.

  The second driver circuit 24 is formed by two inverters 34a and 34b connected in series. The inverters 34a and 34b are supplied with power from the third power supply line 28 and the fourth power supply line 31, and transmit a signal output from the second level shifter 22 to the gate of the output transistor Q1.

  On the other hand, the first driver circuit 23 is formed by a plurality (five in FIG. 5) of inverters 32a to 32e connected in series. The inverters 32a to 32e are supplied with electric power from the first power supply line 26 and the second power supply line 27, and transmit the signal output from the first level shifter 21 to the gate of the output transistor Q4.

  The bias voltage generation circuit 29 generates a bias voltage for turning on and off the transistors Q22 and Q25. For example, as shown in FIG. 6, the bias voltage generation circuit 29 is formed by two resistance values Rb1 and Rb2 connected between a first power supply line 26 and a third power supply line 28, and a resistor Rb1. , Rb2 is connected to the gates of the transistors Q22 and Q25. When the voltage of the first power supply line 26 is 0V and the voltage of the third power supply line 28 is 3.3V, the bias voltage generation circuit 29 generates a bias voltage Vb of 2.7V, for example.

  The protection circuit 25 is formed by p-type MOS transistors Q51 and Q52, an n-type MOS transistor Q53, resistors R1 to R4, and a capacitor C1.

  The resistors R2 and R3 are connected in series between the third power supply line 28 and the second power supply line 27. A connection portion (node G) between the resistors R2 and R3 is connected to the gate of the transistor Q51 and the gate of the transistor Q52.

  The source of the transistor Q51 is connected to the third power supply line 28, and a resistor R1 is connected between the drain of the transistor Q51 and the second power supply line 27. A connection portion between the drain of the transistor Q51 and the resistor R1 is connected to the fourth power supply line 31.

  The source of the transistor Q52 is connected to the third power supply line 28, and the drain is connected to the gate of the transistor Q53. Further, a resistor R4 is connected between the drain of the transistor Q52 and the first power supply line 26.

  The transistor Q53 is connected between the first power supply line 26 and the second power supply line 27, and the capacitor C1 is also connected between the first power supply line 26 and the second power supply line 27.

  In the present embodiment, when a voltage is supplied in the order of the second power supply line 27 and the third power supply line 28, the transistor Q51 is turned off, and in the order of the third power supply line 28 and the second power supply line 27. When the voltage is supplied, the transistor Q51 is turned on. Specifically, the resistance values of the resistors R2 and R3 are determined by the following procedure.

  When voltages are supplied in the order of the third power supply line 28 and the second power supply line 27, assuming that the voltage of the fourth power supply line 31 is 0 V, the voltage Vg1 at the node indicated by G in FIG. 1) It is represented by the formula.

Vg1 = (3.3-0) × R2 / (R3 + R2) (1)
Since the voltage Vg1 at this time is a voltage for turning on the transistor Q51, if the threshold voltage of the transistor Q51 is Vth, the voltage Vg1 needs to satisfy the following inequality (2).

3.3- | Vth |> Vg1 (2)
On the other hand, when the voltage is supplied in the order of the second power supply line 27 and the third power supply line 28, the voltage Vg2 of the node G is expressed by the following equation (3).

Vg2 = 1.8 + (3.3-1.8) × R2 / (R3 + R2) (3)
Since the voltage Vg2 at this time is a voltage for turning off the transistor Q51, the voltage Vg2 needs to satisfy the following inequality (4).

3.3- | Vth | <Vg2 (4)
Therefore, the resistance values of the resistors R2 and R3 are determined so as to satisfy these equations (1) to (4). However, after the voltages of the first to fourth power supply lines 21, 27, 28, and 31 reach predetermined values, static currents flow through the resistors R2 and R3. When the current flowing through the resistors R2 and R3 is large, power is consumed wastefully, so it is important to consider the current flowing through the resistors R2 and R3 when determining the resistance values of the resistors R2 and R3. It is.

  On the other hand, the resistance value of the resistor R1 and the size of the transistor Q51 are determined according to the withstand voltage ΔVh of the element connected to the fourth power supply line 31. Here, the voltage of the fourth power supply line 31 before the voltage of 1.8V is supplied to the second power supply line 27 and when the voltage of 3.3V is supplied to the third power supply line 28. Is Vh.

  In this embodiment, as described above, when the voltage of 3.3V is supplied to the third power supply line 28 before the voltage of 1.8V is supplied to the second power supply line 27, the transistor Q51 is turned on. The resistance values of the resistors R2 and R3 are determined so that Here, when the current flowing through the transistor Q51 when the transistor Q51 is on is Ih and the voltage of the second power supply line 27 is 0V, the voltage Vh of the fourth power supply line 31 is Vh = Ih × R1. .

  In order for each element connected between the third power supply line 28 and the fourth power supply line 31 not to be destroyed, the value of (3.3-Vh) needs to be smaller than the withstand voltage ΔVh of each element. It is. In order to satisfy this condition, the resistance value of the resistor R1 and the element size of the transistor Q51 through which the current Ih flows are determined.

  Note that when the transistor Q51 is turned on, the transistor Q52 is also turned on, and the gate voltage of the transistor Q53 increases. As a result, the transistor Q53 is turned on and the first power supply line 26 and the second power supply line 27 are electrically connected, and the voltage of the second power supply line 27 becomes the voltage (0V) of the first power supply line 26. ).

  FIG. 7 shows a simulation of voltage changes in the power supply lines 26, 27, 28, and 31 and the node N1 when the voltage rises in the order of the first power supply line 26, the second power supply line 27, and the third power supply line 28. It is a figure showing the result of calculation. Here, a voltage of 1.8 V is supplied to the second power supply line 27 2 ns after the voltage of the first power supply line 26 becomes 0 V, and a voltage of 3.3 V is applied to the third power supply line 28 after 6 ns. It is supposed to be supplied.

  When the voltage rises in the order of the first power supply line 26, the second power supply line 27, and the third power supply line 28, as shown in FIG. 7, the second power supply line 28 is between 2 ns and 2.3 ns. Is changed from 0V to 1.8V. Before the voltage supplied to the third power supply line 31 rises, the voltage of the fourth power supply line 31 is about 0.8V. When the voltage of the third power supply line 28 becomes 3.3V, the voltage of the fourth power supply line 31 becomes about 1.805V.

  As can be seen from FIG. 7, the voltage difference between the second power supply line 27, the third power supply line 28, the fourth power supply line 31, and the node N1 is 2 V or less. The voltage difference between the first power supply line 26 and the second power supply line 27 and the voltage difference between the third power supply line 28 and the fourth power supply line 31 are also 2 V or less. For this reason, even if the breakdown voltage of each element forming the level shifter circuit 20 is about 2 V, the element is not destroyed.

  FIG. 8 shows a simulation of voltage changes in the power supply lines 26, 27, 28, and 31 and the node N1 when the voltage rises in the order of the first power supply line 26, the third power supply line 28, and the second power supply line 27. It is a figure showing the result of calculation. Here, a voltage of 3.3 V is supplied to the third power supply line 28 2 ns after the voltage of the first power supply line 26 becomes 0 V, and a voltage of 1.8 V is applied to the second power supply line 28 after 6 ns. It is supposed to be supplied.

  When a voltage of 3.3V is supplied to the third power supply line 28, the transistor Q51 is turned on, a current flows through the resistor R1, and the voltage of the fourth power supply line 31 becomes about 1.5V. For this reason, each element connected between the third power supply line 28 and the fourth power supply line 31 only takes a voltage of about 1.8V. Also in this case, each element forming the level shifter circuit 20 is not destroyed.

  DESCRIPTION OF SYMBOLS 10,20 ... Level conversion circuit 11, 12, 21, 22 ... Level shifter 13, 14, 23, 24 ... Driver circuit, 16, 26 ... First power supply line, 17, 27 ... Second power supply line, 18 , 28 ... third power supply line, 19, 29 ... bias voltage generation circuit, 25 ... protection circuit, 31 ... fourth power supply line, 32a to 32e, 34a, 34b ... inverter.

Claims (4)

A first power supply line to which a first voltage is supplied;
A second power supply line to which a second voltage higher than the first voltage is supplied;
A third power supply line to which a third voltage higher than the second voltage is supplied;
A fourth power line;
A first level shifter connected to the first power supply line and the second power supply line for converting the level of an input signal;
A second level shifter that is connected to the third power supply line and the fourth power supply line and converts a level of a signal output from the first level shifter;
A protection circuit connected to the first power line, the second power line, the third power line, and the fourth power line;
The protection circuit is
A transistor and a first resistor connected in series between the third power supply line and the second power supply line;
A second resistor and a third resistor connected in series between the third power supply line and the second power supply line;
A gate of the transistor is connected to a connection portion between the second resistor and the third resistor, and a connection portion between the transistor and the first resistor is connected to the fourth power supply line. level conversion circuit characterized in that there. The protection circuit is
After the first voltage is supplied to the first power supply line, the second voltage is supplied to the second power supply line before the third voltage is supplied to the third power supply line. The transistor is turned off when
After the first voltage is supplied to the first power supply line, the third voltage is supplied to the third power supply line before the second voltage is supplied to the second power supply line. 2. The level conversion circuit according to claim 1 , wherein the transistor is turned on when it is set. The protection circuit, when the transistor is turned on, according to claim 1 or 2, characterized in that it comprises a circuit for connecting said second power supply line and said first power supply line electrically Level conversion circuit. A first output transistor connected between the third power supply line and an output terminal;
A second output transistor connected between the output terminal and the first power supply line;
A first driver circuit for transmitting a signal output from the first level shifter to the second output transistor;
4. The level conversion circuit according to claim 1, further comprising: a second driver circuit configured to transmit a signal output from the second level shifter to the first output transistor. 5.

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