JP5858889B2 - Solar cell substrate, method for manufacturing the same, solar cell and method for manufacturing the same - Google Patents

Description

  The present invention relates to a solar cell substrate, a manufacturing method thereof, a solar cell, and a manufacturing method thereof, and in particular, a solar cell substrate having a concavo-convex portion (texture) constituting an antireflection structure, a solar cell, and a solar cell manufacturing method. About.

  In a solar cell that converts incident light into electricity by a photoelectric conversion unit, if the light reflection at the surface is large, the light that enters the solar cell is reduced, and the power obtained is also reduced. Therefore, in order to increase the photoelectric conversion efficiency of the solar cell, it is important to reduce the light reflectivity on the surface and capture more light. In order to reduce the light reflectance, for example, it is effective to provide an antireflection film on the surface of the solar cell.

  However, even if an antireflection film is used, loss due to reflection of several percent of incident light occurs. Therefore, a minute uneven part called a texture is formed on the surface of the solar cell to reduce the reflectance by the light confinement effect. Yes.

  For example, single crystal silicon can easily form a random pyramid-shaped uneven portion as a texture by performing anisotropic etching using an alkaline solution. By these methods, it is possible to significantly reduce the light reflectivity on the surface of the solar cell by the effect of light confinement by multiple scattering.

  Conventionally, in a solar cell using a crystalline silicon substrate such as a single crystal silicon substrate, a pyramidal uneven portion caused by a {111} plane is obtained by etching the surface of a silicon (100) substrate by anisotropic etching. Form.

  On the other hand, a heterojunction solar cell technology in which an amorphous silicon layer or a microcrystalline silicon layer is stacked on a single crystal silicon substrate to form a pn junction is disclosed (Patent Document 1). However, in such a heterostructure, many defects are generated at the heterojunction interface, and the generated carriers are recombined. Therefore, there is a problem that high conversion efficiency cannot be obtained. Therefore, a solar cell technology is disclosed in which a thin intrinsic amorphous silicon layer is sandwiched between a single crystal silicon substrate and an amorphous silicon substrate to reduce defects at the heterojunction interface (Patent Document 2). .

  However, even in the solar cell structure as in Patent Document 2, since the {111} plane constituting the texture surface is not flat at the atomic level, defects may occur in the amorphous silicon layer formed on the substrate. It has been confirmed that an epitaxial layer partially containing crystals is formed.

  Thus, various techniques for solving the above problems have been disclosed. In Patent Document 3, the above problem is solved by having a step portion and a terrace portion that can be defined on the {111} surface. In Patent Document 4, the {111} surface is composed of a terrace portion and a step portion, and an epitaxial layer having a height of 2 nm or less is formed between the amorphous layer and the substrate to solve the above problem. Furthermore, in patent document 5, the said problem is solved by making the unevenness | corrugation height of a {111} surface into 2 nm or less.

JP 59-175170 A Japanese Patent Publication No. 7-95603 Japanese Patent Laid-Open No. 2004-221142 Japanese Patent No. 4660561 JP 2009-164625 A

  However, as a result of intensive studies, we have found that the cell characteristics may be deteriorated even when the height of the stepped portion and the uneven portion on the {111} surface is low. This is because even if the step height or unevenness height of the {111} surface is suppressed to 2 nm or less, due to the steep shape, defects and epitaxial portions are formed from the step portion to the crystalline substrate-amorphous film interface and in the film. It is thought that this is because it occurs.

  Therefore, the present invention has an object to obtain a textured solar cell substrate, a manufacturing method thereof, a solar cell, and a manufacturing method thereof that capture the surface roughness shape of the {111} surface in three dimensions and give high photoelectric conversion efficiency. And

To solve the above problems and achieve the object, a solar cell according to the present invention, the average surface roughness in the pyramid sides of the pyramid-shaped concave and convex portion formed on crystalline substrate surface and the (Ra), spatial All the ratios (λ / Ra) of the periods (λ) are 100 or more.

According to the present invention, the crystal system front surface shape of the substrate is slowed with the uneven portion as a texture, since sharp shape change point, such as a terrace / step does not exist, amorphous it was the core Generation of defects in the silicon layer and formation of the epitaxial layer are suppressed. As a result, the texture substrate-amorphous silicon film interface and defects in the film are reduced, and the cell characteristics such as the open circuit voltage (Voc) and fill factor (FF) of the solar cell are improved.

FIG. 1 is a cross-sectional view showing a schematic configuration of a solar cell according to Embodiment 1 of the present invention. FIG. 2 is an enlarged perspective view of the surface of the solar cell substrate (n-type single crystal silicon substrate) according to Embodiment 1 of the present invention. FIGS. 3-1 is sectional drawing which shows the manufacturing method of the solar cell of Embodiment 1 of this invention. FIGS. 3-2 is sectional drawing which shows the manufacturing method of the solar cell of Embodiment 1 of this invention. FIGS. 3-3 is sectional drawing which shows the manufacturing method of the solar cell of Embodiment 1 of this invention. 3-4 is sectional drawing which shows the manufacturing method of the solar cell of Embodiment 1 of this invention. 3-5 is sectional drawing which shows the manufacturing method of the solar cell of Embodiment 1 of this invention. FIGS. 3-6 is sectional drawing which shows the manufacturing method of the solar cell of Embodiment 1 of this invention. FIG. 4 is a flowchart showing manufacturing steps of the solar cell according to Embodiment 1 of the present invention. FIG. 5 is an atomic force microscope measurement result of the {111} plane of the texture substrate when IPA is used as the organic substance in the texture liquid. FIG. 6 is an atomic force microscope measurement result of the {111} plane of the texture substrate when sulfonic acid is used as the organic substance in the texture liquid. FIG. 7 is an image of the shape of the {111} surface when Ra is aligned and changed by λ. FIG. 8 is a shape image diagram of the {111} surface when Ra of a component having a short spatial period is halved from the case of FIG. FIG. 9 is a flowchart showing manufacturing steps of the solar cell according to the second embodiment of the present invention. FIG. 10 is a flowchart showing manufacturing steps of the solar cell according to the third embodiment of the present invention.

  EMBODIMENT OF THE INVENTION Below, the board | substrate for solar cells concerning this invention, the solar cell using the same, and embodiment of the manufacturing method of a solar cell are described in detail based on drawing. In addition, this invention is not limited to the following description, In the range which does not deviate from the summary of this invention, it can change suitably. In the drawings shown below, the scale of each member may be different from the actual scale for easy understanding.

Embodiment 1 FIG.
FIG. 1 is a cross-sectional view showing a schematic configuration of a solar cell according to Embodiment 1 of the present invention. In this solar cell, an n-type single crystal silicon substrate having a specific resistance of 1 to 10 Ω · cm, a crystal orientation plane composed of (100) as a main surface (first surface 1A), and a thickness of 50 μm to 300 μm 1 is used. On the surface of the n-type single crystal silicon substrate 1, a texture (uneven portion 1T) composed of {111} planes of λ / Ra ≧ 100 or more is processed.

  Here, λ is the surface shape waveform of the {111} surface obtained by measuring the {111} surface (side surface S) of the textured substrate, that is, the n-type single crystal silicon substrate 1 on which the concavo-convex portion is formed, with an atomic force microscope. This refers to the spatial period obtained by Fourier transforming a curve. Ra refers to the average surface roughness of the {111} plane obtained by measuring the {111} surface of the texture substrate with an atomic force microscope. The {111} plane, which is the crystal lattice plane of the Miller index {111}, refers to a plane group equivalent to the crystal lattice plane of the Miller index (111), and the Miller index (−111), (1-11), (− 1-11) and the like. FIG. 2 shows an enlarged perspective view of the surface of the n-type single crystal silicon substrate 1. In the atomic force microscope measurement in this embodiment, the surface of the n-type single crystal silicon substrate 1 {111} as a texture substrate is measured using a probe having a tip tip radius of 10 nm or less and a height of about 10 μm or more. did. In the measurement, the height h of the step portion and the period λ in the {111} plane (side S) are measured by scanning a 500 nm × 500 nm region of the n-type single crystal silicon substrate 1 {111} surface, and the average value thereof Was calculated.

  I-type amorphous silicon layers 2a and 2b each having a thickness of about 5 nm are formed on both surfaces of the first surface 1A and the second surface 1B of the n-type single crystal silicon substrate 1 subjected to the uneven processing. ing. A p-type amorphous silicon layer 3 having a thickness of about 5 nm is formed on the i-type amorphous silicon layer 2a. A thickness of about 5 nm is formed on the i-type amorphous silicon layer 2b formed on the second surface 1B opposite to the first surface 1A side where the p-type amorphous silicon layer 3 is formed. The n-type amorphous silicon layer 4 is formed. Here, the i-type amorphous silicon layers 2a and 2b act to reduce the interface state of the substrate surface. The n-type amorphous silicon 4 is a BSF (Back Surface Field) layer for preventing carrier recombination in the vicinity of the back electrode and capturing generated carriers efficiently. The layers 2a and 2b and the n-type amorphous silicon 4 do not necessarily have to be formed. The texture structure may be formed only on the light receiving surface side.

  Furthermore, translucent electrodes 5 a and 5 b having a thickness of about 70 nm are formed on the p-type amorphous silicon layer 3 and the n-type amorphous silicon layer 4. A current collecting electrode 6a having a thickness of about 50 μm made of silver (Ag) is formed on the light transmitting electrode 5a, and a current collecting electrode having a thickness of about 40 μm made of silver (Ag) is formed on the light transmitting electrode 5b. An electrode 6b is formed.

Next, a method for manufacturing a crystalline silicon solar cell according to Embodiment 1 of the present invention will be described.
FIG. 3 is a cross-sectional view showing the procedure of the method for manufacturing the crystalline silicon solar cell according to Embodiment 1 of the present invention. FIG. 4 is a flowchart showing the manufacturing process.

  First, an n-type single crystal silicon substrate 1 having a crystal plane orientation of <100> as a crystal substrate is prepared (FIG. 3A). The n-type single crystal silicon substrate 1 is formed by slicing with a multi-wire saw from a single crystal silicon ingot doped to an n-type with a desired concentration.

  Here, the n-type single crystal silicon substrate 1 is used as the substrate, but since it is usually cut out by slicing an ingot obtained by pulling, a natural oxide film and structural defects are formed on the surface. It is contaminated with metals. Therefore, the n-type single crystal silicon substrate 1 used here is cleaned and damaged layer etched (S1001).

  After cleaning and damage layer etching are performed on the n-type single crystal silicon substrate 1, gettering is performed to remove impurities in the n-type single crystal silicon substrate 1 (S1002). In the gettering step, impurities are segregated in a phosphorus glass layer formed by thermal diffusion of phosphorus at a processing temperature of about 1000 ° C., and the phosphorus glass layer is etched with hydrogen fluoride or the like.

  Next, anisotropic etching is performed on the surfaces of the first surface 1A, which is the light receiving surface of the n-type single crystal silicon substrate 1, and the second surface 1B, which is the back surface, so that the n-type single crystal silicon substrate 1 Textures are formed on the first surface 1A and the second surface 1B (FIG. 3-2: S1003). In this anisotropic etching, for example, an alkaline solution containing an appropriate amount of an organic substance is supplied to the surface of the n-type single crystal silicon substrate 1. As the alkaline solution, for example, a sodium hydroxide (NaOH) aqueous solution or a potassium hydroxide (KOH) aqueous solution is used. The concentration of these aqueous solutions is appropriately changed depending on the kind of the organic substance to be added. For example, the alkali concentration is preferably 1% by weight or more and 10% by weight or less, and the organic substance is an alcohol such as isopropyl alcohol (IPA). , Sulfonic acid, and ester are used. Further, a surfactant or the like may be added in order to enable uniform texture formation in the surface. Furthermore, in order to form a texture with good in-plane uniformity, the temperature of these aqueous solutions during etching is preferably 70 ° C. or higher and 90 ° C. or lower. The texture formation on the entire surface of the substrate may be performed by etching for about 20 to 40 minutes. In this embodiment mode, the etching process is performed by the dipping method. However, the etching solution may be stirred during the etching, and the uneven portion may be formed only on the light incident side.

  When the surface of the n-type single crystal silicon substrate 1 is anisotropically etched with an alkaline aqueous solution, the etching proceeds on a {100} plane having a high etching rate, and a pyramidal uneven portion having a {111} plane having a very low etching rate. Is formed, and the progress of etching is delayed. Therefore, the pyramidal concavo-convex portion is constituted by a slope whose crystal plane is {111}.

  Strictly speaking, since the ratio of the etching rate of {100} plane or {110} plane and the etching rate of {111} plane is not infinite, the concave angle of the texture formed by {111} plane is It is larger than the theoretical value of 70.5 °, and the {111} plane described in this embodiment means a substantially {111} plane.

  On the other hand, before the formation of the concavo-convex portion 1T, the substrate is cleaned to suppress etching unevenness, but this step may be omitted. Furthermore, although the process of removing the damage layer on the substrate surface at the time of slicing is performed by wet etching using an acid or alkali solution, this process may be omitted. In addition, it is desirable to improve the performance by performing gettering treatment of impurities in the substrate after the damaged layer removing step, but it is not necessary to carry out it.

After forming the texture (uneven portion 1T) in this way, organic matter contamination and metal contamination adhered to the surface of the textured n-type single crystal silicon substrate 1 are removed by washing (S1004). If the target contaminant can be removed, examples of the cleaning method include a method of cleaning the substrate surface by ozone water cleaning or RCA cleaning. The substrate surface was cleaned by various cleaning methods to obtain substrates of various contamination levels, solar cells were manufactured using the substrates, and their output characteristics were measured. As a result of the experiment, the amount of metal contamination such as titanium (Ti), chromium (Cr), iron (Fe), nickel (Ni), copper (Cu), zinc (Zn), etc. on the substrate surface after cleaning is 1 × 10 ^11. It has been clarified that the output characteristic (Voc) of the solar cell is remarkably deteriorated at atoms / cm ² or more. In addition, regarding organic contamination, it was confirmed that the total organic contamination amount must be controlled to ³ ng / cm ² or less. When there is metal contamination on the substrate surface, metal ions are taken into the silicon substrate, forming a defect level in the band gap, and when operating as a solar cell, the generated carriers recombine at the defect level. This is because the characteristics are degraded.

  Since the metal contamination amount and the total organic contamination amount are considered to be related to the surface roughness of the textured surface, the metal contamination and the total contamination amount can be obtained by a cleaning process prior to the texture etching process if possible to obtain a smoother textured surface. It is desirable to reduce organic contamination.

  Next, as shown in FIG. 3C, an i-type amorphous silicon layer 2a and a p-type amorphous silicon layer 3 are formed on one side of an n-type single crystal silicon substrate 1 in this order by chemical vapor deposition (CVD). (S1005, 1006). Each of the i-type amorphous silicon layer 2a and the p-type amorphous silicon layer 3 has a thickness of 5 nm. Although the layer thickness is 5 nm in this embodiment mode, the layer thickness may be in the range of 3 nm to 10 nm depending on the layer formation conditions. As the CVD method, it is desirable to use a plasma CVD method, a thermal CVD method, or the like. In order to generate a sufficient built-in electric field with respect to the n-type single crystal silicon substrate 1 which is a photoelectric conversion layer, the band gap and activation energy of the p-type amorphous silicon layer 3 are 1.7 eV or more and 0. It must be 4 eV or less. Instead of the i-type amorphous silicon layer 2a, an i-type amorphous silicon carbide layer, an i-type amorphous silicon oxide layer, or a multilayer film in which these layers are stacked may be used. Instead of the p-type amorphous silicon layer 3, a p-type amorphous silicon carbide layer, a p-type amorphous silicon oxide layer, a p-type microcrystalline silicon layer, or a multilayer film in which these layers are stacked may be used.

  After forming the i-type amorphous silicon layer 2a and the p-type amorphous silicon layer 3 on one side of the n-type single crystal silicon substrate 1, the opposite side of the n-type single crystal silicon substrate 1 as shown in FIG. Then, the i-type amorphous silicon layer 2b and the n-type amorphous silicon layer 4 are formed in this order using the CVD method (S1007, 1008). Each of the i-type amorphous silicon layer 2b and the n-type amorphous silicon layer 4 has a thickness of 5 nm. Although the layer thickness is 5 nm in this embodiment mode, the layer thickness may be in the range of 3 nm to 20 nm depending on the layer formation conditions. Here again, it is desirable to use a plasma CVD method, a thermal CVD method or the like as the CVD method.

  In order to generate a sufficient built-in electric field with respect to the n-type single crystal silicon substrate 1 which is a photoelectric conversion layer, the band gap and activation energy of the n-type amorphous silicon layer 4 are 1.7 eV or more and 0. It must be 3 eV or less. Instead of the i-type amorphous silicon layer 2b, an i-type amorphous silicon carbide layer, an i-type amorphous silicon oxide layer, or a multilayer film in which these layers are stacked may be used. Instead of the n-type amorphous silicon layer 4, an n-type amorphous silicon carbide layer, an n-type amorphous silicon oxide layer, an n-type microcrystalline silicon layer, or a multilayer film in which these layers are stacked may be used.

  After forming the i-type amorphous silicon layer 2b and the n-type amorphous silicon layer 4 on one surface of the n-type single crystal silicon substrate 1, the interface between the i-type amorphous silicon layer 2b and the n-type single crystal silicon substrate 1 In order to reduce defects, thermal annealing may be performed in an inert gas or hydrogen gas diluted with an inert gas. The annealing temperature is desirably 200 ° C. or lower.

After the thermal annealing treatment, translucent electrodes 5a and 5b are formed on the p-type amorphous silicon layer 3 and the n-type amorphous silicon layer 4 by sputtering or vapor deposition as shown in FIG. S1009). The film thickness of the translucent electrodes 5a and 5b is preferably about 70 nm from the viewpoint of reducing the reflectance. As the translucent electrode material, indium tin oxide (ITO) or indium oxide (In ₂ O ₃ : Indium Oxide) is used. In addition, it is desirable that the translucent electrode has a low resistivity, but if the carrier density responsible for conductivity is high, the light absorptance increases. Therefore, the material used as the translucent electrode must have high mobility. In order to achieve a sufficiently low resistivity with a layer thickness of 70 nm, the mobility is desirably 100 cm ² / Vs or more. Note that zinc oxide (ZnO: Zinc Oxide) to which aluminum (Al), gallium (Ga), or the like is added may be used as the lower transparent electrode material.

  After forming the translucent electrodes 5a and 5b, the collector electrodes 6a and 6b made of Ag are formed on the translucent electrodes 5a and 5b as shown in FIG. 3-6 by screen printing (S1010). The width of the grid electrode constituting the current collecting electrode 6a is preferably as narrow as possible to suppress light shielding, but the resistance increases. Therefore, it is desirable that the collecting electrode 6a has a narrow width and a large layer thickness. In this embodiment, the width is 70 μm and the layer thickness is 50 μm. The width of the grid electrode constituting the current collecting electrode 6b is preferably as narrow as possible for cost reduction, but the contact resistance with the translucent conductive film constituting the translucent electrode 5b is increased. Therefore, it is desirable that the current collecting electrode 6b has a narrow width and hardly increases the contact resistance with the translucent electrode 5b. In this embodiment, the width is 100 μm and the layer thickness is 40 μm. In addition to the screen printing method, the current collecting electrode may be formed by a plating method or the like, and aluminum (Al), gold (Au), copper (Cu), or the like may be used instead of Ag. After the collector electrode is printed, firing is performed at 200 ° C. or lower.

  In Embodiment 1 of the present invention, n after texture formation when IPA or sulfonic acid is used as a main component in an organic substance in an etching solution (hereinafter sometimes referred to as a texture solution) for performing texture etching. Table 1 shows the reflectivity of the single crystal silicon substrate 1 at a wavelength of 700 nm, the unevenness height of the surface roughness of the {111} plane, and the cell characteristic results.

  The unevenness height on the {111} plane that is the side surface of the textured uneven portion 1T is about 3 nm when sulfonic acid is used as the organic substance in the etching solution for texture etching, and when IPA is used. About 2 nm. When sulfonic acid is used as the organic substance in the etching solution for texture etching, the photoelectric conversion efficiency (cell) is high even though the unevenness on the {111} plane is 3 nm higher than when IPA is used. Efficiency).

  FIG. 5 shows an atomic force microscope measurement result of the {111} plane which is the side surface of the uneven portion 1T of the substrate when texture etching is performed using IPA as an organic substance in the texture liquid. FIG. 6 shows the atomic force microscope measurement result of the {111} plane that is the side surface of the uneven portion 1T of the substrate. 5 and 6, when IPA is used as the organic substance in the texture liquid, the interval between the surface irregularities on the {111} surface of the irregularities 1T that are the side surfaces of the substrate is shorter than when sulfonic acid is used. It can be seen that the shape is steeper.

  Therefore, on the {111} plane, in order to extract the periodic component of the shape waveform curvature constituting the surface shape, the surface shape waveform curve of the {111} plane obtained by atomic force microscope measurement is Fourier transformed, The spatial frequency of the surface shape was obtained, and the spatial period λ was calculated.

  As a result, when the sulfonic acid is used, the {111} plane of the uneven portion 1T of the substrate consists of only a spatial frequency component with a long period, whereas when IPA is used, in addition to those components, It contained many short spatial frequency components.

In order to evaluate the gentleness of the shape, the ratio (λ / Ra) of λ and Ra determined by measurement was determined. Here, in order to understand the magnitude relationship of λ / Ra and the surface roughness shape of the {111} plane, a figure of the shape of the {111} surface when Ra is set to a constant value Ra _{1 and} is changed by λ is shown. 7 shows. a is a curve indicating the case of the period λ ₁ , and b is a curve indicating the case of the period λ ₂ . Here, λ ₂ = 0.2λ ₁ . Even if Ra is the same, when the surface shape period is short (1/5 period), it can be seen that the shape of the {111} surface becomes steep.

Furthermore, FIG. 8 shows a shape image diagram of the {111} surface when Ra of a component having a short spatial period (broken line b) is halved from the case of FIG. When the spatial period is short, even if Ra ₂ is reduced to 1/2 (Ra ₂ = 0.5R ₁ ), the spatial period indicated by the broken line b is shorter than the case where the spatial period is long as indicated by the solid line a. It can be seen that the shape is steep. Here, since λ ₂ = 0.2λ ₁ and Ra ₂ = 0.5R ₁ , λ ₂ / Ra ₂ = 0.4 (λ ₁ / Ra ₁ ), and the ratio of λ to Ra (λ / Ra) is smaller. That is, it does not depend only on Ra, but the surface shape becomes gentler as λ / Ra increases. From the above, it can be determined that the spatial period is important together with the height of the {111} surface shape in order to define the gradient of the surface shape. That is, λ / Ra is effective as a parameter that three-dimensionally expresses the features related to the steepness of the fine unevenness of the {111} surface shape.

  Table 2 shows the results of λ / Ra and cell characteristics when IPA or sulfonic acid is used as the main component for the organic substance in the texture liquid. Λ / Ra shown here is obtained by extracting λ having a peak from λ having a power value of 0.3 or more when the highest power value obtained by Fourier transform is 1.

  When sulfonic acid is used as the organic substance in the texture liquid, the height of the irregularities is higher, but λ / Ra is composed of 100 or more components, most of which are composed of shape waveform components with λ / Ra = 398. It was found that the shape was gradual. On the other hand, when IPA is used, the {111} plane is composed of shape waveform components consisting of five types of periods, and λ / Ra = 78, which includes many sharper shapes than the substrate. It was. The {111} plane of the texture substrate when IPA is used indicates that a gentle shape and a steep shape are mixed.

  From Table 2, it is confirmed that Voc and FF are improved as the shape of the {111} plane which is the side surface of the uneven portion 1T of the substrate becomes gentle. When sulfonic acid is used as the organic substance in the texture liquid, the unevenness height was high, but the shape was gentle, so the formation of an epitaxial layer centered on the steep shape was suppressed, and the substrate-amorphous silicon film It is considered that the interface and defects in the film are reduced, and as a result, Voc and FF are improved.

  Further, when the translucent electrodes 5a and 5b and the back surface side electrode 7 are formed by sputtering or the like, the {111} plane is inclined by about 55 ° with respect to the surface orientation <100>. When there is a steep shape on the 111} plane, a part of the steep shape is shaded with respect to the film forming direction, resulting in nonuniform film quality and film thickness. Therefore, it is considered that a substrate having a {111} surface shape with λ / Ra ≧ 100 has the accompanying effect that the above problem is reduced due to the gentle shape, and as a result, the FF is improved.

  As described above, a solar cell formed by a textured substrate having a {111} surface shape, which is the side surface of the concavo-convex portion of the substrate having the pyramidal concavo-convex portion 1T according to the present invention, is λ / Ra ≧ 100, The texture substrate-amorphous silicon film interface formed by the steep shape and defects in the film are reduced, and as a result, Voc and FF are improved. As a result, according to Embodiment 1 of the present invention, a solar cell having high Voc and FF and good photoelectric conversion efficiency can be realized.

Embodiment 2. FIG.
The second embodiment relates to a substrate in which the surface of {111} is smoothed by performing a smoothing process as an additional process on the substrate for solar cells on which the uneven portion 1T as the texture is formed. FIG. 9 is a flowchart showing the manufacturing process of this solar cell. The schematic configuration diagram of the solar cell is the same as that of the first embodiment, and the manufacturing method is the same as that of the first embodiment except for the additional processing after the formation of the uneven portion 1T.

  In the present embodiment, as shown in the flowchart in FIG. 9, the texture formation step S1003 and the substrate cleaning step S1004 are finished, and the substrate surface is smoothed before the i-type amorphous silicon layers 2a and 2b are formed. A smoothing processing step S2000 is added. Other steps are the same as those in the flowchart of the first embodiment shown in FIG.

Regarding the {111} surface smoothing treatment (step S2000) after the formation of the uneven portion 1T, at least one of a hydrofluoric acid solution, ammonium fluoride (NH ₄ F), aqueous ammonia (NH ₄ OH), and hydrofluoric acid (HF) is used. The method of immersing in the aqueous solution containing two or more is mentioned. The treatment temperature may be room temperature, and the treatment time is 10 seconds to 5 minutes although it varies depending on the type and concentration of the solution used.

A substrate textured using a texture liquid mainly composed of IPA as an organic substance is mixed with a solution mixed at a volume ratio of NH ₄ F: NH ₄ OH: HF: H ₂ O = 5: 1: 1: 4 at room temperature. Table 3 shows the results of measuring λ / Ra for the solar cell substrate subjected to the immersion treatment for 1 minute. Table 3 shows the cell characteristics when a solar cell was formed using this solar cell substrate in the same manner as in the first embodiment.

  It can be seen that by performing the smoothing process after the texture formation, the value of λ / Ra increases and the shape of the {111} surface becomes gentle. As described above, by performing the smoothing process as an additional process after the texture formation, it is possible to smooth the uneven portions of the {111} surface and obtain a smooth surface shape. As a result, the embodiment Voc and FF improved for the same reason as 1.

  From the above, the solar cell formed by the textured substrate in which the {111} surface shape, which is the concavo-convex portion side surface of the crystalline substrate having the pyramidal concavo-convex portion according to the present invention, is λ / Ra ≧ 100 is steep. The texture substrate-amorphous silicon film interface and defects in the film formed by the shape are reduced, and as a result, Voc and FF are improved. As a result, according to Embodiment 2 of the present invention, a solar cell with high Voc and FF and good photoelectric conversion efficiency can be realized.

Embodiment 3 FIG.
In the third embodiment, a step of measuring {111} surface roughness, which is a side surface of the uneven portion 1T, using an atomic force microscope with respect to the solar cell substrate on which the uneven portion 1T as a texture is formed (step S2001). The solar cell is created only for the smooth surface. FIG. 10 is a flowchart showing the manufacturing process of this solar cell. The schematic configuration diagram of the solar cell is the same as in the first and second embodiments, and the manufacturing method is the same as in the first embodiment except for the measurement process after the formation of the concavo-convex portion 1T and the additional processing.

  In the present embodiment, as shown in the flowchart of FIG. 10, the texture forming step S1003 and the substrate cleaning step S1004 are finished, and the concavo-convex portion 1T is formed prior to forming the i-type amorphous silicon layers 2a and 2b. The solar cell substrate is characterized by adding a step (step S2001) of measuring {111} surface roughness using an atomic force microscope. In order to extract the periodic component of the shape waveform curvature constituting the surface shape on the {111} plane, the surface shape waveform curve of the {111} plane obtained by atomic force microscope measurement is Fourier transformed to obtain the surface shape And the spatial period λ was calculated.

  And in order to evaluate the gentleness of a shape, ratio (lambda / Ra) of (lambda) and Ra calculated | required by measurement was calculated | required, and the average value of (lambda) / Ra was computed. And if it is No after the process (step S2002) which judges whether the average value of (lambda) / Ra is 100 or more, like the said Embodiment 2, the smoothing process process (smoothing the substrate surface) ( Step S2000) is added. On the other hand, if it is Yes in the step of determining whether or not the average value of λ / Ra is 100 or more (step S2002), the i-type amorphous silicon layer forming step (step S1005) is entered, and the solar cell is installed. To manufacture. Other steps are the same as those in the flowchart of the first embodiment shown in FIG.

  After texture formation, the surface roughness is measured with an atomic force microscope, and if the value of λ / Ra is not 100 or more, a smoothing process is performed. Then, a solar cell is manufactured by forming a functional film made of an amorphous silicon layer on the solar cell substrate that has been determined that the value of λ / Ra has increased and the shape of the {111} surface has become gentle. .

  According to the present embodiment, the step of forming the concavo-convex portion includes the step of measuring the {111} surface roughness of the side surface of the concavo-convex portion using an atomic force microscope after the etching step, and the average surface roughness And calculating a ratio between the roughness Ra and the spatial period λ, and determining whether or not the ratio is 100 or more. As described above, when the surface roughness is measured and the value of λ / Ra is not 100 or more, the unevenness portion of the {111} surface is smoothed by performing a smoothing process as an additional process after the texture formation. Thus, it is possible to obtain a smooth surface shape and improve Voc and FF as in the first embodiment.

  In addition, it is effective to reduce the amount of metal contamination in the etching solution, and the cleaning treatment after texture formation is very important in improving the characteristics of the heterojunction solar cell. This is important from the viewpoint of suppressing surface recombination on the substrate surface, apart from the roughness of the {111} plane. Even in this cleaning process, if the metal contamination in the cleaning liquid is large, the surface of the formed texture {111} may be roughened. In order to obtain the best state, it is extremely important that the metal contamination in the processing solution is low even in the cleaning process to keep the substrate surface clean and form a smooth texture.

  Note that the crystalline semiconductor substrate can be applied to a crystalline silicon substrate such as a silicon compound substrate such as a silicon carbide substrate in addition to a crystalline silicon substrate such as a single crystal silicon substrate or a polycrystalline silicon substrate. As for the intrinsic or conductive amorphous silicon layer, an amorphous silicon layer such as an amorphous silicon carbide film and an amorphous silicon oxide film, a microcrystalline silicon thin film, a polycrystalline silicon thin film, etc. It can also be applied to crystalline thin films.

  The solar cell substrates of the first and second embodiments are particularly effective in preventing abnormal film formation of an epitaxially grown layer in a so-called heterojunction solar cell in which an amorphous thin film or the like is formed on a crystalline semiconductor substrate. . On the other hand, in the case of a diffusion type solar cell in which a junction is formed by diffusion from the surface of the crystalline semiconductor substrate, it is possible to prevent defects from being formed even when a passivation film such as SiN is formed on the light receiving surface side. The solar cell substrates of Embodiments 1 and 2 are also effective for solar cells having other structures.

  As described above, the solar cell substrate according to the present invention is suitable for realizing a solar cell having a pyramidal texture structure and having low light reflectance and high photoelectric conversion efficiency.

  1 n-type single crystal silicon substrate, 2a, 2b i-type amorphous silicon layer, 3 p-type amorphous silicon layer, 4 n-type amorphous silicon layer, 5a, 5b translucent electrode, 6a, 6b electrode.

Claims (13)

Consists of a substrate of one conductivity type having a concavo-convex portion on the surface,
The solar cell substrate, wherein the ratio of the average surface roughness Ra of the surface roughness to the spatial period λ on the side surface of the uneven portion is 100 or more.   2. The solar cell substrate according to claim 1, wherein the substrate is a single crystal silicon substrate, and a side surface of the concavo-convex portion is a {111} plane. On the surface of the substrate, metal contamination of titanium (Ti), chromium (Cr), iron (Fe), nickel (Ni), copper (Cu), and zinc (Zn) is 1 × 10 ¹¹ atoms / cm ² or less, respectively. The solar cell substrate according to claim 1, wherein the substrate is a solar cell substrate. A method for manufacturing a substrate for a solar cell including a step of forming a concavo-convex portion on a surface of a crystalline silicon substrate,
Forming the concavo-convex portion,
It is an etching process for forming the concavo-convex portion so that the ratio of the average surface roughness Ra of the surface roughness and the spatial period λ is 100 or more, which is obtained by measuring the side surface of the concavo-convex portion with an atomic force microscope. The manufacturing method of the board | substrate for solar cells characterized by the above-mentioned. The step of forming the uneven portion includes
Wherein after the etching process, characterized in that it comprises a smoothing process, a manufacturing method of a substrate for a solar cell according to claim 4. The step of forming the uneven portion includes
After the etching process,
Metal contamination of titanium (Ti), chromium (Cr), iron (Fe), nickel (Ni), copper (Cu), and zinc (Zn) on the substrate surface is 1 × 10 ¹¹ atoms / cm ² or less, respectively. The method for producing a substrate for a solar cell according to claim 4 or 5, further comprising a step of cleaning the surface of the substrate so as to exist. A solar cell in which a second conductivity type semiconductor layer is formed on the surface of a first conductivity type substrate having a large number of irregularities formed on the surface,
A solar cell, wherein the ratio of the average surface roughness Ra of the surface roughness to the spatial period λ on the side surface of the concavo-convex portion provided on the surface of the substrate is 100 or more.   The solar cell according to claim 7, wherein the substrate of the first conductivity type is a single crystal silicon substrate, and the side surface of the concavo-convex portion is a {111} plane.   The solar cell according to claim 7, wherein the second conductivity type semiconductor layer is an amorphous semiconductor layer. Metal contamination of titanium (Ti), chromium (Cr), iron (Fe), nickel (Ni), copper (Cu), and zinc (Zn) on the surface of the substrate is 1 × 10 ¹¹ atoms / cm ² or less, respectively. The solar cell according to claim 7, wherein the solar cell is provided. Forming a concavo-convex portion on the surface of the first conductive type crystalline silicon substrate;
Forming a second conductivity type semiconductor layer on the surface of the crystalline silicon substrate,
Forming the concavo-convex portion,
It is an etching process for forming the concavo-convex portion so that the ratio of the average surface roughness Ra of the surface roughness and the spatial period λ is 100 or more, which is obtained by measuring the side surface of the concavo-convex portion with an atomic force microscope. The manufacturing method of the solar cell characterized by the above-mentioned. The step of forming the uneven portion includes
The method for manufacturing a solar cell according to claim 11, further comprising a smoothing treatment step after the etching step. The step of forming the uneven portion includes
After the etching process,
Metal contamination of titanium (Ti), chromium (Cr), iron (Fe), nickel (Ni), copper (Cu), and zinc (Zn) on the substrate surface is 1 × 10 ¹¹ atoms / cm ² or less, respectively. The method for manufacturing a solar cell according to claim 11, further comprising a step of cleaning the substrate surface.