JP5835809B2 - Multilane transmission method and apparatus using the same - Google Patents

Description

  The present invention relates to a multilane transmission method and system in an optical transmission network, and in particular, a multilane transmission method for transmitting transmission frames each mapped with a plurality of data sequence signals using a plurality of physical channels. And about the system.

  Internet traffic continues to increase, and research institutes and companies in each country are actively conducting research and development for innovative technologies to further increase the capacity and economy of optical backbone networks.

  Among them, transmission systems using the polarization multiplexing technology can increase the frequency utilization efficiency twice as compared with the conventional single polarization transmission system, and therefore, studies for introduction into commercial systems are being continued actively. In addition, with the increase in the speed of Ethernet (registered trademark), which is one of OTN (Optical Transport Network) client signals, the baud rate of the OTN frame signal itself continues to increase.

  However, it has been pointed out that optical signals are more susceptible to the effects of polarization in the optical transmission line, that is, polarization dependent loss and polarization mode dispersion, due to the increase in polarization multiplexing technology and baud rate. (Non-Patent Document 1).

  The optical signal degradation caused by such a phenomenon caused by polarization has a remarkable property that it differs between physical channels even at the same time. Utilizing the above properties, a wavelength interleave transmission system, that is, a system capable of statistically mitigating extremely significant optical signal degradation by transmitting one signal sequence using a plurality of physical channels, has been proposed. (Non-Patent Document 2).

  In the wavelength interleaved transmission scheme, when a plurality of signal sequences are considered, it is necessary to transmit the plurality of signal sequences after mapping them to a transmission frame between a plurality of physical channels in order not to reduce the transmission speed and efficiency. is there. At this time, a part of all signal sequences is interleaved in one transmission frame, so that the effect of the wavelength interleave transmission method is most apparent.

M.M. Shtaiif et al. "Performance degradation in coherent polarization multiplexed systems as a result of polarization dependent loss", Optics Express, Vol. 16, pp. 13918-13932, 2008. Shibahara et al., “Quantitative evaluation of PDL tolerance improvement by wavelength interleaved transmission method”, IEICE Society Conference, Communications Society 2, Vol. 2011, pp. 267, 2011 Recommendation ITU-T G. 709 / Y. 1331.

  As an example of a multi-lane transmission method in which a single data sequence is transmitted using a plurality of physical channels, the ITU-T Recommendation G. 709 (Non-Patent Document 3).

  However, the multilane transmission method for transmitting a plurality of data series using a plurality of physical channels is not currently defined in Non-Patent Document 3. In particular, in order to apply the wavelength interleaved transmission method between a plurality of data sequences, it is necessary that a signal of each data sequence is mapped (interleaved) to each transmission lane on the transmission side, and a lane after transmission is transmitted on the reception side It is necessary to perform skew adjustment and lane identification between the frames to restore the original frames of a plurality of data series signals.

  An object of the present invention is to enable multi-lane transmission using a plurality of different physical channels for a plurality of transmission frames each mapped with a plurality of data sequences.

  In order to achieve the above object, the present invention uses a synchronization signal as a transmission lane synchronization signal and a transmission lane identification signal, so that a plurality of physical channels are mapped to a transmission frame in which a plurality of data sequences are mapped respectively. Provided are a transmission method and a transmission system that enable multi-lane transmission using the.

The multilane transmission method of the present invention is a multilane transmission method for transmitting a transmission frame in which a plurality of data sequences are mapped to a plurality of transmission lanes using a plurality of physical channels, For each of the data series , each data block obtained by dividing the transmission frame is mapped to a plurality of transmission lanes while performing lane rotation so that the lane to which the transmission frame synchronization signal is mapped differs for each transmission frame. For the data series excluding the one data series of the plurality of data series, the data blocks obtained by dividing the transmission frame are divided into the plurality of data blocks so that the synchronization signal of the transmission frame is different from the one data series. a mapping procedure for mapping the transmission lanes, each transmission lane With the mapped transmission frame multiplexing procedure for time-multiplexing between data series, in this order.

  In the multilane transmission method of the present invention, the number of data sequences of the plurality of data sequences may be N (N is a natural number) sequence, and the bit pattern of the synchronization signal may be N frames continuous and the same pattern.

The multi-lane transmission system of the present invention is a multi-lane transmission system for transmitting a transmission frame in which a plurality of data sequences are mapped to a plurality of transmission lanes from a transmitter to a receiver using a plurality of physical channels, The transmitter divides the transmission frame while performing lane rotation so that a lane to which a synchronization signal of a transmission frame is mapped differs for each transmission frame with respect to one data sequence of the plurality of data sequences Mapping each data block to a plurality of transmission lanes, mapping each data block obtained by dividing the transmission frame to the plurality of transmission lanes for a data sequence excluding the one data sequence of the plurality of data sequences, Transfer frames mapped to each transmission lane between data sequences Time multiplexing, the receiver, by performing transmission lanes synchronization with the transmission lanes identified using the synchronization signal of the transmission frame of said one data sequence and demapping each transmission frame.

  The multilane transmission apparatus of the present invention receives a plurality of data sequences, a framer for generating a transmission frame for each data sequence, and a transmission frame synchronization signal for one data sequence of the plurality of data sequences. A mapping circuit that maps each data block obtained by dividing the transmission frame to a plurality of transmission lanes while performing lane rotation so that the lane to be mapped differs for each transmission frame, and the one of the plurality of data sequences For a data series excluding a data series, a serial-parallel conversion circuit that maps each data block obtained by dividing the transmission frame to the plurality of transmission lanes, each data block from the mapping circuit, and each data from the serial-parallel conversion circuit Block many times between data series Comprising a multiplexing circuit for, a.

  According to the present invention, multilane transmission using a plurality of different physical channels can be enabled for a plurality of transmission frames each mapped with a plurality of data sequences.

An example of the multilane transmission system which concerns on this embodiment is shown. An example of the mapping of the transmission frame to the lane in the mapping circuit and the serial / parallel conversion circuit is shown. An example of each logical lane after multiplexing by the multiplexing circuit 14 is shown. An example of overhead in an OTU frame is shown. An example of the bit pattern in FAS of data series # 1 is shown. An example of bit patterns in FAS of data series # 2 to #N is shown. An example of the mapping of the transmission frame to the lane in Embodiment 2 is shown.

  Embodiments of the present invention will be described with reference to the accompanying drawings. The embodiments described below are examples of the present invention, and the present invention is not limited to the following embodiments. In the present specification and drawings, the same reference numerals denote the same components.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. An example of a transmission frame according to the embodiment of the present invention is an OTU (Optical Transport Unit) frame below. As a transmission frame, a synchronization signal such as FAS (Frame Alignment Signal) or LLM (Logical Lane Marker) is used. The present invention is applicable as long as it is included therein.

  FIG. 1 shows an example of a multilane transmission system according to this embodiment. The multilane transmission system according to this embodiment includes a transmitter 100 and a receiver 200. The multilane transmission method according to this embodiment includes a mapping procedure and a multiplexing procedure in this order. In the mapping procedure, the transmitter 100 uses the FAS of the OTU frame of the data sequence # 1 as the lane synchronization signal and the transmission lane identification signal in each transmission lane, and maps the OTU frame of each data sequence to each transmission lane. In the multiplexing procedure, the transmitter 100 time-multiplexes transmission frames mapped to each transmission lane between data sequences. Hereinafter, signal flows in the transmitter 100 and the receiver 200 will be described in detail.

(Transmitter 100)
N series (N is a natural number) client data is input to the transmitter 100. The transmitter 100 includes N OTU framers 11, one mapping circuit 12, (N−1) serial / parallel conversion circuits 13, one multiplexing circuit 14, and N optical modulators 15. And one multiplexer 16.

  In the transmitter 100, the N data sequences are mapped to OTU frames by different OTU framers 11, respectively. At this time, the bit pattern is filled in the synchronization signal by a method described later. Further, the N OTU framers 11 need to be clock-synchronized, but need not be frame-synchronized.

  If the number of logical lanes per physical channel is K, the total number of logical lanes is KN. The number of logical lanes per physical channel is determined according to the function of the optical modulator 15. For example, when the optical modulator 15 modulates using polarization multiplexing of X polarization and Y polarization, K = 2. Become. When N = 10 and K = 2, the total number of logical lanes is 20. Hereinafter, description will be given mainly using an example of K = 2.

  FIG. 2 shows an example of a method for mapping a transmission frame to a logical lane. An OTU frame is divided into blocks each having a minimum unit of 8 bytes of an OTU frame of one data series (in this embodiment, data series # 1), and KN blocks corresponding to the number of logical lanes are set at the same time. Map on the slot. Here, “time slot” means “time slot” when mapping to a logical lane, and does not mean “time slot” when modulating to an optical signal, so that KN blocks can be mapped to the same time slot. . After mapping KN blocks for data sequence # 1 on the same time slot, KN blocks for data sequence # 2 are mapped on the same time slot. For data series # 3 to #N, KN blocks are mapped in the same time slot in order. This is sequentially repeated for the data series # 1 to #N.

  After mapping one frame to KN logical lanes, the next frame performs lane rotation shown in Annex C of Non-Patent Document 3. A shaded block is a block in which synchronization signals are arranged, and in lane rotation, lanes in which synchronization signals are arranged are sequentially changed. In this way, a certain data series is mapped while being rotated for each frame, so that a synchronization signal appears in all logical lanes.

  Since the interval at which the synchronization signal appears is every 1 OTU frame time length, for example, it is 3.035 μsec for OTU3 and 1.168 μsec for OTU4. The target of lane rotation is an OTU frame of any one data sequence (in this embodiment, data sequence # 1) out of N data sequence OTU frames, and the other data sequence # 2 to #N OTU frames are targets. Get out. The OTU frames of the data sequences # 2 to #N are arranged on KN identical time slots with a block having 8 bytes as a minimum unit as one unit without being subjected to lane rotation. That is, (N−1) serial / parallel conversion circuits 13 perform serial / parallel conversion in units of blocks for the OTU frames of the data series # 2 to #N.

  These are multiplexed in the time axis direction by the multiplexing circuit 14. KN logical lanes in which the OTU frames of each data series are interleaved with each lane are completed. Then, KN logical lanes are output to each optical modulator 15. FIG. 3 shows an example of each logical lane multiplexed by the multiplexing circuit 14. As shown in FIG. 3, the multiplexing circuit 14 performs time multiplexing between data series.

  At the time of optical transmission, the optical modulator 15 generates an optical signal of each physical channel. At this time, when the number of logical lanes KN is larger than the number of physical lanes, a plurality of logical lanes are multiplexed into a single physical lane. For example, G. For example, in the case of OTU4, KN = 20 logical lanes are bit-multiplexed into 10 (OTL 4.10) or 4 (OTL 4.4) physical lanes. The generated physical lane is optically modulated by the optical modulator 15 and input to the optical transmission line 300 through a plurality of physical channels.

In this embodiment, the number of logical lanes is KN, whereas the number of physical channels is N, the logical lane K for one physical channel is 2, and the number of logical lanes is larger than the number of physical channels. In this case, the optical modulator 15 of the physical channel λ ₁ uses polarization multiplexing to multiplex logical lanes # 1 and # 2, and the optical modulator 15 of the physical channel λ ₂ uses polarization multiplexing. multiplexes logical lanes # 3 and # 4, the optical modulator 15 of ... physical channel lambda _N are multiplexed logical lanes # (KN-1) and #KN, such as using the polarization multiplexing.

(Receiver 200)
The receiver 200 includes one demultiplexer 26, N optical demodulators 25, one lane synchronization / identification circuit 27, one separation circuit 24, N demapping circuits 22, N One OTU framer 21 is provided.

In the receiver 200, a plurality of physical channels that have propagated through the optical transmission line 300 are demodulated into physical lanes by separate optical demodulators 25. When a plurality of logical lanes are multiplexed for a single physical lane, the optical demodulator 25 separates the logical lanes into a plurality of logical lanes. In this embodiment, since two logical lanes are multiplexed per single physical channel, the optical demodulator 25 of the physical channel λ ₁ demodulates the optical signal of the channel λ ₁ to the logical lanes # 1 and # 2. The optical demodulator 25 of the physical channel λ _N demodulates the optical signal of the channel λ _N and separates it into logical lanes # (KN−1) and #KN.

  Next, the lane synchronization / identification circuit 27 finds the head of each transmission lane from the synchronization signal of each logical lane, as shown in Annex C of Non-Patent Document 3, using the FAS fixed pattern as the synchronization signal. Thus, lane synchronization is performed, and lane identification is performed by looking at the MFAS or LLM pattern.

  When synchronization and identification are completely performed in the lane synchronization / identification circuit 27, the separation circuit 24 separates KN lanes in time. At this time, as described with reference to FIG. 2, it is output to a different demapping circuit 22 for each time slot. Then, the blocks allocated on the same time slot are recombined into the original N OTU frames by each demapping circuit 22. From these, N data series are respectively extracted by the N OTU framers 21.

(Frame structure)
The bit pattern of the synchronization signal in the transmitter 100 is filled in each OTU frame as follows. The diagram described in FIG. 709 shows the overhead (OH) of the OTU frame described in 709, and represents the configuration of the synchronization signal. A FAS (Frame Alignment Signal) is used as a synchronization signal in the OTU frame. The first to sixth bytes of the FAS contain a fixed pattern and are used as a logical lane synchronization signal for finding the head of the logical lane in the receiver 200. The seventh byte contains a logical lane number identification signal called MFAS (Multi FAS), and numbers from 0 to 255 are assigned.

  FIG. 5 shows an example of the FAS of the data series # 1, and FIG. 6 shows an example of the FAS of the data series # 2 to #N. The FAS of the OTU frame of data series # 1 is G. The OH of the OTU frames of the other data series # 2 to #N has the FAS fixed pattern of G.709. Filled differently from 709. This is a change for preventing the receiver 200 from erroneously synchronizing with the synchronization signal included in the client data of the data sequences # 2 to #N that are not subject to lane rotation.

  The difference is that the FAS originally has a structure in which OA1 is 3 bytes and OA2 is 3 bytes, and the FAS may be changed within this range and recognized as “not FAS”. In other words, assuming that the error threshold of the original FAS is m bits (assuming FAS if the number of error bits is within m bits), the changed FAS is different from the original FAS by (m + 1) bits or more. Just do it. As an example, the pattern is such that there are three OA2 (00101000) and three OA1 (11110110) from the beginning of OH. As a result, the (N−1) original FAS patterns are not identified as FAS by the receiver 200.

  When the total logical lane number KN is not a power of 2, the sixth byte of FAS can be changed from a fixed pattern to a lane identification signal instead of MFAS as a lane number identification signal. The sixth byte is called LLM (Logical Lane Marker). The LLM starts from 0 and increases by 1 until ([256 / (NK)] × (NK) −1). When the LLM reaches the maximum value, the value is increased from 0 again. Therefore, the period in which the same LLM pattern appears can be expressed as [256 / (NK)] × (NK). However, when x is a real number, [x] represents the maximum number not exceeding x.

As described above, the multi-lane transmission system according to the present embodiment maps only the data sequence # 1 while performing lane rotation of the synchronization signal, and does not map the synchronization signal for other data sequences. the OTU frame data series #. 1 to # N by using multiple physical channels lambda ₁ to [lambda] _N is transmitted in the optical transmission line 300, take out each data sequence #. 1 to # N by the optical receiver 200 be able to.

  In the present embodiment, the case where one data series using the synchronization signal among the plurality of data series is the data series # 1, but the one data series is any of # 1 to #N. May be a data series. In this embodiment, the same number of N physical channels is provided for N data sequences. However, the present invention is not limited to this, and the present invention can be applied to an arbitrary number of physical channels. In addition, the number of logical lanes for one physical channel is not limited to K = 2, and an arbitrary number of logical lanes can be set according to the function of the optical modulator 15.

  In the present embodiment, the receiver 200 includes N demapping circuits 22. However, for the data series # 2 to #N that are not subjected to lane rotation, the parallel serial is used instead of the demapping circuit 22. It is also possible to use the conversion circuit 13.

(Embodiment 2)
FIG. 7 shows an example of mapping of transmission frames to lanes in the present embodiment. In the figure, the number of lanes per physical channel is set to 1 for simplicity. By using the same pattern for the LLMs of N consecutive OTU frames when using the LLM, the period in which the FAS appears in each lane is N times as shown in FIG. By this effect, the period until the same LLM pattern appears is N times, and the skew tolerance is improved.

The skew tolerance M in the receiver 200 is expressed by using the frame length as a unit.
(Equation 1)
M = (LCM (cycle in which the same LLM pattern appears, cycle in which the same MFAS pattern appears) / 2-1 (formula 1)
Expressed as a frame. However, LCM (a, b) represents the least common multiple of a and b, where a and b are natural numbers. The period in which the same MFAS pattern appears is 256 (= 2 to the 8th power) frame.

As described above, when the period in which the same LLM pattern appears becomes N times, assuming that N can be factored as N = (2 to the power of Q) × R, the skew tolerance is given by Equation 2.
(Equation 2)
M = (LCM (period in which the same LLM pattern appears) × R, 256) / 2-1 (Formula 2)
However, Q is a natural number of 8 or less, and R is a natural number of 256 or less not including 2 as a factor.

  For example, when the number of logical lanes K per physical channel is K = 2 and the number of data series N is 10, the total number of logical lanes is 20. However, assuming that the method of the present embodiment is not used, the same LLM pattern appears. Is [256/20] × 20 = 240 OTU frame length. In this case, the skew tolerance M is LCM (240, 256) / 2-1 = 1919 OTU frame. When the method of the present embodiment is used, the period in which the same LLM pattern appears is 240 × 10 = 2400 OTU frames, so that the skew tolerance M is approximately five times the LCM (2400,256) / 2-1 = 9599 OTU frame length. And can be expanded.

  Note that other methods of mapping the transmission frame to the logical lane are conceivable, but the present invention is not limited to the above-described embodiment, and various modifications and applications can be made within the scope of the claims.

  The present invention can be applied to the information communication industry.

11: OTU framer 12: mapping circuit 13: serial / parallel conversion circuit 14: multiplexing circuit 15: optical modulator 16: multiplexer 21: OTU framer 22: demapping circuit 24: separation circuit 25: optical demodulator 26: demultiplexing Device 27: Lane synchronization / identification circuit 100: Transmitter 200: Receiver 300: Optical transmission line

Claims (4)

A multi-lane transmission method for transmitting a transmission frame in which a plurality of data sequences are mapped to a plurality of transmission lanes using a plurality of physical channels,
For one data sequence of the plurality of data sequences, a plurality of data blocks obtained by dividing the transmission frame are divided while performing lane rotation so that a lane to which a transmission frame synchronization signal is mapped differs for each transmission frame. And the transmission frame is divided so that the synchronization signal of the transmission frame is different from the one data series for the data series excluding the one data series of the plurality of data series. A mapping procedure for mapping each data block to the plurality of transmission lanes ;
A multiplexing procedure for time-multiplexing transmission frames mapped to each transmission lane between data sequences;
In order. The number of data series of the plurality of data series is an N (N is a natural number) series,
2. The multilane transmission method according to claim 1, wherein the bit pattern of the synchronization signal is the same pattern for N consecutive frames. A multi-lane transmission system for transmitting a transmission frame in which a plurality of data sequences are mapped to a plurality of transmission lanes from a transmitter to a receiver using a plurality of physical channels,
The transmitter is
For one data sequence of the plurality of data sequences, a plurality of data blocks obtained by dividing the transmission frame are divided while performing lane rotation so that a lane to which a transmission frame synchronization signal is mapped differs for each transmission frame. To the transmission lane
Mapping each data block obtained by dividing the transmission frame to the plurality of transmission lanes for the data series excluding the one data series of the plurality of data series;
Transmission frames mapped to each transmission lane are time-multiplexed between data sequences,
The multi-lane transmission system, wherein the receiver demaps each transmission frame by performing transmission lane synchronization and transmission lane identification using the synchronization signal of the transmission frame of the one data series. A framer for inputting a plurality of data series and generating a transmission frame of each data series;
For one data sequence of the plurality of data sequences, a plurality of data blocks obtained by dividing the transmission frame are divided while performing lane rotation so that a lane to which a transmission frame synchronization signal is mapped differs for each transmission frame. A mapping circuit for mapping to a transmission lane of
A serial-parallel conversion circuit for mapping each data block obtained by dividing the transmission frame to the plurality of transmission lanes for a data series excluding the one data series of the plurality of data series;
A multiplexing circuit for time-multiplexing each data block from the mapping circuit and each data block from the serial-parallel conversion circuit between data series;
A multilane transmission apparatus comprising:

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