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JP5960622B2 - RF circuit - Google Patents

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JP5960622B2
JP5960622B2 JP2013030833A JP2013030833A JP5960622B2 JP 5960622 B2 JP5960622 B2 JP 5960622B2 JP 2013030833 A JP2013030833 A JP 2013030833A JP 2013030833 A JP2013030833 A JP 2013030833A JP 5960622 B2 JP5960622 B2 JP 5960622B2
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circuit
transmission line
power supply
frequency
terminal
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JP2014160750A (en
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慎介 中野
慎介 中野
正史 野河
正史 野河
弘 小泉
弘 小泉
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Nippon Telegraph and Telephone Corp
NTT Inc
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Description

本発明は、ミリ波帯やそれ以上の周波数帯を扱うRF(Radio Frequency)回路に直流バイアスを与える電源配線実装において、ワイヤボンディング等の簡易かつ低コストな実装を許容する高周波RF回路に関するものである。   The present invention relates to a high-frequency RF circuit that allows simple and low-cost mounting such as wire bonding in a power supply wiring mounting that applies a DC bias to an RF (Radio Frequency) circuit that handles a millimeter wave band or higher frequency band. is there.

IC(Integrated Circuit)にDC電圧を与える電源用パッドを実装する手法として、ワイヤボンディングが一般的である。高周波帯を扱うRF回路では、実装時のワイヤボンディングによって電源用パッド外に寄生するインダクタンス成分が生じるので、このインダクタンス成分の影響を考慮した設計をしておくことが必要である。   As a method for mounting a power supply pad for applying a DC voltage to an IC (Integrated Circuit), wire bonding is generally used. In an RF circuit that handles a high-frequency band, an inductance component that is parasitic outside the power supply pad is generated by wire bonding at the time of mounting. Therefore, it is necessary to design in consideration of the influence of this inductance component.

従来技術では、ICの電源用パッドに付着するワイヤによる寄生インダクタンスの影響を低減する為に、IC上の電源用パッド間にコンデンサ素子を挿入したり、同一レベルの直流バイアスを供給する電源用パッドを複数並列化して用いたりする事によって、実装による寄生インダクタンスの影響を低減する方法(非特許文献1参照)や、高周波帯でも良好な電気特性が得られる実装方法であるフリップチップ実装を用いる方法(非特許文献2、非特許文献3参照)などが知られている。   In the prior art, in order to reduce the influence of parasitic inductance caused by wires adhering to the power supply pad of the IC, a power supply pad that inserts a capacitor element between the power supply pads on the IC or supplies a DC bias of the same level A method of reducing the influence of parasitic inductance due to mounting by using a plurality of parallel circuits (see Non-Patent Document 1) and a method of using flip-chip mounting, which is a mounting method that can obtain good electrical characteristics even in a high frequency band (See Non-Patent Document 2 and Non-Patent Document 3).

Behzad Razavi著,黒田忠広監訳,“アナログCMOS集積回路の設計 応用編”,丸善株式会社,p.816−819,2003年Behzad Razavi, translated by Tadahiro Kuroda, “Design and application of analog CMOS integrated circuits”, Maruzen Co., Ltd., p. 816-819, 2003 William J.Dally,John W.Poulton著,黒田忠広監訳,“デジタルシステム工学 基礎編”,丸善株式会社,p.38−40,2003年William J. et al. Dally, John W. By Paulton, translated by Tadahiro Kuroda, “Digital System Engineering Fundamentals”, Maruzen Co., Ltd., p. 38-40, 2003 津留正臣,田中俊行,稲垣隆二,谷口英司,中山正敏,亀田卓,末松憲治,高木直,坪内和夫,“フリップチップ実装した60GHz受信フロントエンドCMOS ICの試作”,2012年電子情報通信学会エレクトロニクスソサイエティ大会,C−2−8,p.34,2012年Tsuru Masaomi, Tanaka Toshiyuki, Inagaki Ryuji, Taniguchi Eiji, Nakayama Masatoshi, Kameda Takuji, Suematsu Kenji, Takagi Nao, Tsubouchi Kazuo, "Prototype of 60 GHz Receiving Front-End CMOS IC with Flip-Chip", 2012 IEICE Electronics Society Convention, C-2-8, p. 34, 2012

しかしながら、非特許文献1に開示された方法では、パッド数増加によってチップ面積が大きくなるという問題点があり、また非特許文献2、非特許文献3に開示された方法では、実装コストが大きくなるという問題点があった。   However, the method disclosed in Non-Patent Document 1 has a problem that the chip area increases due to an increase in the number of pads, and the methods disclosed in Non-Patent Document 2 and Non-Patent Document 3 increase the mounting cost. There was a problem.

本発明は、上記課題を解決するためになされたもので、チップサイズの増加や実装コストの増加を抑えることができる高周波RF回路を提供することを目的とする。   The present invention has been made to solve the above-described problems, and an object thereof is to provide a high-frequency RF circuit capable of suppressing an increase in chip size and an increase in mounting cost.

本発明の高周波RF回路は、半導体基板上に形成されるRF回路と、前記RF回路に直流バイアスを与える為に前記半導体基板上に形成される複数の電源用パッドと、前記半導体基板上に形成され、前記複数の電源用パッドとこれに対応する前記RF回路の複数の端子とを接続する複数の配線とを備え、前記配線のうちの一つに、所望の周波数帯域において特性インピーダンスが略0の分布定数型の伝送線路を用い、当該伝送線路が接続されたRF回路の端子と、前記伝送線路が接続された電源用パッド以外の他の電源用パッドとの間を、電源用パッド毎に個別に容量素子を介して接続することを特徴とするものである。
また、本発明の高周波RF回路の1構成例において、前記伝送線路は、所望の周波数帯域において、前記RF回路の端子から見た反射特性がスミスチャート上のインピーダンス0付近に存在するように前記特性インピーダンスが設定されることを特徴とするものである。
また、本発明の高周波RF回路の1構成例は、前記伝送線路を前記複数の電源用パッドのうちの一つとこれに対応する前記RF回路の端子との間に接続することを特徴とするものである。
また、本発明の高周波RF回路の1構成例は、前記伝送線路の一端を前記複数の電源用パッドのうちの一つとこれに対応する前記RF回路の端子との間の配線に接続し、前記伝送線路の他端を電気的に開放することを特徴とするものである。
また、本発明の高周波RF回路の1構成例において、前記伝送線路は、マイクロストリップ線路である。
また、本発明の高周波RF回路の1構成例において、前記伝送線路は、GND付コプレーナ線路である。
The high-frequency RF circuit of the present invention is formed on the semiconductor substrate, an RF circuit formed on the semiconductor substrate, a plurality of power supply pads formed on the semiconductor substrate for applying a DC bias to the RF circuit, and the semiconductor substrate. A plurality of wirings for connecting the plurality of power supply pads and the corresponding plurality of terminals of the RF circuit, and one of the wirings has a characteristic impedance of approximately 0 in a desired frequency band. For each power supply pad, between the terminal of the RF circuit to which the transmission line is connected and a power supply pad other than the power supply pad to which the transmission line is connected. It is characterized by being individually connected through a capacitive element .
Further, in one configuration example of the high-frequency RF circuit of the present invention, the transmission line has the characteristics such that a reflection characteristic viewed from a terminal of the RF circuit exists in the vicinity of impedance 0 on the Smith chart in a desired frequency band. The impedance is set.
Also, one configuration example of the high-frequency RF circuit of the present invention is characterized in that the transmission line is connected between one of the plurality of power supply pads and the corresponding terminal of the RF circuit. It is.
Further, in one configuration example of the high-frequency RF circuit of the present invention, one end of the transmission line is connected to a wiring between one of the plurality of power supply pads and the corresponding terminal of the RF circuit, The other end of the transmission line is electrically opened.
In one configuration example of the high-frequency RF circuit of the present invention, the transmission line is a microstrip line.
In one configuration example of the high-frequency RF circuit of the present invention, the transmission line is a coplanar line with GND.

本発明によれば、同一の半導体基板上に形成された電源用パッドとRF回路の端子とを接続する配線の一部あるいは全てに所望の周波数帯域において特性インピーダンスが略0の分布定数型の伝送線路を用いることにより、ミリ波帯やそれ以上の周波数帯を扱うRF回路において、実装時に電源用パッドに寄生するインダクタンス成分の影響を受けにくい高周波RF回路の設計が可能となる為、電源用パッド数を増加する事によるチップサイズの増加や、寄生インダクタンスが生じにくいフリップチップ実装などの高コスト実装を不要とし、より低コストな高周波RF回路が実現可能となる。   According to the present invention, a distributed constant type transmission having a characteristic impedance of approximately 0 in a desired frequency band is applied to a part or all of the wiring connecting the power supply pad and the RF circuit terminal formed on the same semiconductor substrate. By using a line, it is possible to design a high-frequency RF circuit that is less susceptible to the inductance component parasitic to the power supply pad during mounting in an RF circuit that handles a millimeter wave band or higher frequency band. Increasing the number eliminates the need for high-cost mounting such as an increase in chip size and flip-chip mounting in which parasitic inductance is unlikely to occur, and a low-cost high-frequency RF circuit can be realized.

理想電源と実装にて寄生するインダクタンスとを模擬した等価回路図である。FIG. 6 is an equivalent circuit diagram that simulates an ideal power supply and an inductance that is parasitic in mounting. 本発明にて提案する、電源パッドとRF回路間に直列に伝送線路を挿入する回路構成を示す図である。It is a figure which shows the circuit structure which inserts a transmission line in series between a power supply pad and RF circuit proposed by this invention. 本発明にて提案する、電源パッドとRF回路間に片端を開放した伝送線路を挿入する回路構成を示す図である。It is a figure which shows the circuit structure which inserts the transmission line which open | released one end between the power supply pad and RF circuit proposed by this invention. 本発明の伝送線路の1例を示す断面図である。It is sectional drawing which shows one example of the transmission line of this invention. 本発明の伝送線路の他の例を示す断面図である。It is sectional drawing which shows the other example of the transmission line of this invention. 本発明に係るRF回路の例を示す回路図である。It is a circuit diagram which shows the example of RF circuit which concerns on this invention. 図6のRF回路に接続する電源配線等価回路を示す図である。It is a figure which shows the power supply wiring equivalent circuit connected to RF circuit of FIG. 図6のRF回路の利得シミュレーション結果を示す図である。It is a figure which shows the gain simulation result of the RF circuit of FIG. 本発明の第1の参考例に係るICチップの構成を示すブロック図である。It is a block diagram which shows the structure of the IC chip which concerns on the 1st reference example of this invention. 本発明の第1の実施の形態に係るICチップの構成を示すブロック図である。 1 is a block diagram showing a configuration of an IC chip according to a first embodiment of the present invention. 本発明の第2の参考例に係るICチップの構成を示すブロック図である。It is a block diagram which shows the structure of the IC chip which concerns on the 2nd reference example of this invention. 本発明の第2の実施の形態に係るICチップの構成を示すブロック図である。It is a block diagram which shows the structure of the IC chip which concerns on the 2nd Embodiment of this invention.

[発明の原理]
本発明で提案する高周波RF回路では、電源電位、バイアス電位、GND電位等のDCバイアスを与えるRF回路の端子と、電源用パッドとの間に数Ω以下という小さな特性インピーダンスを持つ伝送線路を挿入する事で、RF回路を含むICチップをセラミック基板等に実装した時に電源用パッドに寄生するインダクタンス成分の影響を低減する事が可能となる。前記伝送線路において、特性インピーダンスが小さい(0Ωに近い)程、必要な線路長が短く、かつ広範囲の周波数帯において寄生するインダクタンスの影響を低減する事が可能となる。
[Principle of the Invention]
In the high-frequency RF circuit proposed in the present invention, a transmission line having a small characteristic impedance of several Ω or less is inserted between the terminal of the RF circuit that applies a DC bias such as a power supply potential, a bias potential, and a GND potential and the power supply pad. By doing so, it is possible to reduce the influence of an inductance component parasitic on the power supply pad when an IC chip including an RF circuit is mounted on a ceramic substrate or the like. In the transmission line, the smaller the characteristic impedance (closer to 0Ω), the shorter the required line length and the less the influence of the parasitic inductance in a wide frequency band.

本発明の原理を説明するため、内部抵抗が0Ωの理想電源100とインダクタ素子101とを直列に接続した図1に示す回路構成において、ノード102から見た反射特性を考える。スミスチャート上で前記反射特性を描くと、周波数fが0→∞となるにつれて、インピーダンス=0の点から半径1の円周上を時計回りに移動し、インピーダンス=∞の点に収束する。内部抵抗が0Ωの理想電源100は常にインピーダンス=0であるので、高周波RF回路において理想電源接続時と同様の特性を得る為には、所望の周波数帯域において、ノード102から見た反射特性がスミスチャート上のインピーダンス=0の点付近に存在する必要がある。しかし、ミリ波帯やそれ以上の高周波帯では、僅かなインダクタンスが寄生するだけでインピーダンス=0の点から遠ざかってしまい、結果として回路の特性が変化する。   In order to explain the principle of the present invention, the reflection characteristic viewed from the node 102 is considered in the circuit configuration shown in FIG. 1 in which an ideal power source 100 having an internal resistance of 0Ω and an inductor element 101 are connected in series. When the reflection characteristic is drawn on the Smith chart, as the frequency f is changed from 0 to ∞, it moves clockwise on the circumference of radius 1 from the point of impedance = 0 and converges to the point of impedance = ∞. Since the ideal power supply 100 with an internal resistance of 0Ω always has an impedance of 0, in order to obtain the same characteristics as when an ideal power supply is connected in a high-frequency RF circuit, the reflection characteristics viewed from the node 102 in the desired frequency band are Smith. It must exist near the point where impedance = 0 on the chart. However, in the millimeter wave band and the higher frequency band beyond it, only a small amount of inductance is parasitic and it moves away from the point where impedance = 0, resulting in a change in circuit characteristics.

一方で、図2に示すようにインダクタ素子101と理想電源100に更に伝送線路103を直列に接続した回路構成を用いた場合、ノード102から見た反射特性をスミスチャート上で描くと、周波数が0→∞となるにつれて、インピーダンス=0の点から半径1の円周上を時計回りに(どこかの点に収束せずに)移動し続ける為、いずれかの周波数帯で再びインピーダンス=0の点に近付く。また、図2中の伝送線路103の特性インピーダンスを0Ωに近づけるほど、この伝送線路103の影響でスミスチャート上を時計回りに周る基準点が0Ω付近にシフトする為、ノード102から見た反射特性がインピーダンス=0の点付近に存在する周波数帯域が広がる。すなわち広い周波数帯域において、RF回路の特性を理想電源接続時に近づける事が出来る。   On the other hand, when the circuit configuration in which the transmission line 103 is further connected in series to the inductor element 101 and the ideal power source 100 as shown in FIG. 2 is used, when the reflection characteristic viewed from the node 102 is drawn on the Smith chart, the frequency is As it goes from 0 to ∞, it continues to move clockwise on the circumference of radius 1 from the point of impedance = 0 (without converging to some point), so impedance = 0 again in any frequency band Approach the point. Further, as the characteristic impedance of the transmission line 103 in FIG. 2 approaches 0Ω, the reference point that rotates clockwise on the Smith chart shifts to near 0Ω due to the influence of the transmission line 103, and thus the reflection seen from the node 102 The frequency band where the characteristic exists near the point where impedance = 0 is widened. That is, in a wide frequency band, the characteristics of the RF circuit can be brought close to the ideal power supply connection.

また、図3に示すようにノード102とインダクタ素子101との接続点に伝送線路104の一端を接続し、伝送線路104の他端を開放した回路構成を用いた場合、伝送線路長が1/4波長以下の周波数帯において、容量性に見える為、ノード102から見た反射特性をスミスチャート上で描くと、周波数が0→∞となるにつれて、インピーダンス=0の点から半径1の円周上を時計回りに(どこかの点に収束せずに)移動し続け、伝送線路長=1/4波長となる周波数帯で再びインピーダンス=0の点に近付く。この際、用いる伝送線路104のインピーダンスが0Ωに近い程、この伝送線路104の影響でスミスチャート上を時計回りに周る基準点が0Ω付近にシフトする為、ノード102から見た反射特性がインピーダンス=0の点付近に存在する周波数帯域が広がり、図2の時と同様に広い周波数帯域において、RF回路の特性を理想電源接続時に近づける事が出来る。   In addition, when a circuit configuration is used in which one end of the transmission line 104 is connected to the connection point between the node 102 and the inductor element 101 and the other end of the transmission line 104 is opened as shown in FIG. Since it looks capacitive in the frequency band of 4 wavelengths or less, when the reflection characteristic viewed from the node 102 is drawn on the Smith chart, as the frequency is changed from 0 to ∞, on the circumference of radius 1 from the point of impedance = 0. Is moved clockwise (without converging to some point), and again approaches the point where impedance = 0 in the frequency band where transmission line length = 1/4 wavelength. At this time, as the impedance of the transmission line 104 to be used is closer to 0Ω, the reference point that rotates clockwise on the Smith chart is shifted to near 0Ω due to the influence of the transmission line 104. The frequency band existing in the vicinity of the = 0 point is widened, and the characteristics of the RF circuit can be brought close to the ideal power supply connection in a wide frequency band as in FIG.

ここで、所望の周波数帯域において特性インピーダンスが0Ωに近い伝送線路103,104の例としては、例えば多層配線構造が可能な半導体基板上に伝送線路103,104を形成する場合、図4に示すように厚さが比較的小さい1層の層間絶縁膜のみを信号線200とGND201間の誘電体層202とし、信号線幅を数十μm〜100μm程度としたマイクロストリップ線路がある。   Here, as an example of the transmission lines 103 and 104 having a characteristic impedance close to 0Ω in a desired frequency band, for example, when the transmission lines 103 and 104 are formed on a semiconductor substrate capable of a multilayer wiring structure, as shown in FIG. In addition, there is a microstrip line in which only one interlayer insulating film having a relatively small thickness is used as the dielectric layer 202 between the signal line 200 and the GND 201 and the signal line width is about several tens to 100 μm.

また、所望の周波数帯域において特性インピーダンスが0Ωに近い伝送線路103,104の他の例としては、図5に示すように厚さが比較的小さい1層の層間絶縁膜のみを信号線300とGND301間の誘電体層302とし、かつ信号線300の両側にもGND301を形成したGND付コプレーナ線路がある。こうして、マイクロストリップ線路またはGND付コプレーナ線路を用いることにより、IC内に搭載可能なサイズにて、特性インピーダンスが0Ωに近い伝送線路を形成する事が可能である。また、配線層数が少ないプロセスにおいては、信号線300とGND301の隙間を小さく設計したコプレーナ線路構造を用いる事が有効となる。   Further, as another example of the transmission lines 103 and 104 having a characteristic impedance close to 0Ω in a desired frequency band, as shown in FIG. 5, only the one-layer interlayer insulating film having a relatively small thickness is used as the signal line 300 and the GND 301. There is a coplanar transmission line with GND in which a dielectric layer 302 is provided between them and GND 301 is formed on both sides of the signal line 300. Thus, by using the microstrip line or the GND coplanar line, it is possible to form a transmission line having a characteristic impedance close to 0Ω with a size that can be mounted in an IC. In a process with a small number of wiring layers, it is effective to use a coplanar line structure in which the gap between the signal line 300 and the GND 301 is designed to be small.

図6にRF回路の一例である狭帯域アンプ回路の構成を示す。狭帯域アンプ回路は、ソースが電源電圧端子VSSに接続されたトランジスタQ1,Q2と、一端がバイアス電圧端子BIASに接続され、他端がトランジスタQ1のゲートに接続された抵抗R1と、一端が電源電圧端子VDDに接続され、他端がトランジスタQ1のドレインに接続された抵抗R2と、一端がバイアス電圧端子BIASに接続され、他端がトランジスタQ2のゲートに接続された抵抗R3と、一端が電源電圧端子VDDに接続され、他端がトランジスタQ2のドレインに接続された抵抗R4と、一端が信号入力端子INに接続され、他端がトランジスタQ1のゲートに接続された容量素子C1と、一端がトランジスタQ1のドレインに接続され、他端がトランジスタQ2のゲートに接続された容量素子C2と、一端がトランジスタQ2のドレインに接続され、他端が信号出力端子OUTに接続された容量素子C3とから構成される。   FIG. 6 shows a configuration of a narrowband amplifier circuit which is an example of an RF circuit. The narrowband amplifier circuit includes transistors Q1 and Q2 whose sources are connected to the power supply voltage terminal VSS, one end connected to the bias voltage terminal BIAS, the other end connected to the gate of the transistor Q1, and one end connected to the power supply. The resistor R2 is connected to the voltage terminal VDD, the other end is connected to the drain of the transistor Q1, the one end is connected to the bias voltage terminal BIAS, the other end is connected to the gate of the transistor Q2, and the other end is the power source. A resistor R4 connected to the voltage terminal VDD and having the other end connected to the drain of the transistor Q2, a capacitor element C1 having one end connected to the signal input terminal IN and the other end connected to the gate of the transistor Q1, and one end The capacitive element C2 is connected to the drain of the transistor Q1 and the other end is connected to the gate of the transistor Q2. It is connected to the drain of the static Q2, composed of a capacitor which is connected C3 Metropolitan the other end signal output terminal OUT.

図7(A)に示すように理想電源100のみを、図6に示した狭帯域アンプ回路のノード102(電源電圧端子VDD、電源電圧端子VSS、バイアス電圧端子BIAS)のそれぞれに接続した際の狭帯域アンプ回路の利得Y0をシミュレーションした結果を図8(A)に示す。また、図7(B)に示すように理想電源100と狭帯域アンプ回路のノード102との間に、実装によって寄生するインダクタンスを模擬したインダクタ素子101(1nH)を付加した場合の狭帯域アンプ回路の利得Y0をシミュレーションした結果を図8(B)に示す。また、図7(C)に示すように前記インダクタ素子101(1nH)と狭帯域アンプ回路のノード102との間に、特性インピーダンスZ0=0.5Ωで線路長L=200μmの伝送線路103を直列に付加した場合の狭帯域アンプ回路の利得Y0をシミュレーションした結果を図8(C)に示す。 As shown in FIG. 7A, only the ideal power supply 100 is connected to each of the nodes 102 (power supply voltage terminal VDD, power supply voltage terminal VSS, bias voltage terminal BIAS) of the narrowband amplifier circuit shown in FIG. A simulation result of the gain Y0 of the narrowband amplifier circuit is shown in FIG. Further, as shown in FIG. 7B, a narrowband amplifier circuit in the case where an inductor element 101 (1 nH) that simulates an inductance parasitic by mounting is added between the ideal power supply 100 and the node 102 of the narrowband amplifier circuit. The result of simulating the gain Y0 is shown in FIG. Further, as shown in FIG. 7C, a transmission line 103 having a characteristic impedance Z 0 = 0.5Ω and a line length L = 200 μm is provided between the inductor element 101 (1 nH) and the node 102 of the narrowband amplifier circuit. FIG. 8C shows the result of simulating the gain Y0 of the narrowband amplifier circuit when added in series.

図8(A)と図8(B)を比較すると、ノード102に理想電源100のみを接続した場合と、実装による寄生インダクタンスを想定した場合には、狭帯域アンプ回路の特性が大きく変化している事が分かる。一方で、図8(A)と図8(C)を比較すると、狭帯域アンプ回路の特性はほぼ同様の値を示している。よって、本発明で提案する高周波RF回路を用いる事で、ミリ波帯やそれ以上の周波数帯の高周波RF回路を搭載するICの電源用パッドに寄生するインダクタンスによる影響を大幅に低減することが可能である事が分かる。   Comparing FIG. 8A and FIG. 8B, when only the ideal power supply 100 is connected to the node 102 and when the parasitic inductance due to mounting is assumed, the characteristics of the narrowband amplifier circuit change greatly. I understand that. On the other hand, when FIG. 8A is compared with FIG. 8C, the characteristics of the narrowband amplifier circuit show almost the same values. Therefore, by using the high-frequency RF circuit proposed in the present invention, it is possible to greatly reduce the influence of the parasitic inductance on the power supply pad of the IC mounting the high-frequency RF circuit in the millimeter wave band or higher frequency band. I understand that.

第1の参考例
次に、図面に示す参考例および実施の形態に基づいて、本発明を詳細に説明する。図9は本発明の第1の参考例に係るICチップの構成を示すブロック図である。図9に示すICチップ3では、RF回路部1(コア回路部)のDCバイアス用の端子2−1(例えば電源電圧端子VDD)と、このRF回路部1と同一の半導体基板上に形成されたDC用パッド4−1(電源電圧VDD供給用のパッド)との間に特性インピーダンスZ0が略0の伝送線路5−1を挿入し、RF回路部1のDCバイアス用の端子2−2(例えば電源電圧端子VSS)と、RF回路部1と同一の半導体基板上に形成されたDC用パッド4−2(電源電圧VSS供給用のパッド)との間に特性インピーダンスZ0が略0の伝送線路5−2を挿入し、RF回路部1のDCバイアス用の端子2−3(例えばバイアス電圧端子BIAS)と、RF回路部1と同一の半導体基板上に形成されたDC用パッド4−3(バイアス電圧BIAS供給用のパッド)との間に特性インピーダンスZ0が略0の伝送線路5−3を挿入している。RF回路部1の構成は、図6に示したとおりである。図4、図5で説明したとおり、伝送線路5−1〜5−3は、RF回路部1と同一の半導体基板上に形成される。端子2−1と伝送線路5−1との間、端子2−2と伝送線路5−2との間、端子2−3と伝送線路5−3との間、伝送線路5−1とDC用パッド4−1との間、伝送線路5−2とDC用パッド4−2との間、伝送線路5−3とDC用パッド4−3との間は、RF回路部1と同一の半導体基板上に形成された配線によって接続されている。
[ First Reference Example ]
Next, the present invention will be described in detail based on reference examples and embodiments shown in the drawings. FIG. 9 is a block diagram showing a configuration of an IC chip according to the first reference example of the present invention. The IC chip 3 shown in FIG. 9 is formed on the same semiconductor substrate as the RF circuit unit 1 and the DC bias terminal 2-1 (for example, the power supply voltage terminal VDD) of the RF circuit unit 1 (core circuit unit). A transmission line 5-1 having a characteristic impedance Z 0 of approximately 0 is inserted between the DC pad 4-1 (pad for supplying the power supply voltage VDD) and a DC bias terminal 2-2 of the RF circuit unit 1. (For example, the power supply voltage terminal VSS) and the DC pad 4-2 (pad for supplying the power supply voltage VSS) formed on the same semiconductor substrate as the RF circuit unit 1 have a characteristic impedance Z 0 of substantially zero. A transmission line 5-2 is inserted, a DC bias terminal 2-3 (for example, a bias voltage terminal BIAS) of the RF circuit unit 1, and a DC pad 4-formed on the same semiconductor substrate as the RF circuit unit 1. 3 (Supply of bias voltage BIAS Characteristic impedance Z 0 between the pad) of use is inserting a transmission line 5-3 of substantially 0. The configuration of the RF circuit unit 1 is as shown in FIG. As described with reference to FIGS. 4 and 5, the transmission lines 5-1 to 5-3 are formed on the same semiconductor substrate as that of the RF circuit unit 1. Between terminal 2-1 and transmission line 5-1, between terminal 2-2 and transmission line 5-2, between terminal 2-3 and transmission line 5-3, transmission line 5-1 and DC The same semiconductor substrate as that of the RF circuit unit 1 is between the pad 4-1, between the transmission line 5-2 and the DC pad 4-2, and between the transmission line 5-3 and the DC pad 4-3. They are connected by the wiring formed above.

このような構成により、本参考例では、ICチップ3をセラミック基板等に実装した時に各DC用パッド4−1〜4−3に寄生するインダクタンスの影響をそれぞれキャンセリングすることができる。本参考例では、ICチップ3をセラミック基板等に実装する際にフリップチップ実装を用いる必要がなく、ワイヤボンディング等の簡単な実装方法を採用することができるので、ミリ波帯やそれ以上の周波数帯を扱うRF回路において、RF回路の性能を低下させることなく、簡易かつ低コストで電源配線実装を行う事が可能となる。 With such a configuration, in the present reference example, it is possible to cancel the influence of the inductance parasitic on each of the DC pads 4-1 to 4-3 when the IC chip 3 is mounted on a ceramic substrate or the like. In this reference example , when the IC chip 3 is mounted on a ceramic substrate or the like, it is not necessary to use flip chip mounting, and a simple mounting method such as wire bonding can be employed. In an RF circuit that handles a band, power supply wiring can be mounted easily and at low cost without degrading the performance of the RF circuit.

第1の実施の形態
次に、本発明の第1の実施の形態について説明する。図10は本発明の第1の実施の形態に係るICチップの構成を示すブロック図であり、図9と同一の構成には同一の符号を付してある。第1の参考例との差異として、第1の参考例では全てのDC用パッド4−1〜4−3とRF回路部1の端子2−1〜2−3との間に特性インピーダンスZ0が略0の伝送線路5−1〜5−3を挿入していたのに対し、本実施の形態では一部のDC用パッド4−1(例えば電源電圧VDD供給用のパッド)とRF回路部1のDCバイアス用の端子2−1(例えば電源電圧端子VDD)との間に特性インピーダンスZ0が略0の伝送線路5−1を挿入している。そして、この伝送線路5−1が接続された端子2−1と、伝送線路5−1が接続されたDC用パッド4−1以外の他のDC用パッド4−2,4−3との間に容量素子6−1,6−2を接続している。容量素子6−1,6−2は、RF回路部1と同一の半導体基板上に形成される。端子2−1と伝送線路5−1との間、伝送線路5−1とDC用パッド4−1との間、端子2−2とDC用パッド4−2との間、端子2−3とDC用パッド4−3との間は、RF回路部1と同一の半導体基板上に形成された配線によって接続されている。
[ First Embodiment ]
Next, a first embodiment of the present invention will be described. FIG. 10 is a block diagram showing the configuration of the IC chip according to the first embodiment of the present invention. The same components as those in FIG. 9 are denoted by the same reference numerals. As a difference from the first reference example , in the first reference example , the characteristic impedance Z 0 is present between all the DC pads 4-1 to 4-3 and the terminals 2-1 to 2-3 of the RF circuit unit 1. In this embodiment, some DC pads 4-1 (for example, pads for supplying the power supply voltage VDD) and the RF circuit section are inserted. A transmission line 5-1 having a characteristic impedance Z 0 of approximately 0 is inserted between the DC bias terminal 2-1 (for example, the power supply voltage terminal VDD). Between the terminal 2-1 to which the transmission line 5-1 is connected and the DC pads 4-2 and 4-3 other than the DC pad 4-1 to which the transmission line 5-1 is connected. Capacitance elements 6-1 and 6-2 are connected to. The capacitive elements 6-1 and 6-2 are formed on the same semiconductor substrate as that of the RF circuit unit 1. Between the terminal 2-1 and the transmission line 5-1, between the transmission line 5-1 and the DC pad 4-1, between the terminal 2-2 and the DC pad 4-2, and between the terminal 2-3 and The DC pad 4-3 is connected by wiring formed on the same semiconductor substrate as the RF circuit unit 1.

このような構成により、本実施の形態では、用いる伝送線路の数を低減しつつ、実装時に各DC用パッド4−1〜4−3に寄生するインダクタンスの影響をそれぞれキャンセリングすることができ、ミリ波帯やそれ以上の周波数帯を扱うRF回路において、RF回路の性能を低下させることなく、簡易かつ低コストで電源配線実装を行う事が可能となる。   With such a configuration, in the present embodiment, it is possible to cancel the influence of the inductance parasitic on each of the DC pads 4-1 to 4-3 at the time of mounting while reducing the number of transmission lines to be used, In an RF circuit that handles a millimeter wave band or higher frequency band, power supply wiring can be easily and inexpensively implemented without degrading the performance of the RF circuit.

第2の参考例
次に、本発明の第2の参考例について説明する。図11は本発明の第2の参考例に係るICチップの構成を示すブロック図であり、図9、図10と同一の構成には同一の符号を付してある。図11に示すICチップ3では、RF回路部1のDCバイアス用の端子2−1とDC用パッド4−1との間に、特性インピーダンスZ0が略0で一端が開放状態の伝送線路7−1の他端を接続し、RF回路部1のDCバイアス用の端子2−2とDC用パッド4−2との間に、特性インピーダンスZ0が略0で一端が開放状態の伝送線路7−2の他端を接続し、RF回路部1のDCバイアス用の端子2−3とDC用パッド4−3との間に、特性インピーダンスZ0が略0で一端が開放状態の伝送線路7−3の他端を接続している。図4、図5で説明したとおり、伝送線路7−1〜7−3は、RF回路部1と同一の半導体基板上に形成される。端子2−1とDC用パッド4−1との間、端子2−2とDC用パッド4−2との間、端子2−3とDC用パッド4−3との間は、RF回路部1と同一の半導体基板上に形成された配線によって接続されている。
[ Second Reference Example ]
Next, a second reference example of the present invention will be described. FIG. 11 is a block diagram showing a configuration of an IC chip according to a second reference example of the present invention. The same components as those in FIGS. 9 and 10 are denoted by the same reference numerals. In the IC chip 3 shown in FIG. 11, between the DC bias terminal 2-1 and the DC pad 4-1 of the RF circuit unit 1, the transmission line 7 having a characteristic impedance Z 0 of approximately 0 and one end open. -1 is connected, and a transmission line 7 having a characteristic impedance Z 0 of approximately 0 and one end open between the DC bias terminal 2-2 and the DC pad 4-2 of the RF circuit unit 1 is connected. -2 is connected, and between the DC bias terminal 2-3 of the RF circuit section 1 and the DC pad 4-3, the transmission line 7 having a characteristic impedance Z 0 of approximately 0 and one end open. -3 is connected to the other end. As described with reference to FIGS. 4 and 5, the transmission lines 7-1 to 7-3 are formed on the same semiconductor substrate as the RF circuit unit 1. Between the terminal 2-1 and the DC pad 4-1, between the terminal 2-2 and the DC pad 4-2, and between the terminal 2-3 and the DC pad 4-3, the RF circuit unit 1 is provided. Are connected by wiring formed on the same semiconductor substrate.

このような構成により、本参考例では、実装時に各DC用パッド4−1〜4−3に寄生するインダクタンスの影響をそれぞれキャンセリングすることができ、ミリ波帯やそれ以上の周波数帯を扱うRF回路において、RF回路の性能を低下させることなく、簡易かつ低コストで電源配線実装を行う事が可能となる。 With such a configuration, in this reference example , it is possible to cancel the influence of the inductance parasitic on each of the DC pads 4-1 to 4-3 at the time of mounting, and the millimeter wave band and higher frequency bands are handled. In the RF circuit, it is possible to mount the power supply wiring easily and at low cost without degrading the performance of the RF circuit.

第2の実施の形態
次に、第2の実施の形態について説明する。図12は本発明の第2の実施の形態に係るICチップの構成を示すブロック図であり、図9〜図11と同一の構成には同一の符号を付してある。第2の参考例との差異として、第2の参考例では全てのDC用パッド4−1〜4−3とRF回路部1の端子2−1〜2−3との間に特性インピーダンスZ0が略0の伝送線路7−1〜7−3を接続していたのに対し、本実施の形態では一部のDC用パッド4−1(例えば電源電圧VDD供給用のパッド)とRF回路部1のDCバイアス用の端子2−1(例えば電源電圧端子VDD)との間に、特性インピーダンスZ0が略0で一端が開放状態の伝送線路7−1の他端を接続している。そして、この伝送線路7−1が接続された端子2−1と、伝送線路7−1が接続されたDC用パッド4−1以外の他のDC用パッド4−2,4−3との間に容量素子6−1,6−2を接続している。端子2−1とDC用パッド4−1との間、端子2−2とDC用パッド4−2との間、端子2−3とDC用パッド4−3との間は、RF回路部1と同一の半導体基板上に形成された配線によって接続されている。
[ Second Embodiment ]
Next, a second embodiment will be described. FIG. 12 is a block diagram showing the configuration of an IC chip according to the second embodiment of the present invention. The same components as those in FIGS. 9 to 11 are denoted by the same reference numerals. As a difference from the second reference example , in the second reference example , the characteristic impedance Z 0 is present between all the DC pads 4-1 to 4-3 and the terminals 2-1 to 2-3 of the RF circuit unit 1. Is connected to the transmission lines 7-1 to 7-3 having substantially zero, in the present embodiment, some DC pads 4-1 (for example, pads for supplying the power supply voltage VDD) and the RF circuit section are connected. The other end of the transmission line 7-1 having a characteristic impedance Z 0 of approximately 0 and one end open is connected to one DC bias terminal 2-1 (for example, the power supply voltage terminal VDD). Between the terminal 2-1 to which the transmission line 7-1 is connected and the DC pads 4-2 and 4-3 other than the DC pad 4-1 to which the transmission line 7-1 is connected. Capacitance elements 6-1 and 6-2 are connected to. Between the terminal 2-1 and the DC pad 4-1, between the terminal 2-2 and the DC pad 4-2, and between the terminal 2-3 and the DC pad 4-3, the RF circuit unit 1 is provided. Are connected by wiring formed on the same semiconductor substrate.

このような構成により、本実施の形態では、用いる伝送線路の数を低減しつつ、実装時に各DC用パッド4−1〜4−3に寄生するインダクタンスの影響をそれぞれキャンセリングすることができ、ミリ波帯やそれ以上の周波数帯を扱うRF回路において、RF回路の性能を低下させることなく、簡易かつ低コストで電源配線実装を行う事が可能となる。   With such a configuration, in the present embodiment, it is possible to cancel the influence of the inductance parasitic on each of the DC pads 4-1 to 4-3 at the time of mounting while reducing the number of transmission lines to be used, In an RF circuit that handles a millimeter wave band or higher frequency band, power supply wiring can be easily and inexpensively implemented without degrading the performance of the RF circuit.

本発明は、ミリ波帯やそれ以上の周波数帯を扱う高周波RF回路に適用することができる。   The present invention can be applied to a high-frequency RF circuit that handles a millimeter wave band or higher frequency band.

1…RF回路部、2−1〜2−3…端子、3…ICチップ、4−1〜4−3…DC用パッド、5−1〜5−3,7−1〜7−3…伝送線路、6−1〜6−2…容量素子。   DESCRIPTION OF SYMBOLS 1 ... RF circuit part, 2-1 to 2-3 ... terminal, 3 ... IC chip, 4-1 to 4-3 ... DC pad, 5-1 to 5-3, 7-1 to 7-3 ... Transmission Lines, 6-1 to 6-2... Capacitance elements.

Claims (6)

半導体基板上に形成されるRF回路と、
前記RF回路に直流バイアスを与える為に前記半導体基板上に形成される複数の電源用パッドと、
前記半導体基板上に形成され、前記複数の電源用パッドとこれに対応する前記RF回路の複数の端子とを接続する複数の配線とを備え、
前記配線のうちの一つに、所望の周波数帯域において特性インピーダンスが略0の分布定数型の伝送線路を用い
当該伝送線路が接続されたRF回路の端子と、前記伝送線路が接続された電源用パッド以外の他の電源用パッドとの間を、電源用パッド毎に個別に容量素子を介して接続することを特徴とする高周波RF回路。
An RF circuit formed on a semiconductor substrate;
A plurality of power supply pads formed on the semiconductor substrate to apply a DC bias to the RF circuit;
Wherein formed on the semiconductor substrate, and a plurality of wire connecting the plurality of terminals of the RF circuit corresponding thereto and the plurality of power supply pads,
For one of the wires, a distributed constant transmission line having a characteristic impedance of approximately 0 in a desired frequency band is used .
An RF circuit terminal to which the transmission line is connected and a power supply pad other than the power supply pad to which the transmission line is connected are individually connected to each power supply pad via a capacitive element. A high frequency RF circuit characterized by
請求項1記載の高周波RF回路において、
前記伝送線路は、所望の周波数帯域において、前記RF回路の端子から見た反射特性がスミスチャート上のインピーダンス0付近に存在するように前記特性インピーダンスが設定されることを特徴とする高周波RF回路。
The high-frequency RF circuit according to claim 1,
The high-frequency RF circuit, wherein the transmission line has the characteristic impedance set so that a reflection characteristic viewed from a terminal of the RF circuit exists in the vicinity of impedance 0 on a Smith chart in a desired frequency band.
請求項1または2に記載の高周波RF回路において、
前記伝送線路を前記複数の電源用パッドのうちの一つとこれに対応する前記RF回路の端子との間に接続することを特徴とする高周波RF回路。
The high-frequency RF circuit according to claim 1 or 2,
A high-frequency RF circuit, wherein the transmission line is connected between one of the plurality of power supply pads and a corresponding terminal of the RF circuit.
請求項1または2に記載の高周波RF回路において、
前記伝送線路の一端を前記複数の電源用パッドのうちの一つとこれに対応する前記RF回路の端子との間の配線に接続し、前記伝送線路の他端を電気的に開放することを特徴とする高周波RF回路。
The high-frequency RF circuit according to claim 1 or 2,
One end of the transmission line is connected to a wiring between one of the plurality of power supply pads and the corresponding terminal of the RF circuit, and the other end of the transmission line is electrically opened. A high frequency RF circuit.
請求項1乃至4のいずれか1項に記載の高周波RF回路において、
前記伝送線路は、マイクロストリップ線路であることを特徴とする高周波RF回路。
In the high frequency RF circuit according to any one of claims 1 to 4,
The high-frequency RF circuit, wherein the transmission line is a microstrip line.
請求項1乃至4のいずれか1項に記載の高周波RF回路において、
前記伝送線路は、GND付コプレーナ線路であることを特徴とする高周波RF回路。
In the high frequency RF circuit according to any one of claims 1 to 4,
The high-frequency RF circuit according to claim 1, wherein the transmission line is a coplanar line with GND.
JP2013030833A 2013-02-20 2013-02-20 RF circuit Expired - Fee Related JP5960622B2 (en)

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