JP5987358B2 - Semiconductor device and manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

  Various mounting forms of semiconductor elements and semiconductor devices including the semiconductor elements are known. For example, a form in which a semiconductor element (semiconductor chip) is flip-chip mounted on a circuit board (FC (Flip Chip) method), a form in which a semiconductor element (semiconductor chip) is mounted on a tape material (TAB (Tape Automated Bonding) method), etc. Are known. Furthermore, a PoP (Package on Package) form in which another semiconductor device (semiconductor package) is stacked on a semiconductor device (semiconductor package) including a semiconductor element is also known. In addition, a configuration in which a semiconductor element (IC chip such as an LSI chip) is built in a multilayer substrate (IC chip built-in multilayer substrate) is also known.

  Also, in the semiconductor field, a technology for thermally connecting a heat radiating member to a mounted semiconductor element, a technology for electrically and magnetically connecting a ground (GND) connecting member, and an electromagnetic shield member are known. .

JP 2004-134669 A Japanese Patent Laid-Open No. 11-251483

  In the technique of Patent Document 1, in a multilayer substrate incorporating a semiconductor element, terminals for electrically connecting upper and lower layers are provided on the outer peripheral portion of each substrate, and the lower surface is provided in the central portion covering the semiconductor element inside the multilayer substrate. However, since the upper surface and side surfaces of the conductive paste are surrounded by the substrate, the heat dissipation to the outside is insufficient.

  Therefore, an object of the present invention is to provide a semiconductor device with improved heat dissipation.

According to one aspect of the present invention, a circuit board, a semiconductor element that is FC-mounted on the circuit board, a layer that is disposed on the circuit board and includes a housing portion that houses the semiconductor element, and the layer disposed within, and the signal electrode which is electrically connected to the circuit board, and the different electrodes and said signal electrodes disposed in the layer, is arranged on an upper surface of the semiconductor element and the layer, the signal electrode There is provided a semiconductor device including an electrically conductive sheet having an opening at a position corresponding to 1 and connecting to an electrode different from the signal electrode .

Further, according to one aspect of the present invention, a circuit board, a semiconductor element that is FC-mounted on the circuit board, a layer that is disposed on the circuit board and includes a housing portion that houses the semiconductor element, An electrode disposed in a layer, electrically connected to the circuit board and exposed from an upper surface of the layer, and disposed on an upper surface of the semiconductor element, the layer, and the electrode, and an insulating portion and dispersed in the insulating portion look including the anisotropic conductive sheet having a arranged conductive particles, the anisotropic conductive sheet, in part, a semiconductor device having a conductive portion to which the conductive particles with each other in contact with each other is provided.

  According to the disclosed technology, it is possible to realize a semiconductor device with high heat dissipation by disposing a conductive sheet on a semiconductor element that is FC-mounted on a circuit board and on a layer that accommodates the semiconductor element. .

It is a figure which shows an example of the semiconductor package which concerns on 1st Embodiment. It is FIG. (1) which shows an example of the formation process of the semiconductor package which concerns on 1st Embodiment. It is FIG. (2) which shows an example of the formation process of the semiconductor package which concerns on 1st Embodiment. It is a figure which shows an example of the semiconductor package of another form. It is a figure which shows an example of the semiconductor device which concerns on 2nd Embodiment. It is explanatory drawing (the 1) of an electroconductive sheet. It is explanatory drawing (the 2) of an electroconductive sheet. It is a figure which shows an example of the formation method of the semiconductor device which concerns on 2nd Embodiment. It is a figure which shows an example of the semiconductor device which concerns on 3rd Embodiment. It is a figure which shows an example of the semiconductor device which concerns on 4th Embodiment. It is explanatory drawing of an anisotropic conductive sheet. It is a figure which shows an example of the semiconductor device which concerns on 5th Embodiment. It is a figure which shows an example of formation and the test process of the semiconductor package which concerns on 5th Embodiment. It is a figure which shows an example of the test process of the semiconductor package which concerns on 5th Embodiment. It is explanatory drawing of the anisotropic conductive sheet in which the opening part was formed. It is a figure which shows an example of the semiconductor package which concerns on 6th Embodiment. It is a figure which shows an example of the test process of the semiconductor package which concerns on 6th Embodiment. It is a figure which shows an example of the anisotropic conductive sheet obtained after the test of the semiconductor package which concerns on 6th Embodiment. It is a figure which shows an example of the semiconductor device which concerns on 6th Embodiment. It is a figure which shows another example of the semiconductor device which concerns on 6th Embodiment. It is explanatory drawing in case a signal terminal is arrange | positioned above a semiconductor chip. It is explanatory drawing of the sheet | seat which concerns on 7th Embodiment. It is FIG. (1) which shows an example of the semiconductor device which concerns on 7th Embodiment. It is FIG. (2) which shows an example of the semiconductor device which concerns on 7th Embodiment. It is explanatory drawing of the sheet | seat which concerns on 8th Embodiment. It is a figure which shows the 1st example of the semiconductor device which concerns on 8th Embodiment. It is a figure which shows the 2nd example of the semiconductor device which concerns on 8th Embodiment. It is a figure which shows the 3rd example of the semiconductor device which concerns on 8th Embodiment. It is a figure which shows the 4th example of the semiconductor device which concerns on 8th Embodiment. It is a figure which shows an example of the semiconductor device which concerns on 9th Embodiment. It is a figure which shows an example of the semiconductor device which concerns on 10th Embodiment. It is a figure which shows an example of the electronic device which concerns on 11th Embodiment.

First, the first embodiment will be described.
FIG. 1 is a diagram showing an example of a semiconductor package according to the first embodiment. FIG. 1 schematically shows a cross-section of an essential part of an example of a semiconductor package.

A semiconductor package (semiconductor device) 10 shown in FIG. 1 includes a package substrate (circuit substrate) 11, a semiconductor chip (semiconductor element) 12, a layer 13, and a sheet 14.
Although not shown here, the package substrate 11 has an insulating portion and a conductive portion provided in the insulating portion. The conductive portion of the package substrate 11 is, for example, a wiring pattern having a predetermined shape, a via that electrically connects wiring patterns of different layers, and a joint (electrode pad, land) provided on the front and back surfaces.

  The semiconductor chip 12 is FC-mounted on one surface (front surface) side of such a package substrate 11. The semiconductor chip 12 is provided with bumps 12a such as solder balls on the surface facing the package substrate 11, and the bumps 12a are bonded to bonding portions (not shown) provided on the surface of the package substrate 11, so that the package substrate 11 is electrically connected.

  On the other surface (back surface) side of the package substrate 11, an insulating film 11 a such as a solder resist and an external terminal 11 b such as a solder ball electrically connected to the conductive portion of the package substrate 11 are provided. The semiconductor package 10 can be mounted on another circuit board such as a mother board via the external terminals 11b.

  The layer 13 is provided on the mounting surface side of the semiconductor chip 12 of the package substrate 11. The layer 13 includes an insulating layer 13a, a housing portion 13b, and an electrode (upper joint portion) 13c. The accommodating portion 13b is an opening that penetrates the insulating layer 13a. The accommodating portion 13b accommodates the semiconductor chip 12 that is FC-mounted on the package substrate 11. The electrode 13 c is provided in a through hole 13 d that penetrates the insulating layer 13 a, is joined to a joint portion (not shown) provided on the surface of the package substrate 11, and is electrically connected to the package substrate 11.

  A material such as prepreg or solder resist is used for the insulating layer 13a. The thickness of the insulating layer 13a (layer 13) is set based on the mounting height of the semiconductor chip 12 that is FC-mounted on the package substrate 11 from the surface of the package substrate 11. For example, the position (height) of the upper surface of the insulating layer 13a is the same as or equivalent to the position (height) of the upper surface (back surface (surface on the semiconductor substrate side)) of the semiconductor chip 12 that is FC-mounted on the package substrate 11. Thus, the thickness of the insulating layer 13a is set. The FC-mounted semiconductor chip 12 is accommodated in the accommodating portion 13b provided in the insulating layer 13a having such a thickness.

  An underfill resin (resin layer) 15 is filled between the semiconductor chip 12 accommodated in the accommodating portion 13b and the package substrate 11 to improve the bonding strength thereof. The underfill resin 15 can be selectively filled between the semiconductor chip 12 and the package substrate 11, or can be entirely filled in the housing portion 13 b. FIG. 1 illustrates a case where the accommodating portion 13b is entirely filled with the underfill resin 15.

  The electrode 13c is provided at a predetermined position of the insulating layer 13a, for example, in the insulating layer 13a in the region where the sheet 14 is disposed. A conductive material such as solder, copper (Cu), silver (Ag), or the like is used for the electrode 13c. For example, the electrode 13c is provided in the insulating layer 13a so that the position of the upper surface thereof is the same as or equivalent to the position of the upper surface of the insulating layer 13a.

  The sheet 14 includes a conductive portion and extends from the FC-mounted semiconductor chip 12 to the layer 13 that accommodates the semiconductor chip 12. As the sheet 14, a sheet in which conductive fillers (conductive portions) such as metal are dispersedly arranged in an insulating portion such as a resin can be used. For example, a conductive sheet exhibiting conductivity or an anisotropic conductive sheet that selectively exhibits conductivity at a pressed portion is used as the sheet 14.

  The sheet 14 extending from the semiconductor chip 12 to the layer 13 functions as a heat radiating member that radiates heat generated during the operation of the semiconductor chip 12 to the outside. Further, the sheet 14 functions as a GND reinforcing wiring of the semiconductor chip 12 by being electrically connected to the electrode 13c provided in the layer 13 in the arrangement region thereof and connected to the GND wiring of the package substrate 11. To do. Further, the GND-connected sheet 14 also functions as an electromagnetic shield member that shields electromagnetic waves radiated from or to the semiconductor chip 12.

  In the semiconductor package 10, by providing the layer 13 as described above, the sheet 14 that contributes to heat dissipation, GND strengthening, or electromagnetic shielding is easily and accurately disposed on the semiconductor chip 12 and the layer 13. Be able to.

  2 and 3 are views showing an example of a semiconductor package forming process according to the first embodiment. 2 (A) and 3 (A) schematically show a cross-section of the main part of an example of the state before the sheet placement, and FIGS. 2 (B) and 3 (B) show the state after the sheet placement. The cross section of the main part of an example of the state is schematically shown.

  In forming the semiconductor package 10, for example, first, as shown in FIG. 2A, the layer 13 is disposed on the package substrate 11. For example, after forming an insulating layer 13a such as a prepreg or a solder resist on the package substrate 11, the layer 13 is formed with an accommodating portion 13b and a through hole 13d, and the through hole 13d is filled with a conductive material to fill the electrode 13c. Can be obtained.

  An etching technique, a laser processing technique, a photolithography technique, or the like can be used to form the accommodating portion 13b and the through hole 13d in the insulating layer 13a. Which technique is used can be selected based on the material of the insulating layer 13a, the order of forming the layer 13, and the like. For filling the through hole 13d with a conductive material, a method of filling a conductive paste by printing, a method of forming and filling a plating layer using a plating technique, or the like can be used. Alternatively, a method of filling the through hole 13d with a conductive material by disposing a conductive material such as a microball in the through hole 13d and melting and solidifying it can also be used.

  Formation of the layer 13 having the accommodating portion 13b and the electrode 13c is performed by, for example, forming the insulating layer 13a on the package substrate 11, forming the accommodating portion 13b in the insulating layer 13a, and then forming the through hole 13d. A method of filling the hole 13d with a conductive material can be used. Alternatively, it is possible to use a method in which after the through hole 13d is formed in the insulating layer 13a formed on the package substrate 11, a conductive material is filled in the through hole 13d to form the accommodating portion 13b. Alternatively, it is possible to use a method in which after the through hole 13d is formed in the insulating layer 13a formed on the package substrate 11, the accommodating portion 13b is formed, and the through hole 13d is filled with a conductive material.

  For example, after the layer 13 is arranged on the package substrate 11 as described above, the semiconductor chip 12 uses the bumps 12a on the package substrate 11 in the accommodating portion 13b as shown in FIG. FC implementation. The layer 13 disposed on the package substrate 11 is set to a thickness such that the position of the upper surface thereof is the same as or equivalent to the position of the upper surface of the semiconductor chip 12 to be FC-mounted. For example, the layer 13 (insulating layer 13a) is set to a thickness of about 60 μm to 100 μm.

  When a prepreg is used for the insulating layer 13a, even if the insulating layer 13a having a predetermined thickness is realized by one prepreg, the insulating layer 13a having a predetermined thickness is realized by stacking a plurality of prepregs. Also good. When a solder resist is used for the insulating layer 13a, the insulating layer 13a having a predetermined thickness may be realized by a single application, or the insulating layer 13a having a predetermined thickness may be realized by a plurality of applications. . Further, the insulating layer 13a having a predetermined thickness may be realized by combining a prepreg and a solder resist and using a method such as forming a prepreg on the package substrate 11 and forming a solder resist thereon.

  Further, an insulating layer 13a in which the accommodating portion 13b and the through hole 13d are formed is separately prepared in advance, the insulating layer 13a is disposed on the package substrate 11, and the electrode 13c is formed in the through hole 13d to form the layer 13. You may make it use the method to do. Alternatively, an insulating layer 13a in which the accommodating portion 13b is formed is separately prepared in advance, the insulating layer 13a is disposed on the package substrate 11, a through hole 13d is formed, and an electrode 13c is formed in the through hole 13d. A method of forming the layer 13 may be used. Alternatively, the layer 13 in which the accommodating portion 13b and the electrode 13c are formed is separately prepared in advance, and the layer 13 is disposed on the package substrate 11 and the electrode 13c is electrically connected to the package substrate 11. May be. After the layer 13 is disposed on the package substrate 11 using such a method, the semiconductor chip 12 is FC-mounted on the package substrate 11 in the accommodating portion 13b. In addition, when using the method of preparing the insulating layer 13a or the layer 13 in which the accommodating portion 13b is formed in this way and arranging it on the package substrate 11 before using the insulating layer 13a or the layer 13, The semiconductor chip 12 may be FC-mounted on the package substrate 11.

  After FC mounting of the semiconductor chip 12, the underfill resin 15 is filled between the semiconductor chip 12 and the package substrate 11. For example, as shown in FIG. 2A, the underfill resin 15 can be entirely filled in the accommodating portion 13b. When filling the underfill resin 15, the inner wall of the accommodating portion 13 b of the layer 13 can function as a dam, and the outflow of the underfill resin 15 to the outside of the mounting region of the semiconductor chip 12 is avoided.

  The underfill resin 15 can also be selectively filled between the semiconductor chip 12 and the package substrate 11 as shown in FIG. Also in this case, outflow of the underfill resin 15 out of the mounting region of the semiconductor chip 12 is avoided by the accommodating portion 13b of the layer 13.

  Note that an insulating film 11a such as a solder resist is provided on the back surface (the surface opposite to the mounting surface side of the semiconductor chip 12) of the package substrate 11, and a bonding portion provided so as to be exposed from the insulating film 11a. The external terminal 11b is connected. For example, the insulating film 11a is provided with a thickness of about 30 μm. The joint exposed from the insulating film 11 a is electrically connected to signal wiring and GND wiring provided in the package substrate 11.

  By using the method as described above, the structure shown in FIGS. 2A and 3A can be obtained. Then, as shown in FIGS. 2B and 3B, a sheet 14 such as a conductive sheet or an anisotropic conductive sheet is disposed on the semiconductor chip 12 and the layer 13. Here, the semiconductor chip 12 and the layer 13 are arranged on the package substrate 11 so that the positions of the upper surfaces thereof are the same or equivalent to each other. Therefore, the sheet 14 can be easily and accurately arranged from the semiconductor chip 12 to the layer 13.

Here, another type of semiconductor package will be described for comparison.
FIG. 4 is a diagram showing an example of another form of semiconductor package. FIG. 4 schematically illustrates a cross section of an essential part of an example of another type of semiconductor package.

  The semiconductor package (semiconductor device) shown in FIG. 4A has a structure in which an insulating film 111a such as a solder resist is provided on the mounting surface side of the semiconductor chip 12 of the package substrate 11 in the same manner as the opposite surface side. Have. The terminal 111b is electrically connected to the land portion 111c of the package substrate 11 exposed from the opening provided in the insulating film 111a. In this semiconductor package, the position of the upper surface of the insulating film 111a is lower than the upper surface of the semiconductor chip 12 that is FC-mounted on the package substrate 11, and a step 110 exists.

  When the sheet 14 as described above is arranged on the semiconductor chip 12 and the insulating film 111a of such a semiconductor package, as shown in FIG. 4B and FIG. There may be a case where 14 cannot be arranged.

  For example, a plurality of semiconductor chips 12 are FC-mounted on a large-sized package substrate 11 on which a plurality of semiconductor chips 12 are FC-mounted, and the large-sized package substrate 11 is cut at a predetermined position. The obtaining method may be adopted. In this case, the step 110 as shown in FIG. 4A exists on the region (insulating film 111a) between the adjacent semiconductor chips 12 that is FC-mounted on the large package substrate 11, so that the sheet 14 may remain as shown in FIG. 4B. Alternatively, even if the sheet 14 can be disposed on the region between the adjacent semiconductor chips 12 (insulating film 111a), the gap 110b partially remains around the semiconductor chip 12 as shown in FIG. 4C. It can happen. The situation as shown in FIG. 4C is not limited to the case where a plurality of semiconductor packages are formed from a large package substrate 11, but when a semiconductor package is individually formed from a plurality of package substrates 11. Can happen as well.

  Thus, if the sheet 14 cannot be disposed on the insulating film 111a, or if the sheet 14 cannot be connected to the terminal 111b of the package substrate 11, sufficient effects of heat dissipation, GND connection, and electromagnetic shielding by the sheet 14 can be obtained. Can be difficult.

  On the other hand, in the semiconductor package 10 shown in FIGS. 1 to 3, the housing portion 13 b that houses the FC-mounted semiconductor chip 12 on the package substrate 11, and the electrode that is electrically connected to the package substrate 11. A layer 13 comprising 13c is provided. Then, the position of the upper surface of the layer 13 is aligned with the position of the upper surface of the semiconductor chip 12. Therefore, the sheet 14 can be easily disposed on the semiconductor chip 12 and the layer 13 while suppressing the generation of a gap between the sheet 13 and the electrode 13c provided on the layer 13 with high accuracy. It becomes possible to connect well. As a result, it is possible to obtain sufficient effects of heat dissipation, GND connection, and electromagnetic shielding by providing the sheet 14, and the semiconductor package 10 having excellent thermal and electromagnetic characteristics can be realized.

Next, a second embodiment will be described.
Here, an example of a semiconductor device using the semiconductor package 10 as described above will be described as a second embodiment. For example, a PoP type semiconductor device can be obtained by mounting another semiconductor package (semiconductor device) on the semiconductor package 10.

FIG. 5 is a diagram illustrating an example of a semiconductor device according to the second embodiment. FIG. 5 schematically shows a cross-section of the main part of an example of a PoP type semiconductor device.
A PoP type semiconductor device 20 shown in FIG. 5 includes a lower semiconductor package 10 and an upper semiconductor package 30 mounted thereon. A sheet 14 is provided in the lower semiconductor package 10. FIG. 5 illustrates an example of the semiconductor device 20 when the conductive sheet 14 </ b> A is used as the sheet 14.

  The upper semiconductor package 30 includes a package substrate (circuit substrate) 31 and a sealing portion 32 including a semiconductor chip (semiconductor element) mounted on the package substrate 31. The semiconductor chip in the sealing portion 32 is mounted on the package substrate 31 by FC connection or wire connection and is sealed with a sealing resin or the like. Terminals (bumps) 33 such as solder balls are provided on the surface of the package substrate 31 opposite to the sealing portion 32 side. The terminal 33 is electrically connected to a semiconductor chip mounted on the package substrate 31 through the package substrate 31. The terminal 33 includes a terminal (signal (Sig) terminal) 33a for exchanging signals between the semiconductor package 30 and the lower semiconductor package 10, and a terminal (GND) for connecting the semiconductor package 30 to the GND. Terminal) 33b.

  Such a semiconductor package 30 is mounted on the semiconductor package 10 on which the conductive sheet 14A is disposed. The conductive sheet 14A has an opening 14a at a position corresponding to the electrode 13c provided on the layer 13 that is electrically connected to the signal terminal 33a of the upper semiconductor package 30 (signal electrode) 13ca. It has been. The signal terminal 33a is connected to the signal electrode 13ca exposed from the opening 14a. On the other hand, among the electrodes 13c, the GND-connected one (GND electrode) 13cb is connected to the conductive sheet 14A. The GND terminal 33b of the upper semiconductor package 30 is connected to the conductive sheet 14A connected to the GND electrode 13cb.

Here, a method of forming the semiconductor device 20 including the conductive sheet 14A and the semiconductor package 10 in which the conductive sheet 14A is disposed will be described.
6 and 7 are explanatory diagrams of the conductive sheet. FIG. 6A and FIG. 7A schematically show a principal plane of an example of the lower semiconductor package before the conductive sheet is arranged. FIG. 6B and FIG. 7B schematically show a principal plane of an example of the conductive sheet. FIG. 6C and FIG. 7C schematically show a principal plane of an example of the lower semiconductor package after the conductive sheet is arranged.

  As shown in FIGS. 6A and 7A, the layer 13 of the lower semiconductor package 10 is provided with a plurality of signal electrodes 13ca and a GND electrode 13cb at predetermined positions as electrodes 13c. . The conductive sheet 14A is disposed on the semiconductor chip 12 accommodated in the layer 13 and the accommodating portion 13b.

  In this case, for example, as shown in FIG. 6 (B), an opening 14a is provided at a position corresponding to each signal electrode 13ca, and an opening 14a is not provided at a position corresponding to the GND electrode 13cb. 14A is used. By disposing such a conductive sheet 14A on the semiconductor chip 12 and the layer 13, as shown in FIG. 6C, each signal electrode 13ca is exposed from the opening 14a, and the GND electrode 13cb is a conductive sheet. The semiconductor package 10 covered with 14A is obtained.

  Further, for example, as shown in FIG. 7B, the openings 14a are provided in the regions corresponding to the plurality of signal electrode 13ca groups, and the openings 14a are not provided in the positions corresponding to the GND electrodes 13cb. The sheet 14A may be used. By disposing such a conductive sheet 14A on the semiconductor chip 12 and the layer 13, as shown in FIG. 7C, each signal electrode 13ca group is exposed from the opening 14a, and the GND electrode 13cb is electrically conductive. The semiconductor package 10 covered with the sheet 14A is obtained.

  FIG. 8 illustrates an example of a method for forming a semiconductor device according to the second embodiment. FIG. 8A schematically shows a cross-section of the main part of an example of the upper semiconductor package mounting process, and FIG. 8B schematically shows the main cross-section of an example of the state after the upper semiconductor package is mounted. It is shown in the figure.

  As shown in FIGS. 8A and 8B, the upper semiconductor package 30 is mounted on the semiconductor package 10 on which the conductive sheet 14A as described above is arranged, and the semiconductor device 20 is obtained. Each signal terminal 33a of the semiconductor package 30 is connected to each signal electrode 13ca exposed from the opening 14a of the conductive sheet 14A. On the other hand, all of the GND terminals 33b of the semiconductor package 30 are connected to one conductive sheet 14A connected to the GND electrode 13cb of the semiconductor package 10, and all the GND terminals 33b are GND-connected through one conductive sheet 14A. The

  Note that when the semiconductor package 30 is mounted, a reflow process of the terminals 33 is performed. By the reflow process, the signal terminal 33a and the signal electrode 13ca are firmly joined by metal joining. In the case where solder is used for the signal electrode 13ca, the solder is supplied from the signal electrode 13ca to the signal terminal 33a during the reflow process, so that an even stronger joint is formed.

  In this semiconductor device 20, the conductive sheet 14 </ b> A effectively functions as a heat radiating member, a GND reinforced wiring, and an electromagnetic shield member by being connected to the upper surface of the semiconductor chip 12 and the GND electrode 13 cb of the layer 13. Further, for heat dissipation, GND reinforcement, and electromagnetic shielding, the conductive sheet 14A can be thinner than the terminal 33 of the upper semiconductor package 30. By aligning the upper surface position of the layer 13 (electrode 13c) with the upper surface position of the semiconductor chip 12 and using the thin conductive sheet 14A, the space between the lower semiconductor package 10 and the upper semiconductor package 30 mounted on the lower semiconductor package 10 is used. A certain gap 21 is secured. Therefore, in the manufacture of the PoP type semiconductor device 20, it is possible to suppress the occurrence of an interference problem such that the lower surface of the semiconductor package 30 contacts or collides with the lower semiconductor package 10 when the upper semiconductor package 30 is mounted. Can do.

Next, a third embodiment will be described.
FIG. 9 is a diagram illustrating an example of a semiconductor device according to the third embodiment. FIG. 9 schematically shows a cross section of an essential part of an example of a PoP type semiconductor device.

  The PoP type semiconductor device 40 shown in FIG. 9 is provided with the through-via 12b electrically connected to the bump 12a connected to the GND wiring of the package substrate 11 in the semiconductor chip 12. This is different from the semiconductor device 20 according to the embodiment. The through via 12b is formed in the semiconductor chip 12 using, for example, TSV (Through Silicon Via) technology.

  In the semiconductor package 10 below the semiconductor device 40, the conductive sheet 14 </ b> A disposed on the semiconductor chip 12 is electrically connected to the through via 12 b of the semiconductor chip 12. According to the semiconductor package 10 as shown in FIG. 9 and the semiconductor device 40 using the same, it is possible to further strengthen the GND.

Next, a fourth embodiment will be described.
FIG. 10 is a diagram illustrating an example of a semiconductor device according to the fourth embodiment. FIG. 10 schematically shows a cross section of an essential part of an example of a PoP type semiconductor device.

  The PoP type semiconductor device 50 shown in FIG. 10 is different from the semiconductor device 20 according to the second embodiment in that an anisotropic conductive sheet 14B is provided as the sheet 14 of the lower semiconductor package 10. To do.

  In the semiconductor device 50, each signal terminal 33a of the upper semiconductor package 30 is connected to each signal electrode 13ca exposed from the opening 14a of the anisotropic conductive sheet 14B of the lower semiconductor package 10. Here, the opening 14a is an opening having a size larger than that of the signal terminal 33a. On the other hand, each GND terminal 33b of the upper semiconductor package 30 is connected to an anisotropic conductive sheet 14B that covers the GND electrode 13cb of the lower semiconductor package 10.

  Note that when the semiconductor package 30 is mounted, a reflow process of the terminals 33 is performed. The signal terminal 33a melted during the reflow process is connected to the signal electrode 13ca. The signal terminal 33a and the signal electrode 13ca are firmly joined by metal joining. In the case where solder is used for the signal electrode 13ca, the solder is supplied from the signal electrode 13ca to the signal terminal 33a during the reflow process, so that an even stronger joint is formed.

Here, the anisotropic conductive sheet 14B will be described.
FIG. 11 is an explanatory diagram of an anisotropic conductive sheet. FIG. 11A schematically illustrates a cross section of a main part of an example of the anisotropic conductive sheet provided in the semiconductor package, and FIG. 11B illustrates the anisotropic conductive sheet provided in the semiconductor package. The principal part cross section of an example of the state in which the sheet | seat was pressed is typically illustrated.

  As shown in FIG. 11A, the anisotropic conductive sheet 14B has an insulating portion 14b and conductive fillers (conductive particles) 14c dispersedly arranged in the insulating portion 14b. For the insulating part 14b, for example, an insulating material such as a thermosetting resin or synthetic rubber is used. For the conductive filler 14c, for example, a conductive material such as metal particles formed using one or more metals is used. In the anisotropic conductive sheet 14B, a conductive path (conductive portion) due to contact between the conductive fillers 14c is not formed in the plane direction (XY direction) and the thickness direction (Z direction) before deformation by pressing as described later. As described above, the conductive fillers 14c are dispersedly arranged in the insulating portion 14b. As shown in FIG. 11A, the anisotropic conductive sheet 14B is not pressed and is only disposed on the layer 13 (and the semiconductor chip 12) of the semiconductor package 10, and the anisotropic conductive sheet 14B is not pressed. The sheet 14B does not exhibit conductivity yet.

  The upper semiconductor package 30 is mounted on the semiconductor package 10 on which the anisotropic conductive sheet 14B is arranged. At the time of mounting, the anisotropic conductive sheet 14B covering the electrode 13c is pressed in the Z direction by the terminal 33 as shown in FIG. FIG. 11B shows only two terminals 33 of the semiconductor package 30 to be mounted. In the portion of the anisotropic conductive sheet 14B that is pressed by the terminal 33, the conductive fillers 14c come into contact with each other. Thereby, a conductive path in the Z direction is formed in the portion pressed by the terminal 33 in the anisotropic conductive sheet 14B, and the terminal 33 and the electrode 13c are electrically connected by the conductive path in the Z direction. Become so.

  On the other hand, the non-contact state between the conductive fillers 14c is maintained in the XY direction of the anisotropic conductive sheet 14B. For example, it is assumed that the pitch P of the terminals 33 arranged adjacent to the semiconductor package 30 is about 0.4 mm to 0.5 mm and the gap G is about 0.2 mm to 0.3 mm. In this case, even if the anisotropic conductive sheet 14 </ b> B is pressed by the adjacent terminals 33 and a conduction path is formed in the Z direction, the non-contact state between the conductive fillers 14 c existing in the region between the adjacent terminals 33 is sufficient. Maintained. Therefore, as shown in FIG. 11B, adjacent terminals 33 are not electrically connected through the anisotropic conductive sheet 14B.

  Note that each of the two terminals 33 shown in FIG. 11B may be a signal terminal 33a, and both may be a GND terminal 33b. Alternatively, one may be the signal terminal 33a and the other may be the GND terminal 33b. In the semiconductor device 50 of FIG. 10, the anisotropic conductive sheet 14B is pressed by the GND terminal 33b, and the GND terminal 33b and the GND electrode 13cb are electrically connected.

  Here, the signal terminal 33a is directly connected to the signal electrode 13ca exposed from the opening 14a of the anisotropic conductive sheet 14B. In addition, a connection structure similar to that of the GND terminal 33b may be adopted as long as a certain bonding strength can be secured between the upper and lower semiconductor packages 10 and 30 and signals can be exchanged. That is, a structure in which the signal terminal 33a and the signal electrode 13ca are electrically connected by a conduction path in the Z direction formed by pressing the anisotropic conductive sheet 14B by the signal terminal 33a may be employed.

Thus, even when the anisotropic conductive sheet 14B is used for the lower semiconductor package 10, the PoP type semiconductor device 50 can be realized.
Next, a fifth embodiment will be described.

FIG. 12 is a diagram illustrating an example of a semiconductor device according to the fifth embodiment. FIG. 12 schematically shows a cross section of an essential part of an example of a PoP type semiconductor device.
The PoP type semiconductor device 60 shown in FIG. 12 has the anisotropic conductive sheet 14B provided on the lower semiconductor package 10 and the terminals 33 (signal terminals 33a and GND terminals 33b) connected thereto. This is different from the semiconductor device 20 according to the fourth embodiment.

  In the semiconductor device 60, the anisotropic conductive sheet 14B is provided with an opening 14a having a size smaller than that of the signal terminal 33a and the GND terminal 33b. The signal terminal 33a and the GND terminal 33b are in contact with the signal electrode 13ca and the GND electrode 13cb through the opening 14a together with the anisotropic conductive sheet 14B, respectively, and are electrically connected to the signal electrode 13ca and the GND electrode 13cb.

  The signal terminal 33a and the signal electrode 13ca, and the GND terminal 33b and the GND electrode 13cb are firmly joined by metal joining. When solder is used for the signal electrode 13ca and the GND electrode 13cb, solder is supplied from the signal electrode 13ca and the GND electrode 13cb to the signal terminal 33a and the GND terminal 33b, respectively, at the time of mounting, so that an even stronger joint is formed. The

The opening 14 a of the anisotropic conductive sheet 14 </ b> B can be formed, for example, during a test performed after the semiconductor package 10 is formed.
FIG. 13 is a diagram illustrating an example of a process for forming and testing a semiconductor package according to the fifth embodiment. FIG. 13A schematically shows a principal plane of an example of the lower semiconductor package before the anisotropic conductive sheet is arranged. FIG. 13B schematically shows a principal plane of an example of the lower semiconductor package after the anisotropic conductive sheet is arranged. FIG. 13C schematically shows a principal plane of an example of the state of the lower semiconductor package after the test. FIG. 14 is a diagram showing an example of a test process for a semiconductor package according to the fifth embodiment. 14A and 14B schematically show a cross-section of the main part of an example of the test process for the lower semiconductor package.

  As shown in FIG. 13A, the layer 13 of the lower semiconductor package 10 is provided with a plurality of signal electrodes 13ca and a GND electrode 13cb at predetermined positions as electrodes 13c. An anisotropic conductive sheet 14B is disposed on the layer 13 and the semiconductor chip 12 accommodated in the accommodating portion 13b as shown in FIG. Here, it is not necessary to previously form an opening in the anisotropic conductive sheet 14B to be arranged. As shown in FIG. 13B, the anisotropic conductive sheet 14 </ b> B in which no opening is formed is disposed on the semiconductor chip 12 and the layer 13.

The semiconductor package 10 thus obtained is tested using a test apparatus 200 as shown in FIG.
The test apparatus 200 includes a socket 210 provided with a probe 211 and a control unit 220. When testing the semiconductor package 10, as shown in FIG. 14A, the socket 210 is arranged with the probe 211 facing the anisotropic conductive sheet 14 </ b> B of the semiconductor package 10. Then, as shown in FIG. 14B, the socket 210 is moved to the semiconductor package 10 side. At this time, the probe 211 penetrates the anisotropic conductive sheet 14B, and the electrode 13c (signal electrode 13ca, GND electrode 13cb) below the electrode 211c (surface wiring of the package substrate 11) further below the electrode 13c. Pattern). In this state, an electrical signal is input from the probe 211 to the electrode 13c or the electrode pad 11cc, or an electrical signal output from the electrode 13c or the electrode pad 11cc is detected by the probe 211. Based on the result, it is determined whether the formed semiconductor package 10 operates according to the specifications or has a performance that can be shipped. The movement of the socket 210, the input of the electrical signal from the probe 211, and the detection of the electrical signal by the probe 211 are controlled by the control unit 220.

  After the test, the socket 210 is separated from the semiconductor package 10 and is brought into a state as shown in FIG. In the anisotropic conductive sheet 14B of the semiconductor package 10 from which the socket 210 is separated, an opening 14a is formed at a portion through which the probe 211 passes. Thus, after the test, as shown in FIG. 13C, the semiconductor package 10 is obtained in which the anisotropic conductive sheet 14 </ b> B having the opening 14 a that is naturally opened by the penetration of the probe 211 is disposed.

  After such a test, the upper semiconductor package 30 is mounted on the semiconductor package 10. Here, the anisotropic conductive sheet 14B in which the opening 14a is formed by the test and the bonding between the upper and lower semiconductor packages 10 and 30 through the anisotropic conductive sheet 14B will be described.

  FIG. 15 is an explanatory diagram of an anisotropic conductive sheet having openings. FIG. 15A schematically illustrates a cross section of a main part of an example of the anisotropic conductive sheet having openings, and FIG. 15B illustrates an anisotropic conductive sheet having openings. The principal part cross section of an example of the pressed state is typically shown.

  As shown in FIG. 15A and FIG. 15A, the anisotropic conductive sheet 14B after the test using the probe 211 has an opening 14a in a portion through which the probe 211 passes. The electrode 13c (signal electrode 13ca, GND electrode 13cb) with which the probe 211 is in contact is partially exposed in the opening 14a. The opening 14a may be smaller than the terminal 33 that is electrically connected to the electrode 13c.

  The upper semiconductor package 30 is mounted on the lower semiconductor package 10 on which the anisotropic conductive sheet 14B is disposed. At the time of mounting, as shown in FIG. 15B, the anisotropic conductive sheet 14B is pressed to the corresponding electrode 13c side by the terminal 33 (signal terminal 33a, GND terminal 33b). FIG. 15B shows only two terminals 33 of the semiconductor package 30 to be mounted. In the portion of the anisotropic conductive sheet 14B pressed by the terminal 33 (excluding the opening 14a), the conductive fillers 14c come into contact with each other to form a conduction path in the Z direction. The corresponding terminal 33 and the electrode 13c are electrically connected by the Z-direction conduction path formed in this way.

  Furthermore, when the semiconductor package 30 is mounted, the terminal 33 is subjected to a reflow process, whereby the molten terminal 33 enters the opening 14a and is connected to the electrode 13c. As a result, the corresponding terminal 33 and the electrode 13c are firmly bonded by metal bonding, and are reliably electrically connected.

  In addition, about the XY direction of the anisotropic conductive sheet 14B, since the non-contact state of the conductive fillers 14c is maintained, between the terminals 33 at different positions as shown in FIG. There is no electrical connection through 14B.

  Here, the case where the probe 211 is brought into contact with all the electrodes 13c (the signal electrode 13ca and the GND electrode 13cb) of the semiconductor package 10 to form the opening 14a is illustrated. In addition, the probe 211 may be brought into contact with only some of the electrodes 13c of the electrodes 13c of the semiconductor package 10 to form the openings 14a. For example, the opening 14a may be formed by the probe 211 for only the signal electrode 13ca among the electrodes 13c. In this case, the Z-direction formed by pressing the anisotropic conductive sheet 14B by the GND terminal 33b is applied to the GND electrode 13cb in which the opening 14a is not formed, as described in the fourth embodiment. The GND terminal 33b may be electrically connected through the conduction path.

Next, a sixth embodiment will be described.
FIG. 16 shows an example of a semiconductor package according to the sixth embodiment. FIG. 16 schematically shows a principal plane of an example of a semiconductor package.

  The semiconductor package 10 shown in FIG. 16 has the fifth embodiment in that the wiring pattern 14d (conductive portion) is provided on the anisotropic conductive sheet 14B disposed on the semiconductor chip 12 and the layer 13. This is different from the semiconductor package 10 according to the embodiment. The wiring pattern 14d of the anisotropic conductive sheet 14B can be performed simultaneously with the formation of the opening 14a by the probe 211, for example, in the test using the probe 211 as described above.

  FIG. 17 is a diagram illustrating an example of a test process for a semiconductor package according to the sixth embodiment. FIGS. 17A and 17B schematically show a cross section of a main part of an example of a semiconductor package testing process. Moreover, FIG. 18 is a figure which shows an example of the anisotropic conductive sheet obtained after the test of the semiconductor package based on 6th Embodiment. FIG. 18 schematically illustrates a cross-section of an essential part of an example of the anisotropic conductive sheet obtained after the semiconductor package test.

  When forming the wiring pattern 14d during the test of the semiconductor package 10, a test apparatus 200a as shown in FIG. 17 is used. In addition to the socket 210 provided with the probe 211, the test apparatus 200a has a guide portion 230 that guides the movement of the socket 210. The guide portion 230 is provided with a protrusion (pressing portion) 231 that protrudes in the same direction as the extending direction of the probe 211. The protrusion 231 is provided in a shape corresponding to the wiring pattern 14d formed on the anisotropic conductive sheet 14B. In addition, the test apparatus 200 a includes a control unit 220 that controls movement of the socket 210 and the guide unit 230, input of an electrical signal from the probe 211, and detection of the electrical signal by the probe 211.

  The test of the semiconductor package 10 using such a test apparatus 200a can be performed in the same manner as when the test apparatus 200 is used. That is, from the state of FIG. 17A, as shown in FIG. 17B, the socket 210 is moved closer to the semiconductor package 10, and the probe 211 is passed through the anisotropic conductive sheet 14B and the electrode below it. 13c, or further contact with the electrode pad 11cc below it. Then, the probe 211 may be used to input and detect electrical signals. When forming the wiring pattern 14d, the socket 210 is moved in this manner to bring the probe 211 into contact with the electrode 13c or the electrode pad 11cc, and the guide portion 230 is moved to press the anisotropic conductive sheet 14B with the protrusion 231. To do.

  When the anisotropic conductive sheet 14B is pressed by the protrusions 231, as shown in FIG. 18, the pressed portions of the conductive fillers 14c come into contact with each other to form a conduction path. In the portion pressed by the protrusion 231, contact between the conductive fillers 14 c in the XY direction as well as the conductive fillers 14 c in the Z direction occurs. By pressing the anisotropic conductive sheet 14B with the protrusion 231 having a shape corresponding to the wiring pattern 14d to be formed, a conduction path along the shape of the protrusion 231, that is, the wiring pattern 14d can be obtained.

By using such a method, it is possible to form wiring patterns 14d having various shapes and connection relations on the anisotropic conductive sheet 14B of the semiconductor package 10.
For example, when the semiconductor package 30 is further mounted on the semiconductor package 10, the wiring pattern 14d is formed in accordance with the position of the terminal 33 of the semiconductor package 30 and the use (for signal transmission and GND connection). Can do. In the example of FIG. 16 described above, among the electrodes 13c of the semiconductor package 10 arranged on the lower side, the GND connection of the semiconductor package 30 mounted on the upper side corresponding to the position of the electrode 13c of the innermost four corners is made. The case where the terminal 33 is arrange | positioned is assumed. When such a semiconductor package 30 is mounted on the upper side, the electrode 13c that is GND-connected including the innermost four corners on the anisotropic conductive sheet 14B of the lower semiconductor package 10 and the back surface of the semiconductor chip 12 are provided. A wiring pattern 14d to be connected is formed. As a result, the GND-connected terminal 33 of the upper semiconductor package 30 can be guided to the position of the GND-connected electrode 13 c of the lower semiconductor package 10.

  Further, the anisotropic conductive sheet 14B of the lower semiconductor package 10 takes into consideration the characteristics required for the lower semiconductor package 10, the configuration of the upper semiconductor package 30, and the like, as shown in FIGS. It is also possible to form a wiring pattern 14d as shown in FIG.

  FIG. 19 shows an example of a semiconductor device according to the sixth embodiment. FIG. 19 schematically illustrates a cross-section of a main part of an example of a semiconductor package having an anisotropic conductive sheet on which a wiring pattern is formed and a semiconductor package mounted thereon.

  A semiconductor package 10 shown in FIG. 19 includes a semiconductor chip 12 that is FC-mounted on a package substrate 11. The semiconductor chip 12 is accommodated in an accommodating portion 13 b of a layer 13 disposed on the package substrate 11. Yes. The accommodating portion 13b is filled with an underfill resin 15. The GND electrode 13 cb provided on the layer 13 is electrically connected to an internal GND wiring (not shown) through the surface wiring pattern 11 c and the via 11 d of the package substrate 11.

  The anisotropic conductive sheet 14 </ b> B is disposed on the semiconductor chip 12 and the layer 13. The anisotropic conductive sheet 14B is a wiring pattern 14d formed by being pressed by the opening portion 14a opened by the probe 211 and the projection 231 of the guide portion 230 in the test using the test apparatus 200a as described above. And have. The wiring pattern 14d is formed in a region extending from the opening 14a to the back surface of the semiconductor chip 12.

  The semiconductor package 30 is mounted on the semiconductor package 10 having such an anisotropic conductive sheet 14B, and a PoP type semiconductor device is formed. FIG. 19 shows only one GND terminal 33b of the semiconductor package 30 to be mounted. When the semiconductor package 30 is mounted, the vicinity of the opening 14a of the anisotropic conductive sheet 14B on the GND electrode 13cb is pressed by the GND terminal 33b, and a reflow process is performed, so that the molten GND terminal 33b (and the GND electrode) 13cb) enters the opening 14a. The GND terminal 33b and the GND electrode 13cb are electrically connected by the conductive path formed in the pressed portion of the anisotropic conductive sheet 14B and the conductive material that has entered the opening 14a.

  The wiring pattern 14d extends from the connection portion of the GND terminal 33b and the GND electrode 13cb to the semiconductor chip 12. Thus, a structure in which the back surface of the semiconductor chip 12 (surface on the semiconductor substrate side) is GND-connected through the wiring pattern 14d is obtained.

  FIG. 20 is a diagram illustrating another example of the semiconductor device according to the sixth embodiment. FIG. 20 schematically illustrates a cross section of a main part of an example of a semiconductor package having an anisotropic conductive sheet on which a wiring pattern is formed and a semiconductor package mounted thereon.

  The semiconductor package 10 shown in FIG. 20 has the same structure as that shown in FIG. In FIG. 20, the semiconductor package 30 mounted on the semiconductor package 10 has a GND terminal 33b disposed above the semiconductor chip 12 in addition to the GND terminal 33b disposed at a position corresponding to the GND electrode 13cb. The case where it has is illustrated. In FIG. 20, only two GND terminals 33b of the semiconductor package 30 to be mounted are illustrated.

  When the GND terminal 33b is above the semiconductor chip 12 as described above, the GND terminal 33b can be brought into contact with and electrically connected to the anisotropic conductive sheet 14B disposed on the semiconductor chip 12. Is possible. The GND terminal 33b can be electrically connected to the back surface of the semiconductor chip 12 through a conduction path formed in the anisotropic conductive sheet 14B immediately below the GND terminal 33b, and the GND terminal 33b and the GND electrode facing each other through the wiring pattern 14d. It can be electrically connected to the connection part of 13cb.

  As shown in FIGS. 19 and 20, when the wiring pattern 14d electrically connected to the back surface of the semiconductor chip 12 is formed, the through-via 12b as described in FIG. The through via 12b and the wiring pattern 14d may be electrically connected. This makes it possible to further strengthen GND.

  Unlike the example of FIG. 20, when the signal terminal 33a is arranged above the semiconductor chip 12 instead of the GND terminal 33b, the problem as shown in FIG.

  FIG. 21 is an explanatory diagram when the signal terminals are arranged above the semiconductor chip. FIG. 21 schematically illustrates a cross section of a main part of an example of a semiconductor package having an anisotropic conductive sheet and a semiconductor package mounted thereon.

  As shown in FIG. 21, it is assumed that a signal terminal 33a is present in the upper semiconductor package 30 as the terminal 33 disposed above the semiconductor chip 12 of the lower semiconductor package 10. In this case, when the semiconductor package 30 is mounted on the semiconductor package 10, the signal terminal 33 a is electrically connected to the back surface of the semiconductor chip 12 through a conduction path pressed and formed on the anisotropic conductive sheet 14 </ b> B. It becomes like this.

  As described above, when the back surface of the semiconductor chip 12 is electrically connected to the signal terminal 33a or the wiring pattern 14d extending from the connection portion is formed on the anisotropic conductive sheet 14B, It may cause malfunction.

  Thus, in the case where the signal terminal 33a is present above the semiconductor chip 12 as described above, a method that can avoid electrical connection between the signal terminal 33a and the back surface of the semiconductor chip 12 will be described below as the seventh and the following. This will be described as an eighth embodiment.

First, a seventh embodiment will be described.
FIG. 22 is an explanatory diagram of a sheet according to the seventh embodiment. FIG. 22 schematically illustrates a cross section of a main part of an example of the sheet.

  The sheet 14 shown in FIG. 22 has a laminated structure of the adhesive sheet 14C and the anisotropic conductive sheet 14B as described above. As the adhesive sheet 14C, a material that can adhere the anisotropic conductive sheet 14B and can adhere to the semiconductor chip 12 and the layer 13 of the semiconductor package 10 and exhibits insulating properties is used. For example, an insulating material such as resin or rubber is used for the adhesive sheet 14C. Such a sheet 14 is disposed on the semiconductor chip 12 and the layer 13 to obtain the semiconductor package 10.

  23 and 24 are diagrams showing examples of the semiconductor device according to the seventh embodiment. FIG. 23 and FIG. 24 schematically illustrate a cross section of an essential part of an example of a semiconductor package having a sheet and a semiconductor package mounted thereon.

  A semiconductor package 10 shown in FIG. 23 includes a semiconductor chip 12 that is FC-mounted on a package substrate 11. The semiconductor chip 12 is accommodated in an accommodating portion 13 b of a layer 13 disposed on the package substrate 11. Yes. The accommodating portion 13b is filled with an underfill resin 15. The electrode 13c provided on the layer 13 is electrically connected to internal wiring (not shown) through the surface wiring pattern 11c and the via 11d of the package substrate 11.

  The sheet 14 as shown in FIG. 22 is arranged on the semiconductor chip 12 and the layer 13 with the adhesive sheet 14C facing the semiconductor chip 12 and the layer 13 side. The sheet 14 has an opening 14a opened by the probe 211 during a test using the test apparatus 200a as described above.

  A semiconductor package 30 is mounted on the semiconductor package 10 having such a sheet 14 to form a PoP type semiconductor device. FIG. 23 shows only two terminals 33 of the semiconductor package 30 to be mounted. The semiconductor package 30 includes a terminal 33 (signal terminal 33a or GND terminal 33b) disposed at a position corresponding to the electrode 13c (signal electrode 13ca or GND electrode 13cb) and a signal terminal 33a disposed above the semiconductor chip 12. Have.

  When the semiconductor package 30 is mounted, the terminals 33 arranged at positions corresponding to the electrodes 13 c press the vicinity of the opening 14 a of the sheet 14. When the reflow process is performed, the molten terminal 33 (and the electrode 13c) enters the opening 14a, and the terminal 33 and the electrode 13c are electrically connected.

  When the semiconductor package 30 is mounted, the signal terminal 33 a disposed above the semiconductor chip 12 also presses the sheet 14 in the same manner. This pressing causes contact between the conductive fillers 14c in the anisotropic conductive sheet 14B of the sheet 14, but since the insulating adhesive sheet 14C is interposed between the semiconductor chip 12 and the signal terminal at this pressed portion. 33a and the semiconductor chip 12 are not electrically connected.

  When the signal terminal 33a above the semiconductor chip 12 is electrically connected to the lower semiconductor package 10, an opening 14a and a wiring pattern 14d are provided in the sheet 14, as shown in FIG. The opening 14a and the wiring pattern 14d are formed by the probe 211 and the protrusion 231 during a test using the test apparatus 200a. The wiring pattern 14d is formed in a region extending from a portion where the signal terminal 33a above the semiconductor chip 12 is arranged to an opening 14a communicating with the signal electrode 13ca provided outside the accommodating portion 13b of the layer 13. The signal electrode 13ca under the opening 14a is electrically connected to an internal signal wiring (not shown) through the surface wiring pattern 11c and the via 11d of the package substrate 11. In the reflow process, the signal electrode 13ca underneath melts and enters the opening 14a, and as a result, a conductive portion that electrically connects the wiring pattern 14d and the surface wiring pattern 11c is formed. Thereby, the signal terminal 33a above the semiconductor chip 12 can be electrically connected to the lower semiconductor package 10 (signal wiring).

  The wiring pattern 14d is formed in the anisotropic conductive sheet 14B of the sheet 14. An adhesive sheet 14C is interposed between the anisotropic conductive sheet 14B and the semiconductor chip 12. Therefore, the electrical connection between the wiring pattern 14d and the back surface of the semiconductor chip 12 and the electrical connection between the signal terminal 33a above the semiconductor chip 12 and the back surface of the semiconductor chip 12 do not occur.

  As described above, the sheet 14 disposed on the semiconductor chip 12 and the layer 13 of the semiconductor package 10 is a laminate of the adhesive sheet 14C and the anisotropic conductive sheet 14B. Thereby, even when the signal terminal 33a is arranged above the semiconductor chip 12, it is possible to avoid electrical connection between the back surface of the semiconductor chip 12 and the signal terminal 33a in the region immediately below the signal terminal 33a.

Next, an eighth embodiment will be described.
FIG. 25 is an explanatory diagram of a sheet according to the eighth embodiment. FIG. 25 schematically illustrates a cross section of a main part of an example of the sheet.

  The sheet 14 shown in FIG. 25 has a laminated structure in which one adhesive sheet 14C is interposed between two anisotropic conductive sheets 14B. For the adhesive sheet 14C, an insulating material such as resin or rubber, which is a material that can adhere the anisotropic conductive sheet 14B to both surfaces and exhibits insulation properties, is used. Such a sheet 14 is disposed on the semiconductor chip 12 and the layer 13 to form the semiconductor package 10.

  FIG. 26 is a diagram illustrating a first example of a semiconductor device according to the eighth embodiment. FIG. 26 schematically illustrates a cross section of an essential part of an example of a semiconductor package having a sheet and a semiconductor package mounted thereon.

  A semiconductor package 10 shown in FIG. 26 includes a layer 13 and an electrode 13c disposed in the layer 13. A sheet 14 as shown in FIG. 25 is disposed on the layer 13. Although not shown in FIG. 26, the layer 13 is provided with a housing portion 13b, and the semiconductor chip 12 is housed in the housing portion 13b.

  The sheet 14 extends on the layer 13 of the semiconductor package 10 and the semiconductor chip 12. The sheet 14 has an opening 14a opened by the probe 211 during the test using the test apparatus 200a as described above, and a wiring pattern 14d pressed by the protrusion 231 of the guide 230. . The wiring pattern 14 d is formed in the anisotropic conductive sheet 14 </ b> B on the upper layer side of the sheet 14. Such a wiring pattern 14d can be formed using a method such as adjusting the height of the protrusion 231 of the guide portion 230 or adjusting the amount of movement of the guide portion 230.

  Now, in such a semiconductor package 10, among the plurality of electrodes 13c provided on the layer 13, there are used electrodes 13c (used electrodes 13cd) and unused electrodes 13c (unused electrodes 13ce). Shall. FIG. 26 illustrates two used electrodes 13cd and one unused electrode 13ce disposed between them. A terminal 33 of the semiconductor package 30 mounted on the upper side is electrically connected to the two use electrodes 13cd by a conductive material that has entered the opening 14a. The terminals 33 connected to these two use electrodes 13cd are terminals of the same potential (both signal terminals 33a or both GND terminals 33b). A wiring pattern 14d is formed on the sheet 14 between the two terminals 33, and the two terminals 33 (use electrodes 13cd) are electrically connected.

  Here, the wiring pattern 14d is formed in the anisotropic conductive sheet 14B on the upper layer side out of the two layers of anisotropic conductive sheet 14B included in the sheet 14, and in the anisotropic conductive sheet 14B on the lower layer side. Is not formed. The wiring pattern 14d can be formed so as to connect the two terminals 33 (used electrode 13cd) through above the unused electrode 13ce.

  For example, a single-layer anisotropic conductive sheet 14B is used as the sheet 14 of the semiconductor package 10, and the two terminals 33 (use electrodes 13cd) are similarly connected in the single-layer anisotropic conductive sheet 14B. Assume that a pattern is formed. In this case, if a wiring pattern passing above the unused electrode 13ce is formed in the single-layer anisotropic conductive sheet 14B, a short circuit occurs between the wiring pattern and the unused electrode 13ce. . Therefore, it is necessary to form a wiring pattern that bypasses the unused electrode 13ce.

  On the other hand, when the sheet 14 having the adhesive sheet 14C interposed between the two layers of the anisotropic conductive sheet 14B as described above is used, it is possible to form a wiring pattern 14d that passes above the unused electrode 13ce. Yes, the degree of freedom of wiring can be increased.

  FIG. 27 is a diagram illustrating a second example of the semiconductor device according to the eighth embodiment. FIG. 27 schematically illustrates a cross section of an essential part of an example of a semiconductor package having a sheet and a semiconductor package mounted thereon.

  A semiconductor package 10 shown in FIG. 27 has a semiconductor chip 12 that is FC-mounted on a package substrate 11, and the semiconductor chip 12 is accommodated in an accommodating portion 13 b of a layer 13 disposed on the package substrate 11. Yes. The accommodating portion 13b is filled with an underfill resin 15. The electrode 13c provided on the layer 13 is electrically connected to internal wiring (not shown) through the surface wiring pattern 11c and the via 11d of the package substrate 11. A sheet 14 as shown in FIG. 25 is disposed on the semiconductor chip 12 and the layer 13. A semiconductor package 30 is mounted on the semiconductor package 10.

  As shown in FIG. 27, in the case where the terminal 33 of the upper semiconductor package 30 is arranged above the semiconductor chip 12 of the semiconductor package 10, similarly, in the anisotropic conductive sheet 14 </ b> B on the upper layer side of the sheet 14. A wiring pattern 14d is formed on the substrate. Then, the wiring pattern 14d is extended to the arrangement position of another terminal 33 electrically connected to the electrode 13c at the same potential as the terminal 33 above the semiconductor chip 12. By using the sheet 14 having the adhesive sheet 14C interposed between the two layers of the anisotropic conductive sheet 14B, the wiring pattern 14d can be formed in a non-contact manner with the back surface of the semiconductor chip 12.

  FIG. 28 is a diagram illustrating a third example of the semiconductor device according to the eighth embodiment. FIG. 28 schematically illustrates a cross section of a main part of an example of a semiconductor package having a sheet and a semiconductor package mounted thereon.

  The semiconductor package 10 shown in FIG. 28 has a sheet 14 in which wiring patterns 14d are formed on anisotropic conductive sheets 14B on both the upper layer side and the lower layer side. Such a wiring pattern 14d can be formed using a method such as adjusting the height of the protrusion 231 of the guide portion 230 or adjusting the amount of movement of the guide portion 230.

  A signal terminal 33a of the semiconductor package 30 mounted on the semiconductor package 10 has a signal wiring (not shown) inside the package substrate 11 through the conductive material in the opening 14a, the signal electrode 13ca, the surface wiring pattern 11c, and the via 11d. ) Is electrically connected. Similarly, the GND terminal 33b of the semiconductor package 30 is also electrically connected to a GND wiring (not shown) inside the package substrate 11 through the conductive material in the opening 14a, the signal electrode 13ca, the surface wiring pattern 11c, and the via 11d. Yes.

  On the anisotropic conductive sheet 14B on the upper layer side of the sheet 14, a wiring pattern 14d for electrically connecting the GND terminal 33b (GND electrode 13cb) to another GND terminal (not shown) is formed. In the anisotropic conductive sheet 14B on the lower layer side of the sheet 14, a wiring pattern 14d for electrically connecting the back surface of the semiconductor chip 12 to the GND terminal 33b (GND electrode 13cb) is formed. By forming such a wiring pattern 14d on the anisotropic conductive sheet 14B on the lower layer side, the GND can be strengthened.

  FIG. 29 is a diagram illustrating a fourth example of the semiconductor device according to the eighth embodiment. FIG. 28 schematically illustrates a cross section of a main part of an example of a semiconductor package having a sheet and a semiconductor package mounted thereon.

  FIG. 28 illustrates the case where the GND terminal 33b and the GND electrode 13cb are electrically connected by the conductive material in the opening 14a. However, the GND terminal 33b is not necessarily connected to the GND electrode 13cb. Is not required. By forming the wiring pattern 14d from the semiconductor chip 12 to the GND electrode 13cb, the back surface of the semiconductor chip 12 and the GND electrode 13cb can be electrically connected through the wiring pattern 14d.

  As shown in FIGS. 28 and 29, when the wiring pattern 14d electrically connected to the back surface of the semiconductor chip 12 is formed, the through via 12b as described in FIG. The through via 12b and the wiring pattern 14d may be electrically connected. This makes it possible to further strengthen GND.

The semiconductor package 10 having the sheet 14 and the PoP type semiconductor device in which another semiconductor package 30 is mounted thereon have been described.
Note that various configurations can be adopted as the package substrate 11 of the semiconductor package 10. With reference to FIGS. 30 and 31, further description will be given of embodiments of the semiconductor device (ninth and tenth embodiments) focusing on the configuration of the package substrate 11. FIG.

First, a ninth embodiment will be described.
FIG. 30 is a diagram illustrating an example of a semiconductor device according to the ninth embodiment. FIG. 30 schematically shows a cross section of an essential part of an example of a PoP type semiconductor device.

  A semiconductor device 70 illustrated in FIG. 30 includes the semiconductor package 10 and the semiconductor package 30 mounted thereon. The semiconductor package 10 includes the package substrate 11, the semiconductor chip 12, the layer 13, the sheet 14, and the underfill resin 15 as described above.

  As the package substrate 11 of the semiconductor package 10, for example, a substrate formed by a build-up method as shown in FIG. The package substrate 11 shown in FIG. 30 has a core substrate 11e. A wiring pattern 11f having a predetermined shape is provided on both surfaces of the core substrate 11e, and the wiring patterns 11f on both surfaces are electrically connected by vias 11g penetrating the core substrate 11e. The wiring pattern 11f includes one that functions as a signal wiring and one that functions as a GND wiring. Insulating layers 11h are provided on both surfaces of the core substrate 11e provided with such wiring patterns 11f, and surface wiring patterns 11c (including electrode pads) are provided on both insulating layers 11h. The surface wiring pattern 11c is electrically connected to the wiring pattern 11f on the core substrate 11e by a via 11d. An insulating film 11a such as a solder resist is provided on one insulating layer 11h side (surface opposite to the mounting surface of the semiconductor chip 12) provided with the surface wiring pattern 11c. The external terminal 11b is electrically connected to the surface wiring pattern 11c partially exposed from the insulating film 11a.

  A package substrate 11 having such a configuration can be used for the semiconductor package 10. On such a package substrate 11, a layer 13 having an accommodating portion 13b for accommodating the semiconductor chip 12 and an electrode 13c (signal electrode 13ca and GND electrode 13cb) electrically connected to a predetermined portion of the surface wiring pattern 11c. Be placed. Then, the semiconductor chip 12 is FC mounted on the package substrate 11 of the housing portion 13b using bumps 12a (for signal transmission and GND connection), and the underfill resin 15 is filled in the housing portion 13b. On the semiconductor chip 12 and the layer 13, a sheet 14 extends and is disposed. The sheet 14 includes the conductive sheet 14A, the anisotropic conductive sheet 14B, a laminate of the anisotropic conductive sheet 14B and the adhesive sheet 14C, or one layer between the two layers of the anisotropic conductive sheet 14B. What interposes the adhesive sheet 14C can be used.

  The semiconductor package 30 is mounted on the semiconductor package 10 having such a configuration using the terminals 33 (the signal terminals 33a and the GND terminals 33b), and the PoP type semiconductor device 70 is obtained. In FIG. 30, the signal terminal 33a is electrically connected directly to the signal electrode 13ca at the corresponding position, and the GND terminal 33b is electrically connected to the GND electrode 13cb at the corresponding position via the sheet 14. The case where it is connected is illustrated.

The semiconductor package 10 using the package substrate 11 as shown in FIG.
Next, a tenth embodiment will be described.

FIG. 31 is a diagram illustrating an example of a semiconductor device according to the tenth embodiment. FIG. 31 schematically shows a cross-section of an essential part of an example of a PoP type semiconductor device.
A semiconductor device 80 illustrated in FIG. 31 includes the semiconductor package 10 and the semiconductor package 30 mounted thereon. The semiconductor package 10 includes the package substrate 11, the semiconductor chip 12, the layer 13, the sheet 14, and the underfill resin 15 as described above.

  As the package substrate 11 of the semiconductor package 10, for example, a substrate having a through via as shown in FIG. A package substrate 11 shown in FIG. 31 has a core substrate 11e provided with a predetermined-shaped wiring pattern 11f on both surfaces, an insulating layer 11h provided on both surfaces of the core substrate 11e, and a surface provided on both insulating layers 11h. A wiring pattern 11c (including electrode pads) is included. The wiring pattern 11f includes one that functions as signal wiring (in this example, provided on the mounting surface side of the semiconductor chip 12) and one that functions as GND wiring (in this example, the surface opposite to the mounting surface of the semiconductor chip 12). Provided on the side). The package substrate 11 has a through via 11k that penetrates the core substrate 11e and the two insulating layers 11h. Between the surface wiring patterns 11c provided on both surfaces of the package substrate 11 or between the surface wiring patterns 11c provided on both surfaces of the package substrate 11 and the wiring pattern 11f (GND wiring) on the core substrate 11e electrically through the through vias 11k. Connected. An insulating film 11a is provided on one insulating layer 11h side (surface opposite to the mounting surface of the semiconductor chip 12) provided with the surface wiring pattern 11c, and the surface wiring pattern 11c partially exposed from the insulating film 11a is provided. The external terminal 11b is electrically connected.

  A package substrate 11 having such a configuration can be used for the semiconductor package 10. On such a package substrate 11, a layer 13 having an accommodating portion 13b for accommodating the semiconductor chip 12 and an electrode 13c (signal electrode 13ca and GND electrode 13cb) electrically connected to a predetermined portion of the surface wiring pattern 11c. Be placed. Then, the semiconductor chip 12 is FC mounted on the package substrate 11 of the housing portion 13b using bumps 12a (for signal transmission and GND connection), and the underfill resin 15 is filled in the housing portion 13b. A sheet 14 extends and is disposed on the semiconductor chip 12 and the layer 13. The sheet 14 includes the conductive sheet 14A, the anisotropic conductive sheet 14B, a laminate of the anisotropic conductive sheet 14B and the adhesive sheet 14C, or one layer between the two layers of the anisotropic conductive sheet 14B. What interposes the adhesive sheet 14C can be used.

  The semiconductor package 30 is mounted on the semiconductor package 10 having such a configuration using the terminals 33 (the signal terminals 33a and the GND terminals 33b), and the PoP type semiconductor device 80 is obtained. In FIG. 31, the signal terminal 33a is electrically connected directly to the signal electrode 13ca at the corresponding position, and the GND terminal 33b is electrically connected to the GND electrode 13cb at the corresponding position via the sheet 14. The case where it is connected is illustrated.

The semiconductor package 10 using the package substrate 11 as shown in FIG.
30 and 31 exemplify a substrate having four layers of wiring (two-layer wiring pattern 11f and two-layer surface wiring pattern 11c) as the package substrate 11, but the number of wiring layers is not limited thereto. It is not limited.

  Further, the semiconductor device as described above can be mounted on another circuit board such as a mother board using the external terminals 11b of the semiconductor package 10. An electronic device obtained by mounting a semiconductor device on a circuit board in this way will be described as an eleventh embodiment.

FIG. 32 shows an example of an electronic apparatus according to the eleventh embodiment. FIG. 32 schematically illustrates a cross section of an essential part of an example of the electronic device.
As an example, FIG. 32 illustrates an electronic device 90 in which the semiconductor device 20 according to the second embodiment is mounted on the circuit board 91 using the external terminals 11b provided in the semiconductor package 10. Yes. The circuit board 91 includes an insulating part and a conductive part (wiring, via) provided in the insulating part, and a connection pad 91a electrically connected to the internal conductive part is provided on the surface of the circuit board 91. It has been. The external terminal 11 b of the semiconductor device 20 is electrically connected to a connection pad 91 a provided on the circuit board 91.

A high-performance electronic device 90 including the semiconductor device 20 including the semiconductor package 10 having excellent thermal and electromagnetic characteristics is realized.
Although the case where the semiconductor device 20 is mounted on the circuit board 91 is illustrated here, the above-described semiconductor devices 40, 50, 60, 70, 80, etc. are similarly mounted on the circuit board 91, and each electronic device is mounted. Can be realized.

  In the above description, the case where one semiconductor chip 12 is FC-mounted in the accommodating portion 13b of the layer 13 arranged on the package substrate 11 of the semiconductor package 10 is illustrated, but a plurality of semiconductors are included in the accommodating portion 13b. The chip may be FC mounted. Furthermore, other electronic components such as a chip capacitor may be mounted in the accommodating portion 13b together with the semiconductor chip. In addition, the housing portion 13 b provided in the layer 13 for housing one or a plurality of semiconductor chips and other electronic components is not limited to one, and may be provided in a plurality of locations in the layer 13.

Regarding the embodiment described above, the following additional notes are further disclosed.
(Appendix 1) Circuit board,
A semiconductor element flip-chip mounted on the circuit board;
A layer that is disposed on the circuit board and includes a housing portion that houses the semiconductor element;
An electrode disposed in the layer and electrically connected to the circuit board;
And a conductive sheet disposed on the entire surface of the semiconductor element and the layer and having an opening at a position corresponding to the electrode.

(Appendix 2) Circuit board,
A semiconductor element flip-chip mounted on the circuit board;
A layer that is disposed on the circuit board and includes a housing portion that houses the semiconductor element;
An electrode disposed in the layer and electrically connected to the circuit board;
And an anisotropic conductive sheet disposed on the entire surface of the semiconductor element and the layer.

(Supplementary note 3)
An insulating part;
The semiconductor device according to appendix 2, further comprising: conductive particles dispersed in the insulating portion.

(Appendix 4) The sheet is
A first sheet containing the conductive particles;
The semiconductor device according to appendix 3, further comprising: an insulating second sheet disposed between the first sheet and the semiconductor element and the layer.

  (Additional remark 5) The said sheet | seat is arrange | positioned between the said 2nd sheet | seat, the said semiconductor element, and the said layer, and has a 3rd sheet | seat containing the said electrically-conductive particle, The semiconductor device of Additional remark 4 characterized by the above-mentioned.

(Additional remark 6) The said sheet | seat has a conduction | electrical_connection part with which the said electrically-conductive particle mutually contacted partially, The semiconductor device in any one of Additional remark 2 thru | or 5 characterized by the above-mentioned.
(Additional remark 7) The said sheet | seat has an opening part which leads to the said electrode, The semiconductor device in any one of Additional remark 2 thru | or 6 characterized by the above-mentioned.

(Additional remark 8) The said sheet | seat is a semiconductor device of Additional remark 6 characterized by the said conductive particles contacting the said sheet surface direction, and forming wiring.
(Supplementary Note 9) The semiconductor element has a through via that penetrates the semiconductor element.
The semiconductor device according to any one of appendices 1 to 8, wherein the sheet is in contact with the through via.

(Additional remark 10) The semiconductor device in any one of additional remark 1 thru | or 9 characterized by including the resin layer with which the said accommodating part is filled.
(Appendix 11) The semiconductor device according to any one of Appendixes 1 to 10, and
Including a semiconductor device having a bump electrically connected to the electrode, a circuit board disposed with a gap between the upper surface of the sheet, and a semiconductor element mounted on the circuit board. A characteristic semiconductor package.

(Additional remark 12) The said bump is electrically connected with the said electrode by the said sheet | seat, The semiconductor package of Additional remark 11 characterized by the above-mentioned.
(Additional remark 13) The process of arrange | positioning the layer provided with the accommodating part which accommodates the said semiconductor element while flip-chip mounting a semiconductor element on a circuit board,
Disposing an electrode electrically connected to the circuit board in the layer;
A method of manufacturing a semiconductor device, comprising: placing a sheet having an opening and conductivity on the entire surface of the layer from the semiconductor element so as to align the opening and the electrode.

(Supplementary Note 14) A step of flip-chip mounting a semiconductor element on a circuit board and disposing a layer including a housing portion that houses the semiconductor element;
Disposing an electrode electrically connected to the circuit board in the layer;
And a step of disposing an anisotropic conductive sheet on the entire surface of the semiconductor element and the layer. A method for manufacturing a semiconductor device, comprising:

(Supplementary Note 15)
An insulating part;
15. The method of manufacturing a semiconductor device according to appendix 14, wherein the conductive particles are dispersedly arranged in the insulating portion.

  (Supplementary note 16) The supplementary note 15, further comprising a step of providing a conductive portion that partially presses the sheet and brings the conductive particles into contact with each other after the step of arranging the sheet. The manufacturing method of the semiconductor device of description.

  (Supplementary note 17) The method for manufacturing a semiconductor device according to supplementary note 15 or 16, further comprising a step of providing the sheet with an opening leading to the electrode after the step of arranging the sheet.

(Supplementary Note 18) After the step of arranging the sheet, the method further includes a step of pressing a member including a probe and a pressing portion against the sheet.
In the step of pressing the member against the sheet, the probe penetrates the sheet and contacts the electrode, thereby providing an opening in the sheet and partially pressing the sheet with the pressing portion. The manufacturing method of the semiconductor device according to supplementary note 15, further comprising a step of providing a conductive portion in which the conductive particles are brought into contact with each other on the sheet.

(Supplementary note 19) After the step of arranging the sheet,
Disposing a semiconductor package having a bump above the semiconductor element and the layer;
The method for manufacturing a semiconductor device according to any one of appendices 13 to 18, further comprising a step of electrically connecting the bump to the electrode.

DESCRIPTION OF SYMBOLS 10 Semiconductor package 11 Package board 11a Insulating film 11b External terminal 11c Surface wiring pattern 11cc Electrode pad 11d Via 11e Core board 11f Wiring pattern 11g Via 11h Insulating layer 11k Through via 12 Semiconductor chip 12a Bump 12b Through via 13 Layer 13a Insulating layer 13b Part 13c Electrode 13ca Signal electrode 13cb GND electrode 13cd Used electrode 13ce Unused electrode 13d Through hole 14 Sheet 14A Conductive sheet 14B Anisotropic conductive sheet 14C Adhesive sheet 14a Opening part 14b Insulating part 14c Conductive filler 14d Wiring pattern 15 Underfill resin 20 , 40, 50, 60, 70, 80 Semiconductor device 21 Gap 30 Semiconductor package 31 Package substrate 32 Sealing portion 33 Terminal 33a Signal end Child 33b GND terminal 90 Electronic device 91 Circuit board 91a Connection pad 110 Step 110a, 110b Air gap 111a Insulating film 111b Terminal 111c Land portion 200, 200a Test device 210 Socket 211 Probe 220 Control portion 230 Guide portion 231 Protrusion

Claims (8)

A circuit board;
A semiconductor element flip-chip mounted on the circuit board;
A layer that is disposed on the circuit board and includes a housing portion that houses the semiconductor element;
A signal electrode disposed in the layer and electrically connected to the circuit board;
An electrode different from the signal electrode disposed in the layer;
Semiconductors wherein disposed on the upper surface of the semiconductor element and the layer having the signal opening at a position corresponding to the electrode, characterized in that it comprises a sheet having an electrically conductive connecting different electrode and the signal electrode apparatus. A circuit board;
A semiconductor element flip-chip mounted on the circuit board;
A layer that is disposed on the circuit board and includes a housing portion that houses the semiconductor element;
An electrode disposed in the layer, electrically connected to the circuit board and exposed from an upper surface of the layer;
The semiconductor element is disposed on an upper surface of the layer and the electrode, seen containing an insulating portion, and an anisotropic conductive sheet having said insulating portion in the distributed conductive particles,
The anisotropic conductive sheet partially includes a conductive portion in which the conductive particles are in contact with each other . The semiconductor device according to claim 2, wherein the anisotropic conductive sheet has an opening that communicates with the electrode. The semiconductor device according to claim 2 , wherein the anisotropic conductive sheet forms a wiring by contacting the conductive particles in the anisotropic conductive sheet surface direction. The semiconductor device according to any one of claims 2 to 4 , and
A semiconductor device comprising a bump electrically connected to the electrode, a circuit board disposed with a gap between the upper surface of the anisotropic conductive sheet, and a semiconductor element mounted on the circuit board A semiconductor package comprising: A step of flip-chip mounting a semiconductor element on a circuit board and disposing a layer having a housing portion for housing the semiconductor element;
Disposing a signal electrode electrically connected to the circuit board and an electrode different from the signal electrode in the layer;
An electrode having an opening on the upper surface of the semiconductor element and the layer and having conductivity, and an electrode different from the signal electrode and the sheet having conductivity are disposed while aligning the position of the opening and the signal electrode. And a step of contacting the semiconductor device. A step of flip-chip mounting a semiconductor element on a circuit board and disposing a layer having a housing portion for housing the semiconductor element;
Disposing an electrode in the layer that is electrically connected to the circuit board and exposed from an upper surface of the layer;
Disposing an anisotropic conductive sheet having an insulating portion and conductive particles dispersed and arranged in the insulating portion on the semiconductor element, the layer, and the upper surface of the electrode ;
After the step of disposing the anisotropic conductive sheet, a step of pressing a member including a probe and a pressing portion against the anisotropic conductive sheet;
Including
The step of pressing the member against the anisotropic conductive sheet includes providing an opening in the anisotropic conductive sheet by causing the probe to penetrate the anisotropic conductive sheet and contact the electrode. A step of partially pressing the anisotropic conductive sheet with the pressing portion to provide a conductive portion that brings the conductive particles into contact with each other on the anisotropic conductive sheet . Production method. After the step of arranging the anisotropic conductive sheet,
Disposing a semiconductor package having a bump above the semiconductor element and the layer;
The method for manufacturing a semiconductor device according to claim 7 , further comprising: electrically connecting the bump to the electrode.

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