JP6090873B1 - Information processing apparatus and serial communication data demultiplexing and conversion method - Google Patents

Abstract

An SPI master circuit having a high SPI communication speed in an information processing apparatus that connects a high-speed SPI master circuit on the main control unit side and a low-speed SPI slave circuit on the option control unit side through an SPI (Serial Peripheral Interface) bus. Provided is an information processing apparatus capable of setting a speed in accordance with When the communication speed of the SPI master circuit is set to n times (n: a positive integer of 2 or more) as compared to the SPI slave circuits, the SPI slave circuit is connected to the option control unit. .., 22 are mounted, and the connection between the SPI master circuit 11 and each of the n SPI slave circuits 21,..., 22 is separated and converted from the data from the SPI master circuit 11 into n data. Are connected via an SPI demultiplexing / converting circuit 3 that multiplexes and converts the data from each of the n SPI slave circuits 21,..., 22 into one data. [Selection] Figure 1

Description

  The present invention relates to an information processing apparatus and a serial communication data demultiplexing / multiplexing method, and more particularly to an information processing apparatus and a serial communication data demultiplexing / multiplexing method configured to include a main control unit and one or more option control units.

  In recent years, in the field of information processing devices such as telephone devices, data communication devices, and notebook PCs (Personal Computers), the progress of miniaturization and high functionality has been remarkable, and the main control unit (main CPU (Central Processing Unit)) Various option control units (sub CPUs) mounted according to the purpose are connected via a serial bus, and the master control unit (main CPU) and option control unit (sub CPU) are connected to A number of configurations that perform slave-type synchronous serial communication have been adopted as configurations capable of high-speed communication.

Here, various types of bus systems for synchronous serial communication, such as an SPI (Serial Peripheral Interface) bus format and an I ² C (Inter-Integrated Circuit) bus format, are known. Of these synchronous serial communication bus systems, as described in Japanese Patent Laid-Open No. 4-287150 “Synchronous Serial Bus System” of Patent Document 1, a 4-wire SPI that can be further increased in speed. Bus formats are expected to become more widespread in the future.

  When the SPI bus format is adopted as a bus system for synchronous serial communication, generally, only one main CPU on the main control unit side mounted in one information processing apparatus is an expensive and high-speed serial communication device, that is, an SPI master. Although it is possible to employ a circuit, it is not possible to employ an expensive and high-speed serial communication device to reduce the device price for the sub CPU on the option control unit side that must be mounted according to the purpose. Only an inexpensive and low-speed serial communication device, that is, an SPI slave circuit can be employed.

  When serial data communication, that is, SPI communication is performed between the high-speed serial communication device that is mounted on the main control unit side, that is, the SPI master circuit, and the low-speed serial communication device that is mounted on the option control unit side, that is, the SPI slave circuit. Serial communication data is transmitted and received at a speed that matches the communication speed of the serial communication device, that is, the SPI master circuit, with the communication speed of the low-speed serial communication device, that is, the SPI slave circuit on the communication partner side.

JP-A-4-287150 (page 3-4)

  As described above, in the field of information processing devices such as telephone devices, communication devices, notebook PCs, etc., the device is composed of one main control unit and a plurality of optional control units mounted as necessary. There are many. In the information processing apparatus configured as described above, only one is mounted as described above in order to configure an SPI bus type bus system, which is one of the master / slave type synchronous serial communication bus systems. In general, an expensive and high-speed processor can be adopted for the main CPU on the main control unit side that is not used, so that a high-speed performance of, for example, several tens of MHz is realized as an operation clock of a high-speed serial communication device, that is, an SPI master circuit Things can be applied. On the other hand, for the sub CPU on the option control unit side that requires a plurality of mountings, in order to reduce the component price, the operation clock of the low-speed serial communication device, that is, the SPI slave circuit mounted therein is, for example, several MHz In many cases, a device capable of realizing only a low communication speed is used.

  Therefore, in the serial data communication (SPI communication) between the SPI master circuit mounted in the main CPU on the main control unit side and the SPI slave circuit mounted in the sub CPU on the option control unit side, for example, the SPI Even if the master circuit is a device capable of high-speed communication, the communication speed of the serial communication data (SPI data) of the SPI master circuit is limited to the communication speed of the serial communication data of the SPI slave circuit on the option control unit side of the communication partner As a result, the amount of data communication per unit time in the system of the entire information processing apparatus becomes insufficient, and sufficient system operation performance as the information processing apparatus cannot be realized.

(Object of the present invention)
The present invention has been made in view of the above problems, and uses an SPI (Serial Peripheral Interface) bus type bus system which is one of the master / slave type synchronous serial communication bus systems. In an information processing apparatus configured by mutually connecting a high-speed SPI master circuit mounted on a main control unit and low-speed SPI slave circuits mounted on one or more option control units, the high-speed SPI master circuit Information processing apparatus and serial communication data demultiplexing and conversion method capable of setting SPI communication speed in SPI communication between a circuit and a low-speed SPI slave circuit to a speed matching the communication speed of a high-speed SPI master circuit Its purpose is to provide.

  In order to solve the above-described problems, the information processing apparatus and serial communication data demultiplexing / multiplexing method according to the present invention mainly adopt the following characteristic configuration.

  (1) An information processing apparatus according to the present invention is mounted on a main control unit using an SPI (Serial Peripheral Interface) bus type bus system, which is one of master / slave type synchronous serial communication bus systems. In an information processing apparatus configured by mutually connecting a high-speed SPI master circuit and low-speed SPI slave circuits mounted on one or more option control units, the communication speed of the SPI master circuit is the SPI speed. When the speed is n times (n: a positive integer greater than or equal to 2) compared to the slave circuit, the speed ratio n: 1 between the SPI master circuit on the high speed side and the SPI slave circuit on the low speed side depends on the speed ratio n: 1. The n SPI slave circuits are mounted on the option control unit side, and the SPI master circuit and the n SPI slave circuits are mounted. The serial communication data from the SPI master circuit is separated and converted into n data, and the serial communication data from each of the n SPI slave circuits is multiplexed into one data. The connection is made via an SPI demultiplexing and converting circuit for conversion.

  (2) The SPI communication data demultiplexing / conversion method according to the present invention uses an SPI (Serial Peripheral Interface) bus type bus system, which is one of the master / slave type synchronous serial communication bus systems, to perform main control. An information processing apparatus configured by interconnecting a high-speed SPI master circuit mounted on a unit and a low-speed SPI slave circuit mounted on one or more option control units. A serial communication data demultiplexing / multiplexing conversion method for demultiplexing / multiplexing serial communication data transferred to / from an SPI slave circuit, wherein the communication speed of the SPI master circuit is n times as high as that of the SPI slave circuit ( n: a positive integer of 2 or more), the SPI master circuit on the high speed side and the low speed side Depending on the speed ratio n: 1 with the PI slave circuit, n optional SPI slave circuits are mounted on the option control unit side, and serial communication data from the SPI master circuit is separated and converted into n data. Then, each of the n separated data is supplied to each of the n SPI slave circuits at a communication speed corresponding to each of the SPI slave circuits, and serial communication from each of the n SPI slave circuits is performed. The data is multiplexed and converted into one piece of data and supplied to the SPI master circuit at a communication speed corresponding to the SPI master circuit.

  According to the information processing apparatus and serial communication data demultiplexing / multiplexing method of the present invention, the following effects can be obtained.

  In the present invention, high-speed serial communication capable of high-speed communication in an information processing apparatus having an SPI (Serial Peripheral Interface) bus system bus system, which is one of the master-slave type synchronous serial communication bus systems. When performing serial data communication (SPI communication) with a low-speed serial communication device that can only communicate at low speed with the device, that is, the SPI master circuit (SPI communication), communication is performed at a speed that matches the high-speed serial communication device, that is, the SPI master circuit. It is possible.

  Therefore, a main control unit capable of performing high-speed serial communication by mounting a high-speed serial communication device, that is, an SPI master circuit, and one or more options capable of realizing only low-speed serial communication by mounting a low-speed serial communication device, that is, an SPI slave circuit. Even in the case of an apparatus configuration including a control unit, it is possible to avoid reducing the communication speed on the high-speed serial communication device, that is, the SPI master circuit side, to the low-speed communication speed on the low-speed serial communication device, that is, the SPI slave circuit side. Therefore, the system operation performance of the entire information processing apparatus such as a telephone apparatus, a data communication apparatus, and a notebook PC can be greatly improved as compared with the conventional system.

It is a block block diagram which shows an example of the principal part of the apparatus structure of the information processing apparatus which concerns on this invention. FIG. 2 is a block configuration diagram illustrating an example of an internal configuration of an SPI demultiplexing / converting circuit illustrated in FIG. 1. FIG. 3 is a circuit configuration diagram illustrating an example of a specific circuit configuration regarding an internal configuration of an SPI demultiplexing / converting circuit illustrated in FIG. 2; 4 is a timing chart illustrating an example of the operation of the SPI demultiplexing / converting circuit illustrated in FIG. 3. It is explanatory drawing for demonstrating an example of the conversion operation | movement of SPI data in the information processing apparatus provided with the SPI demultiplexing / multiplexing circuit shown in FIG.

  Preferred embodiments of an information processing apparatus and a serial communication data demultiplexing / multiplexing method according to the present invention will be described below with reference to the accompanying drawings. In addition, it is needless to say that the drawing reference numerals attached to the following drawings are added for convenience to the respective elements as an example for facilitating understanding, and are not intended to limit the present invention to the illustrated embodiments. Yes.

(Features of the present invention)
Prior to the description of the embodiments of the present invention, an outline of the features of the present invention will be described first. The present invention provides an information processing apparatus having an SPI (Serial Peripheral Interface) bus type bus system, which is one of the master / slave type synchronous serial communication bus systems. SPI communication between a high-speed serial communication device capable of communication, that is, an SPI master circuit, and each low-speed serial communication device capable of performing only low-speed communication mounted on one or a plurality of option control units, that is, each SPI slave circuit When performing the above, it is possible to perform serial communication at a speed matched to the high-speed SPI master circuit by applying the following configuration, and therefore, the maximum of each SPI slave circuit on the option control unit side Enable serial data communication (SPI communication) with data amount n times the communication speed It has been a major feature of the Rukoto.

  That is, as the configuration to be applied, a high-speed serial communication device, that is, an SPI master circuit, and a low-speed serial communication device, in which the data communication speed is 1 / n (n: a positive integer of 2 or more) as compared with the SPI master circuit, The SPI slave circuit is connected via an SPI demultiplexing / multiplexing circuit that performs demultiplexing / multiplexing conversion of serial communication data (SPI data) to be transferred between the two, and the option control unit side has a low speed. A configuration is adopted in which n serial communication devices, that is, SPI slave circuits (the number corresponding to the speed ratio n: 1 with respect to the communication speed of the SPI master circuit) is mounted.

  For example, when one option control unit is mounted and the option control unit has half the communication speed of the high-speed serial communication device on the main control unit side, that is, the SPI master circuit (1 / n = 1/2). In the case where a low-speed serial communication device, that is, an SPI slave circuit, having a communication capability of (1) is mounted, two low-speed serial communication devices, that is, SPI slave circuits (n = 2) are mounted in the option control unit.

  When serial data communication is performed between one high-speed serial communication device, that is, the SPI master circuit, and two low-speed serial communication devices, that is, the SPI slave circuit, the downlink from the SPI master circuit to the two SPI slave circuits. With respect to serial communication data (SPI data) in the direction, by performing conversion that separates the data amount into two pieces of data each having a half (1 / n = 1/2), and reducing the data amount by half, The data is distributed to each SPI slave circuit at a communication speed corresponding to each SPI slave circuit. On the other hand, with respect to serial communication data (SPI data) in the upward direction from two SPI slave circuits to one SPI master circuit, serial communication data (SPI data) from each of the two SPI slave circuits is stored as one data. The data is doubled (n = 2) by performing conversion to be multiplexed, and distributed to the SPI master circuit at a communication speed corresponding to the SPI master circuit.

  Thus, in serial data communication (SPI communication) between a high-speed serial communication device, that is, an SPI master circuit, and a plurality (n) of low-speed serial communication devices, that is, SPI slave circuits, the high-speed serial communication device, that is, the SPI master circuit. Since serial communication can be performed at the combined speed, a main control unit capable of high-speed serial communication by mounting a high-speed serial communication device, that is, an SPI master circuit, and a low-speed serial communication device, that is, an SPI slave circuit are mounted. Even in an apparatus configuration composed of a plurality of option control units that can implement only low-speed serial communication, the communication speed on the high-speed serial communication device, that is, the SPI master circuit side, is set to be the low speed communication speed on the low-speed serial communication device, that is, the SPI slave circuit side. Until it is possible to avoid lowering the telephone device and a data communication device, the information processing apparatus overall system operation performance such as a notebook PC can be conventionally greatly improved.

(Configuration example of embodiment of the present invention)
Next, an example of an apparatus configuration of the information processing apparatus according to the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing an example of the main part of the device configuration of an information processing apparatus according to the present invention. As an example, one main control unit (main CPU) and one option control unit ( However, it is of course possible to mount one or more optional control units (sub CPUs) as necessary.

  The information processing apparatus shown in the block diagram of FIG. 1 is a master / slave type synchronous system as a bus system for connecting the main control unit 1 (main CPU) and the option control unit 2 (sub CPU). An SPI (Serial Peripheral Interface) bus type bus system, which is one of serial communication bus systems, is provided. That is, the information processing apparatus shown in the block configuration diagram of FIG. 1 includes one main control unit 1 (main CPU) and one option control unit 2 (sub CPU) as described above. In order to form an SPI bus type bus system, an SPI master circuit 11 is mounted as a high-speed serial communication device in the main control unit 1, while an SPI slave as a low-speed serial communication device is installed in the option control unit 2. Two sets of a circuit 21 and an SPI slave circuit 22 are mounted.

  Also, the SPI master circuit 11 on the main control unit 1 side and the SPI slave circuit 21 and SPI slave circuit 22 on the option control unit 2 side are respectively connected to each other by using a serial bus composed of four signal lines. They are connected via the conversion circuit 3. The SPI demultiplexing / conversion circuit 3 is configured to receive two pieces of data each having a half data amount with respect to serial communication data (SPI data) in the downstream direction from the SPI master circuit 11 to the two SPI slave circuits 21 and the SPI slave circuit 22. The data amount is reduced by half and distributed to the SPI slave circuit 21 and the SPI slave circuit 22 at communication speeds corresponding to the SPI slave circuit 21 and the SPI slave circuit 22, respectively.

  On the other hand, for the serial communication data (SPI data) in the upward direction from each of the two SPI slave circuits 21 and SPI slave circuits 22 in the reverse direction to the one SPI master circuit 11, the SPI demultiplexing / converting circuit 3 includes two SPI The serial communication data (SPI data) from each of the slave circuit 21 and the SPI slave circuit 22 is converted into a single data, the data amount is doubled, and the communication speed corresponding to the SPI master circuit 11 And delivered to the SPI master circuit 11. Here, the SPI demultiplexing / converting circuit 3 can be realized with a simple circuit configuration, and is configured by a CPLD (Complex Programmable Logic Device) or a LOGIC IC (Logic Integrated Circuit). Is possible.

  In the configuration example shown in FIG. 1, the SPI data communication speed of the high-speed SPI master device 11 is twice the communication speed of the low-speed SPI slave circuit 21 and SPI slave circuit 22. Is assumed. Therefore, two SPI slave circuits 21 and SPI slave circuits 22 are mounted on the option control unit 2 side with respect to one SPI master circuit 11 mounted on the main control unit 1 side.

  In general, the SPI data communication speed of the high-speed SPI master device mounted on the main control unit 1 side is n times the communication speed of the low-speed SPI slave circuit mounted on the option control unit 2 side (n: 2 or more). In the case of a positive integer), n SPI slave circuits are mounted on the option control unit side of the SPI communication partner with respect to one SPI master circuit 11 mounted on the main control unit side. Configure. Then, the SPI demultiplexing / conversion circuit 3 performs conversion for separating the serial communication data (SPI data) in the downlink direction from the SPI master circuit 11 to each of the n SPI slave circuits into n data, Is reduced by (1 / n) and distributed to each of the n SPI slave circuits at a communication speed corresponding to each of the SPI slave circuits. On the other hand, as for serial communication data (SPI data) in the upward direction from each of the n SPI slave circuits in the reverse direction to one SPI master circuit, serial communication data (SPI data) from each of the n SPI slave circuits 22. ) Is multiplexed into one data, the data amount is increased by a factor of n, and distributed to the SPI master circuit at a communication speed corresponding to the SPI master circuit.

  Next, the internal configuration of the SPI demultiplexing / converting circuit 3 shown in FIG. 1 will be described. FIG. 2 is a block configuration diagram showing an example of the internal configuration of the SPI demultiplexing / converting circuit 3 shown in FIG. As shown in FIG. 2, the SPI demultiplexing / multiplexing circuit 3 has a simple circuit configuration, and includes an SPI clock frequency dividing circuit 31, an SPI upstream data multiplexing circuit 32, an SPI downstream data shift circuit 33, and an SPI enable. A buffer circuit 34 is included.

  Also, the SPI signal line forming the SPI bus of the high-speed SPI master circuit 11 mounted on the main control unit 1 is, as shown in FIG. 2, a master-side clock signal SCK (clock signal of the SPI master circuit 11). Serial Clock), master side upstream data signal MISO (Master In Slave Out) indicating upstream data transmitted from the SPI slave circuits 21 and 22 side, and master side indicating downstream data transmitted to the SPI slave circuits 21 and 22 Four types of signals are transmitted: a downlink data signal MOSI (Master Out Slave In) and a master-side slave selection signal SS (Slave Select: master-side SPI enable signal) that transmits enable information related to the SPI slave circuits 21 and 22. It consists of four signal lines.

  On the other hand, the signal lines forming the SPI bus of the low-speed SPI slave circuits 21 and 22 mounted on the option control unit 2 are SPI slaves obtained by dividing the master-side clock signal SCK by half (1/2). First and second slave side clock signals SCK1 and SCK2 which are clock signals of the circuits 21 and 22, respectively, and first and second slave side upstream data signals MISO1 and MISO2 indicating upstream data to be transmitted to the SPI master circuit 11. First and second slave-side downlink data signals MOSI1 and MOSI2 indicating downlink data transmitted from the SPI master circuit 11 side, and first and second slave-side slaves receiving enable information from the SPI master circuit 11 4 types of selection signals SS1, SS2 (ie slave side SPI enable signal) One of which is the signal line of each four to transmit signals.

  The SPI clock frequency dividing circuit 31 converts the master side clock signal of the high speed side SPI master circuit 11 to (1 / n) according to the speed ratio n: 1 with the low speed side SPI slave circuits 21,. The clock signal is divided into clock signals and the phase of the clock signal divided into (1 / n) is adjusted and generated as slave-side clock signals to be supplied to the low-speed SPI slave circuits 21,. In this embodiment, first and second slave clock signals SCK1 and SCK2 are generated by dividing the master clock signal SCK from the SPI master circuit 11 by half (1/2). This is a circuit that supplies the SPI slave circuits 21 and 22 respectively.

  The SPI upstream data multiplexing circuit 32 multiplexes SPI upstream data transmitted from each of the n SPI slave circuits 21,..., 22 in synchronization with each slave-side clock signal into one data, and generates an SPI master. This circuit is supplied to the SPI master circuit 11 at a speed that matches the communication speed of the circuit 11. In this embodiment, the SPI slave frequency signal SCK1 generated by the SPI clock frequency dividing circuit 31 is used to generate the SPI master circuit 11. The first and second slave-side uplink data signals MISO1 and MISO2 transmitted from the slave circuits 21 and 22 are multiplexed into one data, and one master-side uplink data signal MISO (first and second data signals) is multiplexed. The data amount of the sum of the data amounts of both the slave side upstream data signals MISO1 and MISO2). To a circuit for supplying the SPI master circuit 11 at a rate matching the data communication speed of the SPI master circuit 11.

  The SPI downlink data shift circuit 33 (SPI downlink data separation circuit) separates SPI downlink data transmitted from the SPI master circuit 11 in synchronization with the master side clock signal into n pieces of data, This is a circuit that supplies each of the n SPI slave circuits 21,..., 22 at a speed that matches the communication speed of each SPI slave circuit 21,. The master side downstream data signal MOSI is synchronized with the first and second slave side clock signals SCK1 and SCK2 divided by the SPI clock frequency dividing circuit 31 to (1/2). The first and second slave-side downlink data signals MOSI1, MO are respectively shifted to the SPI slave circuits 21, 22 while being shifted in period or as they are. Constitute a circuit for supplying a I2.

  Although details will be described later in the present embodiment, in each of the SPI slave circuits 21 and 22, the SPI downstream data shift circuit is at the falling timing of each of the first and second slave clock signals SCK1 and SCK2. 33, the first and second slave-side downlink data signals MOSI1 and MOSI2 supplied from 33 are respectively received. As a result, the first and second slave-side downlink data signals MOSI1 and MOSI2 are received as the master side. A data signal (a data signal having a data amount half that of the master-side downlink data signal MOSI) obtained by alternately dividing the downlink data signal MOSI into two in bit order is received.

  The SPI enable buffer circuit 34 is a circuit that supplies an enable signal of the SPI master circuit 11 to each of the n SPI slave circuits that are communication partners. In this embodiment, the SPI enable buffer circuit 34 enables the master side enable of the SPI master circuit 11. This is a circuit that supplies the master slave selection signal SS to the SPI slave circuits 21 and 22 as first and second slave enable signals, ie first and second slave selection signals SS1 and SS2, respectively. .

  Next, an example of a specific circuit configuration relating to the internal configuration of the SPI demultiplexing / converting circuit 3 illustrated in FIG. 2 will be described with reference to FIG. FIG. 3 is a circuit configuration diagram showing an example of a specific circuit configuration related to the internal configuration of the SPI demultiplexing / converting circuit 3 illustrated in FIG. In the circuit configuration example shown in FIG. 3, it is assumed that the first and second SPI slave-side downlink data signals MOSI1 and MOSI2 from the SPI demultiplexing / converting circuit 3 are all first and second. The SPI slave circuits 21 and 22 receive the slave clock signals SCK1 and SCK2 at the falling timing, respectively, while the first and second slave side SPI upstream data signals MISO1 and MISO2 have the first, It is assumed that the second slave clock signals SCK1 and SCK2 are output in synchronization with the rising timing.

  As shown in the circuit configuration of FIG. 3, the SPI clock frequency dividing circuit 31 is configured by using two D Philip flops 311 and 312. First, a clock signal obtained by dividing the master side clock signal SCK into (1/2) by the D flip-flop 311 is generated and output to the SPI slave circuit 21 as the first slave side clock signal SCK1. In addition, the first slave side clock signal SCK1 is further input to the D flip-flop 312 to generate a (1/2) frequency-divided clock signal that is shifted to the falling timing of the master side clock signal SCK. Is output to the SPI slave circuit 22 as the slave side clock signal SCK2.

  The SPI uplink data multiplexing circuit 32 is configured using a selector 321, and the first slave clock signal SCK 1 output from the D flip-flop 311 of the SPI clock frequency dividing circuit 31 is used as a selection signal for the selector 321. The selector 321 is switched at the timing of “1” (High Level) and “0” (Low Level) of the slave side clock signal SCK1. That is, one of the first and second slave-side uplink data signals MISO1 and MISO2 transmitted from the SPI slave circuits 21 and 22 at the rising timing of the first and second slave-side clock signals SCK1 and SCK2, respectively. Are multiplexed by alternately selecting each bit according to the timing of '1' (High Level) and '0' (Low Level) of the first slave side clock signal SCK1 by the selector 321. An SPI master circuit that generates a master-side data signal MISO (a data signal having a total data amount of both the first and second slave-side upstream data signals MISO1 and MISO2) at a speed that matches the communication speed of the SPI master circuit 11. 11 is output.

  The SPI downstream data shift circuit 33 is configured using a D flip-flop 331, and the master-side data signal MOSI output from the SPI master circuit 11 at the rising timing of the master-side clock signal SCK is transmitted by the D flip-flop 331. The signal is converted into a signal phase-shifted to the falling position of the master side clock signal SCK, generated as the first slave side SPI down data signal MOSI1 for the SPI slave circuit 21, and output to the SPI slave circuit 21. For the second slave side SPI down data signal MOSI2 for the SPI slave circuit 22, the master side data signal MOSI is output as it is.

  Here, as described above, the first and second SPI slave side downlink data signals MOSI1 and MOSI2 from the SPI demultiplexing / conversion circuit 3 are the falling edges of the first and second slave side clock signals SCK1 and SCK2, respectively. The SPI slave circuits 21 and 22 are configured to receive at the timing shown in FIG. Therefore, although details will be described later, in each of the SPI slave circuits 21 and 22, data at different bit positions of the master side data signal MOSI output from the SPI master circuit 11 are alternately selected for each bit. As a result, each of the SPI slave circuits 21 and 22 separates and receives half the data amount of the master-side data signal MOSI, and receives the data at the communication speed of each of the SPI slave circuits 21 and 22. It will be.

  The SPI enable buffer circuit 34 uses the master SPI enable signal SS as it is, as a first slave enable signal SS1 for the SPI slave circuit 21 and a second slave enable signal SS2 for the SPI slave circuit 22, respectively. Output to the SPI slave circuit 21 and the SPI slave circuit 22.

(Description of operation of embodiment)
Next, the operation of the SPI demultiplexing / converting circuit 3 exemplified as a configuration example of the embodiment in FIGS. 1 to 3 will be described in detail. FIG. 4 is a timing chart showing an example of the operation of the SPI demultiplexing / converting circuit 3 shown in FIG.

  As described above, as basic operations in the SPI demultiplexing / multiplexing circuit 3, the SPI master circuit 11, and the SPI slave circuits 21 and 22, respectively, the master-side SPI upstream data signal MISO, the first and second slave-side SPI upstream data The signals MISO1 and MISO2 all operate so as to be output at a timing synchronized with the rising of the master side clock signal SCK and the first and second slave side clock signals SCK1 and SCK2, respectively.

  That is, with respect to the output timing of the SPI upstream data signal, as shown in the timing chart of FIG. 4, from the master side SPI upstream data signal MISO output from the SPI demultiplexing / multiplexing circuit 3 to the SPI master circuit 11, the SPI slave circuit 21. The first slave-side SPI upstream data signal MISO1 output to the SPI demultiplexing and converting circuit 3 and the second slave-side SPI upstream data signal MISO2 output from the SPI slave circuit 22 to the SPI demultiplexing and converting circuit 3 are respectively Are output from the SPI demultiplexing / converting circuit 3, the SPI slave circuit 21, and the SPI slave circuit 22 at a timing synchronized with the rising of the master side clock signal SCK and the first and second slave side clock signals SCK1 and SCK2, respectively. .

  The same applies to the output timing of the master-side SPI downlink data signal MOSI output from the SPI master circuit 11 to the SPI demultiplexing / conversion circuit 3, and the SPI master circuit is synchronized with the rising edge of the master-side clock signal SCK. 11 is output.

  On the other hand, regarding the reception timing of the SPI downlink data signal, the first slave-side SPI downlink data signal MOSI1 output from the SPI demultiplexing / conversion circuit 3 to the SPI slave circuit 21 and the SPI demultiplexing / conversion circuit 3 to the SPI slave circuit 22 are output. The output second slave-side SPI downstream data signal MOSI2 is received by the SPI slave circuits 21 and 22, respectively, at a timing synchronized with the fall of the first and second slave-side clock signals SCK1 and SCK2. To work.

  That is, regarding the reception timing of the SPI downlink data signal, as shown in the timing chart of FIG. 4, the master-side SPI downlink output to the SPI demultiplexing / conversion circuit 3 at the rising timing of the master-side clock SCK from the SPI master circuit 11. The data signal MOSI is separated into first and second slave-side SPI downlink data signals MOSI1 and MOSI2 in the SPI demultiplexing / multiplexing circuit 3 and output to the SPI slave circuit 21 and the SPI slave circuit 22, respectively. Thereafter, the first and second slave-side SPI downstream data signals MOSI1 and MOSI2 are synchronized with the falling edges of the first and second slave-side clock signals SCK1 and SCK2, respectively, and the SPI slave circuit 21, SPII. The data is received by each slave circuit 22.

  The same applies to the reception timing of the master-side SPI uplink data signal MISO output from the SPI demultiplexing / conversion circuit 3 to the SPI master circuit 11, and the first and first from the SPI slave circuit 21 and SPI slave circuit 22 respectively. The first and second slave-side SPI upstream data signals MISO1 and MISO2 output to the SPI demultiplexing / conversion circuit 3 at the rising timing of the two slave-side clock signals SCK1 and SCK2 It is multiplexed as a side SPI upstream data signal MISO and then received by the SPI master circuit 11 at a timing synchronized with the falling edge of the master side clock signal SCK.

  Also, the master-side slave selection signal SS and the first and second slave-side slave selection signals SS1, SS2 are all in the enabled state of “0” (Low Level). In the timing chart of FIG. Side slave selection signal SS is '0' (Low Level), and therefore, the master side slave selection signal SS is output from the SPI demultiplexing / conversion circuit 3 as it is, the first and second slave side slave selection signals SS1, SS2 Also, it is at “0” (Low Level), indicating that both the SPI master circuit 11 and the SPI slave circuits 21 and 22 of the communication counterpart are in an enabled state.

  Further, as described in FIG. 3, the master side clock signal SCK output from the SPI master circuit 11 is input to the D flip-flop 311 of the SPI clock frequency dividing circuit 31, and the D flip-flop 311 (1 / 2) and is generated as the first slave side clock signal SCK1, and as shown in the timing chart of FIG. 4, in the state where the rising timing coincides with the rising timing of the master side clock signal SCK, It is output to the slave circuit 21.

  The first slave clock signal SCK1 output from the D flip-flop 311 is further input to the D flip-flop 312, and the D flip-flop 312 has (1/2) cycles of the master clock signal SCK. As shown in the timing chart of FIG. 4, a (1/2) frequency-divided clock signal in which the rising timing is shifted to the falling timing of the master side clock signal SCK is generated as shown in the timing chart of FIG. The slave clock signal SCK2 is output to the SPI slave circuit 22.

  The first and second slave-side SPI upstream data signals MISO1 and MISO2 output from the SPI slave circuits 21 and 22 are respectively the first and second slave sides as shown in the timing chart of FIG. The clock signals SCK1 and SCK2 are output to the SPI upstream data multiplexing circuit 32 of the SPI demultiplexing and converting circuit 3 at the rising timing. Here, in the SPI uplink data multiplexing circuit 32, as described with reference to FIG. 3, '1' (High Level) and '0' of the first slave side clock signal SCK1 output from the D flip-flop 311. The selection operation of the selector 321 is switched at the (Low Level) timing.

  Therefore, while the first slave side clock signal SCK1 is “1” (High Level), the first slave side SPI upstream data signal MISO1 is output from the selector 321 and the first slave side clock signal SCK1 is “0”. During '(Low Level), the second slave-side SPI upstream data signal MISO 2 is output from the selector 321. As a result, both the first and second slave-side SPI upstream data signals MISO1 and MISO2 are alternately multiplexed bit by bit, and serial communication (SPI) upstream data to be transmitted to the SPI master circuit 11 is generated. . Thereafter, as shown in the timing chart of FIG. 4, the rising timing of the master side data signal MISO is output to the SPI master circuit 11 in accordance with the rising timing of the master side clock signal SCK.

  The master-side SPI upstream data signal MOSI output from the SPI master circuit 11 is the SPI downstream data of the SPI demultiplexing / conversion circuit 3 at the rising timing of the master-side clock signal SCK, as shown in the timing chart of FIG. It is output to the multiplexing circuit 33. Here, in the SPI downlink data multiplexing circuit 33, as described in FIG. 3, the data signal input to the D flip-flop 331 and shifted to the falling timing of the master side clock signal SCK, and the master side The data is separated into two data signals: a data signal through which the SPI upstream data signal MOSI is passed as it is.

  Then, the data signal shifted up to the falling timing of the master side clock signal SCK in the SPI down data multiplexing circuit 33 is the SPI slave down data signal MOSI1 as shown in the timing chart of FIG. It is output to the slave circuit 21. On the other hand, the data signal passed as it is in the SPI downlink data multiplexing circuit 33 is output to the SPI slave circuit 22 as the second slave-side downlink data signal MOSI2, as shown in the timing chart of FIG.

  The master-side SPI enable signal SS passes through the SPI enable buffer circuit 34 of the SPI demultiplexing / converting circuit 3 as described above with reference to FIG. 3, and the first and second slave SPI enable signals SS1, As SS2, it is output to the SPI slave circuits 21 and 22, respectively.

  Next, the serial communication data (SPI data) signal conversion operation in the information processing apparatus provided with the SPI demultiplexing / conversion circuit 3 as shown in FIGS. 2 and 3 will be described in more detail with reference to the explanatory diagram of FIG. explain. FIG. 5 is an explanatory diagram for explaining an example of the conversion operation of serial communication data (SPI data) in the information processing apparatus provided with the SPI demultiplexing / conversion circuit 3 shown in FIG. A data conversion example in which MOSI is separated into first and second slave-side SPI downlink data signals MOSI1 and MOSI2, respectively, and first and second slave-side SPI uplink data signals MISO1 and MISO2 are multiplexed to obtain master-side uplink data. An example of data conversion to be converted into the signal MISO is shown.

  In the explanatory diagram shown in FIG. 5, the data length of the serial communication (SPI) data signal transmitted and received on the SPI master circuit 11 side is from the 15th bit (B15) on the MSB (Most Significant Bit) side to the LSB (Least Significant). 16 bits up to the 0th bit (B0) on the (Bit) side, while the data length of the serial communication (SPI) data signal transmitted and received on the SPI slave circuits 21 and 22 side is both transmitted and received on the SPI master circuit 11 side. An example of data in the case of 8 bits from the 7th bit (B7) on the MSB side to the 0th bit (B0) on the LSB side is shown. ing. Here, as illustrated in FIG. 5, the master-side SPI downlink data signal MOSI to be separated and converted is 16 bits of '2C48h' in hexadecimal notation, and the first and second to be multiplexed and converted. The case where the two slave-side SPI upstream data signals MISO1 and MISO2 are 8 bits each of '55h' and '55h' in hexadecimal notation is described.

  First, with respect to 16-bit data of “2C48h” of the master-side SPI downlink data signal MOSI to be separated and converted, as described in FIGS. 3 and 4, the SPI demultiplexing conversion is performed at the rising timing of the master-side clock signal SCK. It is output to the circuit 3. Thereafter, in the SPI downlink data shift circuit 33 of the SPI demultiplexing / converting circuit 3, the first slave side SPI downlink data signal MOSI1 of the data signal shifted to the falling timing of the master side clock signal SCK is passed as it is. The data signal is separated into the second slave side SPI downstream data signal MOSI2 and output to the SPI slave circuit 21 and the SPI slave circuit 22, respectively.

  In the SPI slave circuit 21 that operates to receive at the falling timing of the first slave side clock signal SCK1 divided by (1/2) of the master side clock signal SCK, the first slave side SPI down data signal MOSI1 As a result, the data signal obtained by shifting the 16-bit data of “2C48h” of the master side SPI down data signal MOSI until the falling timing of the master side clock signal SCK is received.

  Therefore, as shown in the timing chart of FIG. 4, among the 16-bit data of “2C48h” of the master side SPI downlink data signal MOSI, the 14th bit (B14) “0”, the 12th bit (B12 ) '0', 10th bit (B10) '1', ... 2nd bit (B2) '0', 0th bit (B0) '0' As a result, as shown in the “MOSI1 (slave-side SPI downlink data 1)” column of FIG. 5, the SPI slave circuit 21 sets the '00101000b from the seventh bit (B7) to the zeroth bit (B0). “In other words, 8-bit data“ 28h ”is received in hexadecimal notation.

  On the other hand, the falling timing of the second slave side clock signal SCK2 divided by (1/2) of the master side clock signal SCK and phase-shifted by (1/2) period from the master side clock signal SCK. In the SPI slave circuit 22 that performs the receiving operation at, the 16-bit data “2C48h” of the master-side SPI downlink data signal MOSI is received as it is as the second slave-side SPI downlink data signal MOSI2.

  Therefore, as shown in the timing chart of FIG. 4, the 15th bit (B15) '0' and the 13th bit (B13) of the 16-bit data of '2C48h' of the master-side SPI downlink data signal MOSI ) “1”, the eleventh bit (B11) “1”,..., The third bit (B3) “1”, the first bit (B1) “0”, and the SPI slave circuit 21 side. Are received by skipping one bit at different bit positions. As a result, the SPI slave circuit 22 receives the seventh bit (B7) to (B7)-as shown in the “MOSI2 (slave-side SPI downlink data 2)” column of FIG. Up to the 0th bit (B0), '01100010b', that is, 8-bit data of '62h' in hexadecimal notation is received.

  Thereafter, in the option control unit 2 equipped with the SPI slave circuits 21 and 22, the 8-bit data “28h” received by the SPI slave circuit 21 and the 8-bit “62h” received by the SPI slave circuit 22 are displayed. The original data is restored to the original “2C48h” 16-bit data output by the SPI master circuit 11 by performing recombination alternately in bit units.

  Next, “55h” of the first slave-side SPI upstream data signal MISO1 and “55h” of the second slave-side SPI upstream data signal MISO2 to be multiplexed and converted have been described with reference to FIGS. In this manner, the first and second slave clock signals SCK1 and SCK2 are output to the SPI demultiplexing / conversion circuit 3 at the rising timing, respectively. Thereafter, in the SPI uplink data multiplexing circuit 32 of the SPI demultiplexing / multiplexing circuit 3, the first slave side clock signal SCK1, which is the clock signal of the SPI slave circuit 211, is set to “1” (High Level), “0” ( Multiplexing is performed by selecting one of the first and second slave-side SPI upstream data signals MISO1 and MISO2 alternately in bit units by a selector 321 that performs a selection operation according to (Low Level). . That is, while the first slave side clock signal SCK1 is “1” (High Level), the first slave side SPI upstream data signal MISO1 is selected, and the first slave side clock signal SCK1 is “0” (Low Level). ), The second slave side SPI upstream data signal MISO2 is selected and output to the SPI master circuit 11 as the master side upstream data signal MISO. The SPI master circuit 11 receives the master-side SPI upstream data signal MISO at the falling timing of the master-side clock signal SCK.

  Therefore, for example, when the SPI master circuit 11 is to receive data of “3333h” in hexadecimal notation as the master-side SPI upstream data signal MISO, by performing a separation operation in bit units, From each of the SPI slave circuits 21 and 22, '55h' data is displayed in hexadecimal notation as the first slave side SPI upstream data signal MISO1, and similarly hexadecimal notation is displayed as the second slave side SPI upstream data signal MISO2. Therefore, it is sufficient to output the data of '55h. That is, 8-bit data of '55h' of the first slave side SPI upstream data signal MISO1 and '55h' of the second slave side SPI upstream data signal MISO2 is output from the SPI slave circuit 211 and the SPI slave circuit 221 respectively. Just do it.

  When each of the 8-bit data is received, the SPI demultiplexing / conversion circuit 3 receives the first SPI uplink data signal MISO output from the SPI uplink data multiplexing circuit 32 as shown in the timing chart of FIG. Of the slave side SPI upstream data signal MOSI1 of the seventh bit (B7) of “55h”, “1” of the sixth bit (B6), “0” of the fifth bit (B5),... '0' of the first bit (B1), '1' of the 0th bit (B0), and '0' of the seventh bit (B7) of the '55h' of the second slave side SPI upstream data signal MOSI2. ', 6th bit (B6)' 1 ', 5th bit (B5)' 0 ', ... 1st bit (B1)' 0 ', 0th bit (B0)' 1 ' To the SPI master circuit 11 alternately for each bit. To and output.

  As a result, as shown in the “MISO (master-side SPI upstream data)” column of FIG. 5, the SPI master circuit 11 performs '0011001100110011b', that is, 16th bit (B15) to 0th bit (B0). The 16-bit data “3333h” is received in the decimal notation.

  By performing the operation as described in detail above, the SPI communication between the high-speed SPI master circuit 11 of the main control unit 1 and the low-speed SPI slave circuits 21 and 22 of the option control unit 2 is performed. It becomes possible to carry out at a communication speed matched to the master circuit 11.

  In the present embodiment, the case where the communication speed of the SPI master circuit 11 is twice the communication speed of the SPI slave circuits 21 and 22 has been described. However, the present invention is not limited to this case. Absent. That is, for example, the communication speed of the high-speed serial communication device, that is, the SPI master circuit is n times (n: a positive integer of 2 or more) the communication speed of the low-speed serial communication device on the option control unit 2 side, that is, the SPI slave circuit. In this case, n low-speed serial communication devices, that is, SPI slave circuits are mounted on the option control unit 2 side, and the SPI demultiplexing / converting circuit 3 separates and converts the SPI downlink data into n data. As for the uplink data, it may be configured to multiplex and convert n data into one data.

  In this embodiment, the information processing apparatus including one main control unit and one option control unit 2 has been described as an example. However, one main control unit and one or more options are provided. Even if it is configured with a control unit or between any control units, it is configured with a control unit equipped with a master / slave type clock synchronous SPI circuit (that is, SPI bus system). As long as this is the case, this embodiment can be applied in exactly the same manner.

(Explanation of effect of embodiment)
As described in detail above, according to the present embodiment, the following effects can be obtained. That is, in an information processing apparatus having an SPI (Serial Peripheral Interface) bus type bus system which is one of the master / slave type synchronous serial communication bus systems, a high-speed SPI master circuit 11 and a low-speed SPI slave are provided. When communicating between the internal peripheral circuits of two control units (CPUs) having different communication speeds such as the circuits 21 and 22 by the SPI circuit / synchronous serial communication, with the normal communication method, In some cases, the communication speed is limited to the low speed side where the communication speed is low, and it is impossible to achieve the performance as designed.

  On the other hand, as in this embodiment, the internal peripheral circuits of two control units (CPUs) having different communication speeds are bus-connected via the SPI demultiplexing / converting circuit 3, and the communication speed is low. On the control unit side, n low-speed serial communication devices, that is, SPI slave circuits (that is, the number corresponding to the speed ratio n: 1 with respect to the communication speed of the high-speed side control unit) are mounted to separate / multiplex serial communication data. By adopting a conversion mechanism, serial communication can be realized at a higher communication speed, and the system operation performance of the entire information processing apparatus can be greatly improved.

  Also, since the SPI demultiplexing / converting circuit 3 can be realized with a simple circuit configuration, it can be realized easily and inexpensively using a logic integrated circuit (LOGIC IC) or CPLD (Complex Programmable Logic Device). can do.

  The configuration of the preferred embodiment of the present invention has been described above. However, it should be noted that such embodiments are merely examples of the present invention and do not limit the present invention in any way. Those skilled in the art will readily understand that various modifications and changes can be made according to a specific application without departing from the gist of the present invention.

1 Main control unit (main CPU)
2 Optional control unit (sub CPU)
3 SPI demultiplexing / converting circuit 31 SPI clock frequency dividing circuit 32 SPI upstream data multiplexing circuit 33 SPI downstream data shift circuit 34 SPI enable buffer circuit 11 SPI master circuit 21 SPI slave circuit 22 SPI slave circuit 311 D flip-flop 312 D flip-flop 321 Selector 331 D flip-flop

Claims (9)

  Using an SPI (Serial Peripheral Interface) bus type bus system, which is one of the master / slave type synchronous serial communication bus systems, a high-speed SPI master circuit mounted on the main control unit and one or more In an information processing apparatus configured by mutually connecting low-speed SPI slave circuits mounted on an option control unit, the communication speed of the SPI master circuit is n times that of the SPI slave circuit (n: 2 is a positive integer greater than or equal to 2), the SPI slave is connected to the option control unit according to the speed ratio n: 1 between the SPI master circuit on the high speed side and the SPI slave circuit on the low speed side. N circuits are mounted, and the connection between the SPI master circuit and each of the n SPI slave circuits is the S The serial communication data from the I master circuit is separated and converted into n pieces of data, and the serial communication data from each of the n pieces of SPI slave circuits is multiplexed and converted into one piece of data via an SPI separation and multiplexing conversion circuit. An information processing apparatus that is connected.   The SPI demultiplexing / converting circuit performs conversion for separating the serial communication data in the downstream direction from the SPI master circuit to each of the n SPI slave circuits into n data, so that the n SPI slave circuits are converted. At the communication speed corresponding to each circuit, the data is distributed to each of the SPI slave circuits. On the other hand, for the serial communication data in the upward direction from each of the n SPI slave circuits to the SPI master circuit, the n SPI slave circuits are transmitted. 2. The information according to claim 1, wherein conversion is performed to multiplex serial communication data from each circuit into one data, and the data is distributed to the SPI master circuit at a communication speed corresponding to the SPI master circuit. Processing equipment.   The SPI demultiplexing / multiplexing circuit divides the master side clock signal of the high speed side SPI master circuit into (1 / n) clock signals according to the speed ratio n: 1 with respect to the low speed side SPI slave circuit. An SPI clock frequency dividing circuit that generates a slave side clock signal to be supplied to each of the n SPI slave circuits by adjusting the phase of the clock signal that has been divided and divided by (1 / n); The serial communication uplink data transmitted from each of the SPI slave circuits in synchronization with each of the slave side clock signals is multiplexed into one data, and the SPI communication is performed at a speed matching the communication speed of the SPI master circuit. An SPI uplink data multiplexing circuit to be supplied to the master circuit, and transmitted from the SPI master circuit in synchronization with the master side clock signal. An SPI downlink data separation circuit that separates serial communication downlink data into n pieces of data and supplies the data to each of the n SPI slave circuits at a speed that matches the communication speed of each of the n pieces of SPI slave circuits; The information processing apparatus according to claim 2, further comprising: an SPI enable buffer circuit that supplies an enable signal of the SPI master circuit to each of the n SPI slave circuits serving as communication partners.   When the speed ratio n = 2 between the SPI master circuit on the high speed side and the SPI slave circuit on the low speed side, the SPI clock frequency dividing circuit of the SPI demultiplexing and converting circuit is the master side of the SPI master circuit. A clock signal obtained by dividing the clock signal by (1/2) is generated as a first slave-side clock signal, and the first slave-side clock signal is generated as a (1/2) cycle of the master-side clock signal. The phase-shifted clock signal is generated as a second slave side clock signal and supplied as the slave side clock signal of each of the two SPI slave circuits, and the SPI master circuit is connected to the master side. Serial communication downlink data is output at the timing synchronized with the rising edge of the clock signal, and each of the two SPI slave circuits. At a timing synchronized with the rising edge of each of said slave clock signal, the information processing apparatus according to claim 3, characterized in that outputs serial communication uplink data.   The SPI uplink data multiplexing circuit of the SPI demultiplexing / converting circuit has two serial communication uplinks transmitted from each of the two SPI slave circuits at a timing synchronized with the rise of each slave side clock signal. One of the data is selected by switching between two slave clock signals according to the first slave clock signal '1' (High Level) and '0' (Low Level). 5. The information according to claim 4, wherein the information is multiplexed to generate one serial communication data, and the data is supplied to the SPI master circuit at a speed matching the communication speed of the SPI master circuit. Processing equipment. The SPI downlink data separating circuit of the SPI demultiplexing / converting circuit is configured such that the serial communication downlink data output from the SPI master circuit is shifted in phase by (1/2) period of the master side clock signal. generated as the first slave serial communication downlink data, and output to the first slave clock signal S PI slave device that is providing, and serial communication downstream of the output from the SPI master circuit The data that has passed the data as it is is output as second slave side serial communication downlink data to the SPI slave device that is supplying the second slave side clock signal, and the two SPI units Each slave circuit transmits the transmitted first slave-side serial communication downlink data and the second thread. 6. The slave-side serial communication downlink data is received at a timing synchronized with a fall of each of the first slave-side clock signal and the second slave-side clock signal. Information processing device.   7. The information processing according to claim 1, wherein the SPI demultiplexing / converting circuit is configured by a logic integrated circuit (LOGIC IC) or a CPLD (Complex Programmable Logic Device). apparatus.   Using an SPI (Serial Peripheral Interface) bus type bus system, which is one of the master / slave type synchronous serial communication bus systems, a high-speed SPI master circuit mounted on the main control unit and one or more Separation of serial communication data transferred between the SPI master circuit and the SPI slave circuit in an information processing apparatus configured by mutually connecting the low-speed SPI slave circuits mounted on the option control unit A serial communication data demultiplexing / multiplexing method for multiplexing, wherein the communication speed of the SPI master circuit is n times (n: a positive integer of 2 or more) as compared with the SPI slave circuit. Depending on the speed ratio n: 1 between the SPI master circuit on the high speed side and the SPI slave circuit on the low speed side, the optical N SPI slave circuits are mounted on the control unit side, and the serial communication data from the SPI master circuit is separated and converted into n data, and each of the separated data is converted into the SPI data. Supplying to each of the n SPI slave circuits at a communication speed corresponding to each of the slave circuits, and multiplexing and converting serial communication data from each of the n SPI slave circuits into one data, and A serial communication data demultiplexing / multiplexing method, characterized in that it is supplied to the SPI master circuit at a communication speed corresponding to the master circuit.   The master-side clock signal of the high-speed SPI master circuit is divided into (1 / n) clock signals according to the speed ratio n: 1 with the low-speed SPI slave circuit, and (1 / The clock signal divided into n) is phase-adjusted to generate a slave clock signal to be supplied to each of the n SPI slave circuits, and an SPI clock frequency dividing step, and each of the n SPI slave circuits. SPI uplink data multiplexing that is multiplexed with serial communication uplink data transmitted in synchronization with the slave side clock signal and supplied to the SPI master circuit at a speed that matches the communication speed of the SPI master circuit. And n serial communication downlink data transmitted from the SPI master circuit in synchronization with the master side clock signal. An SPI downlink data separation step for supplying data to each of the n SPI slave circuits at a speed that matches the communication speed of each of the n SPI slave circuits, and an enable signal for the SPI master circuit, 9. The serial communication data demultiplexing / conversion method according to claim 8, further comprising: an SPI enable buffering step for supplying each of the n SPI slave circuits serving as communication partners.

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