JP6092696B2 - Memory cell using variable resistance element - Google Patents

Description

  The present invention relates to a first cell, a second electrode, and a memory cell including a nonvolatile variable resistance element configured by sandwiching a metal oxide film between the two electrodes as a variable resistor and a selection transistor.

  In recent years, various devices such as FeRAM (Ferroelectric RAM), MRAM (Magnetic RAM), PRAM (Phase Change RAM), etc. as next-generation non-volatile random access memory (NVRAM) capable of high-speed operation instead of flash memory. A structure has been proposed, and intense development competition has been conducted from the viewpoint of high performance, high reliability, low cost, and process consistency.

  For these existing technologies, a resistive non-volatile memory RRAM (Resistive Random Access Memory: registered trademark) using a variable resistive element whose electric resistance reversibly changes by applying a voltage pulse has been proposed. An example of this configuration is shown in FIG.

  As shown in FIG. 10, the variable resistance element 10 having a conventional configuration has a structure in which a lower electrode 103, a variable resistor 102, and an upper electrode 101 are sequentially stacked, and between the upper electrode 101 and the lower electrode 103. By applying a voltage pulse, the resistance value can be reversibly changed. A novel nonvolatile memory device can be realized by reading a resistance value that changes by this reversible resistance change operation (hereinafter referred to as “switching operation”).

  The nonvolatile memory device forms a memory cell array by arranging a plurality of memory cells including variable resistance elements in a matrix in the row direction and the column direction, and writes and erases data to and from each memory cell of the memory cell array And a peripheral circuit for controlling the read operation. As this memory cell, one memory cell is composed of one select transistor T and one variable resistance element R (referred to as “1T1R type”) because of the difference in the components. There is a memory cell or the like composed of only one variable resistance element R (referred to as “1R type”). Among these, FIG. 11 shows a configuration example of a 1T1R type memory cell.

  FIG. 11 is an equivalent circuit diagram showing a configuration example of the memory cell array 200 using 1T1R type memory cells. The gate of the selection transistor T of each memory cell is connected to the word lines (WL1 to WLn), and the source of the selection transistor T of each memory cell is connected to the source lines (SL1 to SLn) (n is a natural number). . One electrode of the variable resistance element R for each memory cell is connected to the drain of the selection transistor T, and the other electrode of the variable resistance element R is connected to the bit lines (BL1 to BLm) (m Is a natural number). The word lines WL1 to WLn are connected to the word line decoder 201, the source lines SL1 to SLn are connected to the source line decoder 203, and the bit lines BL1 to BLm are connected to the bit line decoder 202, respectively. Yes. A specific bit line, word line, and source line for write, erase, and read operations to a specific memory cell in the memory cell array 200 are selected according to an address input (not shown).

  As described above, the selection transistor T and the variable resistance element R are arranged in series, so that the transistor of the memory cell selected by the change in the potential of the word line is turned on, and the memory selected by the change in the potential of the bit line. The cell can be selectively written or erased only to the variable resistance element R of the cell.

  FIG. 12 is an equivalent circuit diagram showing a configuration example of the memory cell array 204 using 1R type memory cells. Each memory cell includes only the variable resistance element R, and one electrode of the variable resistance element R is connected to the word lines (WL1 to WLn) and the other electrode is connected to the bit lines (BL1 to BLm). Each word line WL1 to WLn is connected to the word line decoder 205, and each bit line BL1 to BLm is connected to the bit line decoder 206. Then, in accordance with an address input (not shown), specific bit lines and word lines for writing, erasing and reading operations to specific memory cells in the memory cell array 204 are selected.

The 1R type memory cell shown in FIG. 12 has an advantage that the memory cell size can be reduced to 4F ² when the minimum processing dimension is F, but it has a disadvantage that a current flows also to an unselected cell.

  On the other hand, the 1T1R type memory cell shown in FIG. 11 has the advantage of allowing current to flow only through the selected cell, but has the disadvantage of generally increasing the memory cell size.

As a method for enabling high integration even for a 1T1R type memory cell, Patent Document 1 discloses a method using a vertical MOS transistor. In Patent Document 1, a DRAM or a phase change memory is used as a storage element. In this case, assuming that the minimum processing dimension is F, a memory cell size of 4F ² is theoretically possible.

In the above variable resistance element R, as a variable resistance material used as a variable resistor, by applying a voltage pulse to a perovskite material known for a super-giant magnetoresistance effect by, for example, Shangquing Liu of the University of Houston of USA or Alex Ignatiev Methods for reversibly changing the electrical resistance are disclosed in Patent Literature 2 and Non-Patent Literature 1 below. Although this method uses a perovskite material known for its giant magnetoresistance effect, a resistance change of several orders of magnitude appears even at room temperature without applying a magnetic field. In the element structure exemplified in Patent Document 2, a praseodymium / calcium / manganese oxide Pr _1-x Ca _x MnO ₃ (PCMO) film, which is a perovskite oxide, is used as a variable resistor material.

Other variable resistor materials include oxides of transition metal elements such as titanium oxide (TiO ₂ ) films, nickel oxide (NiO) films, zinc oxide (ZnO) films, and niobium oxide (Nb ₂ O ₅ ) films. It is known from Non-Patent Document 2 and Non-Patent Document 3 that it exhibits reversible resistance change.

JP 2008-311641 A US Pat. No. 6,204,139

Liu, S.Q. et al., "Electric-pulse-induced reversible Resistance change effect in magnetoresistive films", Appl. Phys. Lett., Vol. 76, pp. 2749-2751, 2000 Baek, I.G., et al., “Highly Scalable Non-volatile Resistive Memory using Simple Binary Oxide Driven by Asymmetric Unipolar Voltage Pulses” IEDM2004, pp. 587-590, 2004 H. Pagnia et al., "Bistable Switching in Electroformed Metal-Insulator-Metal Devices" Phys. Stat. Sol. (A), Vol.108, pp.11-65, 1988

  In a variable resistance element using a transition metal oxide as a variable resistor as shown in Non-Patent Document 2, it is necessary to perform a soft breakdown process called so-called forming in order to make resistance switching possible. As a result of such soft breakdown, a conductive path (hereinafter referred to as “filament path” as appropriate) is generated due to oxygen defects formed in a filament shape in the metal oxide, and a resistance change occurs due to opening and closing of the filament path. It is said that.

  Therefore, it is considered that how the filament path is formed greatly affects the subsequent resistance switching characteristics.

  Here, even when the variable resistance element is used as a memory element, if Patent Document 1 is applied, it is considered that a highly integrated memory array is possible by using a memory cell having a vertical MOS transistor as a selection element. It is done.

  However, it has been clarified that the variable resistance element generally tends to cause a write failure in a low resistance operation (set write) when the write current is reduced. As a solution to this problem, first, it is desired to develop an element that stably operates even with a small write current. Alternatively, it is necessary to perform a stable write operation even when a large amount of current is passed.

  However, when the latter method is adopted and an attempt is made to flow a large amount of current, the current driving capability of the selection transistor must be increased. In general, in order to increase the current drive capability of a transistor while maintaining a desired breakdown voltage performance or the like, it is necessary to increase the channel width. Increasing the channel width increases the area occupied by the transistor, which hinders high integration.

  This situation is the same when the vertical MOS transistor shown in Patent Document 1 is adopted as the selection transistor, and the occupied area of the transistor becomes a bottleneck, and it is difficult to miniaturize it beyond a certain level.

  Furthermore, it is assumed that a memory cell using a vertical MOS transistor as a selection element is manufactured in a minute processing dimension region, and naturally the dimension of the variable resistance element is also minute. If the element becomes finer, it is necessary to configure the memory cell in such a manner that the characteristics of the formed filament path can be controlled in consideration of damage to the end face of the element due to processing.

  In view of the above-described problems, the present invention provides a memory cell structure capable of achieving both a large write current and high integration in a 1T1R type memory cell in which a selection transistor is connected in series to a variable resistance element. The first purpose.

  Furthermore, a second object of the present invention is to provide a memory cell composed of a select transistor and a variable resistance element, which can control the formation of a filament path even with a fine element size.

In order to achieve the above object, a memory cell according to the present invention includes a metal oxide film sandwiched between a first electrode and a second electrode, and the both electrodes are applied in response to an electrical stress applied between the electrodes. A variable resistance element in which a resistance state defined by an electrical resistance between the electrodes changes reversibly; and a selection transistor for cell selection, wherein the second electrode of the variable resistance element and a drain region of the selection transistor are connected to each other. Memory cells,
The selection transistor is a vertical transistor;
The vertical transistor is
A source layer, a drain layer, and a bulk portion sandwiched between the source layer and the drain layer have a structure in which the substrate is stacked in a direction perpendicular to the substrate;
The source layer, the drain layer, and the bulk portion are made of n-type silicon, and the dopant concentration of the bulk portion is in the range of 1 × 10 ^{17 to} 5 × 10 ¹⁸ cm ⁻³ ,
The gate electrode is disposed on the insulating film covering the side wall surface of the bulk part so as to sandwich the bulk part,
A first feature is that the bulk portion is completely depleted in a state where no voltage is applied between the gate electrode and the source layer and the drain layer.

The memory cell according to the first aspect of the present invention further includes:
The dielectric constant of the bulk part is εs, the dopant concentration is Nd, the capacitance per unit area of the insulating film is Ci, and the energy between the Fermi level and the vacuum level of the bulk part from the work function of the gate electrode When the difference is φms, the elementary charge is q, and the dimension of the bulk part in the direction in which the gate electrode faces is R,


Satisfying the above relationship is a second feature.

The memory cell according to the first or second feature of the present invention further includes:
The gate electrode is preferably disposed on the insulating film covering the side wall surface of the bulk portion so as to cover the entire side wall surface of the bulk portion.

The memory cell according to the first or second feature of the present invention further includes:
In the variable resistance element, it is preferable that the first electrode, the metal oxide film, and the second electrode are stacked in a direction perpendicular to the substrate.

The memory cell according to the first or second feature of the present invention further includes:
The center of the bulk part is disposed so as to be inside the formation region of the metal oxide film when viewed from the direction perpendicular to the substrate,
A line width in at least one specific direction parallel to the substrate of the metal oxide film may be equal to or less than a line width in the specific direction of the bulk portion.

  In the memory cell according to the first or second feature of the present invention, the line width in the first direction of the metal oxide film and the line width in the first direction of the bulk part are both 50 nm. The following is preferable.

The memory cell according to the first or second feature of the present invention further includes:
The second electrode is in contact with the drain layer;
It is preferable that a ratio of a height of the drain layer and the second electrode combined with a line width of the second electrode in one cross-sectional direction parallel to the substrate is 0.9 or less.

The memory cell according to the first or second feature of the present invention further includes:
The variable resistance element is subjected to a forming process to change the resistance state between the electrodes from the initial high resistance state before the forming process to a variable resistance state.
In the variable resistance state, by applying the electrical stress between the electrodes, the resistance state transitions between two or more different states, and one resistance state after the transition is used for storing information. Is preferred.

According to the present invention, a memory cell capable of achieving both a large write current and high integration can be realized by configuring the selection transistor with a vertical accumulation type transistor (storage type transistor). Furthermore, by appropriately setting the dopant concentration (carrier concentration) in the bulk portion of such a transistor, a large current driving capability necessary for writing can be maintained and a normally-off operation can be performed, so that a memory cell array is configured. In this case, high integration is possible, and a 4F ² memory cell configuration is facilitated with a minimum processing dimension of F.

  Further, since the current flows through the center of the bulk portion in the direction perpendicular to the substrate, the center of the bulk portion is located inside the formation region of the metal oxide film that is a variable resistor when viewed from the direction perpendicular to the substrate. By disposing the filament path, the filament path is mainly formed in a region inside the metal oxide film in which a portion where the current of the bulk portion flows is extended in a direction perpendicular to the substrate. In other words, the characteristics of the filament path to be formed can be controlled without being affected by the damage associated with the processing of the end face of the variable resistor element.

Structural cross-sectional view schematically showing the configuration of a conventional 1T1R type memory cell including a vertical transistor Structural cross-sectional view schematically showing the configuration of a conventional 1T1R type memory cell including a vertical transistor 1 is a structural cross-sectional view schematically showing a configuration of a 1T1R type memory cell according to an embodiment of the present invention. Band diagram showing the electronic state change of the bulk part due to the voltage application of the gate electrode, for explaining the operation of the Accumulation type vertical transistor Energy band diagram in thermal equilibrium when metal-insulating film-n-type semiconductor is contacted Graph showing the relationship between the diameter R of the n-type layer necessary for complete depletion and its dopant concentration (carrier concentration) Nd in an Accumulation type vertical transistor Graph showing the relationship between the diameter R of the n-type layer and the bulk resistance in the flat band state in an Accumulation type vertical transistor Diagram showing the radial current near the micro-contact that simulates the contact between the center of the n-type layer and the n ⁺ layer in an Accumulation-type vertical transistor The figure which shows the distribution of the current density in the n ⁺ layer / electrode interface of the electric current which flows into the micro contact from an electrode Structural sectional view schematically showing an example of a conventional variable resistance element 1 is a circuit diagram illustrating a configuration example of a memory cell array including 1T1R type memory cells. 1 is a circuit diagram illustrating a configuration example of a memory cell array including 1R type memory cells.

<First Embodiment>
Hereinafter, an embodiment of a memory cell according to the present invention will be described with reference to the drawings while comparing with a memory cell having a conventional configuration.

  First, a conventional memory cell will be described with reference to FIGS. 1 and 2 are diagrams schematically showing a cross-sectional structure of a conventional 1T1R type memory cell in which a vertical transistor and a variable resistance element are connected in series.

<< Conventional configuration using Inversion type MOS transistor >>
In general, transistors used as switches are of the Inversion type.
The Inversion type transistor has a structure in which the conductivity types of the source / drain and the channel portion are different. For example, the source / drain is n-type and the region for forming the channel is p-type. When an on voltage is applied to the gate, electrons are induced at the interface between the gate insulating film and the p-type channel layer, and the source / drain is made conductive.

FIG. 1 shows an example of a structure in which an Inversion type vertical MOSFET and a variable resistance element are stacked. The second electrode 103 of the variable resistance element 10 in which the metal oxide film 102 as a variable resistor is sandwiched between the first electrode 101 and the second electrode 103 is n ^{+ of the} vertical MOSFET 11 provided in the lower layer. A memory cell is formed by being electrically connected to the layer 104 (drain layer). The vertical MOSFET 11 includes an n ⁺ layer 104 (drain layer), an n ⁺ layer 105 (source layer), a p-type layer 106 in which a channel is formed, and a gate electrode 107 that controls the channel. The gate electrode 107 is formed on the insulating film 108 covering the side wall surface of the p-type layer 106 so as to surround the entire side wall surface of the p-type layer 106. The first electrode 101 is connected to the bit line 110 extending in the horizontal direction (first direction) on the paper surface, and the bit line 110 connects memory cells adjacent in the first direction. On the other hand, the gate electrode 107 extends in a direction perpendicular to the paper surface (second direction) and becomes a word line 111 extending in the second direction, and connects adjacent memory cells in the second direction. The n ⁺ layer 105 is connected to a common line 109 common to all memory cells. A plurality of memory cells are two-dimensionally connected by the bit line 110 and the word line 111 to constitute a memory cell array. By applying a predetermined ON voltage to the word line 111, turning on the vertical MOSFET 11 and applying a write voltage between the bit line 110 and the common line 109, the resistance state of the variable resistance element 10 is reversibly changed. At this time, a write current flows through the variable resistance element 10.

  The variable resistance element 10 is in an initial high resistance state immediately after manufacture. In the initial high resistance state, the variable resistance element operates as a simple capacitor. By applying a voltage application process called forming, a filament path is formed in the metal oxide film 102 and is defined by the electrical resistance between the first electrode 101 and the second electrode 103 in accordance with the application of electrical stress. The resistance state changes to a variable resistance state capable of reversibly transitioning.

  Incidentally, when the variable resistance element 10 is manufactured, damage due to etching or the like is inevitably caused at the end portion of the element. For this reason, the damaged area at the end of the element differs from the intended film quality. In FIG. 1, the damaged region in the metal oxide film 102 is indicated by a region 120 (shown in black). Therefore, it is necessary to prevent the filament path from being formed in the damaged region 120.

  However, in the Inversion type transistor, the channel is generated at or near the interface between the insulating film 108 and the p-type layer 106. Therefore, as shown in FIG. There is a possibility that the filament path 121 is formed in the vicinity. As a result, the resistance switching characteristics are deteriorated.

  As a method for solving this, for example, as shown in FIG. 2, there is a method in which the line width in the direction parallel to the substrate of the variable resistance element 10 is made wider than the line width of the p-type layer 106 of the vertical MOSFET 11. However, since the occupation area of the variable resistance element 10 increases, there is a problem that hinders high integration.

  Furthermore, if the size of the transistor 11 is reduced along with high integration, the current driving capability naturally decreases accordingly. In the Inversion transistor 11, a channel is generated at or near the interface between the insulating film 108 and the p-type layer 106, so that current sufficient to stably write the variable resistance element 10 can be supplied along with the miniaturization. There is a risk of disappearing.

<Configuration using Accumulation type transistors>
In contrast, FIG. 3 shows an example of the configuration of a memory cell according to an embodiment of the present invention using an accumulation type transistor. FIG. 3 is a diagram schematically showing a cross-sectional structure of a 1T1R type memory cell in which an accumulation type vertical MOS transistor 20 and a variable resistance element 10 are connected in series.

Unlike the Inversion type MOS transistor 11 shown in FIGS. 1 and 2, the accumulation type MOS transistor 20 has the same conductivity type in the channel region as the source / drain region. In FIG. 3, the second electrode 103 of the variable resistance element 10 in which the metal oxide film 102 as a variable resistor is sandwiched between the first electrode 101 and the second electrode 103 is an n ⁺ layer 104 of the vertical MOSFET. A memory cell is configured in electrical connection with the (drain layer). The variable resistance element is formed by stacking the first electrode 101, the metal oxide film 102, and the second electrode 103 on the n ⁺ layer 104 in a direction perpendicular to the substrate. The configuration of the variable resistance element is the same as in FIG.

On the other hand, the accumulation-type MOS transistor 20 includes an n ⁺ layer 104 (drain layer), an n ⁺ layer 105 (source layer), and an n-type layer 112 (bulk portion) in which a channel is formed stacked in a direction perpendicular to the substrate. A gate electrode 107 is arranged on the insulating film 108 that covers the sidewall surface of the n-type layer 112 so as to surround the entire sidewall surface of the n-type layer 112. Therefore, the gate electrode 107 is disposed on the insulating film 108 so as to face each other with the n-type layer 112 interposed therebetween.

As in the conventional memory cell shown in FIGS. 1 and 2, the first electrode 101 is connected to the bit line 110 extending in the horizontal direction (first direction) on the paper surface, and the bit line 110 extends in the first direction. Adjacent memory cells are connected to each other. On the other hand, the gate electrode 107 extends in a direction perpendicular to the paper surface (second direction) and becomes a word line 111 extending in the second direction, and connects adjacent memory cells in the second direction. The n ⁺ layer 105 is connected to a common line 109 common to all memory cells. A plurality of memory cells are two-dimensionally connected by the bit line 110 and the word line 111 to constitute a memory cell array. By applying a predetermined on-voltage to the word line 111, turning on the vertical MOSFET 20 and applying a write voltage between the bit line 110 and the common line 109, the resistance state of the variable resistive element 10 is reversibly changed. At this time, a write current flows through the variable resistance element 10.

Here, simply connecting the three layers of the n ⁺ layer 104, the n-type layer 112, and the n ⁺ layer 105 is always in a conductive state, but the direction perpendicular to the channel of the n-type layer 112 (that is, The OFF state can be realized by reducing the thickness in the direction parallel to the substrate and completely depleting the n-type layer 112.

The operation of the accumulation-type MOS transistor 20 will be described using a band diagram showing the electronic state of the n-type layer 112 shown in FIG. By using a material having a work function larger than the Fermi level of the isolated n-type layer 112 (bulk portion) as the gate electrode 107, the interface between the gate electrode 107 and the insulating film 108, the insulating film 108 and the n-type layer 112 The band bends at the interface as shown in FIG. As a result, in a state where no voltage is applied between the gate electrode 107 and the n ⁺ layers 104 and 105, the n-type layer 112 is completely depleted and turned off.

At this time, when a positive voltage is applied to the gate electrode 107 with respect to the n ⁺ layer 105 (source layer), the electronic states of the gate electrode 107, the insulating film 108, and the n-type layer 112 are as shown in FIG. As shown in b), the state shifts to a flat band state. At this time, electrons are induced in the n-type layer 112 and a bulk conduction current flows.

  When the voltage applied to the gate electrode 107 is further increased, as shown in FIG. 4C, an electron accumulation layer is induced at the interface between the insulating film 108 and the n-type layer 112, and the conductivity increases. (Accumulation state).

  Therefore, when the voltage applied to the gate electrode 107 is increased from the off state, electrons are first induced in the central portion of the n-type layer 112 and a bulk conduction current starts to flow.

  By utilizing this feature, the problem of forming a filament path when using an Inversion type transistor can be avoided. In the Accumulation type transistor 20, first, a current tends to flow through the central portion of the n-type layer 112, so that the filament path 121 of the variable resistance element part is separated from the damage region 120 at the element end as shown in FIG. 3. It is generated in the element central region. Therefore, since the filament path can be formed at a place where the processing / damage is small and the composition / film quality is as intended, the resistance switching after forming the filament path can be performed without variation and with high reliability.

  That is, the n-type layer 112 (bulk portion) where the channel is formed in the flat band state is arranged so that it is inside the formation region of the metal oxide film 102 when viewed from the direction perpendicular to the substrate. Therefore, the formation of a filament path in the damaged region 120 can be avoided. In this case, as shown in FIG. 2, it is not necessary to make the line width of the variable resistance element portion including the metal oxide film 102 wider than the line width of the n-type layer 112. The line width of the metal oxide film 102 can be made the same as the line width of the n-type layer 112 or narrower than the line width of the n-type layer 112 in a specific direction parallel to the substrate. For this reason, high integration is not hindered.

  Since the n-type layer 112 must be completely depleted when no gate voltage is applied, the width in the direction parallel to the substrate must be set to a predetermined value or less according to the carrier concentration.

  Hereinafter, the conditions for complete depletion will be described. FIG. 5 shows an energy band diagram in a thermal equilibrium state when a metal-insulating film-n-type semiconductor is contacted. Assuming that the voltage induced in the insulating film is Vi and the capacitance per unit area of the insulating film is Ci, the amount of charge Qi per unit area induced in the metal / insulator interface is expressed by the following equation (1). Here, εi is the dielectric constant of the insulating film, and di is the film thickness of the insulating film.

  On the other hand, when the elementary charge is q, the width of the depletion layer is W, the dopant concentration of the n-type semiconductor is Nd, the voltage applied to the depletion layer is Vs, and the dielectric constant of the semiconductor is εs, it is induced in the depletion layer of the n-type semiconductor. The charge amount Qs per unit area is expressed by the following formula 2. Here, the dopant concentration is an electrically active net donor concentration, that is, an electrically active donor concentration minus an electrically active acceptor concentration.

The flat band voltage is V _FB , the metal work function minus the energy difference between the Fermi level Ef and the vacuum level of the n-type semiconductor is φms, and the interface fixed charge per unit area and the interface state When the trap charge density of Qss is Qss, the following equations 3 and 4 are satisfied. Accordingly, the depletion layer width W is given by the following equation 5 from the equations 1 to 4.

The reason why Qss / Ci is ignored in Equation 4 is that, in a transistor of several tens of nm generation, since the SiO ₂ equivalent film thickness of the insulating film is 1 nm to several nm, Ci is 1 to several μF / cm. ^This is because Qss is controlled to about q × 10 ¹¹ / cm ² in a product level transistor, so that Qss / Ci is about 10 to 50 mV, and φms is dominant.

  The width of the depletion layer obtained in Equation 5 is that when an n-type semiconductor and a metal are joined via an insulating film at one interface, but in the case of a vertical MOSFET, the columnar n-type layer 112 is opposite to It is sandwiched between the gate electrodes 107 arranged to do so. In this case, in order for the n-type layer 112 to be completely depleted in a thermal equilibrium state (when no gate voltage is applied), a depletion layer is formed at both portions of the opposing gate electrode. However, it is sufficient that the dimension in the opposite direction is not more than twice the depletion layer width R derived in Equation 5. In particular, when the entire sidewall surface of the n-type layer 112 is covered with the gate electrode 107 through the insulating film 108, a depletion layer is formed on the entire sidewall surface of the n-type layer 112. Dimension of the short side (approximately rectangular or approximately square) of the cross section of the n-type layer 112 as viewed from the channel direction (direction perpendicular to the substrate) of the n-type MOSFET or dimension along the minor axis (approximately circular or approximately elliptical) ) Is less than or equal to twice the W expressed by Equation 5, it can be fully depleted with a margin.

6, when n-type layer is columnar, a complete dopant concentration (carrier concentration) of depleted of the n-type layer 112 need diameter R and the n-type layer 112 relationship with Nd, SiO ₂ insulating film 108 It is calculated by changing the equivalent film thickness. Here, it is calculated as φms = 0.5 eV, which is a condition in which the Fermi level of the gate electrode is located approximately at the center of the band gap of silicon. In the case of a highly integrated memory, since the line width in the direction parallel to the substrate of the n-type layer 112 is assumed to be 50 nm or less (preferably about 20 to 50 nm), the dopant concentration (carrier concentration) Nd of the n-type layer 112 is 5 ×. It is preferable to be about 10 ¹⁸ cm ⁻³ or less.

  On the other hand, in order to stably perform writing in the variable resistance element 10, the accumulation type MOS transistor 20 needs to have a driving ability to apply a voltage necessary for writing and to allow a sufficient current to flow. The resistance value of the variable resistance element in the low resistance state is suitably in the range of 10 to 100 kΩ. However, in order to sufficiently supply voltage / current to the element having the resistance in this range, the n-type layer 112 has a flat band state. The resistance value must be equal to or less than the resistance value of the variable resistance element in the low resistance state.

FIG. 7 shows a calculation of the bulk resistance in the flat band state with respect to the diameter R of the n-type layer 112. FIG. 6 shows the results when the thickness of the n-type layer 112 in the channel direction (that is, the direction perpendicular to the substrate) is 50 nm. In the case of a highly integrated memory, since the line width in the direction parallel to the substrate of the n-type layer 112 is assumed to be 50 nm or less (preferably about 20 to 50 nm), the resistance value of the variable resistance element is assumed to be about 50 kΩ. Then, from FIG. 7, it is preferable that the dopant concentration (carrier concentration) Nd of the n-type layer 112 is about 1 × 10 ¹⁷ cm ⁻³ or more.

From the above, by setting the dopant concentration (carrier concentration) Nd of the n-type layer 112 in the range of 1 × 10 ^{17 to} 5 × 10 ¹⁸ cm ⁻³ , the MOS that performs normally-off operation and has excellent current driving capability A transistor can be realized.

Furthermore, in order to utilize the bulk conductivity of the Accumulation-type MOS transistor 20 in the filament path formation includes a n ⁺ layer 104 and n ⁺ layer 104 of the section parallel direction to the height of the substrate in conjunction with the second electrode 103 and the second It is preferable to reduce the aspect ratio (height dimension / lateral dimension) with respect to the line width of each electrode 103. This is because when the aspect ratio is large, the current flowing through the center of the n-type layer 112 spreads in the diameter direction while flowing through the n ⁺ layer 104 and the second electrode 103. The aspect ratio is preferably such that the ratio of the height of the combined n ⁺ layer 104 and the second electrode 103 to the line width in at least one cross-sectional direction parallel to the substrate of the second electrode 103 is 0.9 or less. Good.

In FIG. 8, current flows from the second electrode 103 and the n ⁺ layer 104 to the center of the n-type layer 112 (electrons flow from the center of the n-type layer 112 to the n ⁺ layer 104 and the second electrode 103. )) Schematically. At the contact portion between the central portion of the n-type layer 112 and the n ⁺ layer 104, current flows radially toward the n-type layer 112. By understanding what this current flow is, knowledge of how the electrode shape should be constructed can be obtained.

Consider an electric field from such a microcontact toward the n ⁺ layer 104 and the second electrode 103. For simplification, the n ⁺ layer 104 and the second electrode 103 are treated as one electrode, and as shown in FIG. 8, the film thickness is d, and the center of the n-type layer 112 and a minute contact point between the electrode are formed. Assume that the position is at coordinates (0, -d). Consider an ideal situation in which the potentials are equal at the end boundary of the electrode not contacting the n-type layer 112, that is, the XY plane (Z = 0) is an equipotential surface. When such a boundary condition is imposed, the electric field generated in the electrode includes an electric field induced by a point charge −Q arranged at a minute contact (0, −d) between the center of the n-type layer 112 and the electrode, and coordinates (0 , + D) and the electric field induced by the mirror image charge + Q. At the opposite boundary (Z = 0) that does not contact the n-type layer 112 of the electrode, the electric field is only the component EZ in the _Z direction, and the distance from the minute contact is x and is expressed by the following formula (6). However, the −Z direction in FIG. 8 is the positive direction of the electric field. Let ε be the dielectric constant of the electrode.

  Therefore, the current density distribution in the XY plane (Z = 0) is expressed by the following equation 7 where ρ is the resistivity of the electrode.

  FIG. 9 shows the distribution of current density J (r) normalized by assuming the film thickness of the electrode as d, the distance from the minute contact as r, and the current density at r = 0 as 1, indicated by a solid line.

  From Equation 7, the range in which the current density is within 90% of the peak value is r / d ≦ 0.27. If the above range occupies less than half of the line width of the electrode, it can be said that the current flowing through the electrode is localized. In this case, the dimensions of the electrodes may be set so that r / d ≧ 0.27 × 2 = 0.54. At this time, the aspect ratio (height dimension / lateral dimension) of the electrode is in a condition of d / 2r ≦ 0.93. That is, the aspect ratio may be about 0.9 or less.

In addition, as a material of the metal oxide film 102 constituting the variable resistor, each oxide or oxynitride of Al, Hf, Ni, Co, Ta, Zr, W, Ti, Cu, V, Zn, Nb, Alternatively, strontium titanate (SrTiO _x ) or the like can be used. Alternatively, a stacked structure of these may be used. The present invention is particularly applicable to a filament-type variable resistance element in which a filament is formed by a forming process, and is limited by the variable resistor and electrode material constituting the variable resistance element, the size of the element, or the like. is not. Further, the structure of the variable resistance element is not limited to the structure in which the first electrode 101, the metal oxide film 102, and the second electrode 103 illustrated in FIG. 3 are sequentially stacked in the direction perpendicular to the substrate.

  As a material for forming the gate electrode 107, a material having a high work function (about 4.5 eV or more) such as nitride such as titanium nitride or tantalum nitride, Co, Ni, W, Mo, or silicide thereof is preferable. is there. Alternatively, high-concentration p-type doped silicon may be used.

  Further, the second electrode 103 may be configured by stacking a plurality of conductor layers.

  A memory cell array can be configured by arranging memory cells including the above-described accumulation-type MOS transistor 20 in at least one of rows and columns. Then, by connecting peripheral circuits such as a control circuit and a decoder circuit (corresponding to the word line decoder 201, the bit line decoder 202, and the source line decoder 203 in FIG. 11) to the memory cell array, a nonvolatile storage device Is configured. In addition, about a structure of a control circuit and a decoder, since a well-known structure can be utilized, detailed description is omitted.

  Also, with respect to the method of manufacturing the above-described Accumulation type MOS transistor 20, the manufacturing process of the p-type layer 106 may be replaced with the forming process of the n-type layer 112 in the manufacturing of the Inversion type vertical MOSFET 11 of the conventional configuration. Since it can be manufactured by the method, detailed description is omitted.

As described above, according to the present invention, the 1T1R type memory cell structure in which the accumulation type vertical transistor 20 is connected in series to the variable resistance element 10 makes it possible to achieve both large write current and high integration, and the minimum processing dimension. 4F ² memory cell configuration is facilitated by F. Furthermore, even when the element size is fine, the characteristics of the filament path can be controlled without being affected by the damage caused by the processing of the end face of the variable resistor element.

  The present invention can be used for a nonvolatile storage device that stores information using a variable resistance element.

DESCRIPTION OF SYMBOLS 10: Variable resistance element 11: Vertical type selection transistor of conventional structure 20: Vertical type selection transistor which concerns on one Embodiment of this invention 101: 1st electrode (upper electrode)
102: Variable resistor (metal oxide film)
103: Second electrode (lower electrode)
104: n ⁺ layer (drain layer)
105: n ⁺ layer (source layer)
106: p-type layer (channel region)
107: Gate electrode 108: Insulating film 109: Common line 110: Bit line 111: Word line 112: N-type layer (bulk part)
120: Damaged area 121: Filament path 200, 204: Memory cell array 201, 205: Word line decoder 202, 206: Bit line decoder 203: Source line decoder R: Variable resistance element T: Selection transistor BL1 to BLm: Bit line SL1 SLn: Source line WL1 to WLn: Word line

Claims (6)

A metal oxide film is sandwiched between the first electrode and the second electrode, and the resistance state defined by the electrical resistance between the two electrodes is reversibly in response to the application of electrical stress between the two electrodes. A memory cell comprising a variable resistance element that changes and a selection transistor for cell selection, wherein the second electrode of the variable resistance element and a drain region of the selection transistor are connected;
In the variable resistance element, the first electrode, the metal oxide film, and the second electrode are stacked in a direction perpendicular to the substrate,
The selection transistor is a vertical transistor;
The vertical transistor is
Source layer, the drain layer, and the bulk portion sandwiched between the source layer and the drain layer has a laminated structure on the substrate and a vertical direction,
The center of the bulk part is disposed so as to be inside the formation region of the metal oxide film when viewed from the direction perpendicular to the substrate,
A line width in a direction parallel to the substrate of the bulk portion is 50 nm or less;
The source layer, the drain layer, and the bulk portion are made of n-type silicon, and the dopant concentration of the bulk portion is in the range of 1 × 10 ^{17 to} 5 × 10 ¹⁸ cm ⁻³ ,
Gate electrode, an insulating film on covering the sidewall surfaces of the bulk portion, so as to sandwich the bulk portion, is disposed opposite,
The memory cell, wherein the bulk portion is completely depleted in a state where no voltage is applied between the gate electrode and the source layer and the drain layer. The dielectric constant of the bulk part is εs, the dopant concentration is Nd, the capacitance per unit area of the insulating film is Ci, and the energy between the Fermi level and the vacuum level of the bulk part from the work function of the gate electrode When the difference is φms, the elementary charge is q, and the dimension of the bulk part in the direction in which the gate electrode faces is R,


The memory cell according to claim 1, wherein:   3. The memory cell according to claim 1, wherein the gate electrode is disposed on the insulating film covering the side wall surface of the bulk portion so as to cover the entire side wall surface of the bulk portion. Before Symbol metal oxide of at least one direction of the line width in a specific direction parallel to the substrate film, any one of the preceding claims, wherein the or less the specific direction of the line width of the bulk portion The memory cell according to item . The second electrode is in contact with the drain layer;
The ratio for the drain layer and the height together the second electrode, the line width of the second electrode in the cross-sectional direction of one parallel to the substrate, characterized in that it is 0.9 or less, according to claim 1 The memory cell according to any one of to 4 . The variable resistance element is:
By performing the forming process, the resistance state between the two electrodes changes from the initial high resistance state before the forming process to a variable resistance state,
In the variable resistance state, by applying the electrical stress between the electrodes, the resistance state transitions between two or more different states, and one resistance state after the transition is used for storing information. memory cell according to any one of claim 1 to 5, wherein.