JP6464609B2 - Image processing apparatus and program - Google Patents

Description

  The present invention relates to an image processing apparatus and a program.

  In Patent Document 1 below, regarding image processing of a binary image, each pixel value before processing of a pixel of interest and its surrounding pixels is input, and a high-speed processing for determining a pixel value after processing of each pixel of interest by calculation As a means for realizing, a method of performing pixel value calculation processing in parallel is disclosed.

Japanese Patent Laid-Open No. 3-98175

  In an image processing apparatus that determines a pixel value after processing of one pixel of interest with one processing circuit in dilation processing or contraction processing of a binary image, a plurality of pixels of interest for the purpose of speeding up the entire image processing In order to perform processing in parallel, the number of processing circuits corresponding to the number of target pixels to be processed in parallel must be provided, and an increase in the circuit scale of the entire image processing apparatus accompanying improvement in parallel processing performance It was a problem.

  An object of the present invention is to reduce an increase in circuit scale when improving the parallel processing performance of a binary image as compared with a configuration in which the number of processing circuits corresponding to the number of target pixels to be processed in parallel is provided. And

[Image processing device]
According to the first aspect of the present invention, N consecutive pixels (N is an integer of 2 or more) on the same line of the binary image data are set as the target pixels, respectively, and the N target images are obtained from the binary image data. A first pixel column of N + 2 pixels composed of two pixels adjacent on the line with the pixel and the N pixels of interest, and adjacent in the two directions orthogonal to the first pixel column and the line direction, respectively. The pixel values of the second and third pixel columns composed of N + 2 pixels to be overlapped in the line direction so that each pixel value overlaps with the first, second, and third pixel columns extracted two times each. Extraction means for sequentially extracting;
The values of the pixels of the first, second, and third pixel columns extracted by the extraction unit are input, and the processed pixel values of the N target pixels are used as the target pixel and the target pixel. and a determination means for determining, respectively, based on the pixel values of the pre-treatment of pixels around the
The determining means is configured to store each N + 2 bit pixel column data composed of pixel values of the first, second and third pixel columns composed of N + 2 pixels based on a predetermined logic. Conversion means for converting the data into three long intermediate data;
The image processing apparatus includes: a logical operation unit that determines a value of the N target pixels by performing a logical operation between the three intermediate data converted by the conversion unit .

[program]
According to a second aspect of the present invention, N consecutive pixels (N is an integer of 2 or more) on the same line of binary image data are set as pixels of interest, and the N images of interest are extracted from the binary image data. Each pixel value of the first pixel column of N + 2 pixels including two pixels adjacent to the pixel and the N pixel of interest on the line, and the first pixel column and the line direction are orthogonal to each other. The pixel values of the second and third pixel columns, each of which is adjacent to each other in the direction, are overlapped by two pixels with the first, second, and third pixel columns extracted previously. Extracting sequentially in the line direction;
The extracted pixel values of the first, second, and third pixel columns are input, and the processed pixel value of each of the N target pixels is set as the target pixel and pixels around the target pixel. When determining each pixel value based on the pixel values before the processing, each N + 2 bit pixel column data composed of the pixel values of the first, second and third pixel columns composed of N + 2 pixels is preliminarily stored. Converting into three intermediate data each having a length of N bits based on the set logic, and determining the value of the N pixels of interest by performing a logical operation between the converted three intermediate data ;
Is a program for causing a computer to execute.

  According to the first aspect of the present invention, when increasing the number of target pixels that can be processed in parallel for speeding up the image processing of a binary image, the number of image processes corresponding to the number of target pixels processed in parallel Compared to the case where a circuit is provided, an increase in circuit scale can be suppressed.

According the present invention according to claim 2, when increasing the number of the pixel of interest that can be processed in parallel for faster image processing a binary image, the number of image processing in accordance with the number of the target pixel to be processed in parallel Compared to the case where a circuit is provided, an increase in circuit scale can be suppressed.

It is a conceptual diagram which shows the specific example of an opening process. It is a conceptual diagram explaining an expansion process. It is a conceptual diagram explaining a contraction process. 1 is a block diagram of an image processing apparatus 100 according to an embodiment. It is a schematic diagram which shows an input pixel area | region. It is a conceptual diagram which shows the process which extracts the pixel value for 10 pixels from the pixel value for 16 pixels. It is a conceptual diagram which shows the conversion process from 10-bit-length pixel row data to 8-bit length intermediate data. It is a block diagram of the image processing apparatus 200 which concerns on a comparative example. It is a block diagram of the image processing apparatus 300 which concerns on a comparative example.

[Background technology]
As a method for reducing noise in a binarized image, an opening process and a closing process are known.

  In both the opening process and the closing process, the expansion process and the contraction process are alternately repeated the same number of times. The expansion process is performed first and then the contraction process is performed. The closing process is performed after the contraction process is performed and then the expansion process is performed.

  Both the expansion process and the contraction process are processes for determining a pixel value after processing of the pixel of interest based on a total of nine pixel values of the pixel of interest and each of the eight adjacent pixels around the pixel of interest. A pixel value after processing of the pixel of interest is calculated by a logical operation of the value.

  In the dilation processing, the pixel value after the processing of the pixel of interest is set to 0 when all nine pixel values are 0, and is set to 1 otherwise, as a result of the logical sum of the nine pixel values. A pixel value after processing of the pixel of interest is determined (see FIG. 2).

  In the contraction process, the processed pixel value of the target pixel is set to 1 when all the nine pixel values are 1, and is set to 0 otherwise. As a result of the logical product of the nine pixel values, The pixel value after processing of the pixel of interest is determined (see FIG. 3).

  Hereinafter, embodiments for carrying out the present invention will be described in detail. However, the embodiment described below shows an example of an image processing apparatus for embodying the technical idea of the present invention, and is not intended to limit the present invention to this embodiment. The invention can be equally applied to various modifications without departing from the technical idea shown in the claims.

[Embodiment]
In the present embodiment, when performing binary image data expansion processing and reduction processing, pixel values after processing are calculated for eight pixels of interest that are continuously present on the same line in a single processing. The image processing apparatus 100 will be described.

  As illustrated in FIG. 4, the image processing apparatus 100 includes a data input unit 20, a pixel column extraction unit 30, a pixel value determination unit 40, and a data output unit 50. Further, the pixel column extraction unit 30 includes line buffers 11, 12, and 13, coupling units 21, 22, and 23, and selectors 31, 32, and 33. The pixel value determination unit 40 includes conversion units 41, 42, 43 and a logical operation unit 44.

  The data input unit 20 stores the input binary image data, and the pixel column extraction unit 30 selects the eight target pixels to be processed and its target from the binary image data stored in the data input unit 20. Pixel values of 30 pixels (hereinafter also referred to as “input pixel area”) including 22 surrounding pixels are extracted as three 10-bit length data.

  The pixel value determination unit 40 determines the processed pixel values of the eight target pixels based on the 30 pixel values in the input pixel region by specific logic, and the data output unit 50 uses the pixel value determination unit 40 to Output image data is generated from the determined pixel values.

  As shown in FIG. 5, the input pixel area is a pixel on a line (also referred to as “M line”) where the target pixel currently being processed exists, that is, eight target pixels to be processed and adjacent to each other in the line direction. A first pixel column, which is 10 pixels on the same line made up of positioned pixels, and two pixels that are each 10 pixels and are adjacent to the first pixel column in a direction orthogonal to the line direction The second pixel column and the third pixel column can be divided, and in the present embodiment, the line (also referred to as “U line”) that is higher than the first pixel column (y coordinate is smaller). ) A pixel column composed of upper pixels will be described as a second pixel column, and a pixel column composed of pixels on a lower (larger y coordinate) line (also referred to as “B line”) will be described as a third pixel column. In FIG. 5 and the like, pixels on the U line are indicated by “U + number”, pixels on the M line are indicated by “M + number”, and pixels on the B line are indicated by “B + number”.

  Hereinafter, the flow of processing in the image processing apparatus 100 until the output image data is generated from the image data stored in the data input unit 20 will be described.

  In the image processing apparatus 100, processing of pixels to be processed is performed according to the order in which each pixel is scanned when the image is raster scanned.

  That is, when the pixel to be processed exists on a different line, processing is performed from the pixel on the line with the smallest y coordinate (from the pixel on the top line on the screen display), and the processing of the pixel on the same line is performed. When all the processing is completed, the pixels on the line having the next larger y coordinate are sequentially processed, and the pixels on the same line are processed from the pixel having the smaller x coordinate (from the leftmost pixel on the screen display). ) Process in order.

[Pixel Extraction]
In the pixel column extraction unit 30, three 10-bit length data based on the 30 pixel values in the input pixel region are generated from the input image data held in the data input unit 20 as follows. The

  Each of the line buffers 11, 12, and 13 is a line buffer that takes in the pixel values of eight consecutive pixels on the same line from the input image data and passes them to the combining units 21, 22, and 23 as 8-bit length data. The line buffer 11 captures the pixel value of the U line pixel, the line buffer 12 captures the pixel value of the M line pixel, and the line buffer 13 captures the pixel value of the B line pixel.

  The combining units 21, 22, and 23 hold the 8-bit data received from the line buffers 11, 12, and 13 at the time of the previous processing, respectively. 16-bit length data is generated by combining the 8-bit length data and the 8-bit length data received from the line buffers 11, 12, and 13 at the time of this processing.

  In the selectors 31, 32, and 33, 10 bits are extracted from the 16-bit data received from the combining units 21, 22, and 23, so that the second pixel column, the first pixel column, and the third pixel column are obtained. Second pixel column data that is 10-bit length data (corresponding to “pixel value corresponding” means that the pixel values of each pixel can be arranged in order from the left), First pixel column data and third pixel column data are generated.

The method of extracting 10-bit length data from 16-bit length data formed by combining the 8-bit length data at the previous processing and the 8-bit length data at the current processing is as shown in FIG.
(1) All 8 bits at the time of previous processing + 10 bits of the first 2 bits of 8 bits at the time of current processing,
(2) The last 2 bits of 8 bits at the time of previous processing + all 8 bits at the time of current processing (3) The last 5 bits at the time of previous processing + The first 5 bits at the time of current processing As a result of sequential processing depending on the method, each of the pixel columns overlaps with the last two pixels of the last two pixels in the previous processing and the last two pixels of the last two pixels in the next processing. (Overlap: see FIGS. 5 and 7).

  Hereinafter, the processing in the pixel column extraction unit 30 will be specifically described with respect to the case of sequentially cutting out by the method (1) above, where the target pixels currently being processed are M1 to M8.

  The line buffer 11 takes in the pixel values of the pixels U8 to U15 and passes the 8-bit data consisting of the pixel values of the pixels U8 to U15 to the combining unit 21.

  As shown in FIG. 6, the combining unit 21 receives 8-bit data composed of the pixel values of the pixels U0 to U7 received from the line buffer 11 and held in the previous processing, and the line buffer 11 in this processing. Are combined with the 8-bit length data received from 1 to generate 16-bit length data consisting of the pixel values of the pixels U0 to U15, and the 8-bit length data consisting of the pixel values of the pixels U8 to U15 is processed until the next processing. Will be retained.

  The selector 31 cuts out the first 10 bits from the 16-bit length data, thereby generating 10-bit length data including the pixel values of the pixels U0 to U9 as the second pixel column data.

  Here, U0 and U1 overlap with the last two pixels of the second pixel row in the previous process. The above process is repeated with the target pixel to be processed shifted by 8 pixels in the line direction, so that the overlap between the first two pixels and the last two pixels is also repeated. For example, in the next processing, the target pixels are M9 to M16 and the first pixel column is 10 pixels M8 to M17. Therefore, the last two pixels of the second pixel column currently being processed are shown in FIG. As shown in FIG. 7B, the first two pixels in the second pixel column in the next processing overlap with U8 and U9.

  Similarly to the second pixel column, the first pixel column and the third pixel column also pass through the line buffer 12, the coupling unit 22, the selector 32, and the line buffer 13, the coupling unit 23, and the selector 33. The first pixel column data composed of the pixel values of the pixels M0 to M9 and the third pixel column data composed of the pixel values of the pixels B0 to B9, respectively, are generated, and for two pixels of each pixel column Duplication is repeated.

  As described above, the pixel column extraction unit 30 sequentially converts the pixel values of the input pixel area including 30 pixels as the first pixel column data, the second pixel column data, and the third pixel column data. Extract.

  The three pixel column data (10-bit length) generated by the pixel column extraction unit 30 as described above is input to the pixel value determination unit 40.

[Pixel value determination]
The pixel value determination unit 40 includes a conversion table (LUT: Look Up Table) for converting 10-bit length data into 8-bit length data with specific logic, and the conversion units 41, 42, and 43 respectively convert the data. By referring to the table, from the second pixel column data, which is 10-bit length data, the first pixel column data, and the third pixel column data, the second intermediate data, which is 8-bit length data, the first Intermediate data and third intermediate data are generated.

The conversion table is created based on the following logic.
(In the case of expansion processing)
The i-th bit value OI _i of 8-bit length data to be output (i is an integer satisfying 1 ≦ i ≦ 8, the same applies hereinafter) is the i-th to i + 2-th 3-bit length of input 10-bit length data. By the minute data value I _i ,
When I _i = 000, OI _i = 0
If I _i ≠ 000, OI _i = 1
It is determined.

This is because the i-th value of the input 10-bit length data is K _i , the i + 1-th value is K _{i + 1} , and the i + 2-th value is K _{i + 2} (K _i , K _{i + 1} , K _{i + 2} is a value of 1 or 0), that is, when I _i can be expressed as K _i K _{i + 1} K _{i + 2} , the i th of the 8-bit intermediate data generated by the conversion process bits of the value OI _i, respectively, K _i, which corresponds to outputting a logical sum of _{K i + 1, K i +} 2.

(In case of shrinkage treatment)
The i-th bit value OI _i of the 8-bit length data to be output is determined by the data values I _{i for} the i-th to i + 2th 3-bit length of the input 10-bit length data,
When I _i = 111, OI _i = 1
If I _i ≠ 111, OI _i = 0
It is determined.

This is because the i-th value of the input 10-bit length data is K _i , the i + 1-th value is K _{i + 1} , and the i + 2-th value is K _{i + 2} , that is, I _i is K _i K _{i. When} it can be expressed as ₊₁ K _{i + 2} , OI _i that is the value of the i-th bit of the N-bit intermediate data generated by the conversion process is represented by K _i , K _{i + 1} , K _{i + 2} , respectively. It is equivalent to outputting as the logical product of.

  That is, in FIG. 7, in the current process (A), the values of the first to tenth bits of the pixel column data that is input 10-bit length data are indicated by U0 to U9, and the first to second intermediate data are displayed. The value of the eighth bit is indicated by A1 to A8. In the next processing (B), the value of the first to tenth bits of the pixel column data is indicated by U8 to U17, and the first to the intermediate data are indicated by Although the value of the eighth bit is indicated by A9 to A16, the conversion from the 10-bit length data to the 8-bit length data in the conversion units 41, 42, 43 may be expansion processing or contraction processing. This is common in that the value of each bit of the intermediate data is obtained by logically calculating the value of 3 bits of the pixel column data. For example, the first bit value A1 of the intermediate data is the logical sum of the values of the first, second, and third bits U0, U1, and U2 of the input pixel column data (in the case of expansion processing) ) Or logical product (in the case of reduction processing).

  Here, the case where the data input to the intermediate data generation unit is 10-bit data such as 0001110101 will be described in detail.

The conversion table in the case of expansion processing corresponds to outputting each OI _i as the logical sum of K _i , K _{i + 1} , K _{i + 2} , respectively.
When I _i = 000, OI _i = 0
If I _i ≠ 000, OI _i = 1
Defined by

Therefore,
I ₁ = 000, so OI ₁ = 0
I ₂ = 001, so OI ₂ = 1
I ₃ = 011, so OI ₃ = 1
I ₄ = 111, so OI ₄ = 1
I ₅ = 110, so OI ₅ = 1
I ₆ = 101, so OI ₆ = 1
I ₇ = 010, so OI ₇ = 1
I ₈ = 101, so OI ₈ = 1
It becomes.

That is, the expansion processing conversion table includes:
Input: 0001110101, output: 01111111,
It will be determined that.

The conversion table in the case of contraction processing corresponds to outputting each OI _i as a logical product of K _i , K _{i + 1} , K _{i + 2} , respectively.
When I _i = 111, OI _i = 1
If I _i ≠ 111, OI _i = 0
Defined by

Therefore,
I ₁ = 000, so OI ₁ = 0
I ₂ = 001, so OI ₂ = 0
I ₃ = 011, so OI ₃ = 0
I ₄ = 111, so OI ₄ = 1
I ₅ = 110, so OI ₅ = 0
I ₆ = 101, so OI ₆ = 0
I ₇ = 010, so OI ₇ = 0
I ₈ = 101, so OI ₈ = 0
It becomes.

That is, in the conversion table for shrinkage processing,
Input: 0001110101, output: 00010000,
It will be determined that.

  The three intermediate data (8-bit length) generated as described above are transferred to the logical operation unit 44, and the logical operation unit 44 performs one 8-bit length by logical operation between the three intermediate data. Data (output pixel data) is generated.

  The output pixel data corresponds to the processed pixel value of the target pixel column, which is the eight consecutive target pixels currently being processed, and the pixel values after processing of the target pixel column are arranged in the line direction. Bit length data.

Specifically, the logical operation between the three pieces of intermediate data is input with the value O _i of the i-th bit of the output pixel data, which is the pixel value after processing of the i-th pixel of the pixel row of interest. The first intermediate data, the second intermediate data, and the third intermediate data are determined by a logical operation that receives the values OI1 _i , OI2 _i , and OI3 _i of each i-th bit of the third intermediate data. In the case of expansion processing, it is logical sum, and in the case of contraction processing, it is logical product.

That is,
(In the case of expansion processing)
If OI1 _i = OI2 _i = OI3 _i I _i = 0, then O _i = 0
If any of OI1 _i , OI2 _i , OI3 _i I _i is 1, O _i = 1
And determined
(In case of shrinkage treatment)
If OI1 _i = OI2 _i = OI3 _i I _i = 1, then O _i = 1
If any of OI1 _i , OI2 _i , OI3 _i I _i is 0, O _i = 0
Is determined.

Here, the process in the pixel value determination unit 40 will be specifically described by taking as an example a case where the input pixel region has the following pixel values.
Second pixel column (U0 to U9): 00100111
First pixel column (M0 to M9): 11100000111
Third pixel column (B0 to B9): 0001000111
* The pixel values of the target pixels M1 to M8 are 11000011.

(In the case of expansion processing)
The three 10-bit length data transferred from the pixel column extraction unit 30 are converted into 8-bit length data by the conversion units 41, 42, and 43, respectively.

Here, since it is an expansion process, the logical operation when OI _i is derived from K _i , K _{i + 1} , K _{i + 2} is a logical sum, and the conversion units 41, 42, 43 have the following definitions:
When I _i = 000, OI _i = 0
If I _i ≠ 000, OI _i = 1
Refer to the expansion processing conversion table defined in (1).

Accordingly, 11100111 is output as the first intermediate data generated from the first pixel column data (1110000111), 11100111 is output as the second intermediate data generated from the second pixel column data (00110000111), and the third 01110111 is output as the third intermediate data generated from the pixel column data (0001000111).
Second intermediate data: 11100111
First intermediate data: 11100111
Third intermediate data: 01110111

The logical operation unit 44 receives the first intermediate data, the second intermediate data, and the third intermediate data as input, and generates one piece of output pixel data that is 8-bit length data by logical operation. Here, it is an expansion process. Therefore, the logical operation for calculating the value of each bit of the output data from the value of each bit of each input data is a logical sum,
OI1 ₁ = 1, OI2 ₁ = 1, OI3 ₁ = 0, so O ₁ = 1
OI1 ₂ = 1, OI2 ₂ = 1, OI3 ₂ = 1, and thus O ₂ = 1
OI1 ₃ = 1, OI2 ₃ = 1, OI3 ₃ = 1, thus O ₃ = 1
OI1 ₄ = 0, OI2 ₄ = 0, OI3 ₄ = 1, and thus O ₄ = 1
OI1 ₅ = 0, OI2 ₅ = 0, OI3 ₅ = 0, thus O ₅ = 0
OI1 ₆ = 1, OI2 ₆ = 1, OI3 ₆ = 1, thus O ₆ = 1
OI1 ₇ = 1, OI2 ₇ = 1, OI3 ₇ = 1, thus O ₇ = 1
OI1 ₈ = 1, OI2 ₈ = 1, OI3 ₈ = 1, thus O ₈ = 1
And “11110111” is output as output pixel data.

(In case of shrinkage treatment)
Since three 10-bit length data transferred from the pixel column extractor 30 is converted respectively by the conversion unit 41, 42 and 43 into 8-bit data, here a shrinkage treatment, K _i, K _The logical operation for deriving OI _i from _{i + 1} , K _{i + 2} is a logical product, and the logic of the conversion table for contraction processing referred to by the conversion units 41, 42, 43 is:
When I _i = 111, OI _i = 1
If I _i ≠ 111, OI _i = 0
It is.

Accordingly, the first intermediate data, the second intermediate data, and the third intermediate data are output as follows.
Second intermediate data: 00000001
First intermediate data: 10000001
Third intermediate data: 00000001

The logical operation unit 44 receives the first intermediate data, the second intermediate data, and the third intermediate data as input, and generates one piece of output pixel data that is 8-bit length data by logical operation. Here, it is an expansion process. Therefore, the logical operation for calculating the value of each bit of the output data from the value of each bit of each input data is a logical sum,
OI1 ₁ = 1, OI2 ₁ = 1, OI3 ₁ = 0, so O ₁ = 1
OI1 ₂ = 1, OI2 ₂ = 1, OI3 ₂ = 1, and thus O ₂ = 1
OI1 ₃ = 1, OI2 ₃ = 1, OI3 ₃ = 1, thus O ₃ = 1
OI1 ₄ = 0, OI2 ₄ = 0, OI3 ₄ = 1, and thus O ₄ = 1
OI1 ₅ = 0, OI2 ₅ = 0, OI3 ₅ = 0, thus O ₅ = 0
OI1 ₆ = 1, OI2 ₆ = 1, OI3 ₆ = 1, thus O ₆ = 1
OI1 ₇ = 1, OI2 ₇ = 1, OI3 ₇ = 1, thus O ₇ = 1
OI1 ₈ = 1, OI2 ₈ = 1, OI3 ₈ = 1, thus O ₈ = 1
And “11110111” is output as output pixel data.

The logical operation unit 44 receives the first intermediate data, the second intermediate data, and the third intermediate data as input, and generates one piece of output pixel data that is 8-bit length data by logical operation. Therefore, the logical operation for calculating the value of each bit of the output data from the value of each bit of each input data is a logical product,
OI1 ₁ = 1, OI2 ₁ = 0, OI3 ₁ = 0, thus O ₁ = 0
OI1 ₂ = 0, OI2 ₂ = 0, OI3 ₂ = 0, thus O ₂ = 0
OI1 ₃ = 0, OI2 ₃ = 0, OI3 ₃ = 0, thus O ₃ = 0
OI1 ₄ = 0, OI2 ₄ = 0, OI3 ₄ = 0, and thus O ₄ = 0
OI1 ₅ = 0, OI2 ₅ = 0, OI3 ₅ = 0, thus O ₅ = 0
OI1 ₆ = 0, OI2 ₆ = 0, OI3 ₆ = 0, thus O ₆ = 0
OI1 ₇ = 0, OI2 ₇ = 0, OI3 ₇ = 0, thus O ₇ = 0
OI1 ₈ = 1, OI2 ₈ = 1, OI3 ₈ = 1, thus O ₈ = 1
And 00000001 is output as output pixel data.

  In the pixel value determination unit 40, as described above, the pixel value of each pixel in the input pixel region is input, and the pixel value after processing of the target pixel is based on the pixel value before processing of the pixels around the target pixel. To decide.

  The data output unit 50 sequentially receives output pixel data corresponding to the processed pixel value of the pixel of interest calculated as described above from the pixel value determination unit 40, and generates output image data.

  As described above, the image processing apparatus 100 according to the present embodiment can determine the processed values of the eight target pixels at a time based on the thirty pixel values constituting the input pixel region.

  In this embodiment, an example in which the number of target pixels to be processed simultaneously is eight has been shown. However, in the present invention, the number of target pixels to be processed simultaneously is not theoretically limited, and a conversion table prepared in advance is used. Depending on the scale, the number of pixels of interest that can be processed simultaneously can be controlled.

[Comparative example]
Next, the image processing unit 120 (the pixel column extraction unit 30 and the pixel value in the image processing apparatus 100 according to the embodiment) that performs processing of one pixel of interest in a single process at the time of dilation processing and contraction processing of the binary image. A conventional image processing apparatus 200 having an equivalent to the determination unit 40 will be described with reference to FIG.

  In addition to the image processing unit 120, the image processing apparatus 200 combines a data input unit 110 that stores input image data, and a combination of eight pixel values output from the image processing unit 120 to generate 8-bit data. Unit 140 and a data output unit 150 that generates output image data using the 8-bit data output from the combining unit 140. The image processing unit 120 includes line buffers 111, 112, and 113, a selector 121, 122 and 123, and a logical operation unit 124

  The image processing apparatus 200 determines a pixel value after processing of the target pixel based on the pixel values of one target pixel and eight neighboring pixels around the target pixel. The line buffers 111, 112, and 113 capture pixel values of eight consecutive pixels on the same line from the input image data stored in the data input unit 110, and receive them as 8-bit length data to the selectors 121, 122, and 123. M line pixels including the pixel of interest M1 are taken into the line buffer 112, U line pixels above the M line are taken into the line buffer 111, and B line pixels below the M line Is taken into the line buffer 113.

  In the selectors 121, 122, and 123, the first 3 bits including the pixel values of the pixels U0 to U2, M0 to M2, and B0 to B2 from the 8-bit data received from the line buffers 111, 112, and 113, respectively. Minutes are cut out, and three pieces of 3-bit length data are transferred to the logical operation unit 124.

In the logical operation unit 124, in the case of dilation processing, a logical sum is taken for the pixel value of the pixel of interest extracted as described above and its eight adjacent pixels (U0 to U2, M0 to M2, B0 to B2), and the dilation is performed. In the case of processing, the pixel value after processing of the pixel of interest M1 is output by taking the logical product.
The image processing unit 120 repeats the above processing for the target pixels M2 to M8, and outputs pixel values after processing of the total eight target pixels.

  The combining unit 140 generates 8-bit data by combining the processed pixel values of the target pixels M1 to M8 that are sequentially output, and outputs the data to the data output unit 150 as output pixel data.

  Similarly to the data output unit 50 according to the embodiment, the data output unit 150 sequentially receives output pixel data from the combination unit 140 and generates output image data.

  Next, the image processing apparatus 200 described above includes eight image processing units 120 including line buffers 111, 112, and 113, selectors 121, 122, and 123, and a logical operation unit 124. A conventional image processing apparatus 300 that can process the determination of the pixel value of the pixel of interest in parallel will be described with reference to FIG.

  The image processing apparatus 300 includes eight image processing units 120 (hereinafter, distinguished from the image processing units 120a to 120h), and processes eight target pixels in parallel for speeding up the image processing. In addition, the pixel values after processing of the eight pixels of interest (M1 to M8) output simultaneously from the eight image processing units 120 are combined to output 8-bit data. As with the image processing apparatus 200, the data input unit 110 and the data output unit 150 are included.

  In the image processing device 300, as described in the image processing device 200, there are eight image processing units 120 that output pixel values after processing of the target pixel, and the image processing unit 120 performs processing in parallel. For the eight target pixels (M1 to M8), pixel values after processing are simultaneously determined and passed to the combining unit 240.

Hereinafter, the flow of processing in the image processing apparatus 300 when an input pixel area having the following pixel values as in the embodiment is set as a processing target will be described.
Second pixel column (U0 to U9): 00100111
First pixel column (M0 to M9): 11100000111
Third pixel column (B0 to B9): 0001000111
* The pixel values of the target pixels M1 to M8 are 11000011.

(Expansion treatment)
[Input pixel value extraction]
The image processing unit 120a obtains pixel values of U0 to U2, M0 to M2, and B0 to B2 including the first pixel of interest M1 and its eight adjacent pixels from the input image data held in the data input unit 110. Extract.

  Since the pixel values of the U line are 0, 0, 1, and the pixel values of the M line are 1, 1, 1, and the pixel values of the B line are 0, 0, 0, the input pixel values are 0, 0, 1, 1, 1, 1, 0, 0, 0 are obtained.

[Output pixel value calculation]
Next, the image processing unit 120a determines the pixel value after processing of the target pixel by calculating the logical sum of the nine obtained pixel values, and sets the pixel value after processing of the first target pixel as “ 1 "is output.

  In the image processing apparatus 300, the remaining target pixels (M2 to M8) are processed in parallel, so that the same processing for calculating output pixel values as in the image processing unit 120a is performed in parallel in the image processing units 120b to 120h. Done.

  In each of the image processing units 120b to 120h, for each of the second to eighth attention pixels (M2 to M8), after extracting the pixel values of the attention pixel and its eight adjacent pixels, the nine pixel values obtained are By taking a logical sum, the pixel value after processing of each pixel of interest is determined.

  The pixel values of the pixel of interest M2 and its eight neighboring pixels are 0, 1, 0, 1, 1, 0, 0, 0, 1, and the image processing unit 120b performs pixel processing on the second pixel of interest M2. “1” is output as the value.

  The pixel values of the pixel of interest M3 and its eight neighboring pixels are 1, 0, 0, 1, 0, 0, 0, 1, 0, and the image processing unit 120c performs pixel processing on the third pixel of interest M3. “1” is output as the value.

  The pixel values of the pixel of interest M4 and its eight adjacent pixels are 0, 0, 0, 0, 0, 0, 1, 0, 0, and the image processing unit 120d performs pixel processing on the fourth pixel of interest M4. “1” is output as the value.

  The pixel values of the pixel of interest M5 and its eight adjacent pixels are 0, 0, 0, 0, 0, 0, 0, 0, 0, and the image processing unit 120e is the pixel after processing of the fifth pixel of interest M5 “0” is output as the value.

  The pixel values of the pixel of interest M6 and its eight adjacent pixels are 0, 0, 1, 0, 0, 1, 0, 0, 1, and the image processing unit 120f performs pixel processing on the sixth pixel of interest M6. “1” is output as the value.

  The pixel values of the pixel of interest M7 and its eight neighboring pixels are 0, 1, 1, 0, 1, 1, 0, 1, 1, and the image processing unit 120g is a pixel after processing of the seventh pixel of interest M7. “1” is output as the value.

  The pixel values of the pixel of interest M8 and its eight adjacent pixels are 1, 1, 1, 1, 1, 1, 1, 1, 1, and the image processing unit 120h is the pixel after processing of the eighth pixel of interest M8. “1” is output as the value.

[Output pixel data generation]
In the combining unit 240, the pixel values output from the image processing units 120a to 120h are input, and the 8-bit length data “11110111” is generated by arranging the pixel values in order, and is output as output pixel data.

(Shrinkage treatment)
Next, the case where the image processing apparatus 300 performs the contraction process will be described. The difference from the above-described expansion process is only the use of a logical product as a logical operation in [output pixel value calculation]. Description of [input pixel value extraction] is omitted.

[Output pixel value calculation]
Each of the image processing units 120a to 120h performs a logical product on the obtained nine pixel values, thereby determining a processed pixel value of each pixel of interest.

  The image processing unit 120a outputs “0” as the pixel value after processing of the first pixel of interest.

  The image processing unit 120b outputs “0” as the pixel value after processing of the second pixel of interest.

  The image processing unit 120c outputs “0” as the pixel value after processing of the third pixel of interest.

  The image processing unit 120d outputs “0” as the pixel value after processing of the fourth pixel of interest.

  The image processing unit 120e outputs “0” as the pixel value after processing of the fifth pixel of interest.

  The image processing unit 120f outputs “0” as the pixel value after processing of the sixth pixel of interest.

  The image processing unit 120g outputs “0” as the pixel value after processing of the seventh pixel of interest.

  The image processing unit 120h outputs “1” as the pixel value after processing of the eighth pixel of interest.

[Output pixel data generation]
The combining unit 240 receives the pixel values output from the image processing units 120a to 120h, generates 8-bit length data “00000001” by arranging the pixel values in order, and outputs the data as output pixel data.

[Image data output]
The data output unit 150 sequentially receives the output pixel data output as described above, and generates image data.

  As shown in the comparative example described above, in a conventional image processing apparatus in which one processing circuit (image processing unit 120) processes one pixel of interest in binary image processing, In order to be able to process a plurality of target pixels in parallel, as many processing circuits as the number of target pixels to be processed in parallel are required.

  On the other hand, in the embodiment described above as the image processing apparatus 100, even if the number of target pixels that can be processed in parallel increases, the pixel column extraction unit 30 and the pixel value determination unit corresponding to the image processing unit 120 in the comparative example. It is not necessary to prepare a plurality of 40, and if only a conversion table is prepared, a plurality of pixels of interest can be processed in parallel. Therefore, an increase in circuit scale when processing performance is improved is suppressed.

DESCRIPTION OF SYMBOLS 100, 200, 300 ... Image processing apparatus 11, 12, 13, 111, 112, 113 ... Line buffer 20, 110 ... Data input part 21, 22, 23, 140, 240 ... Combining part 30 ... Pixel row extraction part 31, 32, 33, 121, 122, 123 ... selector 40 ... pixel value determination unit 41, 42, 43 ... conversion unit 44, 124 ... logic operation unit 50, 150 ... data output unit 120 ... image processing unit

Claims (2)

N consecutive pixels (N is an integer of 2 or more) on the same line of the binary image data are set as the target pixels, and the N target pixels and the N target pixels are determined from the binary image data. Each pixel value of the first pixel column of N + 2 pixels composed of two pixels adjacent on the line and N + 2 pixels adjacent to each other in two directions orthogonal to the first pixel column and the line direction Extraction means for sequentially extracting the respective pixel values of the second and third pixel columns comprising: in the line direction so as to overlap each of the first, second, and third pixel columns previously extracted by two pixels; ,
The pixel values of the first, second, and third pixel columns extracted by the extraction unit are input, and the processed pixel values of the N target pixels are determined as the target pixel and the target pixel. and a determination means for determining, respectively, based on the pixel values of the pre-treatment of the surrounding pixels
The determining means is configured to store each N + 2 bit pixel column data composed of pixel values of the first, second and third pixel columns composed of N + 2 pixels based on a predetermined logic. Conversion means for converting the data into three long intermediate data;
Logical operation means for determining a value of the N target pixels by performing a logical operation between the three intermediate data converted by the conversion means,
Image processing device. N consecutive pixels (N is an integer of 2 or more) on the same line of the binary image data are set as the target pixels, and the N target pixels and the N target pixels are determined from the binary image data. A first pixel column of N + 2 pixels composed of two pixels adjacent on the line, and a second pixel composed of N + 2 pixels adjacent to each other in two directions orthogonal to the first pixel column and the line direction. And sequentially extracting the pixel values of the third pixel column and the third pixel column in the line direction so as to overlap each of the first, second, and third pixel columns extracted by two pixels,
The extracted pixel values of the first, second, and third pixel columns are input, and the processed pixel value of each of the N target pixels is used as the target pixel and pixels around the target pixel. When determining each pixel value based on the pixel values before the processing, each N + 2 bit pixel column data composed of the pixel values of the first, second and third pixel columns composed of N + 2 pixels is preliminarily stored. Converting into three intermediate data each having a length of N bits based on the set logic, and determining the value of the N pixels of interest by performing a logical operation between the converted three intermediate data ;
A program that causes a computer to execute.

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