JP6677402B2 - Image display device, image display control device, and image display method - Google Patents

Description

  The present invention relates to an image display device, an image display control device, and an image display method.

  When each pixel of a display is configured using a self-luminous display device (hereinafter, also referred to as a self-luminous display element) such as an organic light emitting diode (OLED), the amount of light emitted at the time of image output at each pixel is reduced. Corresponding luminance degradation occurs. Therefore, depending on the output image, display quality may be degraded due to uneven brightness between pixels. This luminance unevenness occurs because an in-plane difference (characteristic distribution) increases due to, for example, electric stress of a driving TFT (Thin Film Transistor).

  Patent Literature 1 discloses an apparatus for compensating for a change in electrical characteristics of each pixel included in an OLED display. In the device described in Patent Document 1, for example, when the power is turned off, the threshold voltage of each driving TFT and the average threshold voltage of each driving TFT are measured. In this measurement, a voltage having a polarity opposite to that at the time of light emission is applied to the power supply line, and a current in a direction opposite to that at the time of light emission is supplied to a self-luminous display element or a parasitic capacitor of the driving TFT. Then, the threshold voltage of the driving TFT is measured by reading the gate voltage when the driving TFT is turned off via the data line. Furthermore, in the device described in Patent Literature 1, a voltage load is applied to a driving TFT having a small electric load based on a comparison result between each measured threshold voltage and an average threshold voltage. According to this configuration, the distribution of the threshold voltage of each driving TFT can be narrowed, so that the adjustment value of the threshold voltage can be unified.

Japanese Patent Publication No. 2009-543123

  In the device described in Patent Document 1, when a voltage load is applied to a driving TFT having a relatively small electric load, the following processing is performed after measuring an average threshold voltage of each driving TFT. That is, the measurement of the threshold voltage of each driving TFT, the comparison with the average threshold voltage, the selection of the load voltage based on the comparison result, and the application of the selected load voltage to the driving TFT are arranged in a matrix. The processing is sequentially performed for each pixel row. For example, when trying to execute these processes in a short time, it is assumed that the circuit scale becomes large. Therefore, for example, if it is attempted to execute these processes without deteriorating the display quality during the display of an arbitrary image, a problem that the configuration becomes complicated may occur. That is, in the technique described in Patent Document 1, a voltage load is applied to a driving TFT with a small electric load in a normal image display state, for example, during display of an arbitrary image without complicating the configuration. There was a problem that can not be.

  An object of the present invention is to provide an image display device, an image display control device, and an image display method that can correct a variation in load of a driving TFT without complicating the configuration.

One embodiment of the present invention is a display portion including a plurality of pixels each including a driving transistor and a self-luminous display element connected to a power supply line through the driving transistor, and a display portion for displaying the image signal based on an image signal. The correction signal for correcting the variation in the load among the plurality of drive transistors caused by the above in one or a plurality of frames and for each pixel is obtained by inverting the brightness value of the image signal for each pixel. And controlling the state of the power supply line so that power can be supplied from the power supply line to the self-luminous display element via the drive transistor from the power supply line alternately for each of the one or more frames and for each pixel. And applying a voltage based on the image signal to the gate of the drive transistor, or the self-luminous display element from the power supply line via the drive transistor Controls the state of the power line so as not to be energized, and an image display apparatus and a control section for controlling the application of a voltage based on the correction signal to the gate of the driving transistor.

  Further, according to one embodiment of the present invention, a display portion including a plurality of pixels each including a driving transistor and a self-luminous display element connected to a power supply line through the driving transistor, a luminance value of an image signal is provided for each of the pixels. When a correction signal is generated by inverting the gradation, and the state of the power supply line is controlled so that current can flow from the power supply line to the self-luminous display element via the drive transistor, the gate of the drive transistor is When a voltage based on an image signal is applied and the state of the power supply line is controlled so that current cannot be supplied from the power supply line to the self-luminous display element via the drive transistor, the correction signal is applied to the gate of the drive transistor. And a control unit for performing control for applying a voltage based on the control signal.

Further, one embodiment of the present invention includes a plurality of power lines, a plurality of gate lines, a plurality of data lines, any one of the plurality of power lines, any one of the plurality of gate lines, and the plurality of data lines. A display unit having a plurality of pixels each connected to one of the lines, and a control unit for controlling a state of the plurality of power lines, a state of the plurality of gate lines, and a state of the plurality of data lines. Wherein each of the pixels has a self-luminous display element, a driving transistor for driving the self-luminous display element, a selection transistor, and a storage capacitor, and in each of the pixels, the self-luminous display element is the driving transistor And the gate of the driving transistor is connected to any of the plurality of data lines via the selection transistor, and the selection transistor A gate is connected to any one of the plurality of gate lines, and the storage capacitor holds a voltage applied from the data line to the gate of the drive transistor via the selection transistor; The unit, a correction signal for correcting the variation in load among the plurality of drive transistors generated at the time of display of the image signal based on an image signal in one or more frame units, and for each pixel , The luminance value of the image signal is generated by inverting the gradation of each pixel, and a voltage based on the image signal or a voltage based on the correction signal is sequentially selected in units of one or a plurality of frames, and And a state in which the self-luminous display element can be energized in synchronization with a voltage selection period based on the image signal. Controlling the plurality of power lines such that the self-luminous display element cannot be energized in synchronization with a voltage selection period based on the correction signal. Applying a voltage based on the image signal to the gate of the drive transistor for each pixel in a state where the self-luminous display element can be energized alternately in units of one or more frames, or An image display device that performs control of applying a voltage based on the correction signal to the gate of the drive transistor for each pixel in a state where an element cannot be energized.

Another embodiment of the present invention is an apparatus for controlling a display portion having a plurality of pixels each including a driving transistor and a self-luminous display element connected to a power supply line through the driving transistor, based on an image signal. A correction signal for correcting a variation in load among the plurality of drive transistors generated at the time of displaying the image signal in units of one or a plurality of frames, and for each pixel, and a luminance value of the image signal. The self-luminous display element is generated by inverting the gradation for each pixel , and is alternately provided for each of the one or a plurality of frames, and for each pixel, from the power supply line to the self-luminous display element via the drive transistor. Controlling the state of the power supply line, and applying a voltage based on the image signal to the gate of the drive transistor, or from the power supply line to the drive transistor An image display control device comprising: a control unit that controls a state of the power supply line so as not to supply current to the self-luminous display element through the control unit, and controls a voltage based on the correction signal to the gate of the drive transistor. It is.

Another embodiment of the present invention is a method for controlling a display portion including a plurality of pixels including a driving transistor and a self-luminous display element connected to a power supply line via the driving transistor, the variation in load between a plurality of the driving transistor generated at the time of display of the image signal based on the image signal in one or more frames, and a correction signal for correcting for each of the pixels, the image signal The self-luminous display element is generated by inverting the brightness value of each pixel for each of the pixels , alternately in units of one or a plurality of frames, and for each of the pixels, from the power supply line via the drive transistor. Controlling the state of the power supply line so as to be able to conduct electricity, and applying a voltage based on the image signal to the gate of the drive transistor, or An image display control method for controlling the state of the power supply line so as not to energize the self-luminous display element via a driving transistor, and performing control of applying a voltage based on the correction signal to the gate of the driving transistor. is there.

  According to the present invention, it is possible to correct the variation in the load of the driving transistor without complicating the configuration.

FIG. 1 is a block diagram illustrating a basic configuration of an image display device according to a first embodiment of the present invention. It is a block diagram showing an example of composition of an image display device concerning a 2nd embodiment of the present invention. FIG. 3 is a block diagram illustrating a configuration example of a display unit 2 illustrated in FIG. 2. FIG. 4 is an equivalent circuit diagram illustrating a configuration example of a pixel PX illustrated in FIG. 3. FIG. 3 is a diagram for explaining an operation example of the image display device 1 shown in FIG. 2. FIG. 3 is a diagram for explaining an operation example of the image display device 1 shown in FIG. 2. FIG. 4 is a schematic diagram for explaining an operation example of the display unit 2 shown in FIG. 3. FIG. 3 is a schematic diagram for explaining an operation example of the image display device 1 shown in FIG. 2. FIG. 3 is a schematic diagram for explaining a comparative example with the operation example of the image display device 1 shown in FIG. 2. FIG. 3 is a schematic diagram for explaining an operation example of the image display device 1 shown in FIG. 2. It is a block diagram showing an example of composition of indicator 2a concerning a 3rd embodiment of the present invention. FIG. 12 is a schematic diagram for explaining an operation example of the display unit 2a shown in FIG. It is a block diagram showing an example of composition of indicator 2b concerning a 4th embodiment of the present invention. It is a mimetic diagram for explaining an example of operation of indicator 2b concerning a 4th embodiment of the present invention. It is a block diagram showing an example of composition of indicator 2c concerning a 5th embodiment of the present invention. It is a mimetic diagram for explaining an example of operation of indicator 2c concerning a 5th embodiment of the present invention. It is a mimetic diagram for explaining an example of operation of indicator 2c concerning a 5th embodiment of the present invention.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

<First embodiment>
FIG. 1 is a block diagram illustrating a basic configuration of an image display device 101 according to the first embodiment of the present invention. The image display device 101 illustrated in FIG. 1 includes a display unit 102 and a control unit 103. The display unit 102 includes a plurality of power lines 104 and a plurality of pixels 105. Each pixel 105 includes a driving transistor 106 and a self-luminous display element 107. The self-luminous display element 107 is connected to the power supply line 104 via the driving transistor 106.

  The drive transistor 106 is a field-effect transistor having a drain, a source, and a gate, and is, for example, a TFT. The driving transistor 106 has one of a drain and a source connected to one of the plurality of power supply lines 104, and the other of the drain and the source connected to one terminal of the self-luminous display element 107. Note that FIG. 1 illustrates a configuration of the pixel 105 in which the self-luminous display element 107 is connected to the power supply line 104 through the driving transistor 106. The form connected to the power supply line 104 may be sufficient. In FIG. 1, the connection between the other terminal of the self-luminous display element 107 and the other terminal (for example, a ground line) of the power supply line 104 (not shown) is omitted.

  The self-luminous display element 107 is an element that emits light when a predetermined voltage is applied and a predetermined current flows, and is, for example, an organic light-emitting diode.

  The control unit 103 determines, based on an input image signal (also referred to as a video signal), a variation in load among the plurality of drive transistors 106 that occurs when the image signal is displayed, in one or a plurality of frame units, and A correction signal for correcting each of the 105 is generated. The image signal is a signal representing an image displayed by the plurality of pixels 105, and is a signal representing the luminance of each pixel 105, for example. In this embodiment, the luminance of each pixel 105 can be controlled by changing the gate voltage of each drive transistor 106 of each pixel 105. Therefore, the voltage applied to the gate of each drive transistor 106 changes according to the image signal.

  The above-described variation in load is a statistical variation in electrical load applied to the plurality of driving transistors 106, and corresponds to, for example, a range of each voltage value applied to each gate of the plurality of driving transistors 106. When a plurality of pixels 105 display an image of one frame, for example, based on the image signal, the variation in load between the plurality of drive transistors 106 that occurs when displaying an image signal means that each of the pixels 105 in the frame has This corresponds to the range of the voltage applied to the gate of the driving transistor 106.

  The correction signal for correcting the variation of the load in one or a plurality of frames and for each pixel 105 refers to a range of the electrical load applied to each drive transistor 106 when displaying an image signal. This signal is a signal for instructing a voltage (load voltage) applied to each gate of each drive transistor 106 for each pixel 105 in order to reduce the width. For example, when displaying an image signal, it is assumed that a high gate voltage is applied to a certain driving transistor 106 and a low gate voltage is applied to a certain driving transistor 106 in a certain frame. In this case, for example, the correction signal instructs the drive transistor 106 to which the high gate voltage has been applied to apply a low gate voltage in the next frame, and the next to the drive transistor 106 to which the low gate voltage has been applied. Is a signal instructing the application of a high gate voltage in the frame of FIG. When correcting the variation in load in units of a plurality of frames, a correction signal can be generated as follows. That is, for example, the correction signal is set so that the load accumulated by displaying the image signal in a plurality of frames and the total value of the loads applied in one or more frames based on the correction signal are equal among the pixels 105. Can be generated.

  The control unit 103 can generate a correction signal by, for example, inverting the gray level of each luminance value of each pixel represented by the image signal for each pixel. Alternatively, the control unit 103 can generate a correction signal according to each voltage value applied to each gate of each drive transistor 106 based on the image signal.

  In the present embodiment, when applying a voltage based on an image signal to each gate of the plurality of driving transistors 106, the control unit 103 connects the plurality of power lines 104 so that the self-luminous display element 107 can emit light. Control. When applying a voltage based on the correction signal to each gate of the plurality of drive transistors 106, the control unit 103 controls the plurality of power supply lines 104 so that the self-luminous display element 107 cannot emit light. The control unit 103 controls the state of the plurality of power lines 104 by outputting a power line control signal to the display unit 102. The power supply line control signal indicates whether the power supply line 104 can be energized from the power supply line 104 to the self-luminous display element 107 via the drive transistor 106 or the power supply line 104 cannot be energized for each power supply line 104 or for each power supply line 104. It is a signal that instructs the power supply line 104 in common. In the present embodiment, the control unit 103 controls the state of the power supply line 104 so that the power supply line 104 can supply electricity to the self-luminous display element 107 via the drive transistor 106, and outputs the image signal to the gate of the drive transistor 106. Control to apply a voltage based on the control signal. Alternatively, the control unit 103 controls the state of the power supply line 104 so that power cannot be supplied from the power supply line 104 to the self-luminous display element 107 via the drive transistor 106, and applies a voltage based on the correction signal to the gate of the drive transistor 106. The application control is performed. That is, in the present embodiment, each light-emitting display element 107 emits light in response to an image signal, but each light-emitting display element 107 does not emit light in response to a correction signal. The correction signal is a signal for applying a load to each gate of each drive transistor 106 without causing each light-emitting display element 107 to emit light.

  In addition, the control unit 103 executes control for applying a voltage based on an image signal and control for applying a voltage based on a correction signal alternately in units of one or a plurality of frames and for each pixel 105.

  Note that the control unit 103 performs control of voltage application based on the image signal, control of voltage application based on the correction signal, and control of the state of the plurality of power lines 104 for all the pixels 105 in each frame. It may be performed uniformly or differently. That is, when displaying an image, in the same frame, all the pixels 105 may be in a display state based on the image signal, or only some of the pixels 105 may be in a display state based on the image signal, and the remaining pixels 105 may be displayed. May be applied to the load voltage based on the correction signal (non-display state).

  The state of the power supply line 104 in which power can be supplied from the power supply line 104 to the self-luminous display element 107 via the driving transistor 106 is as follows. In other words, when the power supply line 104 is connected to a voltage source having a polarity and a voltage that allow the self-luminous display element 107 to emit light when the driving transistor 106 is turned on, and having a predetermined output impedance or less. is there. The polarity and voltage that can be in the light emitting state are, for example, a polarity corresponding to the forward voltage and a voltage larger than the forward voltage (threshold voltage) when the self-luminous display element 107 is an organic light emitting diode. Further, a voltage source having a predetermined output impedance or less means a voltage source capable of securing a predetermined voltage value or more to each self-luminous display element 107 and supplying a sufficient conduction current. The state of the power supply line 104 in which power cannot be supplied from the power supply line 104 to the self-luminous display element 107 via the driving transistor 106 is as follows. That is, a state in which a voltage source having a polarity opposite to the polarity that can be in a light emitting state is connected to the power supply line 104, or a voltage source having an output voltage that is forward in polarity but smaller than the forward voltage is connected to the power supply line 104. The state is a state where a switch or the like inserted between the voltage source and the power supply line 104 is cut off, or a state where a voltage source having a predetermined output impedance or less is not connected.

  In the present embodiment, the control unit 103 can, for example, alternately control the plurality of power lines 104 in one or a plurality of frame units to the following two states. That is, one state is a state in which the control unit 103 controls the plurality of power lines 104 so that all the pixels 105 can supply electricity to the self-luminous display element 107 from the power line 104 via the driving transistor 106. The other state is a state in which the control unit 103 controls the power supply line 104 so that no power can be supplied to the self-luminous display element 107 from the power supply line 104 via the driving transistor 106 for all the pixels 105. Then, the control unit 103 selects a voltage to be applied to the gate of the driving transistor 106 for each pixel 105 so as to be in one of the following states. That is, the control unit 103 controls the state of the power supply line 104 so that the power supply line 104 can supply electricity to the self-luminous display element 107 via the drive transistor 106, and applies a voltage based on the image signal to the gate of the drive transistor 106. . Alternatively, the control unit 103 controls the state of the power supply line 104 so that the power supply line 104 cannot supply electricity to the self-luminous display element 107 via the drive transistor 106, and applies a voltage based on the correction signal to the gate of the drive transistor.

  Further, in the present embodiment, the control unit 103 can alternately control the plurality of power lines 104 in the following two states in units of one or a plurality of frames, for example. That is, on the other hand, the control unit 103 controls the state of the power supply line 104 so that a part of each pixel 105 can be energized from the power supply line 104 to the self-luminous display element 107 via the driving transistor 106, and controls the state of each pixel 105. The state of the power supply line 104 can be controlled so that the remaining part cannot be energized. On the other hand, the state of the power supply line 104 is controlled so that the part of the power supply line 104 cannot be energized to the self-luminous display element 107 via the drive transistor 106, and the state of the power supply line 104 is controlled so that the remaining part can be energized. Can be controlled. Then, the control unit 103 selects a voltage to be applied to the gate of the driving transistor 106 for each pixel 105 so as to be in one of the following states. That is, the control unit 103 controls the state of the power supply line 104 so that the power supply line 104 can supply electricity to the self-luminous display element 107 via the drive transistor 106, and applies a voltage based on the image signal to the gate of the drive transistor 106. . Alternatively, the control unit 103 controls the state of the power supply line 104 so that the power supply line 104 cannot supply current to the self-luminous display element 107 via the drive transistor 106, and applies a voltage based on the correction signal to the gate of the drive transistor 106. .

  As described above, according to the present embodiment, in each pixel 105, normal display by an image signal and application of a load to the drive transistor 106 by a correction signal are alternately performed in one frame unit or a plurality of frame units. can do. At this time, the application of the load to the driving transistor 106 by the correction signal is performed in a state where the power supply line 104 is controlled so that the self-luminous display element 107 does not display. In this case, since a non-light emitting period is provided between the image signals, it is possible to obtain a moving image blur suppression effect by the pseudo impulse drive. Further, the correction signal is generated based on the image signal without performing processing such as measurement of the threshold voltage. Therefore, the configuration is not complicated. As described above, according to the present embodiment, it is possible to correct the variation in the load of the driving transistor without complicating the configuration and without deteriorating the display quality during image display.

<Second embodiment>
Next, a second embodiment of the present invention will be described with reference to FIGS. FIG. 2 is a block diagram illustrating a configuration example of the image display device 1 according to the second embodiment of the present invention. FIG. 3 is a block diagram showing a configuration example of the display unit 2 shown in FIG. FIG. 4 is an equivalent circuit diagram showing a configuration example of the pixel PX shown in FIG. The image display device 1 shown in FIG. 2 includes a display unit 2, a signal output unit 3, and a signal conversion unit 4.

  In the image display device 1 shown in FIG. 2, the display unit 2 has a configuration corresponding to the display unit 102 of the first embodiment shown in FIG. A combination of the signal output unit 3 and the signal conversion unit 4 shown in FIG. 2 or a combination of the power supply line control unit 24 shown in FIG. 3 is added to the control unit 103 of the first embodiment shown in FIG. Corresponding.

  The signal conversion unit 4 includes a correction signal generation unit 41 and a storage unit 42. The storage unit 42 stores the input image signal for one or a plurality of frames. The correction signal generation unit 41 generates a correction signal based on one or more frames of image signals stored in the storage unit 42. Similar to the first embodiment, the correction signal is generated by inverting the luminance value of the image signal in gradation, or is generated based on the value of the gate voltage supplied to the driving TFT based on the image signal. be able to.

  The signal output unit 3 inputs the image signal input to the signal conversion unit 4 and the correction signal output from the correction signal generation unit 41. The signal output unit 3 combines, for example, the image signal of the current frame and the correction signal generated based on the image signal of the past frame such as the previous one by time division, and displays the combined signal on the display unit 2. Output to Hereinafter, a signal obtained by combining the image signal and the correction signal in a time-division manner is also referred to as an image signal / correction signal. The signal output unit 3 outputs a power supply line control signal to the display unit 2 in synchronization with a composite signal of the image signal and the correction signal. The power line control signal is a signal corresponding to the power line control signal of the first embodiment shown in FIG. 1, and is used to control the power line in the display unit 2 to a state corresponding to a light emitting state or a non-light emitting state. Signal.

  As shown in FIG. 3, the display unit 2 includes a display panel 21, a gate line driving unit 22, a data line driving unit 23, and a power line control unit 24. The display panel 21 includes a plurality of (n × m) pixels PX arranged in a matrix of n rows × m columns. The display panel 21 has a plurality (m) of power lines (power lines) PL1, PL2,..., Plm, and a plurality (n) of gate lines (gate lines) GL1, GL2,. A plurality of (m) data lines (data lines) DL1, DL2,..., DLm are provided. The power lines PL1, PL2,..., Plm are connected to the output of the power line controller 24 via a common power line PL0. The gate lines GL1, GL2,..., GLn are connected to n outputs of the gate line driving unit 22. The data lines DL1, DL2,..., DLm are connected to m outputs of the data line driving unit 23.

  Each pixel PX shown in FIG. 3 has the configuration shown in FIG. FIG. 4 is an equivalent circuit diagram illustrating a configuration example of each pixel PX. The pixel PX shown in FIG. 4 includes an EL element (electroluminescence element) ELD such as an OLED, a driving TFT (TFT2), a selection TFT (TFT1), and a storage capacitor Cs. The gate of the selection TFT (TFT1) is connected to the gate line GLi connected to the gate line driving unit 22, and the drain is connected to the data line DLi connected to the data line driving unit.

  In each pixel PX, the EL element ELD is connected to the power supply line PLi via the driving TFT (TFT2). The gate of the driving TFT (TFT2) is connected to the data line DLi via the selection TFT (TFT1). The storage capacitor Cs holds the voltage Vsi applied from the data line DLi to the gate of the driving TFT (TFT2) via the selection TFT (TFT1).

  The source of the selection TFT (TFT1) is connected to the gate of the driving TFT (TFT2) and the storage capacitor Cs. The drain of the driving TFT (TFT2) is connected to the anode electrode of the EL element ELD, and the source is connected to the power supply line PLi. When the driving TFT (TFT2) is turned on (on), a driving potential (Vcc-Vcath) is applied to the EL element ELD, and the EL layer emits light by recombination of holes and electrons injected into the EL element ELD.

  4, power supply line PLi corresponds to any of power supply lines PL1 to PLm shown in FIG. Gate line GLi corresponds to any of gate lines GL1 to GLn shown in FIG. Data line DLi corresponds to any of data lines DL1 to DLm shown in FIG. The power supply line PLi is applied with a voltage Vcc having a predetermined forward voltage value that can supply current to the EL element ELD during light emission control, and a forward low voltage or voltage that cannot supply current to the EL element ELD during non-light emission control. A voltage Vcc of a predetermined voltage in the reverse direction is applied. The voltage Vcath is a cathode voltage of the EL element ELD. When the driving TFT (TFT2) is turned on, a potential having a difference between the voltage Vcc and the voltage Vcath is applied to the EL element ELD.

  In the pixel PX shown in FIG. 4, a predetermined gate voltage Vgi (voltage Von) is applied to the selection TFT (TFT1) during the gate selection period. Gate voltage Vgi corresponds to any of voltages Vg1 to Vgn of gate lines GL1 to GLn shown in FIG. This selection period is one time / one frame, and ON Duty (on duty) is determined by the ratio of 1 / the number of scanning lines. The gate voltage Vsi is applied to the driving TFT (TFT2) until the next selection period by the electric charge supplied to the storage capacitor Cs when the selection TFT (TFT1) is turned on.

  The driving TFT (TFT2) has a longer gate voltage stress application time than the selection TFT (TFT1), and the gate voltage stress is applied in all periods. Therefore, deterioration of the TFT characteristics (shift of the threshold voltage Vth) is greatly promoted as compared with the selection TFT. Since the potential Vsi of the image signal supplied from the data line DLi differs for each image, the gate voltage stress of the driving TFT (TFT2) depends on the use conditions. This potential Vsi corresponds to any of voltages Vs1 to Vsm of data lines DL1 to DLn shown in FIG. For example, when the threshold voltage Vth in the TFT characteristics of the n-channel TFT shifts in the positive direction, the current supplied from the driving TFT to the EL element ELD decreases, and the light emission luminance decreases. When used for a long time, the difference in deterioration of each driving TFT (TFT2) accumulated according to the image signal becomes large, and a luminance difference (unevenness, burn-in) occurs on the screen.

  On the other hand, the gate line driving unit 22 shown in FIG. 3 sequentially scans a plurality of gate lines GL1, GL2,..., GLn in synchronization with a predetermined clock signal, and outputs the voltages Vg1, GL2,. , Vgn are set to a voltage Von for turning on the selection transistors TFT1 connected to the gate lines GL1, GL2,..., GLn for a predetermined period.

  The data line driving unit 23 receives the composite signal of the image signal and the correction signal output from the signal output unit 3 shown in FIG. 2 and inputs the combined signal to the corresponding pixel PX so that the gate lines GL1, GL2,. The data is distributed to a plurality of data lines DL1, DL2,..., DLm and output in synchronization with the scanning timing of GLn.

  The power line control unit 24 controls the states of the power lines PL0 to PLm according to the power line control signal output from the signal output unit 3 shown in FIG. The power supply line control unit 24 controls the state of the output voltage Vcc according to the power supply line control signal. When the power supply line control signal indicates the light emission state, the power supply line control unit 24 controls the voltage Vcc of the power supply line PL0 to a voltage that can supply electricity to the EL element ELD and has a predetermined voltage value in the forward direction. When the power supply line control signal indicates the non-light-emitting state, the power supply line control unit 24, for example, changes the voltage Vcc of the power supply line PL0 to a forward low voltage having a predetermined voltage value that cannot be supplied to the EL element ELD or has a predetermined voltage value. Control is performed to a voltage having a predetermined voltage value in the reverse direction.

  Next, an example of generating a correction signal in the signal conversion unit 4 will be described. The signal conversion unit 4 records the correction signal in the image signal of the previous frame period in the storage unit 42, and the correction signal generation unit 41 executes a predetermined conversion process based on the pixel data recorded in the storage unit 42. Generate. One example of the conversion process is a gradation inversion process. In this case, the correction signal generation unit 41 generates a correction signal by directly converting the luminance data of the image signal. An example of the conversion formula is as follows. That is, if the RGB value (R, G, B) of the image signal is (r, g, b) (where r, g, b are integers from 0 to 255), the RGB value (R ′) of the correction signal , G ′, B ′) = (255-r, 255-g, 255-b). FIG. 5A shows an example of an image signal (an image based on the image signal), and FIG. 5B shows a distribution of gradation values. FIG. 6A shows a grayscale inversion signal (image based on the grayscale inversion signal) obtained by grayscale inversion of the image signal shown in FIG. 5A, and FIG. 6B shows a grayscale value distribution. FIGS. 5B and 6B show, as an example, the distribution of the gradation value of r among the gradation values (r, g, b). Here, in FIG. 5B and FIG. 6B, the distribution of the gradation values of g and b is not shown, but the same distribution can be extracted. This is because the distribution of the gradation values is correlated with the luminance data, the voltage applied to the driving TFT, and the current value flowing through the light emitting element for the element.

  Next, an operation example of the image display device 1 shown in FIG. 2 and the display unit 2 shown in FIG. 3 will be described with reference to FIG. FIG. 7 is a diagram schematically showing the display unit 2 shown in FIG. 3 assuming that the number of pixels PX is 16, and the left side of the arrow AR1 shows a display state of each pixel PX of a 2N-1 (odd number) frame. The right side of the arrow AR1 indicates the display state of each pixel PX of the 2N (even number) frame. Here, N is an integer. The pixel PX marked “R” is displaying an image signal. The pixel PX marked “C” is in a state in which a voltage corresponding to the correction signal is applied to the gate of the driving TFT (TFT2) and the power supply line PLi is controlled to a non-display state. In the present embodiment, an image signal and a correction signal are supplied from the signal output unit 3 to the display unit 2 for each frame. That is, in the 2N-1 frame, an image signal is supplied to each pixel PX, and in the 2N frame, a correction signal generated according to the 2N-1 image signal is supplied. The signal output unit 3 generates a power line control signal so as to synchronize the timing of the image signal / correction signal with the current supply / non-supply of the power line PLi, and outputs the signal to the display unit 2. That is, in the 2N-1 frame, the voltage Vcc is controlled so that current can be supplied to each pixel PX, and in the 2N frame, the voltage Vcc is controlled so that current cannot be supplied to each pixel PX.

  Referring to FIG. 4, in the present embodiment, on the other hand, in the case of 2N-1 frame, the gate line GLi, the data line DLi, the power supply line PLi, the selection TFT (TFT1), the driving TFT (TFT2), and the storage capacitor Cs , The EL element ELD operates in a desired state, and outputs and displays the image signal R. On the other hand, in the case of the 2N frame, no current is supplied to the power supply line PLi (or a voltage of the opposite polarity is applied), and the correction signal C based on the image signal R of the previous frame (2N-1) is supplied to the data line DLi. Is done. In this case, by providing a non-light emitting period in the entire screen, pseudo impulse driving is performed, and the moving image quality can be improved.

  Here, effects of the second embodiment will be described with reference to FIGS. FIG. 8 is a schematic diagram illustrating an example of a display pattern on the display panel 21 used in the description. The display area on the display panel 21 shown in FIG. 8 includes a bright display area A1 and a dark display area A2. In this case, the drive TFT (TFT2) of the pixel PX corresponding to the bright display area A1 deteriorates quickly, and the drive TFT (TFT2) of the pixel PX corresponding to the dark display area A2 deteriorates slowly. 9 and 10 are diagrams schematically showing a change in luminance between the display area A1 and the display area A2, with the horizontal axis representing time t and the vertical axis representing luminance level Lv. FIG. 9 shows a case where no load is applied by the correction signal, and FIG. 10 shows a case where the load is applied by the correction signal according to the present embodiment. As shown in FIG. 9, when the load is not applied by the correction signal, the luminance change in the display area A1 and the luminance change in the display area A2 have different characteristics. In this case, the brightness of the display area A1 and the brightness of the display area A2 in a time T1 shorter than the time T0 with respect to a time T0 (normal product life due to half the brightness) until the brightness level Lv is reduced to half of the initial level 100. The difference in luminance increases, and the display unevenness increases. On the other hand, as shown in FIG. 10, when the load is applied by the correction signal according to the present embodiment, the luminance change in the display area A1 and the luminance change in the display area A2 have similar characteristics. In this case, the difference between the brightness of the display area A1 and the brightness of the display area A2 is kept small until the time T0 (normal product life due to half the brightness), and the display unevenness does not increase.

  According to the present embodiment, a voltage based on the image signal and the correction signal is applied to the gate of the driving TFT (TFT2) in the mutually adjacent frame periods, thereby reducing the luminance deterioration variation (the range of the TFT threshold distribution) of the entire screen. can do. As a result, excellent display quality without luminance unevenness or image sticking can be maintained even when used for a long time. In particular, it is possible to suppress a decrease in display quality when a still image is displayed.

  Further, since the pixel PX applying the correction signal to the driving TFT (TFT2) is in a non-light emitting state, the correction process can be executed in a display state without giving a sense of incongruity to the user.

  In addition, by providing a period of a non-light emitting state to the user, pseudo impulse driving is performed, an effect of reducing moving image blur can be obtained, and moving image response performance can be improved.

  Note that the second embodiment can be modified as follows, for example. That is, in the description with reference to FIG. 7, the image signal and the correction signal are supplied alternately in successive frames. However, the present invention is not limited to this, and the correction signal may be calculated from image signals of several frames.

  Further, the calculation of the correction signal is not limited to the generation by the grayscale inversion, and the correction amount may be calculated from the voltage value supplied to each driving TFT (TFT2). In this case, the present invention can be applied to not only pixels composed of RGB pixels but also pixels composed of RGBW pixels.

  Further, the frame frequency f1 when the correction signal is applied and the frequency f2 when the correction signal is not applied may be changed according to the image signal. For example, the frequency f1 can be a frequency f2 × 2. Specifically, for example, the frequency f2 when no correction signal is applied can be 60 Hz, and the frequency f1 when the correction signal is applied can be 120 Hz. When the correction signal is applied, the frame frequency looks large due to the influence of the correction period. Therefore, by adjusting the frequency, the difference between the application of the correction signal and the non-application of the correction signal is inconspicuous and natural.

  As described above, in the image display device 1 according to the second embodiment, the signal conversion unit 4 reduces the variation in load between a plurality of driving TFTs (TFT2) generated when displaying an image signal based on the image signal. Alternatively, a correction signal for performing correction in units of a plurality of frames and for each pixel PX is generated. Further, the signal output unit 3 controls so that the voltage based on the image signal or the voltage based on the correction signal is sequentially selected in units of one or a plurality of frames and supplied to the plurality of data lines DL1 to DLm. In addition, the signal output unit 3 controls the plurality of power lines PL1 to PLm so that the EL element ELD can be energized in synchronization with the voltage selection period based on the image signal, and outputs the voltage based on the correction signal. The plurality of power supply lines PL1 to PLm are controlled so that the self-luminous display element cannot be energized in synchronization with the selection period. With these controls, the signal output unit 3 alternately applies a voltage based on an image signal to the gate of the driving TFT (TFT2) for each pixel PX in a state where the EL element ELD can be energized in units of one or a plurality of frames. Alternatively, control is performed to apply a voltage based on the correction signal to the gate of the driving TFT (TFT2) for each pixel PX in a state where the EL element ELD cannot be energized. Further, the correction signal is generated based on the image signal without performing processing such as measurement of the threshold voltage. Therefore, according to the second embodiment, it is possible to correct the variation in the load of the driving TFT during image display without complicating the configuration.

  In the image display device 1 according to the second embodiment, the power supply line control unit 24 alternately performs one or a plurality of frame units for all the pixels PX based on the power supply line control signal output from the signal output unit 3. The plurality of power supply lines PL1 to PLm are controlled so that the EL element ELD can be energized, or the plurality of power supply lines PL1 to PLm are controlled such that the EL element ELD cannot be energized for all the pixels PX. can do. According to this configuration, since a non-light emitting period is provided between the image signals, it is possible to obtain an effect of suppressing blurring of a moving image by pseudo impulse driving.

<Third embodiment>
Next, a third embodiment of the present invention will be described with reference to FIGS. FIG. 11 is a block diagram illustrating a configuration example of a display unit 2a according to the third embodiment of the present invention. FIG. 12 is a schematic diagram for explaining an operation example of the display unit 2a shown in FIG.

  The configuration of the image display device according to the third embodiment is basically the same as the image display device 1 according to the second embodiment shown in FIG. However, the configuration of the display unit 2 shown in FIGS. 2 and 3 is different from the configuration of the image signal / correction signal and the power supply line control signal supplied to the display unit 2 shown in FIGS.

  As shown in FIG. 11, the display unit 2a according to the third embodiment includes a power line control unit 24a instead of the power line control unit 24 shown in FIG. The difference is that a power supply line PLo0 and a power supply line PLe0 are provided instead. In FIGS. 3 and 11, the same components are denoted by the same reference numerals.

  The power supply line control unit 24a illustrated in FIG. 11 supplies two systems of power to each pixel PX using the power supply line PLo0 and the power supply line PLe0. The power line PLo0 is connected to the odd-numbered power lines PL1, PL3,. The power supply line PLe0 is connected to the power supply lines PL2, PL4,. In the example shown in FIG. 11, it is assumed that the power supply line PLm is an even-numbered column (m is an even number). The power supply line control unit 24a emits light in accordance with the power supply line control signal supplied from the signal output unit 3 shown in FIG. 2 to indicate the state of the power supply line PLo0 common to the odd-numbered columns and the state of the power supply line PLe0 common to the even-numbered columns. The state and the non-light emitting state are alternately controlled. That is, when one of the power supply line PLo0 and the power supply line PLe0 is controlled to emit light, the other is controlled to emit no light.

  In the display unit 2a of the third embodiment shown in FIG. 11, the power supply lines PL1 to PLm are arranged along the data lines DL1 to DLm, and the voltage Vcc_o of the odd-numbered power supply lines PL1, PL3,. , And the voltage Vcc_e of the power lines PL2, PL4,... Can be individually controlled by the power line control unit 24a.

  In the third embodiment, a correction signal for one frame is generated from an image signal for one frame by the signal conversion unit 4 (FIG. 2), and a correction signal for two frames is generated by the signal output unit 3 (FIG. 2). A composite signal with the signal is generated. In this case, the composite signal of one of the two frames is sent to the image signal corresponding to the pixel PX connected to the odd-numbered data lines DL1, DL3,... And the even-numbered data lines DL2, DL4,. This is a signal in which correction signals corresponding to the connected pixels PX are arranged. The combined signal of the other frame includes a correction signal corresponding to the pixel PX connected to the odd-numbered data lines DL1, DL3,... And a pixel PX connected to the even-numbered data lines DL2, DL4,. Is a signal obtained by arranging image signals corresponding to.

  In the third embodiment, as shown for 16 pixels PX in FIG. 12, in the 2N-1 frame (N: integer) shown on the left of the arrow AR2, current is supplied to the odd-numbered power lines PL1 and PL3. However, no current is supplied to power supply lines PL2 and PL4 in the even columns. The image signal R is supplied to the odd-numbered data lines DL1 and DL3, and the correction signal C is supplied to the even-numbered data lines DL2 and DL4. On the other hand, in the 2N frame shown to the right of arrow AR2, current is not supplied to power supply lines PL1 and PL3 in odd columns, but current is supplied to power supply lines PL2 and PL4 in even columns. Further, the correction signal C is supplied to the data lines DL1 and DL3 in the odd columns, and the image signal R is supplied to DL2 and DL4 in the even columns.

  In the present embodiment, since there is a pixel PX that contributes to display in any frame period, it is possible to reduce a sense of discomfort due to a non-light emitting period during input of a correction signal.

  As described above, in the third embodiment, the plurality of pixels PX, the plurality of gate lines GL1 to GLn lines, and the plurality of data lines DL1 to DLm are arranged in a matrix, and each of the power supply lines PL1 to PLm are arranged along the data lines DL1 to DLm arranged in a column. In each frame, the signal output unit 3 selects one of the voltage based on the image signal or the voltage based on the correction signal and supplies the selected voltage to the plurality of data lines DL1, DL3,. By generating the image signal / correction signal so that the other of the voltage based on the signal or the voltage based on the correction signal is selected and supplied to the plurality of data lines DL2, DL4,. Control. Further, the signal output unit 3 controls the image so that the voltage based on the image signal or the voltage based on the correction signal supplied to each column of the data lines DL1, DL2, DL3, DL4,... The display unit 2a is controlled by generating a signal / correction signal. Also, the signal output unit 3 is configured such that in each frame, the states of the odd-numbered power lines PL1, PL3,... And the even-numbered power lines PL2, PL4,. , PL2, PL3, PL4,... Alternately differ in the unit of one frame to control the power line control unit 24a. By performing these controls, the signal output unit 3 alternately applies a voltage based on the image signal to the gate of the driving TFT (TFT2) for each pixel PX in a state where the EL element ELD can be energized in units of one frame. Alternatively, control is performed to apply a voltage based on the correction signal to the gate of the driving TFT (TFT2) for each pixel PX in a state where the EL element ELD cannot be energized. Further, the correction signal is generated based on the image signal without performing processing such as measurement of the threshold voltage. Therefore, according to the third embodiment, it is possible to correct the variation in the load of the driving TFT during image display without complicating the configuration. Further, in the present embodiment, since there is a pixel PX that contributes to display in any frame period, it is possible to reduce a sense of discomfort due to a non-light emitting period while a correction signal is input.

<Fourth embodiment>
Next, a fourth embodiment of the present invention will be described with reference to FIGS. FIG. 13 is a block diagram illustrating a configuration example of a display unit 2b according to the fourth embodiment of the present invention. FIG. 14 is a schematic diagram for explaining an operation example of the display unit 2b shown in FIG. 13 in the fourth embodiment. The configuration of the image display device according to the fourth embodiment is basically the same as the image display device 1 according to the second embodiment shown in FIG. However, the configuration of the display unit 2 shown in FIGS. 2 and 3 is different from the configuration of the image signal / correction signal and the power supply line control signal supplied to the display unit 2 shown in FIGS.

  As shown in FIG. 13, the display unit 2b of the fourth embodiment has a power line control unit 24b instead of the power line control unit 24 shown in FIG. 3, and the display unit 2b has a power line PL0 shown in FIG. The difference is that a power supply line PLo0 and a power supply line PLe0 are provided instead. In FIGS. 3 and 13, the same components are denoted by the same reference numerals.

  The power line control unit 24b illustrated in FIG. 13 supplies two systems of power to each pixel PX using the power line PLo0 and the power line PLe0. Power supply line PLo0 is connected to odd-numbered power supply lines PL1,. The power supply line PLe0 is connected to the even-numbered power supply lines PL2,..., PLn. In the example shown in FIG. 13, it is assumed that the power supply line PLn is an even-numbered row (n is an even number). The power supply line control unit 24b emits light according to the power supply line control signal supplied from the signal output unit 3 shown in FIG. 2 to indicate the state of the power supply line PLo0 common to the odd-numbered rows and the state of the power supply line PLe0 common to the even-numbered rows. The state and the non-light emitting state are alternately controlled. That is, when one of the power supply line PLo0 and the power supply line PLe0 is controlled to emit light, the other is controlled to emit no light. The light emitting state and the non-light emitting state are inverted for each frame, for example.

  In the display unit 2b of the fourth embodiment shown in FIG. 13, the power supply lines PL1 to PLn are arranged along the gate lines GL1 to GLn, the voltage Vcc_o of the odd-numbered power supply lines PL1,. The voltages Vcc_e of the lines PL2,... Can be individually controlled by the power supply line control unit 24b.

  In the fourth embodiment, a correction signal for one frame is generated from an image signal for one frame by a signal conversion unit 4 (FIG. 2), and a correction signal for two frames is generated by a signal output unit 3 (FIG. 2). A composite signal with the signal is generated. In this case, the composite signal of one of the two frames is a signal in which image signals corresponding to the pixels PX in the odd rows and correction signals corresponding to the pixels PX in the even rows are alternately arranged. The composite signal of the other frame is a signal in which correction signals corresponding to the pixels PX in the odd rows and image signals corresponding to the pixels PX in the even rows are alternately arranged.

  In the fourth embodiment, current is supplied to the odd-numbered power supply lines PL1 and PL3 in the 2N-1 frame (N: integer) shown to the left of the arrow AR3, as shown in FIG. 14 for 16 pixels PX. However, no current is supplied to power supply lines PL2 and PL4 in even rows. Further, in accordance with the current supply / non-supply from the power supply lines PL1 to PL4, the data lines DL1 to DL4 alternately output the image signal R and the correction signal C in synchronization with the scanning timing of each row of the plurality of gate lines GL1 to GL4. And sequentially supplies them to each pixel PX. Also, in the 2N frame shown to the right of arrow AR3, no current is supplied to power lines PL1 and PL3 in odd rows, and current is supplied to power lines PL2 and PL4 in even rows. Further, in accordance with the current supply / non-supply from the power supply lines PL1 to PL4, the data lines DL1 to DL4 alternately synchronize the correction signal C and the image signal R in synchronization with the scanning timing of each row of the plurality of gate lines GL1 to GL4. And sequentially supplies them to each pixel PX.

  In the present embodiment, the calculation of the correction signal in the correction signal generator 41 (FIG. 2) may be calculated from the image signal data for each line using a line memory. In this case, a frame delay at the time of calculation can be suppressed.

  As described above, in the fourth embodiment, the plurality of pixels PX, the plurality of gate lines GL1 to GLn lines, and the plurality of data lines DL1 to DLm are arranged in a matrix, and each of the power supply lines PL1 to PLn are arranged along each of the gate lines GL1 to GLn arranged in a row. In addition, the signal output unit 3 alternately selects a voltage based on the image signal or a voltage based on the correction signal in synchronization with the scanning timing of each row of the plurality of gate lines GL1 to GLn, and applies a voltage to the plurality of data lines DL1 to DLm. The display unit generates the image signal / correction signal so that the voltage based on the image signal or the voltage based on the correction signal, which is supplied in synchronization with the scanning timing of each row, and alternately changes in units of one frame. 2b is controlled. Further, in each frame, the state of the odd-numbered power lines PL1, PL3,... And the even-numbered power lines PL2, PL4,. The power line control unit 24b is controlled by generating a power line control signal so that the states of PL2, PL3, PL4,... By performing these controls, the signal output unit 3 alternately applies a voltage based on the image signal to the gate of the driving TFT (TFT2) for each pixel PX in a state where the EL element ELD can be energized in units of one frame. Alternatively, control is performed to apply a voltage based on the correction signal to the gate of the driving TFT (TFT2) for each pixel PX in a state where the EL element ELD cannot be energized. Further, the correction signal is generated based on the image signal without performing processing such as measurement of the threshold voltage. Therefore, according to the fourth embodiment, it is possible to correct the variation in the load of the driving TFT during image display without complicating the configuration. Further, in the present embodiment, since there is a pixel PX that contributes to display in any frame period, it is possible to reduce a sense of discomfort due to a non-light emitting period while a correction signal is input.

<Fifth embodiment>
Next, a fifth embodiment of the present invention will be described with reference to FIGS. FIG. 15 is a block diagram illustrating a configuration example of a display unit 2c according to the fifth embodiment of the present invention. 16 and 17 are schematic diagrams for explaining an operation example of the display unit 2c shown in FIG. 15 in the fifth embodiment. The configuration of the image display device according to the fifth embodiment is basically the same as the image display device 1 according to the second embodiment shown in FIG. However, the configuration of the display unit 2c of the fifth embodiment is different from the configuration of the display unit 2 shown in FIGS. In addition, the configuration of the image signal / correction signal and the power supply line control signal supplied from the signal output unit 3 (FIG. 2) to the display unit 2c shown in FIG. The points are different.

  In the fifth embodiment, as shown in FIG. 15, power supply lines PL1 to PLm are arranged along data lines DL1 to DLm, and odd-numbered power supply lines PL1, PL3,. The applied voltage Vcc_o and the voltage Vcc_e applied via the even-numbered power lines PL2, PL4,..., Power line PLe0 can be individually controlled by the power line control unit 24b. Further, power supply lines PL1d, PL2d,..., PL (n-1) d, PLnd for applying the cathode voltage Vcath from the power supply line control unit 24b to the EL element ELD shown in FIG. 4 are arranged along the gate lines GL1 to GLn. Are arranged. , PL (n-1) d, PLnd among the power supply lines PL1d, PL2d,..., PL (n-1) d, and the voltage Vcath_o applied to the odd-numbered power supply lines PL1d,. And the voltage Vcath_e applied to the even-numbered power lines PL2d,..., PLnd via the power line PLe0d are individually controlled by the power line control unit 24c. In this configuration, each pixel PX in which the power supply lines PL1 to PLm and the power supply lines PL1d to PLnd are both in the current supply state is in the display state.

  In the fifth embodiment, the signal converter 4 (FIG. 2) generates three frames of correction signals from one frame of image signal, and the signal output unit 3 (FIG. 2) generates four frames of image signals. And a correction signal are generated. In this case, the combined signal of four frames is a signal in which the image signal R and the correction signal C are combined in a checkered pattern over four frames. Here, as shown in FIG. 16 and FIG. 17, the combined relationship of the four frames is such that the arrangement relationship between each pixel PX to which the image signal R is assigned and each pixel PX to which the correction signal C is assigned is every four adjacent pixels. Have a mutually interchangeable relationship.

  Next, an operation example of the display unit 2c illustrated in FIG. 15 will be described with reference to FIGS. FIGS. 16 and 17 show the upper left 16 pixels PX of the display unit 2c shown in FIG. FIG. 16 illustrates an example of an operation state of a 2N-1 frame (N: an integer) to the left of the arrow AR4, and illustrates an example of an operation state of the 2N frame to the right of the arrow AR4. FIG. 17 shows an example of the operation state of the 2N + 1 frame on the right of the arrow AR5, and shows an example of the operation state of the 2N + 2 frame on the right of the arrow AR6.

  In the fifth embodiment, in the 2N-1 frame, for example, as shown in FIG. 16, the power supply lines PL1 and PL3 in the odd columns are controlled to be in the current supply state, and the power lines PL2 and PL4 in the even columns are not supplied with current. It is controlled to the feeding state. Power supply lines PL1d and PL3d in odd rows are controlled to supply current, and power supply lines PL2d and PL4d in even rows are controlled to supply no current. Further, an image signal and a correction signal are alternately supplied to the odd-numbered data lines DL1 and DL3 in synchronization with the scanning timing of each row. On the other hand, the correction signal is supplied to the even-numbered data lines DL2 and DL4 in synchronization with the scanning timing of each row. Also, as shown in FIG. 16, in the 2N frame, the odd-numbered power lines PL1 and PL3 are controlled to supply current, and the even-numbered power lines PL2 and PL4 are controlled to supply no current. Power supply lines PL1d and PL3d in odd rows are controlled to supply no current, and power supply lines PL2d and PL4d in even rows are controlled to supply current. Further, the correction signal and the image signal are alternately supplied to the odd-numbered data lines DL1 and DL3 in synchronization with the scanning timing of each row. On the other hand, the correction signal is supplied to the even-numbered data lines DL2 and DL4 in synchronization with the scanning timing of each row.

  As shown in FIG. 17, at the time of 2N + 1 frame, power supply lines PL1 and PL3 in odd columns are controlled to supply no current, and power lines PL2 and PL4 in even columns are controlled to supply current. Power supply lines PL1d and PL3d in odd rows are controlled to supply current, and power supply lines PL2d and PL4d in even rows are controlled to supply no current. Further, a correction signal is supplied to the odd-numbered data lines DL1 and DL3 in synchronization with the scanning timing of each row. On the other hand, the image signal and the correction signal are alternately supplied to the even-numbered data lines DL2 and DL4 in synchronization with the scanning timing of each row. Further, as shown in FIG. 17, in the 2N + 2 frame, the power supply lines PL1 and PL3 in the odd-numbered columns are controlled to supply no current, and the power supply lines PL2 and PL4 in the even-numbered columns are controlled to supply current. Power supply lines PL1d and PL3d in odd rows are controlled to supply no current, and power supply lines PL2d and PL4d in even rows are controlled to supply current. Further, a correction signal is supplied to the odd-numbered data lines DL1 and DL3 in synchronization with the scanning timing of each row. On the other hand, correction signals and image signals are alternately supplied to the even-numbered data lines DL2 and DL4 in synchronization with the scanning timing of each row.

  As described above, in the fifth embodiment, the plurality of pixels PX, the plurality of gate lines GL1 to GLn, and the plurality of data lines DL1 to DLm are arranged in a matrix, and the power supply lines PL1 to PLm Are arranged along the data lines DL1 to DLm arranged in a column. The power supply lines PL1d to PLnd are arranged along the gate lines GL1 to GLn arranged in a row. The signal output unit 3 is supplied with an image signal or a correction signal in a predetermined frame unit, and supplies an image signal or a correction signal or a correction signal supplied to a plurality of data lines DL1, DL3,. The image signals / correction signals are arranged such that the arrangement of the voltages based on the signals is different from the arrangement of the correction signals supplied to the plurality of data lines DL2, DL4,. The display unit 2b is controlled by the generation. Further, the signal output unit 3 is configured such that the state of the odd-numbered power lines PL1, PL3,... And the state of the even-numbered power lines PL2, PL4,. Control the states of the lines PL1d, PL3d,... And the power lines PL2d, PL4d,... Of the even-numbered rows so that the EL elements ELD can or cannot be energized. Further, the display unit 2c is controlled so that the state of the power supply line of each column and each row is alternately changed in units of one frame, and the image signal / correction signal is generated in units of a predetermined frame. By performing these controls, the signal output unit 3 applies a voltage based on an image signal to the gate of the driving TFT (TFT2) for each pixel PX in a predetermined frame unit and in a state where the EL element ELD can be energized, or In addition, control is performed to apply a voltage based on the correction signal to the gate of the driving TFT (TFT2) for each pixel PX in a state where the EL element ELD cannot conduct electricity. Further, the correction signal is generated based on the image signal without performing processing such as measurement of the threshold voltage. Therefore, according to the fifth embodiment, it is possible to correct the variation in the load of the driving TFT during image display without complicating the configuration. Further, in the present embodiment, since there is a pixel PX that contributes to display in any frame period, it is possible to reduce a sense of discomfort due to a non-light emitting period while a correction signal is input.

  In the configuration example shown in FIG. 15, power supply lines PL1 to PLm are arranged in the column direction and power supply lines PL1d to PLnd are arranged in the row direction. However, the configuration is changed so that the column direction and the row direction are switched. You may.

  The embodiments of the present invention have been described in detail with reference to the drawings. However, the specific configuration is not limited to the embodiments, and includes a design and the like within a range not departing from the gist of the present invention. For example, a part of the configuration and a part of the operation of the first to fifth embodiments can be appropriately replaced or combined. Further, for example, the pattern of the power supply line may be controlled independently in accordance with the pattern for inputting the image signal and the correction signal, and is not limited to the above-described configuration and operation. In addition, for example, in the above, the embodiment of the present invention has been described with an example of an active matrix drive display using a self-luminous display element, but the present invention is also applied to a passive drive display using a self-luminous display element. be able to. The present invention relates to a self-luminous display and can be suitably applied to a transmissive self-luminous display (such as a transparent OLED). When applied to a transparent self-luminous display, the non-luminous period is in a transparent state, so that it is possible to provide a display quality in which both luminescent display information and a see-through state (transmissive state) are compatible. Further, the present invention can be suitably applied to a mirror type self-luminous display.

1, 101 Image display device 2, 2a, 2b, 2c, 102 Display unit 21 Display panel 24, 24a, 24b, 24c, Power line control unit 22 Gate line drive unit 23 Data line drive unit 3 Signal output unit 4 Signal conversion unit 41 correction signal generation unit 42 storage unit 103 control unit 104 power supply line 105, PX pixel 106 drive transistor 107 self-luminous display element TFT1 selection TFT
TFT2 drive TFT
Cs holding capacitor ELD EL elements PL0, PL1, PL2, PL3, PL4, PLm, PLo0, PLe0, PL1d, PL2d, PL3d, PL4d, PL (n-1) d, PLnd, PLo0d, PLe0d Power supply lines GL1, GL2, GL3 , GL4, GLn Gate lines DL1, DL2, DL3, DL4, DLm Data lines

Claims (13)

A display section having a plurality of pixels including a driving transistor and a self-luminous display element connected to a power supply line via the driving transistor;
The variation in load between a plurality of the driving transistor generated at the time of display of the image signal based on the image signal in one or more frames, and a correction signal for correcting for each of the pixels, the image signal The self-luminous display element is generated by inverting the brightness value of each pixel for each of the pixels , alternately in units of one or a plurality of frames, and for each of the pixels, from the power supply line via the drive transistor. Controlling the state of the power supply line so that power can be supplied to the drive transistor, and applying a voltage based on the image signal to the gate of the drive transistor, or the light-emitting display element from the power supply line via the drive transistor. To control the state of the power supply line so that power cannot be supplied to the drive transistor and to apply a voltage based on the correction signal to the gate of the drive transistor. An image display device and a part. The control unit includes:
Alternately in units of one or more frames,
Either controlling the state of the power supply line so that electricity can be supplied from the power supply line to the self-luminous display element through the drive transistor from the power supply line for all of the pixels, or controlling the drive transistor from the power supply line for all of the pixels By controlling the state of the power supply line so as not to energize the self-luminous display element through
For each of the pixels,
Applying a voltage based on the image signal to the gate of the drive transistor by controlling the state of the power supply line so that current can flow from the power supply line to the self-luminous display element via the drive transistor, or 2. A control for applying a voltage based on the correction signal to the gate of the drive transistor by controlling a state of the power supply line so that power cannot be supplied to the light emitting display element from the power supply line via the drive transistor. An image display device according to claim 1. The control unit includes:
Alternately in units of one or more frames,
Controlling the state of the power supply line so that a portion of each pixel can be energized from the power supply line to the self-luminous display element via the drive transistor through the drive transistor, and controlling the drive transistor from the power supply line for the remainder of each pixel Controlling the state of the power supply line so that power cannot be supplied to the self-luminous display element via the power supply line, or controlling the power supply so that power cannot be supplied to the self-luminous display element from the power supply line via the drive transistor for the part. By controlling the state of the power supply line so as to control the state of the line and to allow the remaining part to be energized from the power supply line to the self-luminous display element via the drive transistor,
For each of the pixels,
Applying a voltage based on the image signal to the gate of the drive transistor by controlling the state of the power supply line so that current can flow from the power supply line to the self-luminous display element via the drive transistor, or 2. A control for applying a voltage based on the correction signal to the gate of the drive transistor by controlling a state of the power supply line so that power cannot be supplied to the light emitting display element from the power supply line via the drive transistor. An image display device according to claim 1. 4. The image display device according to claim 1, wherein the correction signal is generated based on the image signal in accordance with a voltage value applied to each of the gates of each of the drive transistors. 5. A display section having a plurality of pixels including a driving transistor and a self-luminous display element connected to a power supply line via the driving transistor;
A correction signal was generated by inverting the brightness value of the image signal for each pixel, and the state of the power supply line was controlled so that current could be supplied from the power supply line to the self-luminous display element via the drive transistor. When applying a voltage based on the image signal to the gate of the drive transistor, when controlling the state of the power supply line so that it can not be energized from the power supply line to the self-luminous display element through the drive transistor, A control unit for performing control to apply a voltage based on the correction signal to the gate of the drive transistor. The control unit is configured to control a state of the power supply line, a state in which the self-luminous display element can be energized from the power supply line through the drive transistor, and a state of energizing the self-luminous display element through the drive transistor from the power line. 6. The image display device according to claim 5 , wherein control is performed alternately in one or a plurality of frame units when the state cannot be performed. A plurality of power lines, a plurality of gate lines, a plurality of data lines, and each of the plurality of power lines, one of the plurality of gate lines, and one of the plurality of data lines, respectively. A display unit having a plurality of pixels;
A control unit that controls a state of the plurality of power lines, a state of the plurality of gate lines, and a state of the plurality of data lines,
Each pixel has a self-luminous display element, a driving transistor for driving the self-luminous display element, a selection transistor, and a storage capacitor,
In each of the pixels,
The self-luminous display element is connected to any of the plurality of power lines via the drive transistor,
A gate of the driving transistor is connected to any of the plurality of data lines via the selection transistor,
The gate of the select transistor is connected to any of the plurality of gate lines,
The storage capacitor holds a voltage applied from the data line to the gate of the drive transistor via the select transistor,
The control unit includes:
The variation in load between said plurality of driving transistors formed during the display of the image signal based on the image signal in one or more frames, and a correction signal for correcting for each of the pixels, the image signal Is generated by inverting the brightness value of each pixel .
A voltage based on the image signal or a voltage based on the correction signal is sequentially selected in units of the one or more frames and controlled so as to be supplied to the plurality of data lines, and a voltage based on the image signal is selected. The plurality of power supply lines are controlled so that the self-luminous display element can be energized in synchronization with a period, and the self-luminous display element cannot energize in synchronization with a voltage selection period based on the correction signal. By controlling the plurality of power lines to be in a state,
Alternately applying the voltage based on the image signal to the gate of the drive transistor for each pixel in a state where the light-emitting display element can be energized, or the light-emitting display element An image display device that performs control for applying a voltage based on the correction signal to the gate of the drive transistor for each pixel in a state where no current can be supplied. The control unit includes:
Alternately in units of one or more frames,
The plurality of power lines are controlled so that the self-luminous display element can be energized for all the pixels, or the plurality of power lines are controlled such that the self-luminous display element cannot be energized for all the pixels. The image display device according to claim 7 , wherein the power supply line is controlled. The plurality of pixels, the plurality of gate lines, and the plurality of data lines are arranged in a matrix, and the power lines are arranged along the data lines in which the power lines are arranged in a column. hand,
The control unit includes:
In each of the frames, one of a voltage based on the image signal or a voltage based on the correction signal is selected and supplied to the plurality of data lines in an odd-numbered column, and a voltage based on the image signal or the correction signal. The other of the voltages based on is controlled to be selected and supplied to the plurality of data lines of an even column, and the voltage based on the image signal supplied to each column of the data lines or the voltage based on the While controlling so that the voltage based on the correction signal is alternately different for each frame,
In each frame, control is performed such that the state of the power lines in the odd columns and the state of the power lines in the even columns are different from each other, and the states of the power lines in each column are alternately different in units of the one frame. By that
Alternately applying the voltage based on the image signal to the gate of the drive transistor for each pixel in a state where the self-luminous display element can be energized, or the self-luminous display element cannot energize in the unit of one frame. The image display device according to claim 7 , wherein control is performed to apply a voltage based on the correction signal to the gate of the drive transistor for each pixel in the state. The plurality of pixels, the plurality of gate lines, and the plurality of data lines are arranged in a matrix,
The control unit includes:
The voltage based on the image signal or the voltage based on the correction signal is alternately selected in synchronization with the scanning timing of each row of the plurality of gate lines and supplied to the plurality of data lines, and the scanning of each row is performed. A voltage based on the image signal or a voltage based on the correction signal selected in synchronization with timing is controlled so as to be alternately changed in units of one frame,
Alternately applying the voltage based on the image signal to the gate of the drive transistor for each pixel in a state where the self-luminous display element can be energized, or the self-luminous display element cannot energize in the unit of one frame. The image display device according to claim 7 , wherein control is performed to apply a voltage based on the correction signal to the gate of the drive transistor for each pixel in the state. The plurality of pixels, the plurality of gate lines, and the plurality of data lines are arranged in a matrix,
The control unit includes:
In each of the frames, the arrangement of the voltage based on the image signal and the voltage based on the correction signal supplied to the odd-numbered data lines is supplied to the even-numbered data lines. The arrangement of the voltage based on the image signal and the voltage based on the correction signal is different, and the voltage based on the image signal or the voltage based on the correction signal is synchronized with the scanning timing of each row of the plurality of gate lines. A voltage based on the image signal or a voltage based on the correction signal, which is alternately selected and supplied to the plurality of data lines, and is selected in synchronization with the scanning timing of each row, in units of the plurality of frames. In addition to controlling them alternately,
Alternately applying the voltage based on the image signal to the gate of the drive transistor for each pixel in a state where the self-luminous display element can be energized, or the self-luminous display element cannot energize in a unit of the plurality of frames. The image display device according to claim 7 , wherein control is performed to apply a voltage based on the correction signal to the gate of the drive transistor for each pixel in the state. An apparatus for controlling a display unit having a plurality of pixels including a driving transistor and a self-luminous display element connected to a power supply line via the driving transistor,
The variation in load between a plurality of the driving transistor generated at the time of display of the image signal based on the image signal in one or more frames, and a correction signal for correcting for each of the pixels, the image signal The self-luminous display element is generated by inverting the brightness value of each pixel for each of the pixels , alternately in units of one or a plurality of frames, and for each of the pixels, from the power supply line via the drive transistor. Controlling the state of the power supply line so that power can be supplied to the drive transistor, and applying a voltage based on the image signal to the gate of the drive transistor, or the light-emitting display element from the power supply line via the drive transistor. To control the state of the power supply line so that power cannot be supplied to the drive transistor and to apply a voltage based on the correction signal to the gate of the drive transistor. The image display control device comprising a part. A method for controlling a display unit having a plurality of pixels including a driving transistor and a self-luminous display element connected to a power supply line via the driving transistor,
The control unit is configured to generate a correction signal for correcting a variation in load among the plurality of drive transistors generated at the time of displaying the image signal based on an image signal in units of one or more frames and for each pixel. The luminance value of the image signal is generated by inverting the gradation for each pixel , and is alternately performed in units of one or a plurality of frames, and for each pixel, from the power supply line via the driving transistor. The state of the power supply line is controlled so that the light-emitting display element can be energized, and a voltage based on the image signal is applied to the gate of the drive transistor, or the power supply line is connected to the drive transistor through the drive transistor. The state of the power supply line is controlled so as not to energize the self-luminous display element, and a voltage based on the correction signal is applied to the gate of the drive transistor. The image display control method for controlling that.