JP6745660B2 - Gate drive circuit - Google Patents

Description

The present invention relates to a gate drive circuit.

Conventionally, as a method of preventing a switching element such as a switching power supply or a motor driver from being accidentally turned on due to noise or the like when turned off, it is recommended to apply a negative voltage (negative bias) to the switching element when turned off. However, conventionally, there has been a tendency to be shunned because it is necessary to prepare a negative power source in addition to a gate drive circuit that applies a positive voltage.

Therefore, studies have been made on a configuration in which a negative voltage can be applied only by changing the gate drive circuit without adding a negative power source. Such a gate drive circuit is proposed in Patent Document 1, for example.

JP, 2013-26924, A

The gate drive circuit of Patent Document 1 is a circuit that drives the switching element on and off by applying a control signal from the control circuit to the gate of the switching element. More specifically, the gate drive circuit includes a parallel circuit including a first capacitor and a first resistor connected between the control circuit and the gate of the first switching element (drive target). A series circuit including a second capacitor, a second switching element, and a second resistor is connected in parallel to the parallel circuit. The anode of the diode is connected to the connection point between the second capacitor and the second switching element. The cathode of the diode and the gate of the second switching element are connected to the source of the first switching element.

With such a configuration, a negative voltage due to the charge accumulated in the first capacitor is applied to the gate of the first switching element in response to the OFF signal of the control signal, and the first switching element is turned off. Also, the first capacitor is discharged with the time constant of the parallel circuit. The second switching element is turned on when the charging voltage of the second capacitor is applied between the gate and the source. Therefore, the discharge circuit of the second capacitor is configured, and the negative voltage due to the discharge of the second capacitor is applied to the gate of the first switching element. By increasing the discharge time constant of the second capacitor, the first resistor, and the second resistor, a negative voltage can be stably applied to the first switching element.

In view of the above situation, it is an object of the present invention to provide a gate drive circuit having a novel configuration capable of applying a negative voltage to a switching element from the viewpoint of technology enrichment.

In order to achieve the above object, a gate drive circuit of the present invention includes a first capacitor and a pulse voltage generator connected in series to the gate terminal of a voltage-driven switching element,
A first resistor connected between the gate and source (emitter) of the switching element;
R1>>T/(C1+Ciss) (where R1: resistance value of the first resistor, C1: capacitance value of the first capacitor, Ciss: input capacitance of the switching element, T: switching cycle)
It is supposed that the condition such as the above is satisfied (first configuration).

Also, in the above-mentioned first configuration, further comprising a second resistor connected between both ends of the first capacitor,
VCC×C1/(C1+Ciss)>VCC×R1/(R1+R2) (where, VCC: High level of voltage generated by the pulse voltage generation unit, R2: resistance value of the second resistor)
Such a condition may be satisfied (second configuration).

In the first configuration, a second resistor connected across the first capacitor,
Further comprising a Zener diode and a first rectifying diode connected in series between the gate and source (emitter) of the switching element,
Vz<VCC×C1/(C1+Ciss) and Vz<VCC×R1/(R1+R2) (where VCC: High level of voltage generated by the pulse voltage generation unit, R2: resistance value of the second resistor, Vz: the above Sum of Zener voltage of Zener diode and forward voltage of the first rectifier diode)
Such a condition may be satisfied (third configuration).

In the third configuration, a third resistor connected in series with the Zener diode may be further provided between the gate and the source (emitter) of the switching element (fourth configuration).

In the first configuration, a Zener diode and a first rectifier diode connected in series between the gate and source (emitter) of the switching element,
A second capacitor and a second rectifier diode connected in series between the gate and source (emitter) of the switching element;
Further comprising a discharging resistor connected in parallel with the second capacitor,
VCC×C1/(C1+C2+Ciss)=Vz (where, VCC: High level of voltage generated by the pulse voltage generation unit, C2: capacitance value of the second capacitor, Vz: Zener voltage of the Zener diode and the first rectification) (Sum of diode forward voltage)
Such a condition may be satisfied (fifth configuration).

According to the present invention, a negative voltage can be applied to the gate when the switching element is off by the gate drive circuit having the novel structure. Further, by satisfying the above condition, it is possible to prevent the electric charge stored in the first capacitor and the input capacitance from being excessively discharged when the switching element is turned on or off.

FIG. 3 is a circuit configuration diagram of the gate drive circuit according to the first embodiment of the present invention. 6 is a graph showing an example of temporal behavior of a gate voltage by the gate drive circuit according to the first embodiment. It is the graph which expanded the saturation area|region in the graph of FIG. 2 temporally. It is a circuit block diagram of the gate drive circuit which concerns on the modification of 1st Embodiment. It is a circuit block diagram of the gate drive circuit which concerns on 2nd Embodiment of this invention. 9 is a graph showing an example of temporal behavior of a gate voltage by the gate drive circuit according to the second embodiment. 7 is a graph in which a saturation region in the graph of FIG. 6 is temporally enlarged. It is a circuit block diagram of the gate drive circuit which concerns on the modification of 2nd Embodiment. It is a circuit block diagram of the gate drive circuit which concerns on 3rd Embodiment of this invention. 11 is a graph showing an example of temporal behavior of a gate voltage by the gate drive circuit according to the third embodiment. 11 is a graph in which the saturation region in the graph of FIG. 10 is temporally enlarged. It is a circuit block diagram of the gate drive circuit which concerns on the modification of 3rd Embodiment. It is a circuit block diagram of the gate drive circuit which concerns on 4th Embodiment of this invention. It is a graph which shows an example of the time behavior of the gate voltage by the gate drive circuit concerning a 4th embodiment.

<First Embodiment>
An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit configuration diagram of a gate drive circuit according to the first embodiment. The gate drive circuit 1 shown in FIG. 1 is a circuit for driving the discrete switching element 10, and includes a pulse voltage generation unit 5, a first capacitor C1, and a first resistor R1.

The pulse voltage generator 5 outputs a binary voltage V1 (power supply voltage VCC or ground voltage GND) from its output terminal in accordance with the logic level of the control signal input to the pulse voltage generator 5 to output the gate of the switching element 10. Drive the terminals by voltage.

The first capacitor C1 is connected between the positive electrode side of the pulse voltage generator 5 and the gate terminal of the switching element 10. That is, the first capacitor C1 and the pulse voltage generator 5 are connected in series to the gate terminal of the switching element 10.

The switching element 10 is a voltage-driven semiconductor switching element that is switched by the gate drive circuit 1, and here, as an example, an N-channel MOSFET (MOS field effect transistor) M1 is used. The semiconductor switching element is made of a semiconductor material such as Si, SiC, or GaN. The switching element 10 may be an IGBT (insulated gate bipolar transistor) (in this case, “source” described below is replaced with “emitter”). The switching element 10 is not limited to the MOSFET and the IGBT.

As shown equivalently in FIG. 1, a gate-source capacitance Cgs as a parasitic capacitance is attached between the gate and the source of the transistor M1. A gate-drain capacitance Cgd as a parasitic capacitance is attached between the gate and drain of the transistor M1. The source of the transistor M1 is connected to the ground potential application terminal. The input capacitance Ciss of the transistor M1 can be expressed as the sum (=Cgs+Cgd) of the gate-source capacitance Cgs and the gate-drain capacitance Cgd.

Note that the transistor M1 is also accompanied by a parasitic resistance, a parasitic diode, and a parasitic inductance, but the illustration and description thereof are omitted here for convenience.

One end of the first resistor R1 is connected to a connection point between one end of the capacitor C1 and the gate terminal of the switching element 10. The other end of the first resistor R1 is connected to the connection point between the negative electrode side of the pulse voltage generator 5 and the source of the switching element 10. That is, the first resistor R1 is connected between the gate and the source of the switching element 10.

The operation of the gate drive circuit 1 having such a configuration will be described below.

When the pulse voltage generator 5 sets the voltage V1 to the high level (=power supply voltage VCC) at the beginning of switching, the gate voltage V2 generated at the node N at the gate of the transistor M1 is the ON voltage Vc( Positive voltage). Since the ON voltage Vc is generated by dividing the power supply voltage VCC (voltage V1) by the capacitor C1 and the input capacitance Ciss, it is expressed by the following equation (1).
Vc=VCC×C1/(C1+Ciss) (1)

When the voltage V1 is High level and the switching element 10 is on, the electric charge stored in the input capacitance Ciss is discharged by the first resistor R1. At this time, discharging is performed according to the time constant of the capacitance value of the input capacitance Ciss and the resistance value of the first resistor R1. As a result, the positive gate voltage V2 is reduced. At this time, the capacitor C1 is also charged.

After that, when the voltage V1 is set to the low level (=ground voltage GND), the gate voltage V2 becomes a negative voltage lower than 0V according to the decrease in the gate voltage V2 when the switching element 10 is on. .. As a result, the switching element 10 is turned off.

Then, when the voltage V1 is set to the high level again, the gate voltage V2 further decreases from the positive voltage at the time of immediately before turning on by the discharge by the first resistor R1. Then, when the voltage V1 is set to the Low level again, the gate voltage V2 becomes a voltage lower than the negative voltage at the time of immediately before turning off.

By repeating the operation by repeating the High/Low level of the voltage V1 as described above, the gate voltage V2 (positive voltage) when the switching element 10 is turned on gradually decreases from the ON voltage Vc at the time of starting switching with time. At the same time, the gate voltage V2 (negative voltage) when the switching element 10 is turned off gradually decreases from 0 V with time. Then, both the on/off gate voltage V2 is gradually saturated.

The ON voltage Von which is the saturated gate voltage V2 at the time of ON and the OFF voltage Voff which is the saturated gate voltage V2 at the time of OFF are represented by the following formula (2): the switching duty D (with respect to the switching cycle of the ON time). Ratio).
Von=(1-D)・Vc
Voff=-D·Vc (2)

According to such a gate drive circuit 1, it is possible to apply a negative voltage to the gate of the switching element 10 when it is off, and it is possible to prevent the switching element 10 from being accidentally turned on due to noise or the like.

Here, as a specific example, the circuit constants are power supply voltage VCC=25 V, capacitance value of the first capacitor C1=23 nF, capacitance value of the input capacitor Ciss=2 nF, and resistance value of the first resistor R1=10 kΩ. The operation under the conditions will be described. The switching frequency is 100 kHz.

FIG. 2 is a graph showing the temporal behavior of the gate voltage V2 under the above conditions. In FIG. 2, the switching start time is represented as 0 ms. FIG. 2 shows the behavior of the gate voltage V2 for different switching duties. Specifically, a duty of 10% is shown by a solid line, a duty of 30% is shown by a broken line, and a duty of 50% is shown by a chain line.

Further, FIG. 2 is simply shown for the sake of convenience, and in actuality, the gate voltage V2 has a waveform that alternates between a positive voltage and a negative voltage. For example, if the duty is 10%, the gate voltage V2 actually goes back and forth between the upper and lower solid lines shown in FIG. Since the switching frequency is 100 kHz, the gate voltage V2 has a waveform that rises and falls in a switching cycle of 0.01 ms (10 μs).

The ON voltage Vc at the start of switching is 23V from the above equation (1). Therefore, as shown in FIG. 2, the gate voltage V2 (positive voltage) at the time of turning on at the start of switching becomes 23 V, and thereafter gradually decreases with time and becomes saturated. Further, the voltage V2 (negative voltage) at the time of off gradually decreases from 0 V with time, and is saturated.

According to the above formula (2), the ON voltage Von at saturation is 20.7 V when the duty is 10%, 16.1 V when the duty is 30%, and 11.5 V when the duty is 50%. Further, according to the equation (2), the OFF voltage Voff at saturation is −2.3 V when the duty is 10%, −6.9 V when the duty is 30%, and −11.5 V when the duty is 50%.

FIG. 3 shows a temporally enlarged graph in the saturated region in FIG. One scale on the time axis represented by the horizontal axis in FIG. 3 is 2 μs. As shown in FIG. 3, the gate voltage V2 when on and the gate voltage V2 when off are different voltages depending on the switching duty.

In the gate drive circuit 1, the first resistor R1 prevents the electric charge stored in the first capacitor C1 and the gate capacitance Cg from being discharged excessively by the first resistor R1 during the on-time and the off-time. Is set so as to satisfy the following expression (3).
R1>>T/(C1+Ciss) (3)
However, T is the switching cycle

In the example of the above condition, the right side of the equation (3) is 400Ω, and the resistance value of the first resistor R1 is set to 10 kΩ which is sufficiently larger than that.

FIG. 4 is a circuit configuration diagram of a gate drive circuit according to a modification of the first embodiment. The difference between the gate drive circuit 1'shown in FIG. 4 and the configuration shown in FIG. 1 is that a resistor Rc is provided. The resistor Rc is connected between the capacitor C1 and a connection point between the resistor R1 and the gate terminal of the switching element 10. The resistor Rc makes it possible to adjust the turn-on and turn-off speeds of the switching element 10.

<Second Embodiment>
Next, a second embodiment of the present invention will be described. FIG. 5 is a circuit configuration diagram of the gate drive circuit according to the second embodiment. The structural difference from the first embodiment (FIG. 1) of the gate drive circuit 2 shown in FIG. 5 is that the second resistor R2 is connected in parallel with the first capacitor C1.

In the gate drive circuit 2, the ON voltage Vc at the start of switching represented by the above formula (1) is generated in the gate voltage V2 at the start of switching. Then, the gate voltage V2 (positive voltage) at the time of ON is gradually reduced and then saturated due to the discharge of the charge accumulated in the input capacitance Ciss by the first resistor R1 and the charging of the capacitor C1. Further, the gate voltage V2 (negative voltage) at the time of off is gradually decreased from 0V and then saturated.

The ON voltage Von, which is the gate voltage V2 at the time of saturation, and the OFF voltage Voff, which is the gate voltage V2 at the time of saturation, are both determined by the switching duty D, as shown in equation (4) below.
Von=Vc-D (Vc-Vr)
Voff=-D(Vc-Vr) (4)
However, Vr=VCC×R1/(R1+R2)

From the equation (4), it is necessary to select each circuit constant of the first capacitor C1, the first resistor R1, and the second resistor R2 so as to satisfy Vc>Vr.

Here, as a specific example, the circuit constants are the power supply voltage VCC=25V, the capacitance value of the first capacitor C1=23 nF, the capacitance value of the input capacitance Ciss=2 nF, the resistance value of the first resistor R1=15 kΩ, the second The operation under the condition that the resistance value of the resistor R2=5 kΩ will be described. The switching frequency is 100 kHz.

Under the above conditions, Vc=23V according to the equation (1) and Vr=18.75V according to the equation (4), which satisfies Vc>Vr.

A graph showing the temporal behavior of the gate voltage V2 under the above conditions is shown in FIG. The graph shown in FIG. 6 has the same representation as in FIG. 2 described above. As shown in FIG. 6, when the switching is started, the gate voltage V2 (positive voltage) at the time of ON is Vc=23V, and thereafter, it gradually decreases with time and becomes saturated. Further, the voltage V2 (negative voltage) at the time of off gradually decreases from 0 V with time, and is saturated.

According to the above formula (4), the ON voltage Von at saturation is 22.6 V when the duty is 10%, 21.7 V when the duty is 30%, and 20.9 V when the duty is 50%. Further, according to the equation (4), the OFF voltage Voff at saturation is −0.43V when the duty is 10%, −1.28V when the duty is 30%, and −2.13V when the duty is 50%.

FIG. 7 shows a temporally enlarged graph in the saturated region in FIG. One scale on the time axis represented by the horizontal axis in FIG. 7 is 5 μs. As shown in FIG. 7, the gate voltage V2 when on and the gate voltage V2 when off are different depending on the switching duty. However, according to the present embodiment, the variation in the gate voltage V2 at the time of on/off due to the difference in duty can be made smaller than that of the first embodiment (FIG. 3).

Also in the present embodiment, in order to prevent the electric charge accumulated in the first capacitor C1 and the input capacitance Ciss from being excessively discharged by the first resistor R1 during the ON time and the OFF time, The resistance value is set so as to satisfy the above expression (3).

In the example of the above condition, the right side of the equation (3) is 400Ω, and the resistance value of the first resistor R1 is set to 15 kΩ which is sufficiently larger than that.

FIG. 8 is a circuit configuration diagram of a gate drive circuit according to a modification of the second embodiment. The gate drive circuit 2'shown in FIG. 8 is different from the configuration shown in FIG. 5 in that it has a resistor Rc. The resistor Rc is connected between the connection point between the capacitor C1 and the resistor R2 and the connection point between the resistor R1 and the gate terminal of the switching element 10. The resistor Rc makes it possible to adjust the turn-on and turn-off speeds of the switching element 10.

<Third Embodiment>
Next, a third embodiment of the present invention will be described. FIG. 9 is a circuit configuration diagram of the gate drive circuit according to the third embodiment. The difference between the gate drive circuit 3 shown in FIG. 9 and the second embodiment (FIG. 5) in configuration is that a third resistor R3, a Zener diode ZD, and a first rectifier diode D1 are sequentially connected. That is, a series circuit is connected between the gate and the source of the switching element 10. The third resistor R3 does not necessarily have to be provided. However, by providing the third resistor R3, the current flowing through the Zener diode ZD and the first rectifying diode D1 can be limited, and the destruction of these can be suppressed.

In the gate drive circuit 3 having such a configuration, the ON voltage Vc represented by the above formula (1) is generated as the gate voltage V2 at the time of switching on when switching is started. After that, the gate voltage V2 (positive voltage) at the time of turning on gradually decreases due to the discharge of the charge stored in the input capacitance Ciss through the path of the zener diode ZD and the first rectifying diode D1. When the gate voltage V2 reaches the specified voltage Vz, which is the sum of the Zener voltage of the Zener diode ZD (breakdown voltage in the reverse direction) and the forward voltage of the first rectifier diode D1, the discharge is stopped and the gate at the time of turning on. The voltage V2 (positive voltage) is fixed at the specified voltage Vz. At this time, the gate voltage V2 at the time of OFF is reduced from 0V and fixed at the negative voltage Voff (=-(Vc-Vz)) corresponding to the specified voltage Vz.

Here, the specified voltage Vz needs to satisfy both of the following expressions (5) and (6). Expression (6) is a condition under which the discharge is stopped by the specified voltage Vz.
Vz<VCC×C1/(C1+Ciss) (5)
Vz<VCC×R1/(R1+R2) (6)

Further, the first rectifier diode D1 has a function of suppressing the reverse flow through the Zener diode ZD when the gate voltage V2 is negatively biased during the OFF period of the switching element 10.

Here, as a specific example, the circuit constants are: power supply voltage VCC=25V, capacitance value of first capacitor C1=23 nF, capacitance value of input capacitance Ciss=2 nF, resistance value of first resistor R1=150 kΩ, second The operation under the condition that the resistance value of the resistor R2=50 kΩ will be described. The switching frequency is 100 kHz.

Under the above conditions, the right side of the equation (5) is 23V and the right side of the equation (6) is 18.75V. Therefore, the prescribed voltage Vz is set to 18V as an example.

A graph showing the temporal behavior of the gate voltage V2 under the above conditions is shown in FIG. The graph shown in FIG. 10 has the same representation as in FIG. 2 described above. As shown in FIG. 10, when the switching is started, the gate voltage V2 (positive voltage) at the time of ON becomes Vc=23V, and thereafter, it gradually decreases with time and is fixed by the specified voltage Vz=18V. Further, the voltage V2 (negative voltage) at the time of OFF gradually decreases from 0V with time, and is fixed at -5V corresponding to the specified voltage Vz=18V.

FIG. 11 shows a graph obtained by temporally enlarging the region where the gate voltage V2 is fixed in FIG. One scale on the time axis represented by the horizontal axis in FIG. 11 is 2 μs. Since the discharge is regulated by the prescribed voltage Vz, the gate voltage V2 (positive voltage) at the time of turning on is fixed to the prescribed voltage Vz=18V regardless of the switching duty. Correspondingly, the gate voltage V2 (negative voltage) at the time of OFF is fixed at -5V regardless of the duty. Therefore, even if the duty changes, the gate voltage V2 at the time of ON/OFF can be matched.

In addition, in the present embodiment, the resistance value of the first resistor R1 is set to the above value in order to prevent the electric charge accumulated in the first capacitor C1 and the gate capacitance Cg from being excessively discharged by the first resistor R1 during the off time. It is set so as to satisfy the expression (3). In the example of the above condition, the right side of the equation (3) is 400Ω, and the resistance value of the first resistor R1 is set to 150 kΩ which is sufficiently larger than that.

In the second embodiment, the time until the gate voltage V2 is saturated is determined by the resistance value of the first resistor R1, but the time until saturation is also limited because of the limitation of the above formula (3). It was On the other hand, according to the present embodiment, the time until saturation is not determined by the first resistor R1, so the time until saturation can be shortened compared to the second embodiment. By adjusting the resistance value of the third resistor R3 and the turn-on time of the voltage V1, it is possible to set the gate voltage V2 to the saturated voltage from the start of switching.

FIG. 12 is a circuit configuration diagram of a gate drive circuit according to a modification of the third embodiment. The difference between the gate drive circuit 3'shown in FIG. 12 and the configuration shown in FIG. 9 is that a resistor Rc is provided. The resistor Rc is connected between the connection point of the capacitor C1, the resistor R2, and the third resistor R3, and the connection point of the resistor R1 and the gate terminal of the switching element 10. The resistor Rc makes it possible to adjust the turn-on and turn-off speeds of the switching element 10. It is also possible to adjust the gate voltage V2 at the start of switching with the resistor Rc.

<Fourth Embodiment>
Next, a fourth embodiment of the present invention will be described. FIG. 13 is a circuit configuration diagram of the gate drive circuit 4 according to the fourth embodiment. The difference between the gate drive circuit 4 shown in FIG. 13 and the third embodiment (FIG. 9) is that a series circuit including a second capacitor C2 and a second rectifier diode D2 is provided between the gate and source of the switching element 10. That is the connection. The resistors may be further connected in series in the above series circuit. By providing the resistor, the current flowing through the diode D2 can be limited and the breakdown thereof can be suppressed. Further, the resistor Rd is connected in parallel with the second capacitor C2.

In the gate drive circuit 4 having such a configuration, since the second capacitor C2 is charged at the beginning of switching when the voltage V1 becomes High level for the first time, the gate voltage V2 at the time of turning on is expressed by the following formula (7). The ON voltage Vc represented is generated.
Vc=VCC×C1/(C1+C2+Ciss) (7)

Then, the capacitance values of the first capacitor C1 and the second capacitor C2 are selected so that the ON voltage Vc represented by the equation (7) matches the specified voltage Vz. As a result, after the gate voltage V2 at ON time becomes the ON voltage Vc at the start of switching, the discharge of the electric charge stored in the input capacitance Ciss is restricted by the specified voltage Vz, so that the gate voltage V2 at ON time becomes the specified voltage. It is fixed at Vz (=ON voltage Vc). Therefore, a constant gate voltage V2 (positive voltage) at the time of ON can be always generated without generating a high gate voltage V2 at the time of ON at the time of starting switching. Corresponding to this, a constant gate voltage (negative voltage) at the time of turning off can be always generated from the start of switching.

The second rectifier diode D2 is used to prevent discharge due to backflow after the second capacitor C2 is charged for the first time. Further, the resistor Rd is provided for the purpose of discharging the electric charge of the second capacitor C2 before switching is restarted when switching is interrupted. As a result, it is possible to suppress the generation of a high voltage in the gate voltage V2 when switching is restarted.

Here, as a specific example, the circuit constants are: power supply voltage VCC=25V, capacitance value of first capacitor C1=23 nF, capacitance value of input capacitance Ciss=2 nF, resistance value of first resistor R1=150 kΩ, second The operation under the condition that the resistance value of the resistor R2=50 kΩ will be described. The switching frequency is 100 kHz.

In the case of the above conditions, in order to make the ON voltage Vc represented by the equation (7) equal to the specified voltage Vz, the specified voltage Vz=18V, and the capacitance value of the second capacitor C2 is selected to 7 nF.

A graph showing the temporal behavior of the gate voltage V2 under the above conditions is shown in FIG. The graph shown in FIG. 14 has the same representation as in FIG. 2 described above. As shown in FIG. 14, when the switching is started, the gate voltage V2 (positive voltage) at the time of ON is Vc=18V, and then fixed at the specified voltage Vz=18V. That is, the gate voltage V2 is always 18V when the switching is started and is on. Correspondingly, the gate voltage V2 (negative voltage) at the time of off is always constant at -5V from the start of switching. Further, even if the switching duty changes, the gate voltage V2 at the time of on/off can be made to match, as in the third embodiment.

In addition, in the present embodiment, the resistance value of the first resistor R1 is set to the above value in order to prevent the electric charge stored in the first capacitor C1 and the input capacitance Ciss from being excessively discharged by the first resistor R1 during the off time. It is set so as to satisfy the expression (3). In the example of the above condition, the right side of the equation (3) is 400Ω, and the resistance value of the first resistor R1 is set to 150 kΩ which is sufficiently larger than that.

<Other>
It should be noted that the above-mentioned embodiments are exemplifications in all respects and should be considered not to be restrictive, and the technical scope of the present invention is not the description of the above-mentioned embodiments but the scope of claims. It is to be understood that it is shown and includes all modifications that come within the meaning and range of equivalency of the claims.

INDUSTRIAL APPLICABILITY The present invention is used as means for driving switching elements such as a switching power supply and a motor driver, and can be widely used in various fields such as consumer equipment and industrial machines.

1 to 4 gate drive circuit 5 pulse voltage generator 10 switching element M1 transistor C1 first capacitor R1 first resistance Rg gate resistance Cgd gate-drain capacitance Cgs gate-source capacitance Ciss input capacitance R2 second resistance R3 third resistance ZD Zener diode D1 First rectifying diode C2 Second capacitor D2 Second rectifying diode Rc, Rd Resistance

Claims (2)

A first capacitor and a pulse voltage generator connected in series to the gate terminal of a voltage-driven switching element;
A first resistor connected between the gate and source (emitter) of the switching element;
R1>>T/(C1+Ciss) (where R1: resistance value of the first resistor, C1: capacitance value of the first capacitor, Ciss: input capacitance of the switching element, T: switching cycle)
Meet the conditions, such as,
A Zener diode and a first rectifying diode connected in series between the gate and source (emitter) of the switching element;
A second capacitor and a second rectifier diode connected in series between the gate and source (emitter) of the switching element;
Further comprising a discharging resistor connected in parallel with the second capacitor,
VCC×C1/(C1+C2+Ciss)=Vz (where, VCC: High level of voltage generated by the pulse voltage generation unit, C2: capacitance value of the second capacitor, Vz: Zener voltage of the Zener diode and the first rectification) Sum of diode forward voltage)
A gate drive circuit characterized by satisfying such conditions . The gate drive circuit according to claim 1, wherein a resistor is further connected in series in a series circuit including the second capacitor and the second rectifying diode.

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