JP6879862B2 - Op amp - Google Patents

Description

The present invention relates to an operational amplifier with measures against high frequency noise.

When a high-frequency signal that greatly exceeds the operating frequency band is input to the operational amplifier, there is a problem that the DC input offset voltage fluctuates. As a method for reducing this effect, low-pass filters 7A and 8A are connected to the inverting input terminal 1 and the non-inverting input terminal 2 of the operational amplifier in which the emitters of the transistors Q1 and Q2 of the PNP as shown in FIG. 6 are differentially connected to the current source I1. Has been proposed to attenuate high-frequency noise entering the operational amplifier (FIG. 4 of Patent Document 1).

Japanese Unexamined Patent Publication No. 9-260973

However, if the cutoff frequencies of the low-pass filters 7A and 8A to be inserted are not set to a frequency sufficiently higher than the frequency band in which the arithmetic amplifier operates, the frequency characteristics of the arithmetic amplifier will be affected. Depending on the relationship between the operating frequency band of the arithmetic amplifier and the cutoff frequency, as in "Frequency characteristics of conventional countermeasure circuits", the phase margin and gain margin, which are indicators of the stability of the arithmetic amplifier, may be significantly reduced, leading to oscillation. ..

If the cutoff frequency that can be set to ensure the stability of the operational amplifier cannot be lowered sufficiently, high-frequency noise cannot be sufficiently attenuated even though the low-pass filters 7A and 8A are inserted. May be inadequate. The lower the cutoff frequency of the low-pass filters 7A and 8A to be inserted, the higher the attenuation effect of high-frequency noise, but on the other hand, the adverse effect on the stability of the operational amplifier becomes large, and there is a trade-off relationship. As described above, the method of only inserting the low-pass filters 7A and 8A in order to improve the high frequency noise immunity of the operational amplifier has a problem of lowering the stability of the operational amplifier.

An object of the present invention is to provide an operational amplifier in which a low-pass filter for improving high-frequency noise immunity is inserted, but the deterioration in stability is improved.

In order to achieve the above object, the invention according to claim 1 has a first transistor to which a base is connected to an inverting input terminal via a first low-pass filter, and a base to a non-inverting input terminal via a second low-pass filter. A second transistor connected, a first differential circuit having a current source commonly connected to the first transistor and the emitter of the second transistor, and an eleventh transistor whose base is connected to the inverting input terminal, said. A twelfth transistor whose base is connected to a non-inverting input terminal, a second differential circuit having a capacitor connected between the emitter of the eleventh transistor and the emitter of the twelfth transistor, and a collector of the first transistor. A first current mirror circuit that mirrors the current to the emitter of the eleventh transistor, a second current mirror circuit that mirrors the collector current of the second transistor to the emitter of the twelfth transistor, a collector of the eleventh transistor, and the above. A load circuit connected to a collector of the twelfth transistor is provided, and at least one of the collector of the eleventh transistor and the collector of the twelfth transistor is connected to an output terminal.
According to the second aspect of the present invention, in the operational amplifier according to the first aspect, the cutoff frequencies of the first low-pass filter and the second low-pass filter are the same as the cutoff frequencies of the high-pass filter of the second differential circuit. It is characterized by being higher or higher.
The invention according to claim 3 is characterized in that, in the operational amplifier according to claim 1 or 2, the first and second transistors and the eleventh and twelfth transistors are replaced with junction FETs, respectively.
The invention according to claim 4 is characterized in that, in the operational amplifier according to claim 1 or 2, the load circuit is composed of an active load circuit including a 13th transistor and a 14th transistor.
The invention according to claim 5 is the operational amplifier according to claim 1 or 2, wherein the load circuit is connected to a first load resistor connected to a collector of the eleventh transistor and a collector of the twelfth transistor. It is characterized by being composed of two load resistors.
The invention according to claim 6 is characterized in that, in the operational amplifier according to claim 1, 2 or 4, all the transistors are replaced with MOSFETs.

According to the present invention, the first and second low-pass filters having a low cutoff frequency capable of sufficiently attenuating high-frequency noise are inserted on the input side of the first differential circuit, and the influence on the stability of the operational amplifier. There is an advantage that both high frequency noise immunity and stability of the operational amplifier, which have a trade-off relationship, can be improved.

It is a circuit diagram of the operational amplifier of 1st Example of this invention. It is a circuit diagram of the operational amplifier of the 2nd Example of this invention. It is a circuit diagram of the operational amplifier of the 3rd Example of this invention. It is a circuit diagram of the operational amplifier of the 4th Example of this invention. It is a circuit diagram of the operational amplifier of the 5th Example of this invention. It is a circuit diagram of the input terminal part of a conventional operational amplifier. It is a frequency characteristic diagram of the gain and phase of an operational amplifier.

<First Example>
FIG. 1 shows the circuit of the operational amplifier according to the first embodiment of the present invention. 1 is an inverting input terminal, 2 is a non-inverting input terminal, 3 is an output terminal, 4 is a high potential power supply terminal, 5 is a low potential power supply terminal, and 6 is grounded. Reference numeral 7 denotes a first low-pass filter, which is composed of a resistor R1 (resistance value = R) and a capacitor C1 (capacity value = C), and one end thereof is connected to the inverting input terminal 1. Reference numeral 8 denotes a second low-pass filter, which is composed of a resistor R2 (resistance value = R) and a capacitor C2 (capacity value = C), and one end thereof is connected to the non-inverting input terminal 2.

Reference numeral 9 denotes a first differential circuit, which is a PNP transistor Q1 to which the other end of the first low-pass filter 7 (common connection point of the resistor R1 and the capacitor C1) is connected to the base, and the other end of the second low-pass filter 8 (resistor). It is composed of a PNP transistor Q2 in which a common connection point between R2 and a capacitor C2) is connected to the base, and a current source I1 in common connection to the emitters of the transistors Q1 and Q2. NPN transistors Q3 and Q4 connected to the current mirror are connected to the collector of the transistor Q1. Further, NPN transistors Q5 and Q6 connected to the current mirror are connected to the collector of the transistor Q2. Then, PNP transistors Q7 and Q8 connected to the current mirror are connected to the transistor Q4. Further, PNP transistors Q9 and Q10 connected to the current mirror are connected to the transistor Q6. The transistors Q3, Q4, Q7, and Q8 realize the first current mirror circuit according to the claim, and the transistors Q5, Q6, Q9, and Q10 realize the second current mirror circuit.

Reference numeral 10 denotes a second differential circuit, in which the PNP transistors Q11 and Q12, the transistors Q8 and Q10 having collectors connected to the emitters of the transistors Q11 and Q12, respectively, and the capacitors C3 connected between the emitters of the transistors Q11 and Q12, respectively. It is composed of. An active load circuit 11 composed of NPN transistors Q13 and Q14 connected to the current mirror is connected to the collectors of the transistors Q11 and Q12 of the second differential circuit, and the output terminal 3 is connected to the collector of the transistor Q14. Has been done.

で表される。このとき、そのトランジスタＱ１のコレクタ電流は、トランジスタＱ３，Ｑ４，Ｑ７，Ｑ８を経由してトランジスタＱ１１のエミッタにミラーされる。また、トランジスタＱ２のコレクタ電流は、トランジスタＱ５，Ｑ６，Ｑ９，Ｑ１０を経由してトランジスタＱ１２のエミッタにミラーされる。 Next, the operation of the operational amplifier of this embodiment will be described. In the first differential circuit 9, since the bases of the transistors Q1 and Q2 are connected to the inverting input terminals 1 and the non-inverting input terminals 2 via the low-pass filters 7 and 8, the cutoffs of the low-pass filters 7 and 8 are cut off. It operates with a signal having a frequency lower than the frequency fc1. This frequency fc1 is

It is represented by. At this time, the collector current of the transistor Q1 is mirrored by the emitter of the transistor Q11 via the transistors Q3, Q4, Q7 and Q8. Further, the collector current of the transistor Q2 is mirrored by the emitter of the transistor Q12 via the transistors Q5, Q6, Q9 and Q10.

The second differential circuit 10 has a high-pass filter configured by the capacitor C3, and cannot perform differential operation with a signal having a frequency lower than the cutoff frequency fc2 of the high-pass filter. However, since the current due to the differential operation of the first differential circuit 9 is mirrored and flows to the emitters of the transistors Q11 and Q12, the transistors Q11 and Q12 of the second differential circuit 10 are pseudo-transistors Q1 and Q1. It operates in the same manner as the first differential circuit 9 with an emitter coupling such as Q2. Therefore, the mirrored current flows from the collectors of the transistors Q11 and Q12 to the transistors Q13 and Q14 of the load circuit 11, and the difference between the signals input to the inverting input terminal 1 and the non-inverting input terminal 2 is amplified at the output terminal 3. The signal is output.

で表される。ｇｍはトランジスタＱ１１，Ｑ１２の相互コンダクタンスである。カットオフ周波数ｆｃ１，ｆｃ２は、

に設定されている。このため、ローパスフィルタ７，８によって第１差動回路９が差動動作できなくなる周波数以上の帯域では、第２差動回路１０が第１差動回路９に代わって差動動作することになる。 On the other hand, when the frequency of the input signal exceeds the cutoff frequency fc1 of the low-pass filters 7 and 8, the AC signal is attenuated by the low-pass filters 7 and 8 and the AC signal is not input to the bases of the transistors Q1 and Q2. .. At this time, the bases of the transistors Q1 and Q2 are biased by the DC in-phase input voltage, respectively, and if the base current is ignored, half of the current of the constant current source I1 is fixed to the collector of the transistors Q1 and Q2. It flows as a current and is mirrored by the emitters of the transistors Q11 and Q12 of the second differential circuit 10. The second differential circuit 10 operates as a high-pass filter and operates differentially at a frequency equal to or higher than the cutoff frequency fc2. The frequency fc2 is

It is represented by. gm is the transconductance of the transistors Q11 and Q12. The cutoff frequencies fc1 and fc2 are

Is set to. Therefore, in the band above the frequency at which the first differential circuit 9 cannot operate differentially due to the low-pass filters 7 and 8, the second differential circuit 10 operates differentially in place of the first differential circuit 9. ..

When high-frequency noise exceeding the cutoff frequency fc1 of the low-pass filters 7 and 8 is input, the transistors Q1 and Q2 of the first differential circuit 9 are transferred to the transistors Q11 and Q12 of the second differential circuit 10 as described above. The second differential circuit 10 operates differentially by mirroring the constant current, but the emitters of the transistors Q11 and Q12 are connected to each other via the capacitor C3, and are not connected in terms of DC. Therefore, it does not become a factor of DC input offset voltage fluctuation due to high frequency noise. The DC input offset voltage is determined by the differential pair consisting of the transistors Q1 and Q2, but since the high-frequency noise entering the base of the transistors Q1 and Q2 is attenuated by the low-pass filters 7 and 8, the influence of the high-frequency noise Can be reduced.

となるようｆｃ１を設定し、安定性を確保していた。 Further, in the prior art, the cutoff frequency fc1 of the low-pass filters 7 and 8 must be set to a frequency sufficiently higher than the frequency band in which the operational amplifier operates so that the stability of the operational amplifier is not significantly deteriorated. In order to ensure stability while inserting the low-pass filters 7 and 8, the relationship between the gain frequency bandwidth product GBW, which is an index of the operating frequency band of the operational amplifier, and the cutoff frequency fc1 of the low-pass filters 7 and 8 is

Fc1 was set so as to ensure stability.

For example, it is often necessary to set the cutoff frequency fc1 to 100 MHz or higher in order to secure stability while inserting low-pass filters 7 and 8 into an operational amplifier having a gain frequency bandwidth product GBW of 10 MHz. In this case, the high frequency noise of 100 MHz cannot be sufficiently attenuated, and even though the low-pass filters 7 and 8 are inserted, the high frequency noise is greatly affected, and the input offset voltage fluctuates more than expected. Will cause.

Further, for example, when the cutoff frequency fc1 is set to a value close to the GBW of the operational amplifier in order to sufficiently attenuate the high frequency noise in the operational amplifier, the stability is significantly reduced even if the high frequency noise can be sufficiently attenuated. It may lead to the worst oscillation.

On the other hand, in the present invention, the operating frequency characteristics can be complemented by the first differential circuit 9 via the low-pass filters 7 and 8 and the second differential circuit 10 that performs the high-pass filter operation on the input side. It is not necessary to ensure stability by setting the relationship between the frequency band GBW of the arithmetic amplifier and the cutoff frequency fc1 of the low-pass filters 7 and 8 as fc1 >> GBW as described above, and the cutoff frequency fc2 of the second differential circuit 10 is set. By appropriately setting, the cutoff frequency fc1 of the low-pass filters 7 and 8 can be set to be the same as the operating frequency band of the arithmetic amplifier, and further, a value lower than the operating frequency band of the arithmetic amplifier can be selected. ..

FIG. 7 shows the “frequency characteristics of this embodiment” when the circuit configuration of the present invention is used for an operational amplifier of GBW = 4 MHz. Here, the cutoff frequency fc1 of the low-pass filters 7 and 8 is set to 8 MHz, and the cutoff frequency fc2 of the second differential circuit 10 is set to 400 kHz. For comparison, the "frequency characteristics of the unmeasured circuit" without any countermeasures and the "frequency characteristics of the conventional countermeasure circuit" with the low-pass filter inserted are also shown. Although the low-pass filter is inserted in the "frequency characteristics of this embodiment", the stability deterioration due to the decrease in the phase margin and gain margin is improved as in the "frequency characteristics of the unmeasured circuit", and the result is good. You can see that it is.

<Second Example>
FIG. 2 shows the circuit of the operational amplifier of the second embodiment of the present invention. Here, the load circuit 11 in FIG. 1 is composed of circuits using load resistors RL1 and RL2, and differential output signals are taken out to the inverting output terminal 3a and the non-inverting output terminal 3b.

<Third Example>
FIG. 3 shows the circuit of the operational amplifier according to the third embodiment of the present invention. Here, the first differential circuit 9 in FIG. 1 is composed of P-type transistors J1 and J2 of the junction FET, and the second differential circuit 10 is composed of P-type transistors J11 and J12 of the junction FET. The differential circuit composed of the junction FET has an advantage that the input bias current can be reduced as compared with the differential circuit composed of the bipolar transistor. For example, the input current in the case of a junction FET can be suppressed to about several pA to several tens of pA, while the input current in the case of a bipolar transistor is about several nA to several μA.

<Fourth Example>
FIG. 4 shows the circuit of the operational amplifier according to the fourth embodiment of the present invention. Here, the PNP transistors Q1, Q2, Q7 to Q12 in FIG. 1 are replaced with the NPN transistors Q1A, Q2A, Q7A to Q12A, and the NPN transistors Q3 to Q6, Q13, Q14 are replaced with the PNP transistors Q3A to Q6A, Q13A, Q14A. This constitutes an operational amplifier, and operates in the same manner as the operational amplifier of FIG.

<Fifth Example>
FIG. 5 shows the circuit of the operational amplifier according to the fifth embodiment of the present invention. Here, the PNP transistors Q1, Q2, Q7 to Q12 in FIG. 1 are replaced with the MIMO transistors M1, M2, M7 to M12, and the NPN transistors Q3 to Q6, Q13, Q14 are replaced with the NMOS transistors M3 to M6, M13, M14. The operational amplifier is configured by replacing it, and operates in the same manner as the operational amplifier of FIG.

<Other Examples>
In the embodiment of FIGS. 3, 4, and 5, the load circuit 11 may be composed of load resistors RL1 and RL2. Further, in the embodiment of FIGS. 4 and 5, the differential pair transistor of the first differential circuit 9 and the second differential circuit 10 may be replaced with a junction FET. Further, in the embodiment of FIG. 5, the NMOS transistor may be replaced with a epitaxial transistor, and the epitaxial transistor may be replaced with an NMOS transistor.

1: Inverted input terminal, 2: Non-inverting input terminal, 3,3a, 3b: Output terminal, 4: High potential power supply terminal, 5: Low potential power supply terminal, 6: Ground, 7: 1st low-pass filter, 8 : 2nd low-pass filter, 9: 1st differential circuit, 10: 2nd differential circuit, 11: load circuit

Claims (6)

The first transistor whose base is connected to the inverting input terminal via the first low-pass filter, the second transistor whose base is connected to the non-inverting input terminal via the second low-pass filter, and the first transistor and the second transistor. A first differential circuit with a current source commonly connected to the emitter of a transistor,
The eleventh transistor whose base is connected to the inverting input terminal, the twelfth transistor whose base is connected to the non-inverting input terminal, and the capacitor connected between the emitter of the eleventh transistor and the emitter of the twelfth transistor. 2nd differential circuit with
A first current mirror circuit that mirrors the collector current of the first transistor to the emitter of the eleventh transistor, and
A second current mirror circuit that mirrors the collector current of the second transistor to the emitter of the twelfth transistor, and
A load circuit connected to the collector of the 11th transistor and the collector of the 12th transistor,
An operational amplifier comprising, at least one of a collector of the 11th transistor and a collector of the 12th transistor connected to an output terminal. In the operational amplifier according to claim 1,
An operational amplifier characterized in that the cutoff frequencies of the first low-pass filter and the second low-pass filter are the same as or higher than the cutoff frequencies of the high-pass filter of the second differential circuit. In the operational amplifier according to claim 1 or 2.
An operational amplifier characterized in that the first and second transistors and the eleventh and twelfth transistors are replaced with junction FETs, respectively. In the operational amplifier according to claim 1 or 2.
An operational amplifier characterized in that the load circuit is composed of an active load circuit including a 13th transistor and a 14th transistor. In the operational amplifier according to claim 1 or 2.
An operational amplifier comprising the load circuit with a first load resistance connected to a collector of the eleventh transistor and a second load resistance connected to a collector of the twelfth transistor. In the operational amplifier according to claim 1, 2 or 4.
An operational amplifier characterized by replacing all transistors with MOSFETs.

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