JP6807816B2 - Power circuit - Google Patents

Description

The present invention relates to a power supply circuit, and more particularly to a power supply circuit including a voltage regulator.

An LDO (Low Drop Out) regulator is a reference voltage circuit that has a function to keep the output voltage value constant by negative feedback of the output voltage and operates even with a low potential difference between input and output (also called dropout voltage). ..

For example, the power supply circuit described in Patent Document 1 includes an LDO regulator and a booster circuit. The LDO regulator includes an amplifier that outputs a voltage corresponding to fluctuations in the output voltage, and a first transistor that outputs an output voltage having a voltage level corresponding to the voltage output from the amplifier. The booster circuit outputs a voltage signal corresponding to a voltage difference between a second transistor that flows an output current proportional to the output current of the first transistor and a voltage corresponding to the output current of the second transistor and a first reference voltage. It includes a 1-differential amplifier and a control circuit that controls the responsiveness of the amplifier according to a voltage signal according to a voltage difference. The power supply circuit described in Patent Document 1 can suppress the instantaneous fluctuation when the output voltage fluctuates instantaneously.

Japanese Unexamined Patent Publication No. 2016-162097

The power supply circuit described in Patent Document 1 has a problem that the current consumption is large even when the output voltage does not fluctuate instantaneously in order to improve the responsiveness.

Therefore, an object of the present invention is to provide a power supply circuit capable of stabilizing instantaneous fluctuations in output voltage and consuming less current.

The power supply circuit of the present invention includes a voltage regulator that outputs an output voltage corresponding to an input voltage. The voltage regulator includes a first power supply terminal to which an input voltage is applied, a second power supply terminal to which a reference voltage is applied, an output terminal for outputting an output voltage, and a first node to which the output terminal is connected. , The output transistor arranged between the first power supply terminal, the differential amplification stage that amplifies the difference between the divided voltage divided by the output voltage and the reference voltage, and the output of the differential amplification stage are amplified. Includes a source grounded amplification stage. The source ground amplification stage includes a constant current source that supplies a bias current, and an amplification transistor that is connected to the constant current source and amplifies the output of the differential amplification stage to control the gate of the output transistor. The power supply circuit includes a current supply circuit that detects the magnitude of the current flowing through the active load included in the differential amplification stage and supplies a current having a magnitude proportional to the magnitude of the detected current to the amplification transistor.

According to the present invention, the current supply circuit detects the magnitude of the current flowing through the active load included in the differential amplification stage, and supplies a current having a magnitude proportional to the magnitude of the detected current to the amplification transistor. To do. As a result, the power supply circuit can reduce the current consumption when the output voltage does not fluctuate instantaneously.

It is a figure which shows the structure of a general LDO regulator. It is a figure which shows another structure of a general LDO regulator. It is a figure which shows the outline of the structure of the power supply circuit described in Patent Document 1. It is a figure which shows the structure of the power supply circuit 1 of Embodiment 1. FIG. It is a figure which shows the structure of the power supply circuit 2 of Embodiment 2. It is a figure for demonstrating the current feedback loop. It is a figure which shows the structure of the power supply circuit 3 of Embodiment 3. It is a figure which shows the structure of the power supply circuit 4 of Embodiment 4. It is a figure which shows the enable signal at the time of power-start, and the waveform of the voltage in a power circuit 4.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
First, a reference example related to the present invention will be described.

Reference example.
FIG. 1 is a diagram showing a configuration of a general LDO regulator.

As shown in FIG. 1, the LDO regulator includes an error amplifier 301, voltage dividing resistors 302 and 303, an output transistor 304, a power supply terminal 306, a ground terminal 307, a reference voltage terminal 309, and a stabilizing capacity 305. To be equipped.

The error amplifier 301, the voltage dividing resistors 302, 303, the output transistor 304, the power supply terminal 306, the ground terminal 307, and the reference voltage terminal 309 are mounted on the IC (Integrated Circuit) chip 350.

This LDO regulator is a method of negatively feeding back the output voltage Vout. That is, this LDO operates so as to keep the output voltage Vout constant by negative feedback as the load current 308 flowing through the output terminal 99 increases or decreases.

However, when the LDO regulator drives a load such as a digital circuit that operates at high speed and consumes a large amount of current, the load current may fluctuate sharply and exceed the negative feedback voltage tracking performance. In this case, an overshoot or undershoot exceeding a specified value is instantaneously generated in the output voltage Vout, which causes a failure or malfunction. Therefore, it is necessary to connect a large amount of stabilizing capacitance to the output terminal 99 to suppress momentary output voltage fluctuations. Since the value of the external stabilizing capacity 305 is generally on the order of several μ or more, it is necessary to connect it to the outside of the IC chip 350.

FIG. 2 is a diagram showing another configuration of a general LDO regulator.
As shown in FIG. 2, this LDO regulator is provided with a stabilizing capacity 405 inside the IC chip 450 in order to reduce the substrate area.

However, when the stabilizing capacity 405 is built in the IC chip 450, it is necessary to make the stabilizing capacity 405 as small as possible in order to suppress an increase in the size of the IC chip 450. That is, it is an issue to suppress abrupt output voltage fluctuations that occur when the load fluctuates or when the power supply is started by using a low stabilizing capacity. In order to solve this problem, Patent Document 1 describes a technique for multiplexing and speeding up negative feedback.

FIG. 3 is a diagram showing an outline of the configuration of the power supply circuit described in Patent Document 1.
This power supply circuit can improve the responsiveness by having double negative feedback using the current addition circuit 508 in addition to the voltage feedback. Similar proposals have been made in the past to improve responsiveness by double negative feedback, but since they are methods that directly detect the output voltage at the moment when load fluctuation occurs, delay and control Difficulty was an issue. On the other hand, the power supply circuit of Patent Document 1 indirectly detects the output voltage Vout via the gate voltage of the output transistor 504. The indirectly detected output voltage Vout causes the current addition circuit 508 to operate, thereby reducing the delay and facilitating the control. The determination circuit 510 compares the reference voltage Vref2 with the detected voltage. Since the detection voltage also increases as the load current increases, the output of the determination circuit 510 is inverted from the low level to the high level. The operation of the determination circuit 510 turns on the NMOS switch 511, and the boost current source 512 supplies current to the error amplifier 501. This current feedback loop operates faster than voltage feedback.

However, since the differential amplifier circuit included in the determination circuit 510 is constantly operating even when the load is not fluctuating in order to improve the responsiveness, there is a problem that the current consumption is large. Further, since this differential amplifier circuit is vulnerable to noise near the comparison voltage and minute load fluctuations, it may cause oscillation or malfunction.

Embodiment 1.
(Constitution)
FIG. 4 is a diagram showing the configuration of the power supply circuit 1 of the first embodiment.

The power supply circuit 1 includes a voltage regulator 100 and a current supply circuit 108.
The voltage regulator 100 always outputs a constant output voltage Vout.

The voltage regulator 100 includes a first power supply terminal 111, a second power supply terminal 102, an output terminal 105, an output transistor 104, voltage dividing resistors 103a and 103b, a differential amplification stage 115, and a source ground amplification stage. It is equipped with 116.

An input voltage VIN is applied to the first power supply terminal 111.
A reference voltage Vref is applied to the second power supply terminal 102.

The output terminal 105 outputs the output voltage Vout.
The voltage regulator 100 is an LDO regulator characterized in that it operates even when the dropout voltage, which is the difference between the input voltage VIN and the output voltage Vout, is low.

The output transistor 104 is arranged between the first node ND3 to which the output terminal 105 is connected and the first power supply terminal 111.

A voltage dividing resistor 103a and a voltage dividing resistor 103b are connected in series between the first node ND3 and the ground GND. When the resistance value of the voltage dividing resistor 103a is Ra and the resistance value of the voltage dividing resistor 103b is Rb, the voltage dividing voltage Vfo (= Vout × Rb /) is transmitted from the node ND1 between the voltage dividing resistor 103a and the voltage dividing resistor 103b. (Ra + Rb)) is sent to the differential amplification stage 115.

The differential amplification stage 115 amplifies the difference between the voltage dividing voltage Vfo and the reference voltage Vref.
The source ground amplification stage 116 amplifies the output of the differential amplification stage 115.

The source ground amplification stage 116 includes a constant current source 183 and an amplification transistor 182.

The constant current source 183, the amplification transistor 182, and the gate of the output transistor 104 are connected to the second node ND2.

The constant current source 183 supplies a bias current.
The gate of the amplification transistor 182 receives the output of the differential amplification stage 115. The amplification transistor 182 amplifies the output of the differential amplification stage 115 and controls the gate of the output transistor 104.

The current supply circuit 108 detects the magnitude of the current flowing through the active load 117 included in the differential amplification stage 115, and supplies a current having a magnitude proportional to the magnitude of the detected current to the amplification transistor 182.

When the output voltage Vout fluctuates momentarily, the voltage of the second node ND2 fluctuates momentarily, the bias current flowing from the constant current source 183 to the amplification transistor 182 fluctuates momentarily, and the current flowing through the active load 117 momentarily fluctuates. fluctuate. The current supply circuit 108 detects the instantaneous fluctuation of the current flowing through the active load 117, and a current that compensates for the instantaneous fluctuation of the bias current flowing from the constant current source 183 to the amplification transistor 182 is amplified through the second node ND2. Supply to 182.

More specifically, when the output voltage Vout overshoots, the voltage of the second node ND2 undershoots, the bias current flowing from the constant current source 183 to the amplification transistor 182 undershoots, and the active load 117. The current flowing through it overshoots. The current supply circuit 108 supplies a current having a magnitude proportional to the overshooting current flowing through the active load 117 to the amplification transistor 182 through the second node ND2. As a result, the current flowing through the amplification transistor 182 and the undershoot of the voltage of the second node ND2 are compensated, and the output voltage Vout can be stabilized at high speed.

When the output voltage Vout undershoots, the current flowing from the constant current source 183 to the amplification transistor 182 overshoots, and the current flowing through the active load 117 undershoots. The current supply circuit 108 supplies the amplification transistor 182 with a current having a magnitude proportional to the undershoot current flowing through the active load 117 through the second node ND2. As a result, the overshoot of the current flowing through the amplification transistor 182 and the voltage of the second node ND2 is compensated, and the output voltage Vout can be stabilized at high speed.

Further, when the output voltage Vout does not fluctuate instantaneously, the current constantly flowing through the current supply circuit 108 is consumed as the steady operating current of the source grounded amplification stage 116 of the power supply circuit 1, so that the current consumption does not increase.

Embodiment 2.
FIG. 5 is a diagram showing the configuration of the power supply circuit 2 of the second embodiment.

The power supply circuit 2 includes a voltage regulator 200 and a current supply circuit 208.
The voltage regulator 200 includes a first power supply terminal 211, a second power supply terminal 202, a bias voltage input terminal 206, an error amplifier 201, and a voltage generation unit 250.

An input voltage VIN is applied to the first power supply terminal 211. In the second embodiment, VIN has the same value as VDD.

A reference voltage Vref is applied to the second power supply terminal 202.
The output terminal 205 outputs the output voltage Vout.

The voltage regulator 200 is an LDO regulator. Therefore, the voltage regulator 200 operates even if the dropout voltage, which is the difference between the input voltage VIN and the output voltage Vout, is low.

A bias voltage Vb is applied to the bias voltage input terminal 206.
The error amplifier 201 includes a differential amplification stage 215 and a source ground amplification stage 216.

The differential amplification stage 215 includes MOSFET transistors P1, P3, P4 and NMOS transistors N1, N2. The source ground amplification stage 216 includes a MOSFET transistor P2 that constitutes a constant current source, and an NMOS transistor N3 that is an amplification transistor.

The current supply circuit 208 includes a current mirror circuit 210 and an NMOS transistor 209. The current mirror circuit 210 includes MOSFET transistors P5 and P6.

The voltage generation unit 250 includes an output transistor 204, which is a MOSFET transistor, and voltage dividing resistors 203a and 203b.

The output transistor 204, the voltage dividing resistor 203a, and the voltage dividing resistor 203b are connected in series between the power supply VDD and the ground GND.

The first node ND3 between the output transistor 204 and the voltage dividing resistor 203a is connected to the output terminal 205.

The gate of the output transistor 204 is connected to the second node ND2.
The node ND1 between the voltage dividing resistor 203a and the voltage dividing resistor 203b is connected to the gate of the NMOS transistor P4 in the differential amplification stage 215. When the resistance value of the voltage dividing resistor 203a is Ra and the resistance value of the voltage dividing resistor 203b is Rb, the voltage dividing voltage Vfo (= Vout × Rb / (Ra + Rb)) is sent from the node ND1 to the gate of the epitaxial transistor P4. ..

The MOSFET transistor P1 is connected between the power supply VDD and the node ND4. A MOSFET transistor P3 and an NMOS transistor N1 are connected in series between the node ND4 and the ground GND. A MOSFET transistor P4 and an NMOS transistor N2 are connected in series between the node ND4 and the ground GND. The NMOS transistor N1 is diode-connected. The node ND5 between the PRIVATE transistor P4 and the NMOS transistor N2 is connected to the gate of the NMOS transistor N3 in the source ground amplification stage 216. The gate of the NMOS transistor N1 and the gate of the NMOS transistor N2 are connected to the gate of the NMOS transistor 209.

The gate of the MOSFET transistor P1 is connected to the bias voltage input terminal 206 and receives the bias voltage Vb. The gate of the MOSFET transistor P3 is connected to the second power supply terminal 202 and receives a reference voltage Vref. The gate of the MOSFET transistor P4 is connected to the first node ND3 and receives a voltage dividing voltage Vfo. The NMOS transistor N1 and the NMOS transistor N2 form an active load 217.

A NMOS transistor P2 is provided between the power supply VDD and the second node ND2. An NMOS transistor N3 is provided between the second node ND2 and the ground GND. The gate of the MOSFET transistor P2 is connected to the bias voltage input terminal 206 and receives the bias voltage Vb. A bias current IB flows from the power supply VDD to the second node ND2 via the MOSFET transistor P2. The DC value of the bias current IB is a constant value regardless of the fluctuation of the output voltage Vout. The gate of the NMOS transistor N3 is connected to the node ND5 between the NMOS transistor P4 and the NMOS transistor N2.

The MOSFET transistor P5 is connected between the power supply VDD and the second node ND2. A MOSFET transistor P6 and an NMOS transistor 209 are connected in series between the power supply VDD and the ground GND. The gate of the MOSFET transistor P5 and the gate of the MOSFET transistor P6 are connected. The MOSFET transistor P6 is diode-connected.

The MOSFET transistor P5 and the MOSFET transistor P6 form a current mirror circuit 210. The NMOS transistor N1, the NMOS transistor N2, and the NMOS transistor 209 form a multi-output current mirror circuit 430.

When the current flowing through the NMOS transistor N1 and the current flowing through the NMOS transistor N2 are I1, the current of I2 (= k1 × I1) flows through the NMOS transistor 209. Since the current I2 flows through the MOSFET transistor P6, the current of I3 (= k2 × I2 = k2 × k1 × I1 = K × I1) flows through the MOSFET transistor P5.

Next, the operation when the current supply circuit 208 supplies the additional current IAc to the second node ND2 in the steady state where the output voltage Vout does not fluctuate momentarily will be described.

In the steady state, the direct current flowing through the active load 217 is determined by the bias voltage Vb, and the current flowing through the NOS transistors N1 and N2 is I1c. At this time, a current of I2c (= k1 × I1c) flows through the NMOS transistor 209 and the NMOS transistor P6, and I3c (= k2 × I2c = k2 × k1 × I1c = K × I1c) flows through the NMOS transistor P5. Current flows. The current I3c corresponds to the additional current IAc supplied by the current supply circuit 208 to the second node ND2 at steady state. At constant time, the current supply circuit 208 can be regarded as a constant current source that supplies the current IAc.

Assuming that the bias current flowing through the epitaxial transistor P2 is IB0 when the power supply circuit 2 does not include the current supply circuit 208 in the steady state, the bias current IB flowing through the epitaxial transistor P2 and the current supply circuit 208 of the present embodiment are assumed. It is assumed that the epitaxial transistor P2 and the transistor in the current supply circuit 208 are designed so that the sum with the additional current IAc supplied by the current IAc matches IB0. Since IB0 = IB + IAC in the constant state, the current that increases in the steady state by providing the current supply circuit 208 is only the current I2c flowing through the NMOS transistor 209 and the NMOS transistor P6. Therefore, in the present embodiment, the current consumption in the steady state can be reduced as compared with the power supply circuit described in Patent Document 1.

Next, the voltage feedback loop included in the power supply circuit 2 will be described.
When the output voltage Vout fluctuates, the output voltage Vout converges to a constant value by a loop circulating through the node ND1, the error amplifier 201, the output transistor 204, and the node ND1.

When the output voltage Vout fluctuates, the voltage dividing voltage Vfo on the node ND1 is input to the gate of the NMOS transistor P4 which is the non-inverting input terminal of the differential amplification stage 215. The differential amplification stage 215 operates so that the magnitude of the reference voltage Vref input to the gate of the epitaxial transistor P3, which is the inverting input terminal, and the magnitude of the voltage dividing voltage Vfo are the same (called a virtual short circuit). , The voltage of the second node ND2, which is the gate voltage of the output transistor 204, is controlled. By such an operation, the output voltage Vout converges to a constant value determined by the magnitude of the reference voltage Vref and the voltage dividing ratio of the output voltage Vout by the voltage dividing resistors 203a and 203b.

However, when a momentary overshoot occurs in the output voltage Vout, an undershoot occurs in the second node ND2 before the voltage feedback occurs. Since the current value flowing through the path from the MOSFET transistor P4 to the NMOS transistor N3 is relatively small, transmission is slow due to the influence of parasitic capacitance, and the output transistor 204 can flow a large current. Therefore, an undershoot occurs in the second node ND2 before the voltage of the node ND4 rises due to the voltage feedback. At this time, the bias current IB flowing from the MOSFET transistor P2 to the NMOS transistor N3 also undershoots, so that the operating current IC of the source ground amplification stage 216 is reduced.

Further, when a momentary undershoot occurs in the output voltage Vout, an overshoot occurs in the second node ND2 before the voltage feedback occurs. At this time, since the bias current IB flowing from the MOSFET transistor P2 to the NMOS transistor N3 also overshoots, the operating current IC of the source grounded amplification stage 216 increases.

Undershoot of the output voltage Vout occurs when the load fluctuates and when the power supply is started. Overshoot of the output voltage Vout occurs when the power supply is started. When the power is turned on, the supply of VDD, Vref, Vb, and VIN is started. This is because when the power supply is started, a rush current, which is a current equal to or higher than a steady value, flows through the output transistor 204 in an attempt to rapidly charge the output capacitor (not shown).

In the present embodiment, when the load fluctuation is so steep that the voltage feedback loop cannot follow the current supply circuit 208, the current supply circuit 208 controls the operating current of the source grounded amplification stage 216 that drives the output transistor 204. This suppresses momentary output fluctuations.

Next, the current feedback loop included in the power supply circuit 2 will be described.
FIG. 6 is a diagram for explaining a current feedback loop.

The solid arrow in FIG. 6 represents the current feedback loop.
When an overshoot occurs in the output voltage Vout, this is transmitted to the differential amplification stage 215 through the node ND1. The current flowing through the NMOS transistor N1 and the NMOS transistor N2 changes from I1c to I1o in the steady state. I1o> I1c. I1o is the overshooting current. As a result, the overshooting current of I2o = k1 × I1o flows through the NMOS transistor 209 and the NMOS transistor P6, and the overshoot of I3o = k2 × I2o = k2 × k1 × I1o = K × I1o) flows through the NMOS transistor P5. The shot current flows. The current I3o corresponds to the overshooted additional current IAo supplied by the current supply circuit 208 to the second node ND2 when the output voltage Vout is overshooted. The overshooted additional current IAo is supplied to the NMOS transistor N3 through the second node ND2. As a result, as described above, the overshooted additional current IAo for compensating for the undershooted bias current IB flowing from the MOSFET transistor P2 to the NMOS transistor N3 due to the overshoot of the output voltage Vout passes through the second node ND2. It is supplied to the NMOS transistor N3. As a result, it is possible to compensate for the undershoot of the operating current IC of the source grounded amplification stage 216, so that the output voltage Vout can be stabilized at high speed.

When an undershoot occurs in the output voltage Vout, this is transmitted to the differential amplification stage 215 through the node ND1. The current flowing through the NMOS transistors N1 and N2 changes from I1c to I1u in the steady state. I1u <I1c. I1u is the undershooted current. As a result, an undershoot current of I2u = k1 × I1u flows through the NMOS transistor 209 and the NMOS transistor P6, and an undershoot of I3u = k2 × I2u = k2 × k1 × I1u = K × I1u) flows through the NMOS transistor P5. The shot current flows. The current I3u corresponds to the undershooted additional current IAu supplied by the current supply circuit 208 to the second node ND2 when the output voltage Vout is undershoot. The undershooted additional current IAu is supplied to the NMOS transistor N3 through the second node ND2. As a result, as described above, the undershooted additional current IAu for compensating for the overshooted bias current IB flowing from the MOSFET transistor P2 to the NMOS transistor N3 due to the undershoot of the output voltage Vout passes through the second node ND2. It is supplied to the NMMOS transistor N3. As a result, it is possible to compensate for the overshoot of the operating current IC of the source grounded amplification stage 216, so that the output voltage Vout can be stabilized at high speed.

The current ratio K (= k1 × k2) can be arbitrarily selected by adjusting the sizes of the NMOS transistors N1, N2, N3 and the MOSFET transistors P5 and P6. When the current ratio K is increased, I3 is increased, so that it can react sensitively to load fluctuations, but the variation in characteristics becomes large. On the other hand, if the current ratio K is made small, it cannot react sensitively to load fluctuations, but the variation in characteristics becomes small. K may be set so that the desired characteristics can be obtained.

Further, when the output voltage Vout does not fluctuate instantaneously, the current constantly flowing through the current supply circuit 208 is consumed as the steady operating current of the source grounded amplification stage 216 of the power supply circuit 2, so that the current consumption does not increase. The reason will be explained in more detail. A current is required for the operation of the error amplifier 211. I1c and I3c are currents that can be shared with the error amplifier 211. I2c is a current that is not shared with the error amplifier 211. By adding the current supply circuit 208 at steady state, the current consumption for I2c increases. However, the value of I2c can be made as small as possible by adjusting the ratios k1 and k2 of the current mirrors (k1 << k2). That is, I2c <I3c can be set. The current supply circuit 208 can be realized only by adding a minute I2c in addition to the I1c and I3c originally required for the operation of the error amplifier 211. Therefore, in Patent Document 1, a differential amplifier circuit is provided in the determination circuit 510 separately from the error amplifier 501, so that a steady current is wasted. However, in the present embodiment, this current is used as an error. It can be used for the amplifier 201, and as a result, the current consumption can be reduced.

Embodiment 3.
In the first embodiment, the second node ND2 may be in a floating state during standby, the voltage may not be fixed, and the output transistor 104 may not be reliably turned off. In order to avoid this, in the third embodiment, a voltage fixing element is provided.

FIG. 7 is a diagram showing the configuration of the power supply circuit 3 of the third embodiment.
The power supply circuit 3 is different from the power supply circuit 1 of the first embodiment as follows.

The power supply circuit 3 includes a control circuit 141.
The control circuit 141 includes a delay circuit (Delay) 112.

The delay circuit 112 delays the external enable signal EN input from the outside by a predetermined time, and outputs the internal enable signal ENA.

Further, the voltage regulator 300 included in the power supply circuit 3 includes a voltage fixing transistor 114 which is a MOSFET transistor.

The MOSFET transistor 113 is arranged between the power supply VDD and the second node ND2. The gate of the MOSFET transistor 113 receives the internal enable signal ENA.

Since the external enable signal EN is at a low level during standby, the voltage fixing transistor 114 is turned on, and the potential of the second node ND2 is fixed at a high level. As a result, the output transistor 104 can be reliably turned off during standby.

On the other hand, the current supply circuit 108 is characterized in that the response is slow because it operates after the fluctuation is transmitted to the internal terminal of the differential amplification stage 115. When the power supply is started, the current supply circuit 108 may not operate in time and an overshoot may occur. Therefore, the control circuit 141 delays the rise of the output transistor 104 when the power supply is started. The delay circuit 112 in the control circuit 141 delays the rise of the internal enable signal ENA supplied to the gate of the output transistor 104 more than the rise of the external enable signal EN. As a result, the output transistor 104 is turned on after the differential amplification stage 115 and the source ground amplification stage 116 are completely activated. As a result, when the power supply is started, the current supply circuit 108 can be operated before the output transistor 204 overshoots or undershoots, so that the output voltage Vout responds to the overshoot or undershoot at high speed. be able to.

Embodiment 4.
FIG. 8 is a diagram showing the configuration of the power supply circuit 4 of the fourth embodiment.

The difference between the power supply circuit 4 and the power supply circuit 2 of the second embodiment is as follows.
The power supply circuit 4 includes a control circuit 241.

The voltage generation unit 260 in the voltage regulator 400 included in the power supply circuit 4 includes a voltage fixing transistor 214 which is a MOSFET transistor.

The voltage fixing transistor 214 is arranged between the power supply VDD and the second node ND2. The gate of the voltage fixing transistor 214 receives the internal enable signal ENA.

At the time of standby, since the external enable signal EN is at a low level, the internal enable signal ENA is at a low level and the voltage fixing transistor 214 is turned on, so that the potential of the second node ND2 is fixed at a high level. As a result, the output transistor 204 can be reliably turned off during standby. When the internal enable signal ENA is at a high level, the voltage fixing transistor 214 is turned off, so that the gate of the output transistor 204 is controlled by the output of the source ground amplification stage 216.

The control circuit 241 includes inverters IV1, IV2, IV3, buffer 212, and inverter IV4 connected in series.

Inverter IV1 receives the external enable signal EN and outputs the internal enable signal EN0 to the inverter IV2. The inverter IV2 receives the internal enable signal EN0 and outputs the internal enable signal EN1.

The inverter IV3 receives the internal enable signal EN1 and outputs the internal enable signal EN2.

The buffer 212 receives the internal enable signal EN2 and outputs the internal enable signal EN3. The buffer 212 is an RC circuit composed of a resistor R1 and a capacitor C1.

The inverter IV4 receives the internal enable signal EN3 and outputs the internal enable signal ENA.

Next, the operation of the control circuit 241 will be described.
FIG. 9 is a diagram showing an enable signal when the power supply is started and a waveform of the voltage in the power supply circuit 4.

In FIG. 9, the time change of the external enable signal EN, the internal enable signal EN1, the internal enable signal ENA, the voltage of the second node ND2, and the output voltage Vout is shown by a solid line. In FIG. 9, the internal enable signal ENA when the control circuit 241 does not include the buffer 212, the voltage of the second node ND2 due to such an internal enable signal ENA, and the time change of the output voltage Vout are broken lines. It is indicated by.

When the power is turned on, the external enable signal EN gradually rises. The rise of the internal enable signal EN1 output from the two-stage inverters IV1 and IV2 that delay the external enable signal EN becomes steep.

When the potential is not fixed when the power supply is floating, but there is a wiring or terminal that can be released from the voltage fixing immediately when the power supply is started, for fixing the voltage between such wiring or terminal and the power supply or ground. A transistor may be provided and the internal enable signal EN1 may be supplied to the gate of the voltage fixing transistor.

The slew rate of the internal enable signal ENA indicated by the broken line output from the two-stage inverters IV3 and IV4 that delay the internal enable signal EN1 remains steep. When this internal enable signal ENA is supplied to the gate of the voltage fixing transistor 214, the additional current is not supplied from the current supply circuit 208 to the grounded source amplification stage 216 in time, and the output voltage Vout overshoots or undershoots. The shoot cannot be compensated.

The slew rate of the internal enable signal ENA indicated by the solid line output from the inverter IV3, the buffer 212, and the inverter IV4 that delays the internal enable signal EN1 is relaxed. As a result, the additional current is supplied from the current supply circuit 208 to the grounded source amplification stage 216 in time, so that the output voltage Vout can compensate for the overshoot or undershoot.

Modification example.
(1) The conductive type of the transistor included in the power supply circuits of the first to fourth embodiments may be changed from N-type to P-type and P-type to N-type, and the positions of the power supply VDD and the ground GND may be exchanged.
(2) In the fourth embodiment, a buffer made of an RC circuit is used in order to slow down the slew rate of the internal enable signal ENA, but the present invention is not limited to this. For example, an inverter in which the sizes of the NMOS transistor and the NMOS transistor are unbalanced may be used.

It should be considered that the embodiments disclosed this time are exemplary in all respects and not restrictive. The scope of the present invention is shown by the scope of claims rather than the above description, and is intended to include all modifications within the meaning and scope equivalent to the scope of claims.

1,2,3,4 power supply circuit, 100,200,300,400 voltage regulator, 102,202 second power supply terminal, 103a, 103b, 203a, 203b, 302, 303, 402, 403, 503a, 503b voltage division Resistance, 104,204,304,404,504 output transistor, 105,205 output terminal, 108,208 current supply circuit, 111,211 first power supply terminal, 112 delay circuit, 114,214 voltage fixing transistor, 115, 215 differential amplification stage, 116,216 source ground amplification stage, 117,217 active load, 141,241 control circuit, 182 amplification transistor, 183 constant current source, 201, 301, 401, 501 error amplifier, 206 bias voltage input Terminal, 209, N1, N2, N3 NMOS transistor, 210,430 current mirror circuit, 212 buffer, 250,260 voltage generator, 350,450,550 IC chip, 305 external stabilization capacitance, 306,406,505 power supply Terminal, 307, 407, 506 GND terminal, 308, 408, 507 Load current, 309, 409 Reference voltage terminal, 405 Built-in stabilization capacity, 500 LDO circuit, 502a 1st reference voltage terminal, 502b 2nd reference voltage terminal, 508 Current addition circuit, 509 detection terminal, 510 judgment circuit, 511 detection transistor, 512 boost current source, P1, P2, P3, P4, P5, P6 ProLiant transistor, IV1, IV2, IV3, IV4 inverter, C capacitor, R resistor ..

Claims (8)

Equipped with a voltage regulator that outputs an output voltage according to the input voltage
The voltage regulator is
The first power supply terminal to which the input voltage is applied and
The second power supply terminal to which the reference voltage is applied and
An output terminal that outputs the output voltage and
An output transistor arranged between the first node to which the output terminal is connected and the first power supply terminal, and
A differential amplification stage that amplifies the difference between the divided voltage obtained by dividing the output voltage and the reference voltage, and
It includes a source ground amplification stage that amplifies the output of the differential amplification stage.
The source ground amplification stage
A constant current source that supplies the bias current,
It includes an amplification transistor connected to the constant current source, amplifying the output of the differential amplification stage, and controlling the gate of the output transistor.
A current supply circuit for detecting the magnitude of the current flowing through the active load included in the differential amplification stage and supplying a current having a magnitude proportional to the magnitude of the detected current to the amplification transistor is provided. Power circuit. The constant current source, the amplification transistor, and the gate of the output transistor are connected to the second node.
The current supply circuit flows to the active load when the output voltage fluctuates instantaneously in order to compensate for the instantaneous fluctuation of the current flowing from the constant current source to the amplification transistor when the output voltage fluctuates instantaneously. The power supply circuit according to claim 1, wherein an instantaneous fluctuation of a current is detected, and a current having a magnitude proportional to the magnitude of the detected current is supplied to the amplification transistor through the second node. When the output voltage overshoots, the current flowing from the constant current source to the amplification transistor undershoots, and the current flowing through the active load overshoots.
The power supply circuit according to claim 2, wherein the current supply circuit supplies a current having a magnitude proportional to the overshooting current flowing through the active load to the amplification transistor through the second node. When the output voltage undershoots, the current flowing from the constant current source to the amplification transistor overshoots, and the current flowing through the active load undershoots.
The power supply circuit according to claim 2, wherein the current supply circuit supplies a current having a magnitude proportional to the undershoot current flowing through the active load to the amplification transistor through the second node. The current supply circuit
A mirror transistor that constitutes a first current mirror circuit together with a transistor that constitutes an active load of the differential amplification stage and outputs a first replicated current that replicates the current flowing through the transistor.
The power supply circuit according to claim 1, further comprising a second current mirror circuit that supplies a second replication current that further replicates the first replication current to the amplification transistor. A voltage fixing transistor connected between the power supply and the second node,
The power supply circuit according to claim 2, further comprising a control circuit for controlling the timing of turning off the voltage fixing transistor. The control circuit generates an internal enable signal by delaying the enable signal input from the outside and supplies it to the gate of the voltage fixing transistor.
The power supply circuit according to claim 6, wherein the potential of the power supply is applied to the second node when the internal enable signal is at the deactivation level. The power supply circuit according to claim 7, wherein the control circuit includes an RC circuit.

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