JP6982457B2 - Charge pump circuit - Google Patents

Description

The present invention relates to a 4-phase clock driven charge pump circuit.

A type of non-volatile semiconductor storage device is a flash memory capable of electrically rewriting data, but the flash memory requires a high voltage (for example, 12V) power supply when writing data. Therefore, the flash memory generally has a built-in charge pump circuit, and a high voltage power supply required from a low voltage (for example, 3V) power supply supplied from the outside is generated by the charge pump circuit.

As the charge pump circuit, there are a charge pump circuit driven by a two-phase clock and a charge pump circuit driven by a four-phase clock (see, for example, Patent Document 1).

The charge pump circuit described in Patent Document 1 describes the substrate bias effect. The HCl transistor of the charge pump unit is a well-separated type µ transistor, and the N-type well for the separation is reverse biased between the N-type well and the P-type board and between the N-type well and the P-type well. Connect to a high potential point so that it is. As a result, in any of the charge pump units connected in series, the potential of the P-type well is set to the same potential as the source potential, and the threshold voltage is set to a constant low value.

FIG. 6 is an example showing the configuration of a 4-phase clock-driven negative voltage charge pump circuit that has been used conventionally.

The negative booster units CNU1 to CNU4 and the negative booster unit output stage CNO are connected in series.
A ground voltage GND is connected to the negative booster unit input terminal CNUi of the negative booster unit CNU1, and the output stage output terminal CNOo of the negative booster unit output stage CNO forms the output terminal VNOUT of the negative booster circuit.
A capacitor COUT and a load ROUT are connected in parallel between the output terminal VNOUT and the ground voltage GND. Here, the capacitor COUT is prepared for smoothing the output voltage. Further, the capacitor COUT also includes a parasitic capacitor generated at the output terminal VNOUT. The load ROUT represents a load driven by the charge pump circuit.

The negative boosting units CNU1 to CNU4 have the same configuration, and for example, the negative boosting unit CNU1 will be described as an example.
The negative booster unit CNU1 has a transfer transistor M41 having a drain connected to the negative booster unit input terminal CNUi and a source connected to the negative booster unit output terminal CNUo, and a first electrode connected to the source of the transfer transistor M41. A pump capacitor CP1 having a second electrode connected to the clock input terminal FN3 and an auxiliary pump capacitor CG1 having a first electrode connected to the gate of the transfer transistor M41 and a second electrode connected to the clock input terminal FN1. And a discharge transistor M51 having the source connected to the source of the transfer transistor M41, the drain connected to the gate of the transfer transistor M41, and the gate connected to the drain of the transfer transistor M41.
Any number of negative booster units may be prepared according to the target voltage and connected in series. In this example, four negative boosting units are temporarily connected.
The negative boost unit CNU2 has a transfer transistor M42 and a discharge transistor M52, the negative boost unit CNU3 has a transfer transistor M43 and a discharge transistor M53, and the negative boost unit CNU4 has a transfer transistor M44 and a discharge transistor M54. have.
The pump capacitors CP1 to CP4 of each negative booster unit are connected to the clock input terminals FN3 in the odd-numbered negative booster units CNU1 and CNU3, and are connected to the clock input terminals FN4 in the even-numbered negative booster units CNU2 and CNU4. ..
Further, the auxiliary pump capacitors CG1 to CG4 of each negative booster unit are connected to the clock input terminal FN1 in the odd-numbered negative booster units CNU1 and CNU3, and are connected to the clock input terminal FN2 in the even-numbered negative booster units CNU2 and CNU4. Will be done.

The negative booster unit output stage CNO has a transfer transistor M45 having a drain connected to the output stage input terminal CNOi and a source connected to the output stage output terminal CNOo, and a first electrode connected to the gate of the transfer transistor M45. The auxiliary pump capacitor CG5 having the second electrode connected to the clock input terminal FN1 and the source of the transfer transistor M45 are connected to the source, and the drain is connected to the gate of the transfer transistor M45 to connect the transfer transistor M45. It has a discharge transistor M55 having its gate connected to the drain.

FIG. 7 shows the clock input terminals FN1 to FN4 in FIG. 6, the drain voltage Vdn1 of the transfer transistor M45, the source voltage Vsn1, and the gate voltage Vgn1. The operation of the charge pump circuit of FIG. 6 will be described with reference to FIG. 7.

The clock input terminal FN1 becomes high level at time t4. As a result, the voltage difference between the gate and the source of the transfer transistor M41 increases through the auxiliary pump capacitor CG1 and the transfer transistor M41 becomes conductive. The clock input terminal FN1 becomes low level at time t5. As a result, the voltage difference between the gate and source of the transfer transistor M41 is reduced through the auxiliary pump capacitor CG1 and no conduction occurs.
The clock input terminal FN2 becomes low level at time t1. As a result, the voltage difference between the gate and the source of the transfer transistor M42 through the auxiliary pump capacitor CG2 becomes low and the conduction does not occur. The clock input terminal FN2 becomes high level at time t8. As a result, the voltage difference between the gate and the source of the transfer transistor M42 increases through the auxiliary pump capacitor CG2, and the transfer transistor M42 becomes conductive.
The clock input terminal FN3 becomes high level at time t2. As a result, the voltage difference between the gate and the source of the discharge transistor M52 increases through the pump capacitor CP1 and becomes conductive. The clock input terminal FN3 becomes low level at time t7. As a result, the voltage difference between the gate and source of the discharge transistor M52 is reduced through the pump capacitor CP1 and no conduction occurs.
The clock input terminal FN4 becomes low level at time t3. As a result, the voltage difference between the gate and source of the discharge transistor M53 is reduced through the pump capacitor CP2, and conduction is not performed. The clock input terminal FN4 becomes high level at time t6. As a result, the voltage difference between the gate and source of the discharge transistor M53 increases through the pump capacitor CP2, and conduction occurs.

The drain voltage Vdn1 shows a waveform synchronized with the clock input terminal FN4. Further, the gate voltage Vgn1 shows a waveform synchronized with the clock input terminal FN1. Originally, the source voltage Vsn1 shows a waveform synchronized with the clock input terminal FN1, but shows the same waveform as the drain voltage Vdn1. This is because the gate voltage Vgn1 of the transfer transistor M45 stays at a higher potential than Vsn1 and the resistance between the drain and the source of the transfer transistor M45 becomes low, so that the gate and source of the discharge transistor M55 are short-circuited. It is caused by the fact that it becomes a short-circuited state and does not function as a transistor.

Sections T1 to T8 in FIG. 7 will be described later.

The problems mentioned above are caused by what will be described below.
At startup, the negative boost is advanced from the negative boost unit CNU1 side close to the ground voltage GND in FIG. 6, so the discharge transistors M52 to M55 arranged further on the negative voltage side in FIG. 6 do not operate. At the time of startup, it is undefined how much charge is accumulated in each wiring, and it is possible that the charge is accumulated in the gates of the transfer transistors M41 to M45. Therefore, the gate-source voltage of the transfer transistors M41 to M45 cannot be cleared at startup, and the transfer transistors M41 to M45 are always turned on, which may not contribute to negative boosting.

Further, since the gate of the discharge transistor M51 of the negative booster unit CNU1 is fixed at the ground voltage GND, the discharge transistor M51 cannot be sufficiently turned on, the transfer transistor M41 is weakly turned on, and the transfer transistor M41 is turned on weakly. A problem may occur in which a backflow occurs from the source to the drain side of the transistor and a sufficient negative boost cannot be obtained.

FIG. 7A shows the operating state of each transistor in the sections T1 to T8 shown in FIG.
It shows a case where the negative booster unit output stage CNO (transfer transistor M45, discharge transistor M55) causes an abnormal operation.
The transfer transistor M44 is operating normally, and only the section T8 is ON.
The discharge transistor M54 is operating normally and is turned on in the sections T2 to T6.
The transfer transistor M45 should be ON only in the section T4 during normal operation, but is ON in all sections during abnormal operation.
The discharge transistor M55 should be ON in the sections T1 to T2 and T6 to T8 during normal operation, but is OFF in all sections during abnormal operation.

FIG. 8 is an example showing the configuration of a positive voltage charge pump circuit driven by a four-phase clock, which has been used conventionally.

The positive booster unit input stage CPI, the positive booster unit CPU1 to CPU3, and the positive booster unit output stage CPO are connected in series.
The power supply voltage VCS (for example, 2V or 3V) is connected to the positive booster unit input terminal CPIi of the positive booster unit input stage CPI, and the output stage output terminal CPOo of the positive booster unit output stage CPO is the output terminal of the positive booster circuit. It forms a VPOUT.
A capacitor COUT and a load ROUT are connected in parallel between the output terminal VPOUT and the ground voltage GND. Here, the capacitor COUT is prepared for smoothing the output voltage. Further, the capacitor COUT also includes a parasitic capacitor generated at the output terminal VPOUT. The load ROUT represents a load driven by the charge pump circuit.

The positive boost unit input stage CPI connects a transfer transistor M11 having a source connected to the input stage input terminal CPIi and a drain connected to the input stage output terminal CPIo, and a first electrode connected to the gate of the transfer transistor M11. The auxiliary pump capacitor CG1 having the second electrode connected to the clock input terminal FP1 and the source of the transfer transistor M11 are connected to the source, the drain is connected to the gate of the transfer transistor M11, and the transfer transistor M11 is connected. It has a discharge transistor M21 having its gate connected to the drain.

The positive booster units CPU1 to CPU3 have the same configuration, and for example, the positive booster unit CPU1 will be described as an example.
The positive boost unit CPU1 connects a transfer transistor M12 having a source connected to the positive boost unit input terminal CPUi and a drain connected to the positive boost unit output terminal CPUo, and a first electrode connected to the source of the transfer transistor M12. The pump capacitor CP1 having the second electrode connected to the clock input terminal FP3 and the auxiliary pump capacitor CG2 having the first electrode connected to the gate of the transfer transistor M12 and the second electrode connected to the clock input terminal FP2. And a discharge transistor M22 having the source connected to the source of the transfer transistor M12, the drain connected to the gate of the transfer transistor M12, and the gate connected to the drain of the transfer transistor M12.
Arbitrary number of positive step-up units may be prepared according to the target voltage and connected in series. In this example, three positive booster units are tentatively connected.
The positive step-up unit CPU 2 has a transfer transistor M13 and a discharge transistor M23, and the positive booster unit CPU 3 has a transfer transistor M14 and a discharge transistor M24.
The pump capacitors CP1 to CP3 of each positive booster unit are connected to the clock input terminal FP3 in the odd-numbered positive booster units CPU1 and CPU3, and are connected to the clock input terminal FP4 in the even-numbered positive booster unit CPU2.
Further, the auxiliary pump capacitors CG2 to CG4 of each positive boost unit are connected to the clock input terminal FP2 in the odd-numbered positive boost unit CPU1 and CPU3, and are connected to the clock input terminal FP1 in the even-numbered positive boost unit CPU2. ..

The positive boost unit output stage CPO connects a transfer transistor M15 having a source connected to the output stage input terminal CPOi and a drain connected to the output stage output terminal CPOo, and a first electrode connected to the source of the transfer transistor M15. A pump capacitor CP4 in which a second electrode is connected to the clock input terminal FP4, and an auxiliary pump capacitor CG5 in which the first electrode is connected to the gate of the transfer transistor M15 and the second electrode is connected to the clock input terminal FP1. And a discharge transistor M25 having the source connected to the source of the transfer transistor M15, the drain connected to the gate of the transfer transistor M15, and the gate connected to the drain of the transfer transistor M15.

FIG. 9 shows the clock input terminals FP1 to FP4 in FIG. 8, the drain voltage Vdp1 of the transfer transistor M14, the source voltage Vsp1, and the gate voltage Vgp1. The operation of the charge pump circuit of FIG. 8 will be described with reference to FIG.

The clock input terminal FP1 becomes low level at time t1. As a result, the voltage difference between the gate and source of the transfer transistor M11 becomes low through the auxiliary pump capacitor CG1, and the source and drain of the transfer transistor M11 do not conduct. The clock input terminal FP1 becomes high level at time t8. As a result, the voltage difference between the gate and source of the transfer transistor M11 increases through the auxiliary pump capacitor CG1, and the source and drain of the transfer transistor M11 become conductive.
The clock input terminal FP2 becomes high level at time t4. As a result, the voltage difference between the gate and source of the transfer transistor M12 increases through the auxiliary pump capacitor CG2, and the source and drain of the transfer transistor M12 become conductive. The clock input terminal FP2 becomes low level at time t5. As a result, the voltage difference between the gate and source of the transfer transistor M12 becomes low through the auxiliary pump capacitor CG2, and the source and drain of the transfer transistor M12 do not conduct.
The clock input terminal FP3 becomes high level at time t2. As a result, the voltage difference between the gate and source of the discharge transistor M21 becomes high through the pump capacitor CP1, and the source and drain of the discharge transistor M21 become conductive. The clock input terminal FP3 becomes low level at time t7. As a result, the voltage difference between the gate and source of the discharge transistor M21 becomes low through the pump capacitor CP1, and the source and drain of the discharge transistor M21 do not conduct with each other.
The clock input terminal FP4 becomes low level at time t3. As a result, the voltage difference between the gate and source of the discharge transistor M22 becomes low through the pump capacitor CP2, and the source and drain of the discharge transistor M22 do not conduct with each other. The clock input terminal FP4 becomes high level at time t6. As a result, the voltage difference between the gate and source of the discharge transistor M22 increases through the pump capacitor CP2, and the source and drain of the discharge transistor M22 become conductive.

The source voltage Vsp1 shows a waveform synchronized with the clock input terminal FP3. Further, the gate voltage Vgp1 shows a waveform synchronized with the clock input terminal FP2. Originally, the drain voltage Vdp1 shows a waveform synchronized with the clock input terminal FP4, but shows the same waveform as the source voltage Vsp1. This is because the gate voltage Vgp1 of the transfer transistor M14 has become a high voltage sufficiently exceeding the threshold of the transfer transistor M14 with respect to Vsp1, the discharge transistor M24 does not function as a transistor, and the transfer transistor M14 becomes It's happening because it's always on.

The sections T1 to T8 in FIG. 9 will be described later.

The problems mentioned above are caused by what will be described below.
At startup, the positive boosting progresses from the positive booster unit input stage CPI side close to the power supply voltage VCS in FIG. 8, so that the discharge transistors M22 to M25 arranged further on the positive voltage side in FIG. 8 do not operate. At the time of startup, it is undefined how much charge is accumulated in each wiring, and it is possible that the charge is accumulated in the gates of the transfer transistors M11 to M15. Therefore, the gate-source voltage of the transfer transistors M11 to M15 cannot be cleared at the time of startup, and the transfer transistors M11 to M15 may always be turned on and contribute to positive boosting.

Further, since the source of the discharge transistor M21 of the positive booster unit input stage CPI is fixed at the power supply voltage VCS, the discharge transistor M21 cannot be sufficiently turned on, and the transfer transistor M11 is weakly turned on for transfer. There may be a problem that a backflow occurs from the drain of the transistor M11 to the source side and the positive voltage cannot be sufficiently boosted.

FIG. 9A shows the operating state of each transistor in the sections T1 to T8 shown in FIG.
It also shows a case where the positive booster unit CPU3 (transfer transistor M14, discharge transistor M24) and the positive boost unit output stage CPO (transfer transistor M15, discharge transistor M25) cause abnormal operation.
The transfer transistor M14 is ON only in the section T4 during normal operation, but is ON in all sections during abnormal operation.
The discharge transistor M24 is ON in the sections T1 to T2 and T6 to T8 during normal operation, but is OFF in all sections during abnormal operation.
The transfer transistor M15 is ON only in the section T8 during normal operation, but is ON in all sections during abnormal operation.
The discharge transistor M25 is ON in the sections T3 to T5 during normal operation, but is OFF in all sections during abnormal operation.

Japanese Unexamined Patent Publication No. 2003-234408

The charge pump circuit described in Patent Document 1 does not disclose the possibility of operational instability of the sub-NMOS transistor.

Further, it has been found by the present inventor that the negative boost type charge pump circuit shown in FIG. 6 or the positive boost type charge pump circuit shown in FIG. 8 has the following problems as described above.

At startup, the negative boost or positive boost proceeds from the side close to the ground voltage GND or the power supply voltage VCS, so the discharge transistor arranged on the higher voltage side does not function. At startup, it is uncertain how much charge is accumulated in each wiring, and it is possible that the charge is accumulated in the gate of the transfer transistor. Therefore, there may be a problem that the gate-source voltage of the transfer transistor cannot be cleared at startup, and the transfer transistor is always turned on, which may not contribute to negative boosting or positive boosting.

Furthermore, since the gate or source of the discharge transistor closest to the ground voltage GND or the power supply voltage VCS is fixed to the ground voltage GND or the power supply voltage VCS, the discharge transistor cannot be sufficiently turned on and the transfer transistor is weak. There is a problem that it is turned on and a backflow is generated in the transfer transistor, so that the negative boost or the positive boost cannot be sufficiently performed.

The present invention has been made in consideration of the above problems, and an object of the present invention is to eliminate malfunctions and improve negative boosting and positive boosting efficiency in a 4-phase clock-driven charge pump circuit.

One aspect of the charge pump circuit of the present invention is a negative boost type charge pump in which a plurality of charge pump type negative boost units are connected in series, and the negative boost unit has a drain at the input terminal of the negative boost unit. A transfer transistor connected to the output terminal of the negative booster unit and a source connected to the output terminal, a pump capacitor connected to the source of the transfer transistor with the first electrode connected to the source of the transfer transistor, and a second electrode connected to the clock input terminal, and the above. An auxiliary pump capacitor in which the first electrode is connected to the gate of the transfer transistor and the second electrode is connected to the clock input terminal, and the source is connected to the source of the transfer transistor, and the gate of the transfer transistor is connected. The drain is connected to the gate, and the transfer transistor of the negative booster unit in the previous stage or the transfer transistor of the negative booster unit input stage is connected to the gate of the transfer transistor.

In another aspect of the charge pump circuit of the present invention, the negative booster unit input stage has a transfer transistor having a drain connected to an input stage input terminal and a source connected to an input stage output terminal, and a transfer transistor. A pump capacitor in which the first electrode is connected to the source and the second electrode is connected to the clock input terminal, and the first electrode is connected to the gate of the transfer transistor, and the second electrode is connected to the clock input terminal. With the auxiliary pump capacitor connected to, the discharge transistor connected to the source of the transfer transistor, the drain connected to the gate of the transfer transistor, and the gate connected to the clock input terminal. It is composed.

In another aspect of the charge pump circuit of the present invention, the negative booster unit output stage has a transfer transistor in which a drain is connected to an output stage input terminal and a source is connected to the output stage output terminal, and a gate of the transfer transistor. Auxiliary pump capacitor with the first electrode connected to the clock input terminal and the second electrode connected to the clock input terminal, the source connected to the output stage output terminal, and the drain connected to the gate of the transfer transistor. It is composed of a discharge transistor having the gate connected to the gate of the transfer transistor of the negative booster unit in the previous stage.

Another aspect of the charge pump circuit of the present invention is a positive boost type charge pump in which a plurality of charge pump type positive boost units are connected in series, and the positive boost unit is connected to a positive boost unit input terminal. A transfer transistor with a source connected and a drain connected to the positive boost unit output terminal, and a pump capacitor with a first electrode connected to the source of the transfer transistor and a second electrode connected to the clock input terminal. , The auxiliary pump capacitor in which the first electrode is connected to the gate of the transfer transistor and the second electrode is connected to the clock input terminal, and the source of the transfer transistor is connected to the source of the transfer transistor. The drain is connected to the gate of the above, and the gate is connected to the gate of the transfer transistor of the positive boost unit of the next stage or the transfer transistor of the output stage of the positive boost unit.

In another aspect of the charge pump circuit of the present invention, the positive booster unit input stage has a transfer transistor in which a source is connected to an input stage input terminal and a drain is connected to an input stage output terminal, and a gate of the transfer transistor. Auxiliary pump capacitor with a first electrode connected to the clock input terminal and a second electrode connected to the clock input terminal, and the source connected to the source of the transfer transistor, and its drain connected to the gate of the transfer transistor. It is composed of a discharge transistor which is connected and the gate is connected to the gate of the transfer transistor of the positive booster unit in the subsequent stage.

In another aspect of the charge pump circuit of the present invention, the positive boost unit output stage includes a transfer transistor in which a source is connected to an output stage input terminal and a drain is connected to an output stage output terminal, and the transfer transistor. An auxiliary pump capacitor in which the first electrode is connected to the gate and the second electrode is connected to the clock input terminal, and the first electrode is connected to the source of the transfer transistor and the second electrode is connected to the clock input terminal. And a discharge transistor having its source connected to the source of the transfer transistor, its drain connected to the gate of the transfer transistor, and its gate connected to the drain of the transfer transistor. , Consists of.

According to the present invention, in a charge pump circuit driven by a four-phase clock, it is possible to eliminate a charge pump malfunction and improve negative boosting and positive boosting efficiency.

It is an example of a negative step-up charge pump showing an example of the configuration of the present invention. The waveforms of the main nodes in FIG. 1 are shown. The state of the transistor in the sections T1 to T8 of FIG. 2 is shown. It is an example of a positive step-up charge pump showing an example of the configuration of the present invention. The waveforms of the main nodes in FIG. 3 are shown. The state of the transistor in the section T1 to T8 of FIG. 4 is shown. It is a voltage waveform of the output terminal VNOUT of the negative step-up type charge pump. The negative step-up charge pump which the inventor examined in advance is shown. The waveforms of the main nodes in FIG. 6 are shown. The state of the transistor in the section T1 to T8 of FIG. 7 is shown. The positive step-up charge pump which the inventor examined in advance is shown. The waveform of the main node of FIG. 8 is shown. The state of the transistor in the section T1 to T8 of FIG. 9 is shown.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows an example of the configuration of the present invention of a negative step-up charge pump. The parts having the same functions as those in FIG. 6 are designated by the same reference numerals.

The negative booster unit input stage CNI, the negative booster units CNU1 to CNU3, and the negative booster unit output stage CNO are connected in series.
A ground voltage GND is connected to the negative booster unit input terminal CNIi of the negative booster unit input stage CNI, and the output stage output terminal CNOo of the negative booster unit output stage CNO forms the output terminal VNOUT of the negative booster circuit.
A capacitor COUT and a load ROUT are connected in parallel between the output terminal VNOUT and the ground voltage GND. Here, the capacitor COUT is prepared for smoothing the output voltage. Further, the capacitor COUT also includes a parasitic capacitor generated at the output terminal VNOUT. The load ROUT represents a load driven by the charge pump circuit.

The negative booster unit input stage CNI has a transfer transistor M41 having a drain connected to the input stage input terminal CNIi and a source connected to the input stage output terminal CNIo, and a first electrode connected to the gate of the transfer transistor M41. Auxiliary pump capacitor CG1 with a second electrode connected to the clock input terminal FN1 and pump capacitor CP1 with the first electrode connected to the source of the transfer transistor M41 and the second electrode connected to the clock input terminal FN3. And a discharge transistor M51 having the source connected to the source of the transfer transistor M41, the drain connected to the gate of the transfer transistor M41, and the gate connected to the clock input terminal FN4.

The negative boosting units CNU1 to CNU3 have the same configuration, and for example, the negative boosting unit CNU1 will be described as an example.
The negative booster unit CNU1 has a transfer transistor M42 having a drain connected to the negative booster unit input terminal CNUi and a source connected to the negative booster unit output terminal CNUo, and a first electrode connected to the source of the transfer transistor M42. A pump capacitor CP2 having a second electrode connected to the clock input terminal FN4 and an auxiliary pump capacitor CG2 having a first electrode connected to the gate of the transfer transistor M42 and a second electrode connected to the clock input terminal FN2. The discharge transistor is connected to the source of the transfer transistor M42, the drain is connected to the gate of the transfer transistor M42, and the gate is connected to the gate of the transfer transistor M41 of the negative boost unit input stage CNI. It has M52. The gate of the discharge transistor M53 of the negative boost unit CNU2 is connected to the gate of the transfer transistor M42 of the negative boost unit CNU1, and the gate of the discharge transistor M54 of the negative boost unit CNU3 is the transfer transistor M43 of the negative boost unit CNU2. The gate of the discharge transistor is connected to the gate of the transfer transistor existing on the ground voltage GND side of one unit so as to be connected to the gate.
Any number of negative booster units may be prepared according to the target voltage and connected in series. In this example, three negative boosting units are tentatively connected.
The negative boost unit CNU2 has a transfer transistor M43 and a discharge transistor M53, and the negative boost unit CNU3 has a transfer transistor M44 and a discharge transistor M54.
The pump capacitors CP2 to CP4 of each negative booster unit are connected to the clock input terminal FN4 in the odd-numbered negative booster units CNU1 and CNU3, and are connected to the clock input terminal FN3 in the even-numbered negative booster units CNU2 and the like. To.
Further, the auxiliary pump capacitors CG2 to CG4 of each negative booster unit are connected to the clock input terminal FN2 in the odd-numbered negative booster units CNU1 and CNU3, and are connected to the clock input terminal FN1 in the even-numbered negative booster units CNU2 and the like. Will be done.

The negative booster unit output stage CNO has a transfer transistor M45 having a drain connected to the output stage input terminal CNOi and a source connected to the output stage output terminal CNOo, and a first electrode connected to the gate of the transfer transistor M45. The auxiliary pump capacitor CG5 having the second electrode connected to the clock input terminal FN1 and the source connected to the source of the transfer transistor M45, the drain connected to the gate of the transfer transistor M45, and the negative booster unit CNU3. It has a discharge transistor M55 connected to the gate of the transfer transistor M44.

The discharge transistors M52 to M55 operate by using the gate voltage of the transfer transistor on the GND side of the ground voltage of one unit, and have a positive voltage as compared with the conventional discharge transistors M52 to M55 in FIG. Since it operates at a voltage close to, it is possible to reliably prevent the transfer transistors M42 to M45 from always turning on.

Further, the discharge transistor M51 is sufficiently turned on or off because its gate is directly driven by the clock input terminal FN4. As a result, the transfer transistor M41 is prevented from being weakly turned on, and the negative boost can be sufficiently performed.

FIG. 2 shows the clock input terminals FN1 to FN4 in FIG. 1, the drain voltage Vdn2 of the transfer transistor M45, the source voltage Vsn2, and the gate voltage Vgn2. The operation of the charge pump circuit of FIG. 1 will be described with reference to FIG.

The clock input terminal FN1 becomes high level at time t4. As a result, the gate voltage of the transfer transistor M41 and the discharge transistor M52 becomes higher and conducts through the auxiliary pump capacitor CG1. The clock input terminal FN1 becomes low level at time t5. As a result, the gate voltage of the transfer transistor M41 and the discharge transistor M52 becomes low through the auxiliary pump capacitor CG1 and does not conduct.
The clock input terminal FN2 becomes low level at time t1. As a result, the gate voltage of the transfer transistor M42 and the discharge transistor M53 becomes low through the auxiliary pump capacitor CG2, and the conduction does not occur. The clock input terminal FN2 becomes high level at time t8. As a result, the gate voltage of the transfer transistor M42 and the discharge transistor M53 becomes high and conducts through the auxiliary pump capacitor CG2.
The clock input terminal FN3 becomes high level at time t2. As a result, the gate of the auxiliary pump capacitor CG1 and the transfer transistor M41 is charged through the parasitic diode between the pump capacitor CP1 and the back gate / drain of the discharge transistor M51. The clock input terminal FN3 becomes low level at time t7. As a result, the source potential of the discharge transistor M51 becomes low through the pump capacitor CP1, and the potential difference between the gate and the source of the discharge transistor M51 becomes large to conduct conduction.
The clock input terminal FN4 becomes low level at time t3. As a result, the source potential of the discharge transistor M52 becomes low through the pump capacitor CP2, and the potential difference between the gate and the source of the discharge transistor M52 becomes large to conduct conduction. Further, the gate voltage of the discharge transistor M51 becomes low and the conduction does not occur. The clock input terminal FN4 becomes high level at time t6. As a result, the gate of the auxiliary pump capacitor CG2 and the transfer transistor M42 is charged through the parasitic diode between the back gate and the drain of the discharge transistor M52 through the pump capacitor CP2. Further, the gate voltage of the discharge transistor M51 becomes high and becomes conductive.

The drain voltage Vdn2 shows a waveform synchronized with the clock input terminal FN4. Further, the gate voltage Vgn2 shows a waveform synchronized with the clock input terminal FN1. Further, the source voltage Vsn2 shows a waveform gradually approaching the drain voltage Vdn2 when the clock input terminal FN1 is at a high level, and is discharged by the load ROUT when the clock input terminal FN1 is at a low level. Compared with FIG. 7, the waveform of the source voltage Vsn2 has changed, and it can be seen that the operation is correct.

The sections T1 to T8 in FIG. 2 will be described below.

FIG. 2A shows the operating state of each transistor in the sections T1 to T8 shown in FIG.
The transfer transistor M44 is operating normally, and only the section T8 is ON.
The discharge transistor M54 is operating normally and is turned on in the sections T3 to T5. However, the sections T3 and T5 are weakly ON. Since the discharge transistor M54 has a configuration in which the clock input terminal FN1 drives the gate and the clock input terminal FN4 drives the source, the time T4 at which the potential difference between the two is maximum is defined as ON.
The transfer transistor M45 is operating normally, and only the section T4 is ON.
The discharge transistor M55 is operating normally, and only the section T8 is ON.
All transistors will operate normally as described above.
It should be noted that the transistor state in the normal state of FIG. 7A does not match with that of the previous circuit, because the configuration is different from that of the conventional circuit.

As a result, the transfer transistor is prevented from being turned on all the time, and the negative boosting operation of the first stage can be sufficiently performed, so that the negative boosting efficiency of the charge pump as a whole is improved.

FIG. 3 shows an example of the configuration of the present invention of a positive step-up charge pump. The parts having the same functions as those in FIG. 8 are designated by the same reference numerals.

The positive booster unit input stage CPI, the positive booster unit CPU1 to CPU3, and the positive booster unit output stage CPO are connected in series.
The power supply voltage VCS (for example, 2V or 3V) is connected to the positive booster unit input terminal CPIi of the positive booster unit input stage CPI, and the output stage output terminal CPOo of the positive booster unit output stage CPO is the output terminal of the positive booster circuit. It forms a VPOUT.
A capacitor COUT and a load ROUT are connected in parallel between the output terminal VPOUT and the ground voltage GND. Here, the capacitor COUT is prepared for smoothing the output voltage. Further, the capacitor COUT also includes a parasitic capacitor generated at the output terminal VPOUT. The load ROUT represents a load driven by the charge pump circuit.

The positive boost unit input stage CPI connects a transfer transistor M11 having a source connected to the input stage input terminal CPIi and a drain connected to the input stage output terminal CPIo, and a first electrode connected to the gate of the transfer transistor M11. Auxiliary pump capacitor CG1 having a second electrode connected to the clock input terminal FP1 and its source connected to the source of the transfer transistor M11, and its drain connected to the gate of the transfer transistor M11 to form a positive boost unit CPU1. It has a discharge transistor M21 connected to the gate of the transfer transistor M12.

The positive booster units CPU1 to CPU3 have the same configuration, and for example, the positive booster unit CPU1 will be described as an example.
The positive boost unit CPU1 connects a transfer transistor M12 having a source connected to the positive boost unit input terminal CPUi and a drain connected to the positive boost unit output terminal CPUo, and a first electrode connected to the source of the transfer transistor M12. The pump capacitor CP1 having the second electrode connected to the clock input terminal FP3 and the auxiliary pump capacitor CG2 having the first electrode connected to the gate of the transfer transistor M12 and the second electrode connected to the clock input terminal FP2. The source is connected to the source of the transfer transistor M12, the drain is connected to the gate of the transfer transistor M12, and the gate is connected to the gate of the transfer transistor M13 of the positive booster unit CPU 2 in the next stage for discharge. It has a transistor M22. The gate of the discharge transistor M23 of the positive boost unit CPU 2 is connected to the gate of the transfer transistor M14 of the positive boost unit CPU 3, and the gate of the discharge transistor M24 of the positive boost unit CPU 3 is for transfer of the positive boost unit output stage CPO. The gate of the discharge transistor is connected to the gate of the transfer transistor existing on the output terminal VPOUT side of one unit, such as being connected to the gate of the transistor M15.
Arbitrary number of positive step-up units may be prepared according to the target voltage and connected in series. In this example, three positive booster units are tentatively connected.
The positive step-up unit CPU 2 has a transfer transistor M13 and a discharge transistor M23, and the positive booster unit CPU 3 has a transfer transistor M14 and a discharge transistor M24.
The pump capacitors CP1 to CP3 of each positive booster unit are connected to the clock input terminal FP3 in the odd-numbered positive booster units CPU1 and CPU3, and are connected to the clock input terminal FP4 in the even-numbered positive booster unit CPU2 and the like. To.
Further, the auxiliary pump capacitors CG2 to CG4 of each positive booster unit are connected to the clock input terminal FP2 in the odd-numbered positive booster units CPU1 and CPU3, and are connected to the clock input terminal FP1 in the even-numbered positive booster unit CPU2 and the like. Will be done.

The positive boost unit output stage CPO connects a transfer transistor M15 having a source connected to the output stage input terminal CPOi and a drain connected to the output stage output terminal CPOo, and a first electrode connected to the gate of the transfer transistor M15. Auxiliary pump capacitor CG5 with a second electrode connected to the clock input terminal FP1 and pump capacitor CP4 with the first electrode connected to the source of the transfer transistor M15 and the second electrode connected to the clock input terminal FP4. And a discharge transistor M25 having the source connected to the source of the transfer transistor M15, the drain connected to the gate of the transfer transistor M15, and the gate connected to the drain of the transfer transistor M15.

The discharge transistors M21 to M24 operate by utilizing the gate voltage of the transfer transistor on the one unit output terminal VPOUT side, and have a higher positive than the conventional discharge transistors M21 to M24 in FIG. Since it operates with a voltage, it is possible to reliably prevent the transfer transistors M11 to M14 from always being turned on.

FIG. 4 shows the clock input terminals FP1 to FP4 in FIG. 3, the drain voltage Vdp2 of the transfer transistor M14, the source voltage Vsp2, and the gate voltage Vgp2. The operation of the charge pump circuit of FIG. 3 will be described with reference to FIG.

The clock input terminal FP1 becomes low level at time t1. As a result, the gate voltage of the transfer transistor M11 becomes low through the auxiliary pump capacitor CG1 and does not conduct. The clock input terminal FP1 becomes high level at time t8. As a result, the gate voltage of the transfer transistor M11 becomes high and conducts through the auxiliary pump capacitor CG1.
The clock input terminal FP2 becomes high level at time t4. As a result, the gate voltage of the transfer transistor M12 and the discharge transistor M21 becomes high and conducts through the auxiliary pump capacitor CG2. The clock input terminal FP2 becomes low level at time t5. As a result, the gate voltage of the transfer transistor M12 and the discharge transistor M21 becomes low through the auxiliary pump capacitor CG2, and the conduction does not occur.
The clock input terminal FP3 becomes high level at time t2. As a result, the gate of the auxiliary pump capacitor CG2 and the transfer transistor M12 is charged through the parasitic diode between the back gate and the drain of the discharge transistor M22 through the pump capacitor CP1. The clock input terminal FP3 becomes low level at time t7. As a result, the source voltage of the discharge transistor M22 is lowered through the pump capacitor CP1, and the gate-source voltage of the discharge transistor M22 is increased to conduct conduction.
The clock input terminal FP4 becomes low level at time t3. As a result, the source voltage of the discharge transistor M23 is lowered through the pump capacitor CP2, the gate-source voltage of the discharge transistor M23 increases and conducts, and the transfer transistor M13 does not conduct. The clock input terminal FP4 becomes high level at time t6. As a result, the gate of the auxiliary pump capacitor CG3 and the transfer transistor M13 is charged through the parasitic diode between the back gate and the drain of the discharge transistor M23 through the pump capacitor CP2.

The source voltage Vsp2 shows a waveform synchronized with the clock input terminal FP3. Further, the gate voltage Vgp2 shows a waveform synchronized with the clock input terminals FP2 and FP3. When the clock input terminal FP3 becomes high level, the source voltage Vsp2 becomes higher through the pump capacitor CP3, and when the source voltage Vsp2 becomes higher potential than the gate voltage Vgp2, the parasitic diode between the back gate and drain of the discharge transistor M24. The gate voltage Vgp2 is charged through. Further, when the clock input terminal FP3 becomes a low level, the source voltage Vsp2 becomes low through the pump capacitor CP3, and when the source voltage Vsp2 becomes a lower potential than the gate voltage Vgp2, it conducts due to the gate-source voltage of the discharge transistor M24. Then, the gate voltage Vgp2 is discharged.
Further, the drain voltage Vdp2 shows a waveform synchronized with the clock input terminal FP4. Compared with FIG. 9, it can be seen that the waveform of the drain voltage Vdp2 is changed and the voltage is correctly boosted.

The sections T1 to T8 in FIG. 4 will be described below.

FIG. 4A shows the operating state of each transistor in the sections T1 to T8 shown in FIG.
The positive booster unit output stage CPO (transfer transistor M15, discharge transistor M25) is shown even during abnormal operation because there is no difference in configuration between the previous (FIG. 8) and the present invention (FIG. 3).
The transfer transistor M14 is operating normally, and only the section T4 is ON.
The discharge transistor M24 is operating normally and is turned on in the sections T1, T7 to T8. However, the sections T1 and T7 are weakly ON. Since the discharge transistor M24 has a configuration in which the clock input terminal FP1 drives the gate and the clock input terminal FP3 drives the source, the time T8 at which the potential difference between the two is maximum is defined as ON.
The transfer transistor M15 is ON only in the section T8 during normal operation, but is ON in all sections during abnormal operation.
The discharge transistor M25 is ON in the sections T3 to T5 during normal operation, but is OFF in all sections during abnormal operation.
All the transistors except the transistor included in the positive boost unit output stage CPO will operate normally as described above.
It should be noted that the transistor state in the normal state of FIG. 9A does not match with that of the previous circuit, because the configuration is different from that of the conventional circuit.

As a result, the transfer transistor is prevented from being turned on all the time, and the positive boosting operation of the first stage can be sufficiently performed, so that the positive boosting efficiency of the charge pump as a whole is improved.
As mentioned above, regarding the positive booster unit output stage CPO (transfer transistor M15, discharge transistor M25), there is no difference in configuration between the previous (FIG. 8) and the present invention (FIG. 3), so there is a possibility of abnormal operation. Still remains.

FIG. 5 shows the temporal transition of the output voltage VN of the negative boost type charge pump shown in FIG. Further, the broken line X1 is the output voltage VN'of the negative boost type charge pump shown in FIG. In the negative boost type charge pump shown in FIG. 6, all the units may not operate normally, but it shows a case where the negative boost unit output stage CNO does not operate normally.

At time t0, the charge pump circuit is activated. At this time, the output voltages VN and VN'are both 0.
At time t1, there is a difference between the output voltage VN and the output voltage VN'. This difference occurs because the output voltage VN'is not operating normally in the negative booster unit output stage CNO.
After that, the start of the charge pump circuit is continued, and the voltage difference between the output voltage VN and the output voltage VN'is gradually increased.
At time t2, the output voltage VN has reached the target set voltage OUT, so that the start-up is terminated. However, since the output voltage VN'has not reached the target set voltage OUT, further start-up is required.
At time t3, the output voltage VN'reaches the target set voltage OUT and ends the start-up.

In this example, only the negative booster unit output stage CNO in FIG. 6 is shown as not operating normally, but in the charge pump circuit of FIG. 6, other units may not operate normally. In that case, it will take a longer time to start the output voltage VN'.

From the above, it can be seen that the negative boosting efficiency of the charge pump as a whole is improved by preventing the transfer transistor from being constantly turned on.

Further, although the present invention has been described with the MPLS transistor, it is easily understood by those skilled in the art that the same can be achieved with the polyclonal transistor.

The present invention improves the negative boost and positive boost efficiency in a 4-phase clock-driven charge pump circuit. Therefore, the present invention has extremely high industrial applicability.

CG1 to CG5 Auxiliary pump capacitor CNI negative boost unit input stage CNIi input stage input terminal CNOo input stage output terminal CNO negative boost unit output stage CNOi output stage input terminal CNOo output stage output terminal CNU1 to CNU4 negative boost unit CNUi negative boost unit input Terminal CNUo Negative boost unit output terminal COUT capacitor CP1 to CP4 Pump capacitor CPI Positive boost unit input stage CPIi Input stage input terminal CPIo Input stage output terminal CPO Positive boost unit output stage CPOi Output stage input terminal CPOo Output stage output terminal CPU1 to CPU3 Positive booster unit CPUi Positive booster unit input terminal CPUo Positive booster unit output terminal FN1 to FN4, FP1 to FP4 Clock input terminal GND Ground voltage M11 to M15, M41 to M45 Transfer transistor M21 to M25, M51 to M55 Discharge transistor OUT Target Set voltage ROUT load t1 to t8 Time T1 to T8 section VCS power supply voltage Vdn1, Vdn2, Vdp1, Vdp2 Drain voltage Vgn1, Vgn2, Vgp1, Vgp2 Gate voltage VN, VN'Output voltage VNOUT output terminal VPOUT output terminal Vsn1, Vsn2 , Vsp2 source voltage

Claims (6)

The m-stage charge pump type negative booster unit is connected in series and is configured to operate by receiving the inputs of the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal having different phases . It is a negative boost type charge pump,
Of the negative boosting units
The input stage of the negative booster unit in the first stage is
A first transfer transistor with a drain connected to the first input terminal and a source connected to the first output terminal.
A first pump capacitor having a first electrode connected to the source of the first transfer transistor and a second electrode connected to the input terminal of the third clock signal.
A first auxiliary pump capacitor having a first electrode connected to the gate of the first transfer transistor and a second electrode connected to the input terminal of the first clock signal.
A first discharge transistor having its source connected to the source of the first transfer transistor, its drain connected to the gate of the first transfer transistor, and its gate connected to the input terminal of the fourth clock signal. ,
Including
The intermediate stages of the negative booster unit in the kth stage (however, k = 2, 3, ..., M-1) are, respectively.
A drain connected to the first k input terminals, and the k transfer transistor having a source connected to the k-th output terminal,
The first electrode is connected to the source of the k-th transfer transistor, and if k is an even number, it is connected to the input terminal of the fourth clock signal, and if k is odd, it is connected to the input terminal of the third clock signal. The k-th pump capacitor connected to the electrodes of
A first electrode is connected to the gate of the k-th transfer transistor, and if k is an even number, it is connected to the input terminal of the second clock signal, and if k is odd, it is connected to the input terminal of the first clock signal. Capacitor for the k-th auxiliary pump to which the electrodes of
The connecting its source to the source of the first k transfer transistor, its drain connected to the gate of the first k transfer transistor, and a gate connected to the gate of the previous stage of the (k-1) transfer transistor k discharge transistor and
Including
The output stage of the negative booster unit in the mth stage is
The mth transfer transistor with the drain connected to the mth input terminal and the source connected to the mth output terminal,
A first electrode is connected to the gate of the m-th transfer transistor, and if m is even, it is connected to the input terminal of the first clock signal, and if m is odd, it is connected to the input terminal of the second clock signal. Capacitor for the mth auxiliary pump to which the electrodes of
The source is connected to the mth output terminal, the drain is connected to the gate of the mth transfer transistor, and the gate is connected to the gate of the (m-1) transfer transistor in the previous stage for the mth discharge. With a transistor
Including charge pump circuit. The first transfer transistor to the m transfer transistor and the first discharge transistor to the m discharge transistor are all N-channel types, and the first section and the first section are arranged in chronological order. Each drive state changes in the order of 2 sections, 3rd section, 4th section, 5th section, 6th section, 7th section and 8th section.
In the first section and the seventh section, the first clock signal, the second clock signal, and the third clock signal are at low level, and the fourth clock signal is at high level, respectively.
In the second section and the sixth section, the first clock signal and the second clock signal are at low level, and the third clock signal and the fourth clock signal are at high level, respectively.
In the third section and the fifth section, the first clock signal, the second clock signal, and the fourth clock signal are at low level, and the third clock signal is at high level, respectively.
In the fourth section, the first clock signal and the third clock signal are at high level, and the second clock signal and the fourth clock signal are at low level.
In the eighth section, the first clock signal and the third clock signal are at low level, and the second clock signal and the fourth clock signal are at high level.
The charge pump circuit according to claim 1. The i-th (where i is an even number of m or less) transfer transistor is in the off state in the first section to the seventh section and in the on state in the eighth section.
The i-discharge transistor is in an off state in the first section, the second section, and the sixth section to the eighth section, and is in a weak on state in the third section and the fifth section.
The j-th (where j is an odd number of m or less) transfer transistor is in the off state in the first section to the third section and in the fifth section to the eighth section and in the on state in the fourth section. ,
The j-discharge transistor is in the off state in the first section to the seventh section and in the on state in the eighth section.
The charge pump circuit according to claim 2. The m-stage charge pump type positive booster unit is connected in series and is configured to operate by receiving the inputs of the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal having different phases . It is a positive boost type charge pump,
Of the positive boosting units
The input stage of the positive booster unit in the first stage is
A first transfer transistor with a source connected to the first input terminal and a drain connected to the first output terminal.
A first auxiliary pump capacitor having a first electrode connected to the gate of the first transfer transistor and a second electrode connected to the input terminal of the first clock signal.
For the first discharge, the source is connected to the source of the first transfer transistor, the drain is connected to the gate of the first transfer transistor, and the gate is connected to the gate of the second transfer transistor in the next stage. With a transistor
Including
The intermediate stages of the positive booster unit in the kth stage (however, k = 2, 3, ..., M-1) are, respectively.
A transistor for k-th transfer, in which the source is connected to the k-th input terminal and the drain is connected to the k-th output terminal.
The first electrode is connected to the source of the k-th transfer transistor, and if k is an even number, it is connected to the input terminal of the third clock signal, and if k is odd, it is connected to the input terminal of the fourth clock signal. The k-th pump capacitor connected to the electrodes of
A first electrode is connected to the gate of the k-th transfer transistor, and if k is an even number, it is connected to the input terminal of the second clock signal, and if k is odd, it is connected to the input terminal of the first clock signal. Capacitor for the k-th auxiliary pump to which the electrodes of
The k-th source is connected to the source of the k-th transfer transistor, the drain is connected to the gate of the k-th transfer transistor, and the gate is connected to the gate of the next (k + 1) transfer transistor . Discharge transistor and
Including
The output stage of the positive booster unit in the mth stage is
The mth transfer transistor with the source connected to the mth input terminal and the drain connected to the mth output terminal,
A first electrode is connected to the gate of the m transfer transistor, and if m is an even number, it is connected to the input terminal of the second clock signal, and if m is odd, it is connected to the input terminal of the first clock signal. Capacitor for the mth auxiliary pump to which the electrodes of
The first electrode is connected to the source of the m-th transfer transistor, and if m is even, it is connected to the input terminal of the third clock signal, and if m is odd, it is connected to the input terminal of the fourth clock signal. The m-th pump capacitor connected to the electrodes of
With the m-th discharge transistor in which the source is connected to the source of the m-th transfer transistor, the drain is connected to the gate of the m-th transfer transistor, and the gate is connected to the drain of the m-th transfer transistor. ,
Including charge pump circuit. The first transfer transistor to the m transfer transistor and the first discharge transistor to the m discharge transistor are all N-channel types, and the first section and the first section are arranged in chronological order. Each drive state changes in the order of 2 sections, 3rd section, 4th section, 5th section, 6th section, 7th section and 8th section.
In the first section and the seventh section, the first clock signal, the second clock signal, and the third clock signal are at low level, and the fourth clock signal is at high level, respectively.
In the second section and the sixth section, the first clock signal and the second clock signal are at low level, and the third clock signal and the fourth clock signal are at high level, respectively.
In the third section and the fifth section, the first clock signal, the second clock signal, and the fourth clock signal are at low level, and the third clock signal is at high level, respectively.
In the fourth section, the first clock signal and the fourth clock signal are at low level, and the second clock signal and the third clock signal are at high level.
In the eighth section, the first clock signal and the fourth clock signal are at high level, and the second clock signal and the third clock signal are at low level.
The charge pump circuit according to claim 4. The i-th (where i is an even number of m or less) transfer transistor is in the off state in the first section to the third section and in the fifth section to the eighth section and in the on state in the fourth section. ,
The i-discharge transistor is in a weak on state in the first section and the seventh section, is in the off state in the second section to the sixth section, and is in the on state in the eighth section.
The j-th (where j is an odd number of m or less) transfer transistor is in the off state in the first section to the seventh section and in the on state in the eighth section.
The j-discharge transistor is in the off state in the first section, the second section, and the sixth section to the eighth section, and is in the on state in the fourth section and the fifth section.
The charge pump circuit according to claim 5.

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