JP7063692B2 - Watchdog timer monitoring system - Google Patents

Description

The present invention relates to a watchdog timer monitoring system that monitors the operation of a processing device using a watchdog timer.

A watchdog timer is widely used as an electronic device for monitoring the operating state of a processing device such as a microcomputer or a CPU. The watchdog timer is a timer that counts a preset time-out time, determines that an abnormality has occurred in the operation of the processing device, and outputs a reset signal for restarting the processing device.

When the processing device to be monitored is operating normally, it outputs a clear pulse to clear the count to the watchdog timer before timing out to prevent unnecessary restart.

Generally, a processing device is provided with a sleep mode (also referred to as a standby mode, a standby power supply mode, or the like) in order to reduce power consumption during standby. The processing device monitored by the watchdog timer is periodically activated even when the device shifts to the sleep mode, and outputs a clear pulse to the watchdog timer.

Japanese Unexamined Patent Publication No. 2006-318306

In the watchdog timer monitoring system that monitors the operation of the processing device using the watchdog timer, in order to further reduce the power consumption during standby, the watchdog timer is linked to the sleep mode transition of the processing device. It is effective to stop the operation as well. This eliminates the need to periodically start the processing device to output a clear pulse when the processing device shifts to the sleep mode, and also eliminates the need for operating power of the watchdog timer.

In order to stop the operation of the watchdog timer in conjunction with the transition to the sleep mode of the processing device, for example, as shown in FIG. 2, the sleep signal output by the processing device 310 by software processing at the transition to the sleep mode is inverted. It is conceivable to use the signal as an enable signal for the watchdog timer 320.

However, if some software abnormality occurs in the processing device 310 and a sleep signal is output even though the sleep mode has not been entered, the watchdog timer that should normally restart the processing device 310 is stopped. Therefore, the processing device 310 in which the abnormality has occurred cannot be restarted. This reduces the reliability of the system.

Therefore, according to the present invention, in the watchdog timer monitoring system in which the operation of the processing device is monitored by using the watchdog timer, the watchdog is linked to the sleep mode transition of the processing device without deteriorating the reliability of the system. The purpose is to stop the timer.

In order to solve the above problems, the watchdog timer monitoring system according to one aspect of the present invention has a sleep mode and monitors the operation of the processing device that outputs the first sleep signal at the time of transition to the sleep mode and the processing device. A watchdog timer, a current detection unit that detects the current including the current flowing from the power supply to the processing device, and a comparison unit that outputs a second sleep signal when the detection result of the current detection unit is lower than the reference value. The watch dog timer is provided with a determination unit for stopping the watch dog timer when both the first sleep signal and the second sleep signal are output.
Here, the watchdog timer includes an enable terminal, and the determination unit can stop the watchdog timer by negating the enable terminal.
Further, a regulator that converts the power supply voltage into the operating voltage of the processing device may be further provided, and the current detecting unit may be arranged in front of the regulator.

According to the present invention, in a watchdog timer monitoring system that monitors the operation of a processing device using a watchdog timer, the watchdog is linked to the sleep mode transition of the processing device without deteriorating the reliability of the system. The timer can be stopped.

It is a block diagram which shows the watchdog timer monitoring system of this embodiment. It is a block diagram which shows an example of a watchdog timer monitoring system.

Embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a watchdog timer monitoring system 100 according to an embodiment of the present invention. As shown in this figure, the watchdog timer monitoring system 100 includes a processing device 110, a watchdog timer 120, a regulator 130, a current detection unit 140, a comparison unit 150, and a determination unit 160.

The watchdog timer monitoring system 100 is a system that monitors the operating state of the processing device 110 by using the watchdog timer 120. The processing device 110 can be a microcomputer, a CPU, a controller, a computer system, or the like.

When the watchdog timer 120 counts the preset timeout time, it determines that an abnormality has occurred in the operation of the processing device 110, and outputs a reset signal for restarting the processing device 110. When the processing device 110 is operating normally, the processing device 110 outputs a clear pulse for clearing the count to the watchdog timer 120 before the time-out occurs, thereby preventing an unnecessary restart.

The watchdog timer 120 includes an enable terminal, and operates when the enable signal input to the enable terminal is asserted, and stops when the enable signal is negated. Here, it is assumed that the operation is performed when the enable signal is high.

The processing device 110 shifts to a sleep mode with low power consumption when a predetermined condition is satisfied, for example, when there is no input signal for a predetermined time, or when the mounted device is stopped. When the processing device 110 shifts to the sleep mode, the processing device 110 asserts the sleep signal by software processing.

In the watchdog timer monitoring system 100 of the present embodiment, the processing device 110 does not need to output a clear pulse at the time of transition to the sleep mode. As a result, it is not necessary to wake up periodically at the time of transition to the sleep mode, and the power consumption during standby can be further reduced.

The processing device 110 is supplied with electric power from a power source such as a battery. At this time, a regulator 130 for converting the output voltage of the battery into the operating voltage of the processing device 110 is used. The output voltage of the regulator 130 is also supplied to a load other than the processing device 110 in the watchdog timer monitoring system 100.

As described above, when the processing device 110 shifts to the sleep mode, the processing device 110 outputs a sleep signal (software) by software processing. However, if some abnormality occurs in the software, a sleep signal may be output even though the sleep mode has not been entered.

Therefore, in the watchdog timer monitoring system 100 of the present embodiment, it is determined that the processing device 110 has shifted to the sleep mode by a hardware-based determination in addition to a software-based determination. However, even when making a hardware-like determination, there is a risk that the sleep mode will be erroneously determined due to a malfunction or failure. Therefore, the watchdog timer 120 is stopped only when the sleep mode determination is made for both the software determination and the hardware determination. This prevents the watchdog timer 120 from being stopped due to an erroneous determination, and enhances the reliability of the system.

The hardware-like judgment will be described. Since the power consumption is significantly reduced in the sleep mode, the processing device 110 has a large difference in the inflowing current value between the normal startup time and the sleep mode.

Therefore, the current detection unit 140 is used to measure the current flowing into the processing device 110, and the sleep mode is determined. Specifically, when the current flowing into the processing device 110 is smaller than the reference value, it is determined that the processing device 110 has entered the sleep mode. The current detection unit 140 can be configured by using, for example, a resistor having a small value, and can measure the current with the voltage drop generated in the resistor as the detection voltage.

If the current detection unit 140 is arranged between the regulator 130 and the processing device 110, the current flowing into the processing device 110 can be accurately measured, but the voltage supplied to the processing device 110 is reduced. .. Therefore, in the present embodiment, the current detection unit 140 is arranged between the power supply and the regulator 130.

In this case, the current detected by the current detection unit 140 includes not only the current flowing into the processing device 110 but also the current flowing into the load. However, since the current flowing into the processing device 110 during normal operation is sufficiently larger than the other currents, it is possible to determine the sleep mode based on the current value measured by the current detection unit 140.

However, another method may be used for measuring the current flowing into the processing device 110. For example, a Hall element or the like may be used to measure the current flowing into the processing device 110 in a non-contact manner, or a current mirror circuit may be configured to measure the current flowing into the processing device 110.

The detection voltage, which is the output of the current detection unit 140, is compared with the reference voltage in the comparison unit 150. The reference voltage is set to a value slightly lower than the detection voltage detected by the current detection unit 140 during normal operation of the processing device 110. Of course, the value is set sufficiently higher than the detection voltage detected by the current detection unit 140 during sleep of the processing device 110.

The comparison unit 150 can be configured by using a comparator or the like, and outputs a sleep signal (hardware) when the detection voltage output by the current detection unit 140 is smaller than the reference voltage. In the present embodiment, both the sleep signal (software) and the sleep signal (hardware) are set to output high when the sleep mode is determined, but low may be output when the sleep mode is determined.

The sleep signal (software) output by the processing device 110 and the sleep signal (hardware) output by the comparison unit 150 are input to the determination unit 160. The determination unit 160 outputs a signal for stopping the watchdog timer 120 when both the sleep signal (software) and the sleep signal (hardware) are high.

In the present embodiment, the determination unit 160 is composed of a NAND circuit, and when both the sleep signal (software) and the sleep signal (hardware) are high, the enable signal for the watchdog timer 120 is set to low and the enable terminal is negated. The watchdog timer 120 is operated by stopping the watchdog timer 120 and asserting the enable terminal by setting the enable signal to high at other times.

As described above, in the watchdog timer monitoring system 100 of the present embodiment, the watchdog timer 120 is stopped only when it is determined that the processing device 110 has entered the sleep mode in both the software-based determination and the hardware-based determination. I try to let you. This prevents the watchdog timer 120 from being stopped even though a monitoring operation is required.

Further, after the stopped state, if either the software-based determination or the hardware-based determination determines that the sleep mode of the processing device 110 has been released, the watchdog timer 120 returns to the activated state.

As described above, according to the watchdog timer monitoring system 100 of the present embodiment, the watchdog timer 120 can be stopped in conjunction with the transition to the sleep mode of the processing device 110 without deteriorating the reliability of the system. become able to.

100 Watchdog timer monitoring system 110 Processing device 120 Watchdog timer 130 Regulator 140 Current detection unit 150 Comparison unit 160 Judgment unit

Claims (3)

A processing device that has a sleep mode and outputs a first sleep signal when the sleep mode is entered,
A watchdog timer that monitors the operation of the processing device,
A current detector that detects the current including the current flowing from the power supply to the processing device, and
A comparison unit that outputs a second sleep signal when the detection result of the current detection unit is lower than the reference value, and a comparison unit.
A determination unit that sets the watchdog timer to a stop state only when both the first sleep signal and the second sleep signal are output.
A watchdog timer monitoring system featuring. The watchdog timer is provided with an enable terminal.
The watchdog timer monitoring system according to claim 1, wherein the determination unit puts the watchdog timer into a stop state by negating the enable terminal. Further equipped with a regulator that converts the power supply voltage into the operating voltage of the processing device.
The watchdog timer monitoring system according to claim 1 or 2, wherein the current detection unit is arranged in front of the regulator.

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