JP7195602B2 - Circuit diagnosis test device and circuit diagnosis test method - Google Patents

Description

The present invention relates to a circuit diagnostic test apparatus and a circuit diagnostic test method.

In order to comply with functional safety standards for vehicle driving support systems, it is important to research and develop self-diagnostic technologies such as integrated circuits incorporated in devices used in vehicle driving support systems.

For example, Patent Document 1 describes a memory test system that includes a BIST (Built In Self Test) circuit built into a chip. In order to test the memory on the chip, this memory test system has a comparator circuit that outputs a test result signal by comparing output data from the memory with expected value data from the test controller. In this memory test system, the flip-flop of the comparator circuit is shared with the flip-flop of the system logic circuit that latches the output data from the memory.

JP 2017-199445 A

Variable timing clock generation for FPGA self-test, Yasuo Sato, Munehiro Matsuura, Arakawa et al., Y. Miyake, Seiji Kajiwara (Kyutech), IEICE Technical Report, vol. 113, no. 353, DC2013-69, pp. 7-12, December 2013

The memory test system described in Patent Document 1 is expected to output a response signature output from a circuit to be diagnosed to which a test pattern is applied, when the circuit to be diagnosed has no failure. Diagnose the diagnostic target circuit by comparing with the signature. In this case, in order to improve the accuracy of specifying the fault location of the circuit to be diagnosed, the test pattern is changed so as to activate the fault in the specific diagnostic area of the circuit to be diagnosed, and the output from the circuit to be diagnosed is changed. The expected response signature must be repeatedly compared to the expected signature. A test for this diagnosis is called a diagnostic test. Activating a fault means applying a test pattern to a circuit to be diagnosed so that the response pattern output from the circuit to be diagnosed differs depending on whether the fault exists or not.

However, the expected signatures have a large amount of data, and a large-capacity nonvolatile memory is required to store the expected signatures of the diagnostic test as many as can identify the fault location of the circuit to be diagnosed. For this reason, there is a problem that the accuracy of identifying the failure location of the diagnostic target circuit is limited by the capacity of the nonvolatile memory.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a circuit diagnostic test apparatus and circuit diagnostic test method capable of performing a highly accurate diagnostic test without being limited by memory capacity.

A circuit diagnostic test apparatus according to an embodiment of the present invention includes a clock cycle setting unit for setting cycles of clock signals output to a plurality of scan FFs of a circuit to be diagnosed to which a test pattern is set, and a clock cycle setting unit. A response signature generated based on a response pattern output from a plurality of scan FFs when a clock signal set to a predetermined first period is output by and an expected signature generated based on response patterns output from the plurality of scan FFs when a clock signal set to have two cycles is output.

A circuit diagnostic test method according to an embodiment of the present invention includes a clock cycle setting step of setting a cycle of a clock signal output to a plurality of scan FFs of a circuit to be diagnosed to which a test pattern is set; a response signature generated based on a response pattern output from a plurality of scan FFs when a clock signal set to a predetermined first period in the setting step is output; and an expected signature generated based on a response pattern output from a plurality of scan FFs when a clock signal set to a long second period is output, and a diagnostic test step of comparing the expected signature. do.

The circuit diagnostic test apparatus of the present invention can perform highly accurate diagnostic tests without being limited by memory capacity.

1 is a diagram showing an example of a configuration of a circuit diagnosis test device according to one embodiment together with a circuit to be diagnosed; FIG. It is a figure which shows an example of the hardware constitutions of the scan FF of a diagnostic target circuit. 3 is a timing chart showing an example of the operation of the scan FF shown in FIG. 2; FIG. 11 is a diagram showing another example of the hardware configuration of the scan FF of the circuit to be diagnosed; FIG. 5 is a timing chart showing an example of the operation of the scan FF shown in FIG. 4; FIG. 4 is a diagram showing a memory map of a storage unit of the circuit diagnostic test device; FIG. FIG. 3 is a diagram showing functional blocks of a control unit of the circuit diagnostic test device; 4 is a flow chart showing an example of circuit diagnostic test processing executed in the circuit diagnostic test device; 4 is a flow chart showing an example of signature generation processing executed in the circuit diagnostic test device; 8 is a flow chart showing another example of signature generation processing executed in the circuit diagnostic test apparatus; 9 is a flowchart showing still another example of signature generation processing executed in the circuit diagnosis test device; 5 is a flow chart showing an example of pre-diagnosis test processing executed in the circuit diagnosis test apparatus; 4 is a flow chart showing another example of pre-diagnosis test processing executed in the circuit diagnosis test apparatus;

The circuit diagnosis test apparatus of the present invention uses a response signature based on the response when the circuit to be diagnosed is operated with a clock signal having a first cycle, which is the same as that for normal operation, and a clock signal having a second cycle longer than the first cycle. Compare with the expected signature based on the response when the target circuit is operated. Then, the circuit diagnostic test apparatus can determine that a delay fault exists in the diagnostic target circuit when the comparison result between the response signature and the expected signature is different.

Since the circuit diagnostic test apparatus of the present invention automatically generates expected signatures in this way, it is not necessary to store expected signatures in advance in a non-volatile memory or the like. Therefore, the circuit diagnostic test apparatus of the present invention can perform highly accurate diagnostic tests without being limited by memory capacity.

Preferred embodiments of the present invention will be described below with reference to the drawings. It should be noted that the present invention is not limited to the following embodiments, and can be modified as appropriate without departing from the scope of the invention. Also, in each figure, the same reference numerals are given to the parts having the same or corresponding functions, and the explanation thereof may be omitted or simplified.

FIG. 1 is a diagram showing an example of the configuration of a circuit diagnosis test apparatus 1 according to one embodiment together with a diagnosis target circuit 2. As shown in FIG. First, the diagnosis target circuit 2 to be diagnosed by the circuit diagnosis test apparatus 1 will be described.

The FFs (flip-flops) of the diagnosis target circuit 2 are replaced with scan FFs 3 capable of executing a scan test. These scan FFs 3 are connected in series to form a shift register called a scan chain.

A scan chain may be a multi-scan chain divided into a plurality of parts. For example, the circuit to be diagnosed 2 shown in FIG. have a chain. This reduces the number of FF stages for each scan chain and reduces the test time.

In such a configuration, the scan FF 3 of the scan chain functions as an input terminal and an output terminal of the combinational circuit 20 in the diagnostic object circuit 2 . Therefore, the combinational circuit 20 can be tested by applying a test pattern to the combinational circuit 20 via the scan FF3 and similarly reading out the response pattern from the combinational circuit 20 via the scan FF3.

FIG. 2 is a diagram showing an example of the hardware configuration of the scan FF3 of the diagnosis target circuit 2. As shown in FIG. The scan FF3 shown in FIG. 2 has an FF31 and a multiplexer 32 arranged in the preceding stage of the FF31.

The multiplexer 32 switches the operation mode of the scan FF 3 between scan mode and non-scan mode according to the control signal SE output from the circuit diagnostic test apparatus 1 . More specifically, when the control signal SE is High, the multiplexer 32 switches the operation mode of the scan FF3 to the scan mode, and the signal SI output from the scan FF3 (or the circuit diagnosis test apparatus 1) at the front stage of the scan chain. Or output SO to FF31. On the other hand, when the control signal SE is Low, the multiplexer 32 switches the operation mode of the scan FF 3 to the non-scan mode, and transfers the signal D output from the combinational circuit 20 (or input terminal) in the preceding stage of the diagnostic target circuit 2 to the FF 31 . output to

The FF 31 operates in synchronization with the clock signal CK output from the circuit diagnostic test device 1 . In the scan mode, the FF 31 holds the signal SI or SO output from the multiplexer 32 and outputs the held signal SI or SO to the scan FF 3 (or the circuit diagnosis test device 1) at the subsequent stage of the scan chain. On the other hand, in the non-scan mode, the FF 31 holds the signal D output from the multiplexer 32 and outputs the held signal as the signal Q to the combinational circuit 20 (or output terminal) in the subsequent stage of the diagnostic target circuit 2 .

3(a) and 3(b) are timing charts showing an example of the operation of the scan FF3 shown in FIG. A scan test is performed by a series of operations of scan-in→capture→scan-out. FIGS. 3A and 3B especially show an example of the operation of the Loc (Launch-off-Capture) scan FF3.

First, the circuit diagnosis test apparatus 1 sets the control signal SE to High to switch the scan FF3 to the scan mode. Then, the circuit diagnosis test apparatus 1 continuously outputs the clock signal CK to the scan chains to shift the scan chains, and performs the scan-in operation of setting the test pattern values SI in the plurality of scan FFs 3 . As a result, the test patterns set in the plurality of scan FFs 3 are output to the combinational circuit 20 in the subsequent stage of the diagnostic object circuit 2 as initialization patterns.

The period T0 of the clock signal CK for this scan-in operation is not particularly limited, and may be any period that allows the scan chain to perform the shift operation. The period T0 of the clock signal CK for the scan-in operation is, for example, the same period as the period of the clock signal CK for the subsequent capture operation, or the first clock period of the normal operation of the diagnostic target circuit 2. The period may be the same as the period T1. The clock signal CK output from the circuit diagnostic test device 1 is generated by the circuit diagnostic test device 1 based on the system clock SCK input to the circuit diagnostic test device 1 from the outside of the circuit diagnostic test device 1 .

Next, the circuit diagnosis test apparatus 1 sets the control signal SE to Low to switch the scan FF3 to the non-scan mode. Then, the circuit diagnostic test apparatus 1 performs a capture operation of outputting two consecutive pulses p1 and p2 of the clock signal CK to the scan FF3. As a result, the launch pattern is output to the combinational circuit 20 in the subsequent stage, and the response pattern from the combinational circuit 20 in the preceding stage is held in the scan FF3.

Thus, in order to test delay faults caused by signal changes, it is necessary to apply an initialization pattern for initializing the combinational circuit 20 to a desired value and a launch pattern for transitioning the combinational circuit 20 . This is called a two-pattern test.

A delay fault is a fault in which the delay of an element or wiring constituting the combinational circuit 20 is increased and the combinational circuit 20 malfunctions. A cause of such a delay fault is, for example, NBTI (Negative Bias Temperature Instability), in which the operation of transistors forming the combinational circuit 20 slows down due to deterioration over time. It is known that delay faults caused by NBTI become a problem as the circuit to be diagnosed 2 is highly integrated and miniaturized.

The period of the clock signal CK for this capture operation is the first period T1, which is the clock period for normal operation, as shown in FIG. It is set as a long second period T2. The second period T2 is, for example, 5% to 50% longer than the first period.

Next, the circuit diagnosis test apparatus 1 sets the control signal SE to High to switch the scan FF3 to the scan mode. Then, the circuit diagnosis test apparatus 1 continuously outputs the clock signal CK to the scan chain to shift the scan chain, and outputs the signal SO of the response pattern from the combinational circuit 20 of the previous stage held in the plurality of scan FFs 3. A scan-out operation is performed to read out each. The cycle T0 of the clock signal CK for this scan-out operation is not particularly limited, like the cycle T0 of the clock signal CK for the scan-in operation.

In this way, the capture operation is performed in two periods, the first period T1, which is the clock period of the normal operation, and the second period T2, which is longer than the first period, and the response patterns output from the diagnosis target circuit 2 are compared. Thus, the delay fault in the diagnosis target circuit 2 can be tested. For example, the circuit diagnosis test apparatus 1 can determine that a delay fault exists in the diagnostic target circuit 2 when the diagnostic target circuit 2 does not operate normally in the first cycle T1 but operates normally in the second cycle. can.

FIG. 4 is a diagram showing another example of the hardware configuration of the scan FF3 of the diagnostic target circuit 2. As shown in FIG. The extended scan FF3b shown in FIG. 4 further has a latch circuit 33 arranged after FF31 in addition to FF31 and a multiplexer 32 arranged before FF31. Others are the same as those of the scan FF 3 shown in FIG. 2, so the differences from FIG. 2 will be described below.

The latch circuit 33 operates in synchronization with the control signal Update output from the circuit diagnosis test apparatus 1 , retains the signal Q output from the FF 31 , and applies the retained signal to the combinational circuit 20 subsequent to the diagnosis target circuit 2 . (or output terminal).

5(a) and 5(b) are timing charts showing an example of the operation of the extended scan FF 3b shown in FIG. FIGS. 5(a) and 5(b) show an example of the operation of the extended scan FF 3b of the extended scan method.

The timing charts shown in FIGS. 5(a) and 5(b) are different from those shown in FIGS. 3(a) and 3(b) in that the capture operation is performed by the pulse p1 of the control signal Update and the pulse p2 of the clock signal CK. ). Others are the same as in FIGS. 3(a) and 3(b). In this case, similarly, the launch pattern is output to the combinational circuit 20 in the subsequent stage, and the response pattern from the combinational circuit 20 in the preceding stage is held in the extended scan FF 3b.

In this manner, the circuit diagnosis test apparatus 1 controls the period from the pulse p1 of the launch pattern to the next pulse p2 in the capture operation, regardless of the type and operation method of the scan flipflop 3, and controls the clock output to the scan flipflop 3. The cycle of signal CK can be varied.

Again, referring to FIG. 1, each component of the circuit diagnostic test apparatus 1 will be described in order. The circuit diagnostic test apparatus 1 includes a test pattern setting circuit 11 , signature generation circuit 12 , multiplexer 13 , expected signature holding section 14 , signature comparison circuit 15 , storage section 16 and control section 17 . Note that the test pattern setting circuit 11 and the signature generation circuit 12 may be included in the diagnosis target circuit 2 instead of the circuit diagnosis test device 1 .

The circuit diagnosis test device 1 is mounted in the same chip as the circuit to be diagnosed 2, for example, as a BIST (Built In Self Test) circuit. As a result, the LSI chip itself can carry out self-testing, eliminating the need for an LSI tester and facilitating field testing. Alternatively, the circuit diagnosis test device 1 may be configured as an LSI tester. In this case, the circuit diagnostic test apparatus 1 may be implemented as a circuit diagnostic test computer program executed by a processor such as a CPU.

The test pattern setting circuit 11 develops a pseudo-random number pattern from the seed set by the control unit 17, and sets it as a test pattern in a plurality of scan FFs 3 of the diagnosis target circuit 2. FIG. The test pattern setting circuit 11 is, for example, an LFSR (Linear Feedback Shift Register).

The signature generation circuit 12 compresses a series of response patterns output from the plurality of scan FFs 3 to generate signatures. The signature generation circuit 12 is, for example, an MISR (multiple input signature register). The signature generation circuit 12 is initialized according to an initialization signal output from the control section 17 . That is, a series of response patterns to be compressed so that signature generation circuit 12 generates a signature is selected according to an initialization signal output from control section 17 .

When the control signal ESS output from the control unit 17 is High, the multiplexer 13 selects an expected signature Sig0 for a pre-diagnosis test, which will be described later, output from the control unit 17 and outputs it to the expected signature holding unit 14 . On the other hand, when the control signal ESS output from the control unit 17 is Low, the multiplexer 13 selects the expected signature Sig1 output from the signature generation circuit 12 and outputs it to the expected signature holding unit 14 . This expected signature Sig1 is a signature generated by the signature generation circuit 12 based on the response patterns output from the plurality of scan FFs 3 when the clock signal CK is output in the slow second period.

The expected signature holding unit 14 holds the expected signature Sig0 or Sig1 selected by the multiplexer 13 . The expected signature holding unit 14 is, for example, a storage element such as a register. Alternatively, the expected signature holding unit 14 may be a volatile semiconductor memory such as RAM (Static Random Access Memory) or DRAM (Dynamic Random Access Memory).

The signature comparison circuit 15 compares the expected signature Sig0 or Sig1 held in the expected signature holding unit 14 with the response signature Sig2 output from the signature generation circuit 12 and outputs the comparison result to the control unit 17 . This response signature Sig2 is a signature generated by the signature generation circuit 12 based on the response patterns output from the plurality of scan FFs 3 when the clock signal CK is output in the first cycle.

The storage unit 16 has a nonvolatile semiconductor memory such as an EEPROM (Electrically Erasable Programmable Read-Only Memory) or a flash EEPROM, for example. The storage unit 16 may further have a volatile semiconductor memory such as SRAM and DRAM.

FIG. 6 is a diagram showing a memory map of the storage section 16 of the circuit diagnosis test device 1. As shown in FIG. The storage unit 16 stores diagnostic test setting information 161, a pre-diagnostic test expected signature 162, a seed 163, a diagnostic test result 164, and the like.

The diagnostic test setting information 161 includes the number of seeds used for a diagnostic test (seed number), the number of test patterns developed from one seed (development number), the number of test patterns developed to generate one signature (diagnosis granularity), number of signatures to be generated (number of diagnostic tests), etc. Here, the diagnostic granularity is a divisor or multiple of the expansion number. Also, the values of these pieces of information are set so as to satisfy the following expression (1).
Number of diagnostic tests = number of seeds x number of deployments / diagnostic granularity (1)

The expected signature 162 for the pre-diagnostic test is the signature expected to be generated by the signature generation circuit 12 based on the response pattern corresponding to the test pattern developed from the seed. The expected signature 162 for the pre-diagnosis test is referred to when the circuit diagnosis test apparatus 1 performs a pre-diagnosis test, which will be described later. Therefore, if circuit diagnostic test equipment 1 does not perform pre-diagnostic tests, expected signatures 162 for pre-diagnostic tests may not necessarily be stored. Storage unit 16 may store a plurality of expected signatures 162 for pre-diagnostic tests, for example expected signatures 162 for pre-diagnostic tests described in FIGS. 10A and 10B for detection tests and for diagnostic tests. Each may be stored separately.

The seed 163 is read by the control section 17 and set in the test pattern setting circuit 11 so that the control section 17 causes the test pattern setting circuit 11 to develop the test pattern. The storage unit 16 may store a plurality of seeds 163, for example, seeds 163 for diagnostic tests, seeds 163 for detection tests of pre-diagnostic tests described in FIG. Seeds 163 for diagnostic tests of the test may be stored separately. Further, the storage unit 16 may store the types or regions of the faults of the diagnostic target circuit 2 whose delay faults are activated by the test pattern developed from the seeds 163 in association with the seeds 163 .

The diagnostic test results 164 include diagnostic test results of the diagnostic target circuit 2 performed by the circuit diagnostic test apparatus 1 . The diagnostic test results 164 may further include response signatures generated by the signature generation circuit 12, comparison result information output from the signature comparison circuit 15, and the like. A later-described diagnosis unit 175 of the control unit 17 narrows down the suspected failure and specifies the location of the failure, for example, based on the diagnostic test result 164 . Further, a later-described failure recovery section of the control section 17 executes recovery processing of the failure portion of the diagnosis target circuit 2 based on the diagnostic test result 164 . Diagnostic test results 164 may be stored in a non-volatile area.

The control unit 17 is an integrated circuit configured by, for example, an ASIC (Application Specific Integrated Circuit) or an FPGA (Field Programmable Gate Array). Alternatively, the control unit 17 may be one or more processors and their peripheral circuits that execute a computer program for circuit diagnosis processing.

FIG. 7 is a diagram showing functional blocks of the control unit 17 of the circuit diagnostic test device 1. As shown in FIG. The control section 17 has a pre-diagnosis test section 171 , a diagnosis test section 172 , a clock cycle setting section 173 , an output section 174 and a diagnosis section 175 . Also, the control unit 17 may further have the function of the signature comparison circuit 15 shown in FIG. Each of these parts of the control unit 17 may be realized as a circuit formed in FPGA or ASIC, or may be realized as a computer program executed on a processor.

FIG. 8 is a flow chart showing an example of circuit diagnostic test processing executed in the circuit diagnostic test apparatus 1. As shown in FIG. Each unit of the control unit 17 shown in FIG. 7 executes the circuit diagnosis test processing of the diagnosis target circuit 2 according to the flowchart shown in FIG. This circuit diagnostic test process is executed, for example, when the device having the circuit to be diagnosed 2 is powered on or placed in a standby state.

Before the diagnostic test section 172 performs the diagnostic test on the diagnostic target circuit 2, the pre-diagnostic test section 171 performs a pre-diagnostic test on the diagnostic target circuit 2 (step S801). Note that the pre-diagnosis test by the pre-diagnosis test section 171 may be omitted. Even in that case, it is possible to determine at least whether or not a delay fault exists in the diagnostic target circuit 2 by performing the diagnostic test of the diagnostic target circuit 2 by the diagnostic test unit 172 .

For example, the pre-diagnosis test unit 171 performs a diagnostic test for determining whether or not there is a fault including a delay fault in the diagnostic target circuit 2 . Accordingly, when it is determined by the pre-diagnostic test that there is no fault including a delay fault in the circuit to be diagnosed 2, the diagnostic test section 172 needs to perform a diagnostic test to identify the fault location in the circuit to be diagnosed 2. Gone. Therefore, the diagnostic test unit 172 performs a diagnostic test for specifying the location of the delay fault in the diagnostic target circuit 2 only when it is determined by the pre-diagnostic test that there is a fault including the delay fault in the diagnostic target circuit 2. You may make it An example of such a pre-diagnostic test is described below with reference to the flowchart of FIG. 10A.

Alternatively, the pre-diagnosis test section 171 performs a diagnostic test for determining whether or not the circuit to be diagnosed 2 has a stuck-at fault other than a delay fault, for example. As a result, when it is determined by the pre-diagnosis test that there is a fault other than the delay fault in the diagnostic object circuit 2, it is difficult to repair the fault other than the delay fault. The need for repairing delay faults is reduced by a fault repairing unit, which will be described later. Therefore, when the pre-diagnostic test determines that there is a fault other than the delay fault in the diagnostic target circuit 2, the diagnostic test section 172 does not perform the diagnostic test for identifying the location of the delay fault in the diagnostic target circuit 2. can be An example of such a pre-diagnostic test is described below with reference to the flowchart of FIG. 10B.

The diagnostic test section 172 determines whether or not to perform a diagnostic test on the diagnostic target circuit 2 according to the result of the pre-diagnostic test performed on the diagnostic target circuit 2 by the pre-diagnostic test section 171 (step S802). When the diagnostic test section 172 determines not to perform the diagnostic test on the diagnostic target circuit 2 (step S802: No), the circuit diagnostic test process ends. On the other hand, when the diagnostic test section 172 determines to perform the diagnostic test of the diagnostic target circuit 2 (step S802: Yes), it performs the following circuit diagnostic test processing.

First, the diagnostic test unit 172 generates an expected signature based on the response of the diagnostic target circuit 2 when the diagnostic target circuit 2 is operated in a second cycle that is longer (slower) than the first cycle, which is the clock cycle of normal operation. The signature generation circuit 12 is made to generate it (step S803).

For example, FIG. 9A is a flowchart showing an example of signature generation processing executed in the circuit diagnosis test apparatus 1. FIG. Each unit of the control unit 17 shown in FIG. 7 executes processing according to the flowchart shown in FIG. 9A to cause the signature generation circuit 12 to generate a signature.

Specifically, the diagnostic test unit 172 first outputs an initialization signal to the signature generation circuit 12 to initialize the signature generation circuit 12 (step S901). As a result, the signature generation circuit 12 compresses a series of response patterns (response pattern set) output from the scan FF 3 after initialization, and starts generation of signatures.

Next, the clock cycle setting unit 173 sets the clock signal CK so that the clock signal CK is output to the scan FF 3 in the capture operation of the scan test with a second cycle longer than the first cycle, which is the clock cycle of the normal operation. period is set (step S902).

More specifically, the clock cycle setting unit 173 can vary the cycle of the clock signal CK by, for example, a test timing control technique using PLL phase shift described in Non-Patent Document 1. Alternatively, the clock cycle setting unit 173 can change the cycle of the clock signal CK by, for example, delaying the clock signal CK through logic elements such as even-numbered NOT gates. Also, other well-known techniques may be used to vary the period of the clock signal CK.

Next, the diagnostic test section 172 sets the seed stored in the storage section 16 in the test pattern setting circuit 11 (step S903). This seed is pre-selected such that a series of test patterns (set of test patterns) developed from the seed will activate a specific type or area of faults in the circuit under diagnosis 2 . As a result, the test pattern setting circuit 11 develops a series of test patterns from the seed and sets them in a plurality of scan FFs 3 .

Next, the diagnostic test section 172 outputs the clock signal CK set to the second period by the clock period setting section 173 to the plurality of scan FFs 3 to perform a scan test (step S904). As a result, the signature generation circuit 12 compresses the response patterns output from the plurality of scan FFs 3 .

Next, the diagnostic test unit 172 determines whether or not a predetermined number of test patterns have been developed since the seed was set in the test pattern setting circuit 11 (step S905). If the predetermined number of test patterns have not been developed (step S905: No), the diagnostic test unit 172 repeats the scan test until the predetermined number of test patterns have been developed.

When a predetermined number of test patterns are developed (step S905: Yes), the diagnostic test unit 172 sets the control signal ESS to Low, and stores the expected signature Sig1 output from the signature generation circuit 12 in the expected signature holding unit 14. to hold.

Returning to FIG. 8, next, the diagnostic test unit 172 generates a response signature based on the response of the diagnostic target circuit 2 when the diagnostic target circuit 2 is operated in the first cycle, which is the clock cycle of normal operation. It is generated by the circuit 12 (step S804).

In this case also, each part of the control unit 17 shown in FIG. 7 executes processing according to the flowchart shown in FIG. 9A, and similarly causes the signature generation circuit 12 to generate a signature. However, in this case, the clock cycle setting unit 173 sets the cycle of the clock signal CK in step S902 so that the clock signal CK is output to the scan FF 3 in the first cycle, which is the clock cycle of normal operation. Further, the diagnostic test section 172 causes the test pattern setting circuit 11 to set the same seed as when the expected signature was generated in step S903. As a result, the response signature Sig2 generated by the signature generation circuit 12 is output to the signature comparison circuit 15. FIG.

Next, the output unit 174 stores the result of comparison between the expected signature Sig1 and the response signature Sig2 by the signature comparison circuit 15 in the storage unit 16 (step S805). Alternatively, the output unit 174 may output the result of comparison between the expected signature Sig1 and the response signature Sig2 by the signature comparison circuit 15 to the outside of the circuit diagnosis test apparatus 1 .

Next, the diagnostic test unit 172 determines whether or not all diagnostic tests have been performed (step S806). If all the diagnostic tests have not been performed (step S806: No), the diagnostic test section 172 repeats the diagnostic tests of the diagnostic target circuit 2 until all the diagnostic tests are performed.

When all diagnostic tests have been performed by the diagnostic test section 172 (step S806: Yes), the output section 174 stores the diagnostic test results of the diagnostic test section 172 in the storage section 16 (step S807). Alternatively, the output section 174 may output the diagnostic test result by the diagnostic test section 172 to the outside of the circuit diagnostic test apparatus 1 . After that, the diagnosis section 175 may diagnose the delay fault of the diagnosis target circuit 2 based on the diagnostic test result by the diagnostic test section 172 .

FIG. 9B is a flow chart showing another example of signature generation processing executed in the circuit diagnosis test apparatus 1. FIG. The signature generation process shown in FIG. 9B is similar to the signature generation process shown in FIG. 9A in that a set of expected signatures and response signatures are generated from a series of test patterns (test pattern set) developed from two or more seeds. different from

Steps S901 to S905 shown in FIG. 9B are the same as steps S901 to S905 shown in FIG. 9A, so description thereof will be omitted.

Next, the diagnostic test unit 172 determines that the total number of test patterns developed since the signature generation circuit 12 was initialized is the number of test patterns developed to generate one signature, and is a predetermined diagnostic granularity. It is determined whether or not the above is satisfied (step S916). This diagnostic granularity is set to a multiple of the number of developments of test patterns developed from one seed in this signature generation process.

If the total number of developed test patterns is less than the predetermined diagnostic granularity (step S916: No), the diagnostic test unit 172 returns the process to step S903, reads out a new seed from the storage unit 16, and set to This new seed is also chosen such that the set of test patterns to be developed will activate the same types or regions of faults as the previous seed. At this time, the diagnostic test unit 172 sets the same seed in the test pattern setting circuit 11 when generating the expected signature and when generating the response signature.

Then, the diagnostic test unit 172 performs the scan test while changing the seed until the total number of developed test patterns after the initialization of the signature generation circuit 12 reaches or exceeds the predetermined diagnostic granularity (step S916: Yes). repeat. As a result, a signature is generated and output by the signature generating circuit 12 based on a series of response patterns corresponding to a series of test patterns developed from two or more seeds.

In this way, by increasing the number of seeds used for developing a series of test patterns, it is possible to develop a series of test patterns that more easily activate failures in the diagnostic target circuit 2 .

FIG. 9C is a flowchart showing still another example of signature generation processing executed in the circuit diagnosis test apparatus 1. FIG. The signature generation process shown in FIG. 9C differs from the signature generation process shown in FIG. 9A in that a plurality of sets of expected signatures and response signatures are generated from a series of test patterns (test pattern set) developed from the same seed. different.

Steps S901 to S902 shown in FIG. 9C are the same as steps S901 to S902 shown in FIG. 9A, so description thereof is omitted.

Next, the diagnostic test unit 172 determines whether or not a predetermined number of test patterns have been developed since the seed was set in the test pattern setting circuit 11 (step S925). If a predetermined number of test patterns have been developed (step S925: Yes), the diagnostic test unit 172 reads a new seed from the storage unit 16 and sets it in the test pattern setting circuit 11 (step S903). At this time, the diagnostic test unit 172 sets the same seed in the test pattern setting circuit 11 when generating the expected signature and when generating the response signature.

On the other hand, if the predetermined number of test patterns have not been developed (step S925: No), the diagnostic test unit 172 continues the series of tests developed from the same seed until the predetermined number of test patterns have been developed. A scan test is performed using the pattern.

In the series of scan tests after this signature generation process, it is necessary to set the same series of test patterns to the multiple scan FFs 3 when generating the expected signature and when generating the response signature. . For this purpose, the circuit diagnostic test apparatus 1 may include, for example, an SBR (Seed Buffer Register) for storing the seed state of the test pattern setting circuit 11 . Then, the diagnostic test section 172 saves the seed state of the test pattern setting circuit 11 in the SBR before performing a series of subsequent scan tests to generate expected signatures. The diagnostic test unit 172 then sets the seed state stored in the SBR to the test pattern setting circuit 11 before performing a subsequent series of scan tests to generate response signatures.

Next, the diagnostic test section 172 outputs the clock signal CK set by the clock cycle setting section 173 to the plurality of scan FFs 3 to perform a scan test (step S904). As a result, the signature generation circuit 12 compresses the response patterns output from the plurality of scan FFs 3 .

Next, the diagnostic test unit 172 determines that the total number of test patterns developed since the signature generation circuit 12 was initialized is the number of test patterns developed to generate one signature, and is a predetermined diagnostic granularity. It is determined whether or not the above is satisfied (step S926). This diagnostic granularity is a divisor of the number of test patterns developed from one seed in this signature generation process.

If the total number of developed test patterns is less than the predetermined diagnostic granularity (step S926: No), the diagnostic test unit 172 continues until the total number of developed test patterns is greater than or equal to the predetermined diagnostic granularity (step S926: Yes). Repeat scan test. As a result, a plurality of sets of expected signatures and response signatures are generated from a series of test patterns developed from the same seed. is identified.

For example, among a series of test patterns developed from the same seed, a first diagnostic region in which the delay fault is activated by the first test pattern and a second diagnostic region in which the delay fault is activated by the second test pattern. is stored in the storage unit 16 in advance. Then, the diagnosis unit 175 determines that a delay fault exists in the first diagnosis area when the comparison result between the response signature generated based on the response pattern corresponding to the first test pattern and the expected signature is different. Further, the diagnosis unit 175 determines that a delay fault exists in the second diagnosis area when the comparison result between the response signature generated based on the response pattern corresponding to the second test pattern and the expected signature is different.

By increasing the number of diagnostic tests performed on the diagnostic target circuit 2 by comparing the expected signature and the response signature in this manner, the accuracy of identifying the fault location of the diagnostic target circuit 2 is improved. In particular, since the circuit diagnostic test apparatus 1 of the present invention automatically generates expected signatures, there is no need to store expected signatures in advance in a non-volatile memory or the like. Therefore, the circuit diagnostic test apparatus 1 of the present invention can increase the number of diagnostic tests for the circuit to be diagnosed 2 and obtain diagnostic test results for highly accurate diagnosis without being limited by the memory capacity.

FIG. 10A is a flowchart showing an example of pre-diagnosis test processing executed in the circuit diagnosis test apparatus 1. FIG. The pre-diagnosis test section 171 executes pre-diagnosis test processing for the diagnosis target circuit 2 according to the following flowchart.

Steps S901 to S905 shown in FIG. 10A are the same as steps S901 to S905 shown in FIG. 9A. However, the clock cycle setting unit 173 sets the cycle of the clock signal CK in step S902 so that the clock signal CK is output to the scan FF 3 in the first cycle, which is the clock cycle of normal operation. As a result, the response of the diagnostic target circuit 2 when the diagnostic target circuit 2 is operated in the first cycle is compressed by the signature generation circuit 12 . Also, in step S903, a seed for a detection test is used.

After that, the pre-diagnosis test unit 171 determines whether or not the detection test has been performed for all the seeds for failure detection (step S1006). If the diagnostic test has not been performed for all seeds (step S1006: No), the pre-diagnostic test unit 171 repeats the scan test while changing seeds until the diagnostic test is performed for all seeds.

When diagnostic tests are performed on all seeds for fault detection (step S1006: Yes), the signature generated by the signature generation circuit 12 is output to the signature comparison circuit 15. FIG. The pre-diagnosis test unit 171 sets the control signal ESS to High, outputs the expected signature Sig0 for the pre-diagnosis test to the multiplexer 13, and holds the expected signature Sig0 for the pre-diagnosis test in the expected signature holding unit .

Next, the pre-diagnosis test unit 171 stores the comparison result of the signature comparison circuit 15 between the signature output from the signature generation circuit 12 and the expected signature Sig0 for the pre-diagnosis test in the storage unit 16 (step S1007). .

After the pre-diagnosis test processing by the pre-diagnosis test section 171 is performed, the diagnosis test section 172 determines whether or not the comparison results stored in the storage section 16 by the pre-diagnosis test section 171 match.

If the comparison results do not match, the diagnostic test section 172 determines that there is a fault including a delay fault in the circuit 2 to be diagnosed, and performs a diagnostic test to identify the location of the delay fault in the circuit 2 to be diagnosed. On the other hand, if the comparison results match, the diagnostic test unit 172 determines that there is no fault including a delay fault in the diagnostic target circuit 2, and performs a diagnostic test to identify the location of the delay fault in the diagnostic target circuit 2. do not.

FIG. 10B is a flow chart showing another example of pre-diagnosis test processing executed in the circuit diagnosis test apparatus 1. FIG. The pre-diagnosis test section 171 executes pre-diagnosis test processing for the diagnosis target circuit 2 according to the following flowchart.

Steps S901 to S905 and S1006 to S1007 shown in FIG. 10B are the same as steps S901 to S905 and S1006 to S1007 shown in FIG. 10A. However, in step S902, the clock cycle setting unit 173 sets the clock signal CK so that the clock signal CK is output to the scan FF 3 in a second cycle longer (slower) than the first cycle, which is the clock cycle of normal operation. Set period. As a result, the response of the diagnostic target circuit 2 when the diagnostic target circuit 2 is operated in the second cycle is compressed by the signature generation circuit 12 . Also, in step S903, a seed for a diagnostic test is used.

After the pre-diagnostic test processing by the pre-diagnostic test unit 171 is performed, the diagnostic test unit 172 performs the comparison result stored in the storage unit 16 by the pre-diagnostic test unit 171 in the same manner as the pre-diagnostic test processing shown in FIG. 10A. match or not.

If the comparison results match, the diagnostic test section 172 determines that there is no fault other than the delay fault in the diagnostic target circuit 2 and performs a diagnostic test to identify the location of the delay fault in the diagnostic target circuit 2 . On the other hand, if the comparison results do not match, the diagnostic test section 172 determines that there is a fault other than the delay fault in the diagnostic target circuit 2, and does not perform the diagnostic test for specifying the location of the delay fault in the diagnostic target circuit 2. .

As described above, the circuit diagnosis test apparatus provides a response signature based on the response when the circuit to be diagnosed is operated with the same clock signal of the first period as that of the normal operation, and the clock signal of the second period longer than the first period. and the expected signature based on the response when the circuit to be diagnosed is operated at . Then, the circuit diagnosis test apparatus determines that a delay fault exists in the circuit to be diagnosed when the comparison result between the response signature and the expected signature is different.

Since the circuit diagnosis test apparatus automatically generates the expected signature in this way, it is not necessary to store the expected signature in advance in a non-volatile memory or the like. Therefore, the circuit diagnostic test apparatus of the present invention can perform a diagnostic test for highly accurate diagnosis without being limited by the memory capacity.

All of the above-described embodiments merely show specific examples for carrying out the present invention, and the technical scope of the present invention should not be construed to be limited by these. That is, the present invention can be embodied in various forms without departing from its technical concept or main features.

As another embodiment, the control unit 17 shown in FIG. 7 further includes a failure recovery unit (not shown) that recovers the failure of the diagnostic target circuit 2 when the comparison result by the diagnostic test unit 172 is different. good too.

For example, when the comparison result by the diagnostic test section 172 is different, the fault recovery section makes the power supply voltage supplied to the power supply terminal of the transistor higher than the power supply voltage before the diagnostic test. Alternatively, the failure recovery unit makes the period of the clock signal CK longer than the period of the clock signal CK before diagnosis when the comparison result by the diagnostic test unit 172 is different. After that, the fault repairing section may cause the diagnostic test section 172 to perform a diagnostic test again on the diagnostic target circuit 2 in order to confirm that the delay fault has been repaired.

As a result, the circuit diagnosis test apparatus 1 can repair the faulty part of the circuit 2 to be diagnosed.

As still another embodiment, the control unit 17 shown in FIG. 7 further includes a failure prediction unit (not shown) that determines whether or not there is a possibility that a failure will occur in the diagnostic target circuit 2 in the near future. You may

For example, the failure prediction unit first generates a first signature in the signature generation circuit 12 based on the response patterns output from the plurality of scan FFs 3 when the clock signal CK set to the first period is output. Let Next, the failure prediction unit generates a signature generation circuit based on the response patterns output from the plurality of scan FFs 3 when the clock signal CK set to a third period shorter (faster) than the first period is output. 12 to generate a second signature. Then, the failure prediction unit determines that there is a possibility that a failure will occur in the diagnosis target circuit 2 in the near future when the comparison result between the first signature and the second signature is different.

As a result, the circuit diagnosis test apparatus 1 can prevent the diagnosis target circuit 2 that has been determined to have a possibility of failure by the same method as the failure recovery unit described above.

1 circuit diagnosis test device 2 circuit to be diagnosed 3 scan FF
3b extended scan FF
11 test pattern setting circuit 12 signature generation circuit 13 multiplexer 14 expected signature holding unit 15 signature comparison circuit 16 storage unit 17 control unit 20 combination circuit 32 multiplexer 33 latch circuit 161 diagnostic test setting information 162 expected signature 163 seed 164 diagnostic test result 171 previous Diagnostic test section 172 Diagnostic test section 173 Clock cycle setting section 174 Output section 175 Diagnostic section

Claims (11)

a clock cycle setting unit for setting cycles of clock signals output to a plurality of scan FFs of a circuit to be diagnosed to which a test pattern is set;
a response signature generated based on a response pattern output from the plurality of scan FFs when the clock signal set to a predetermined first cycle by the clock cycle setting unit is output; and the clock cycle setting unit. with an expected signature generated based on the response pattern output from the plurality of scan FFs when the clock signal set to a second period longer than the first period is output by Department and
A circuit diagnostic test device comprising: The test pattern setting circuit further comprises a storage unit for storing a seed for developing the test pattern,
The diagnostic test unit sets the seed in the test pattern setting circuit, and compares the response signature generated based on the response pattern corresponding to the test pattern developed from the seed with the expected signature.
2. The circuit diagnostic test apparatus of claim 1. The diagnostic test unit sets, in the test pattern setting circuit, two or more seeds for developing the test pattern that activates the same fault in the circuit to be diagnosed, and sets a series of seeds developed from the two or more seeds. comparing the expected signature with the response signature generated based on a set of response patterns corresponding to the test pattern of
3. The circuit diagnostic test apparatus of claim 2. a diagnostic unit that determines that a delay fault exists in the circuit to be diagnosed when the comparison result by the diagnostic test unit is different;
a first diagnosis area of the circuit to be diagnosed in which a delay fault is activated by a first test pattern among a series of the test patterns developed from the same seed by the test pattern setting circuit; storing a second diagnosis region of the circuit to be diagnosed in which a delay fault is activated by a second test pattern in association with the seed;
The diagnostic test unit sets the seed in the test pattern setting circuit,
The diagnosis unit determines that a delay fault exists in the first diagnosis region when a comparison result between the response signature generated based on the response pattern corresponding to the first test pattern and the expected signature is different. determining that a delay fault exists in the second diagnostic area when a comparison result between the response signature generated based on the response pattern corresponding to the second test pattern and the expected signature is different;
3. The circuit diagnostic test apparatus of claim 2. The storage unit pre-stores a pre-diagnostic test expected signature that is expected to be generated based on a response pattern corresponding to the test pattern developed from the seed,
The seed is set in the test pattern setting circuit, a signature generated based on a response pattern corresponding to the test pattern developed from the seed, and the pre-diagnostic test expected signature stored in the storage unit. further comprising a pre-diagnosis test unit for determining whether or not a failure exists in the circuit to be diagnosed based on the comparison result of
The diagnostic test unit determines whether or not to perform a diagnostic test on the circuit to be diagnosed according to a result of a pre-diagnostic test of the circuit to be diagnosed by the pre-diagnostic test unit.
5. A circuit diagnostic test apparatus according to any one of claims 2-4. The pre-diagnostic test unit includes a signature generated based on a response pattern output from the plurality of scan FFs when the clock signal set to the first cycle by the clock cycle setting unit is output; determining that a fault including a delay fault exists in the circuit to be diagnosed when the result of comparison with the expected signature for the pre-diagnosis test is different;
The diagnostic test unit performs a diagnostic test on the circuit to be diagnosed when the pre-diagnostic test unit determines that a fault including a delay fault exists in the circuit to be diagnosed.
6. The circuit diagnostic test apparatus of claim 5. The pre-diagnostic test unit includes a signature generated based on a response pattern output from the plurality of scan FFs when the clock signal set to the second cycle by the clock cycle setting unit is output; determining that a fault other than a delay fault exists in the circuit to be diagnosed when the result of comparison with the expected signature for the pre-diagnosis test is different;
The diagnostic test unit does not perform a diagnostic test on the circuit to be diagnosed when the pre-diagnostic test unit determines that a fault other than a delay fault exists in the circuit to be diagnosed.
7. A circuit diagnostic test apparatus according to claim 5 or 6. When the comparison result by the diagnostic test unit is different, the voltage supplied to the power supply terminal of the transistor is made higher than the power supply voltage before the diagnostic test, or the period of the clock signal is made higher than the period of the clock signal before the diagnostic test. further comprising a fault repair section that lengthens the
8. A circuit diagnostic test apparatus according to any one of claims 2-7. a first signature generated based on a response pattern output from the plurality of scan FFs when the clock signal set to the first period by the clock period setting unit is output; and the clock period setting unit. A second signature generated based on a response pattern output from the plurality of scan FFs when the clock signal set to a third period shorter than the first period is output by further comprising a failure prediction unit that determines that there is a possibility that a failure will occur in the circuit to be diagnosed if different;
9. A circuit diagnostic test apparatus according to any one of claims 1-8. mounted in the same chip as the diagnostic target circuit,
10. Circuit diagnostic test equipment according to any one of claims 1-9. a clock cycle setting step of setting a cycle of a clock signal output to a plurality of scan FFs of a circuit to be diagnosed in which a test pattern is set;
a response signature generated based on a response pattern output from the plurality of scan FFs when the clock signal set to a predetermined first period in the clock period setting step is output; and the clock period setting step. with an expected signature generated based on the response pattern output from the plurality of scan FFs when the clock signal set to a second period longer than the first period is output in a step;
A circuit diagnostic test method characterized by comprising:

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