JP7259248B2 - A/D conversion processor - Google Patents

Description

The disclosed technique relates to an A/D conversion processing device.

When simultaneously performing A/D conversion (analog/digital conversion) on a plurality of analog signals respectively input from a plurality of input systems, normally the same number of A/D converters as the number of analog signals are used. However, if a plurality of A/D converters are used, the manufacturing cost of the A/D conversion processing device equipped with the A/D converters will increase.

Therefore, while sequentially switching the analog signals to be input to the A/D converter among a plurality of analog signals, " There is a prior art that enables a single A/D converter to perform A/D conversion on a plurality of analog signals respectively input from a plurality of input systems by performing "interpolation processing". In this prior art, interpolation processing is performed using an FIR (Finite Impulse Response) filter having multiple multipliers.

Japanese Patent Application Laid-Open No. 2008-199220

However, an FIR filter that performs the above interpolation processing is required for each of a plurality of input systems respectively corresponding to a plurality of analog signals. For this reason, in the prior art, the total number of multipliers included in the FIR filter that performs interpolation processing increases, resulting in an increase in the circuit scale of the A/D conversion processing device.

The disclosed technology has been made in view of the above, and aims to reduce the circuit scale of an A/D conversion processing device.

In an aspect of the disclosure, an A/D conversion processing device has a selection section, an A/D converter, a distribution section, and an FIR filter. The selection unit sequentially selects one input system from α (where α is an integer equal to or greater than 3) input systems. The A/D converter converts an analog signal input from the input system selected by the selection section into a digital signal. The distribution unit distributes the digital signal output from the A/D converter to each of the α input systems. The FIR filter is provided corresponding to each of the α input systems, and interpolates the digital signals distributed by the distributing unit to generate digital signals corresponding to the α input systems. Interpolation processing is performed to align the sampling timings. In the A/D conversion processing device, the number of taps of the FIR filter determined based on the accuracy required for the interpolation process is the number of comparison taps, and the number of comparison taps is n (where n is α+1 (integers above), the total number of multipliers included in the α FIR filters is α+n−1.

According to the aspect of the disclosure, the circuit scale of the A/D conversion processing device can be reduced.

FIG. 1 is a diagram showing a configuration example of an A/D conversion processing device of Comparative Example 1. As shown in FIG. FIG. 2 is a diagram illustrating a configuration example of a filter of Comparative Example 1. FIG. FIG. 3 is a diagram for explaining an operation example of the A/D conversion processing device of Comparative Example 1. FIG. FIG. 4 is a diagram showing a configuration example of an A/D conversion processing device of Comparative Example 2. As shown in FIG. FIG. 5 is a diagram for explaining an operation example of the A/D conversion processing device of Comparative Example 2. FIG. FIG. 6 is a diagram showing a configuration example of an A/D conversion processing device of Comparative Example 3. As shown in FIG. FIG. 7 is a diagram illustrating a configuration example of a filter of Comparative Example 3. FIG. FIG. 8 is a diagram for explaining an operation example of the A/D conversion processing device of Comparative Example 3. FIG. FIG. 9 is a diagram illustrating a configuration example of a filter according to the first embodiment; FIG. 10 is a diagram illustrating a configuration example of a filter according to the first embodiment; FIG. 11 is a diagram illustrating a configuration example of a filter according to the first embodiment; 12A is a diagram for explaining an operation example of the A/D conversion processing device according to the first embodiment; FIG. 12B is a diagram for explaining an operation example of the A/D conversion processing device according to the first embodiment; FIG. 12C is a diagram for explaining an operation example of the A/D conversion processing device according to the first embodiment; FIG. 13A is a diagram for explaining an operation example of the A/D conversion processing device according to the first embodiment; FIG. 13B is a diagram for explaining an operation example of the A/D conversion processing device according to the first embodiment; FIG. 13C is a diagram for explaining an operation example of the A/D conversion processing device according to the first embodiment; FIG. 14A is a diagram for explaining an operation example of the A/D conversion processing device according to the first embodiment; FIG. 14B is a diagram for explaining an operation example of the A/D conversion processing device according to the first embodiment; FIG. 14C is a diagram for explaining an operation example of the A/D conversion processing device according to the first embodiment; FIG. 15A is a diagram for explaining an operation example of the A/D conversion processing device according to the first embodiment; FIG. 15B is a diagram for explaining an operation example of the A/D conversion processing device according to the first embodiment; FIG. 15C is a diagram for explaining an operation example of the A/D conversion processing device according to the first embodiment; FIG. 16A is a diagram for explaining an operation example of the A/D conversion processing device according to the first embodiment; FIG. 16B is a diagram for explaining an operation example of the A/D conversion processing device according to the first embodiment; FIG. 16C is a diagram for explaining an operation example of the A/D conversion processing device according to the first embodiment; FIG. FIG. 17 is a diagram illustrating a configuration example of a filter according to the second embodiment; FIG. 18 is a diagram illustrating a configuration example of a filter according to the second embodiment; 19A is a diagram for explaining an operation example of the A/D conversion processing device according to the second embodiment; FIG. 19B is a diagram for explaining an operation example of the A/D conversion processing device according to the second embodiment; FIG. 19C is a diagram for explaining an operation example of the A/D conversion processing device according to the second embodiment; FIG. 19D is a diagram for explaining an operation example of the A/D conversion processing device according to the second embodiment; FIG. 20A is a diagram for explaining an operation example of the A/D conversion processing device according to the second embodiment; FIG. 20B is a diagram for explaining an operation example of the A/D conversion processing device according to the second embodiment; FIG. 20C is a diagram for explaining an operation example of the A/D conversion processing device according to the second embodiment; FIG. 20D is a diagram for explaining an operation example of the A/D conversion processing device according to the second embodiment; FIG. FIG. 21A is a diagram for explaining an operation example of the A/D conversion processing device according to the second embodiment; 21B is a diagram for explaining an operation example of the A/D conversion processing device according to the second embodiment; FIG. 21C is a diagram for explaining an operation example of the A/D conversion processing device according to the second embodiment; FIG. FIG. 21D is a diagram for explaining an operation example of the A/D conversion processing device according to the second embodiment; 22A is a diagram for explaining an operation example of the A/D conversion processing device according to the second embodiment; FIG. 22B is a diagram for explaining an operation example of the A/D conversion processing device according to the second embodiment; FIG. 22C is a diagram for explaining an operation example of the A/D conversion processing device according to the second embodiment; FIG. 22D is a diagram for explaining an operation example of the A/D conversion processing device according to the second embodiment; FIG. 23A is a diagram for explaining an operation example of the A/D conversion processing device according to the second embodiment; FIG. 23B is a diagram for explaining an operation example of the A/D conversion processing device according to the second embodiment; FIG. 23C is a diagram for explaining an operation example of the A/D conversion processing device according to the second embodiment; FIG. 23D is a diagram for explaining an operation example of the A/D conversion processing device according to the second embodiment; FIG. FIG. 24 is a diagram illustrating a configuration example of a filter according to the third embodiment; FIG. 25 is a diagram illustrating a configuration example of a filter according to the third embodiment; FIG. 26 is a diagram illustrating a configuration example of a filter according to the third embodiment; FIG. 27 is a diagram illustrating a configuration example of a filter according to the third embodiment; FIG. 28 is a diagram illustrating a configuration example of a filter according to the third embodiment; 29A is a diagram for explaining an operation example of the A/D conversion processing device according to the third embodiment; FIG. 29B is a diagram for explaining an operation example of the A/D conversion processing device according to the third embodiment; FIG. 29C is a diagram for explaining an operation example of the A/D conversion processing device according to the third embodiment; FIG. 29D is a diagram for explaining an operation example of the A/D conversion processing device according to the third embodiment; FIG. 29E is a diagram for explaining an operation example of the A/D conversion processing device according to the third embodiment; FIG. 30A is a diagram for explaining an operation example of the A/D conversion processing device according to the third embodiment; FIG. 30B is a diagram for explaining an operation example of the A/D conversion processing device according to the third embodiment; FIG. 30C is a diagram for explaining an operation example of the A/D conversion processing device according to the third embodiment; FIG. 30D is a diagram for explaining an operation example of the A/D conversion processing device according to the third embodiment; FIG. 30E is a diagram for explaining an operation example of the A/D conversion processing device according to the third embodiment; FIG. 31A is a diagram for explaining an operation example of the A/D conversion processing device according to the third embodiment; FIG. 31B is a diagram for explaining an operation example of the A/D conversion processing device according to the third embodiment; FIG. 31C is a diagram for explaining an operation example of the A/D conversion processing device according to the third embodiment; FIG. 31D is a diagram for explaining an operation example of the A/D conversion processing device according to the third embodiment; FIG. 31E is a diagram for explaining an operation example of the A/D conversion processing device according to the third embodiment; FIG. 32A is a diagram for explaining an operation example of the A/D conversion processing device according to the third embodiment; FIG. 32B is a diagram for explaining an operation example of the A/D conversion processing device according to the third embodiment; FIG. 32C is a diagram for explaining an operation example of the A/D conversion processing device according to the third embodiment; FIG. 32D is a diagram for explaining an operation example of the A/D conversion processing device according to the third embodiment; FIG. 32E is a diagram for explaining an operation example of the A/D conversion processing device according to the third embodiment; FIG. 33A is a diagram for explaining an operation example of the A/D conversion processing device according to the third embodiment; FIG. 33B is a diagram for explaining an operation example of the A/D conversion processing device according to the third embodiment; FIG. 33C is a diagram for explaining an operation example of the A/D conversion processing device according to the third embodiment; FIG. 33D is a diagram for explaining an operation example of the A/D conversion processing device according to the third embodiment; FIG. 33E is a diagram for explaining an operation example of the A/D conversion processing device according to the third embodiment; FIG. FIG. 34 is a diagram illustrating an example of correspondence between taps and coefficients according to the fourth embodiment. FIG. 35 is a diagram illustrating an example of correspondence between taps and coefficients according to the fourth embodiment. FIG. 36 is a diagram illustrating an example of correspondence between taps and coefficients according to the fourth embodiment. FIG. 37 is a diagram illustrating an example of a correspondence relationship between taps and coefficients according to the fourth embodiment.

An embodiment of the A/D conversion processing apparatus disclosed in the present application will be described below with reference to the drawings. Note that the A/D conversion processing apparatus disclosed in the present application is not limited to this embodiment. Moreover, the same code|symbol is attached|subjected to the structure which has the same function in an Example.

[Comparative Example 1]
<Configuration of A/D conversion processing device>
FIG. 1 is a diagram showing a configuration example of an A/D conversion processing device of Comparative Example 1. As shown in FIG. In FIG. 1, the A/D conversion processing device 1 includes a selection unit 11A, an A/D converter 12, a distribution unit 13A, a control unit 14, filters 15-1, 15-2, and 15-3. have The selection unit 11A, the A/D converter 12, and the distribution unit 13A operate under the control of the control unit 14. FIG. The control unit 14 is implemented by, for example, a processor. Examples of processors include CPUs (Central Processing Units), DSPs (Digital Signal Processors), and FPGAs (Field Programmable Gate Arrays).

Three input systems IN1, IN2, and IN3 are connected to the input side of the selector 11A, and the A/D converter 12 is connected to the output side of the selector 11A. An analog signal is input to each of the input systems IN1, IN2, and IN3. The selector 11A sequentially selects one of the input systems IN1, IN2, IN3 and connects the selected input system to the A/D converter 12. FIG. The selector 11A is implemented by, for example, a switching circuit.

The A/D converter 12 converts an analog signal input from the input system selected by the selection unit 11A among the input systems IN1, IN2, and IN3 into a digital signal, and converts the digital signal, which is sampling data, into a distribution unit 13A. Output to

The distribution unit 13A distributes the sampling data input from the A/D converter 12 to the filters 15-1, 15-2 and 15-3 corresponding to the input systems IN1, IN2 and IN3. The sorting unit 13A sends the converted sampling data of the analog signal of the input system IN1 to the filter 15-1, the converted sampling data of the analog signal of the input system IN2 to the filter 15-2, and the analog signal of the input system IN3. The converted sampling data are distributed to the filters 15-3 and output. 13 A of distribution parts are implement|achieved by the switching circuit or S/P (serial/parallel) converter, for example.

By providing the A/D conversion processing device 1 with the selection unit 11A and the distribution unit 13A, the A/D conversion processing device 1 converts the three analog signals input to the input systems IN1, IN2, and IN3 into one signal. A/D conversion can be performed in a time division manner by the two A/D converters 12 .

The filter 15-1 is provided corresponding to the input system IN1, performs filtering for interpolating the converted analog signal sampling data of the input system IN1, and outputs the filtered data to the output system OUT1. The filter 15-2 is provided corresponding to the input system IN2, performs filtering for interpolating the converted analog signal sampling data of the input system IN2, and outputs the filtered data to the output system OUT2. The filter 15-3 is provided corresponding to the input system IN3, performs filtering for interpolating the converted analog signal sampling data of the input system IN3, and outputs the filtered data to the output system OUT3. By interpolating the sampling data by the filters 15-1, 15-2, and 15-3, it is possible to match the sampling timings of the sampling data corresponding to all the input systems IN1, IN2, and IN3 to the same timing. become. Each of the filters 15-1, 15-2, 15-3 is an FIR filter.

Hereinafter, the sampled data after the A/D conversion by the A/D converter 12 and before filtering by the filters 15-1, 15-2, and 15-3 will be referred to as "pre-interpolation data", and the filter 15- The data after filtering at 1, 15-2, and 15-3 will be called "post-interpolation data".

Here, when the sampling frequency per input system is fs, the control unit 14 outputs a sampling clock of 3fs, which is three times the sampling frequency fs, to the A/D converter 12 . The A/D converter 12 converts the analog signals sequentially input from the input systems IN1, IN2, IN3 into digital signals at sampling intervals of 1/(3fs) according to a sampling clock with a frequency of 3fs. In this case, the control unit 14 switches the connection state between the input systems IN1, IN2, IN3 and the A/D converter 12 in the selection unit 11A at a cycle of 1/(3fs). Further, the distribution unit 13A distributes the sampling data input from the A/D converter 12 to the filters 15-1, 15-2, and 15-3 according to the control from the control unit 14 by 1/(3 fs ).

<Configuration of filter>
FIG. 2 is a diagram illustrating a configuration example of a filter of Comparative Example 1. FIG. The three filters 15-1, 15-2 and 15-3 in FIG. 1 have the same configuration as shown in FIG. FIG. 2 shows an example in which each of the filters 15-1, 15-2, and 15-3 has five taps TA1 to TA5.

In FIG. 2, the filters 15-1, 15-2, 15-3 have delayers 21-1 to 21-4, multipliers 22-1 to 22-5, and an adder 23. Each of multipliers 22-1 to 22-5 is connected to each of taps TA1 to TA5.

The pre-interpolation data output from the distribution unit 13A is input to the delay element 21-4. The pre-interpolation data is delayed by one unit time in each of the delay elements 21-4, 21-3, 21-2 and 21-1, and then is applied to the multipliers 22-4, 22-3, 22-2 and 22- 1.

Therefore, the multiplier 22 - 5 multiplies the pre-interpolation data with a delay of 0 (zero) by the coefficient a, and outputs the pre-interpolation data after the coefficient multiplication to the adder 23 . The multiplier 22 - 4 multiplies the pre-interpolation data delayed by one unit time by the coefficient b, and outputs the pre-interpolation data after the coefficient multiplication to the adder 23 . The multiplier 22 - 3 multiplies the pre-interpolation data delayed by two unit times by the coefficient c, and outputs the pre-interpolation data after the coefficient multiplication to the adder 23 . The multiplier 22 - 2 multiplies the pre-interpolation data delayed by three unit times by the coefficient b, and outputs the pre-interpolation data after the coefficient multiplication to the adder 23 . The multiplier 22 - 1 multiplies the pre-interpolation data delayed by 4 unit times by the coefficient a, and outputs the pre-interpolation data after the coefficient multiplication to the adder 23 .

Adder 23 obtains post-interpolation data by adding all pre-interpolation data after coefficient multiplication output from multipliers 22-1 to 22-5.

<Operation of A/D conversion processing device>
FIG. 3 is a diagram for explaining an operation example of the A/D conversion processing device of Comparative Example 1. FIG. In FIG. 3, IN1_D1 to IN1_D6 indicate pre-interpolation data input to the filter 15-1 (that is, pre-interpolation data after A/D conversion of the analog signal input from the input system IN1). IN2_D1 to IN2_D5 indicate pre-interpolation data input to the filter 15-2 (that is, pre-interpolation data after A/D conversion of the analog signal input from the input system IN2). IN3_D1 to IN3_D5 indicate pre-interpolation data input to the filter 15-3 (that is, pre-interpolation data after A/D conversion of the analog signal input from the input system IN3).

Pre-interpolation data IN1_D1 is input from the A/D converter 12 to the distribution unit 13A at time t0, pre-interpolation data IN2_D1 is input at time t1, and pre-interpolation data IN3_D1 is input at time t2. Further, the pre-interpolation data IN1_D2 is input from the A/D converter 12 to the distribution unit 13A at time t3, the pre-interpolation data IN2_D2 at time t4, and the pre-interpolation data IN3_D2 at time t5. Further, the pre-interpolation data IN1_D3 is input from the A/D converter 12 to the distribution unit 13A at time t6, the pre-interpolation data IN2_D3 at time t7, and the pre-interpolation data IN3_D3 at time t8. Further, the pre-interpolation data IN1_D4 is input from the A/D converter 12 to the distribution unit 13A at time t9, the pre-interpolation data IN2_D4 at time t10, and the pre-interpolation data IN3_D4 at time t11. Further, the pre-interpolation data IN1_D5 is input from the A/D converter 12 to the distribution unit 13A at time t12, the pre-interpolation data IN2_D5 at time t13, and the pre-interpolation data IN3_D5 at time t14. Also, at time t15, pre-interpolation data IN1_D6 is input from the A/D converter 12 to the sorting section 13A.

The distribution unit 13A copies the pre-interpolation data input from the A/D converter 12 according to the number of input systems. In Comparative Example 1, the number of input systems is IN1, IN2, and IN3. copy times. In FIG. 3, unhatched data indicates copy source pre-interpolation data, and hatched data indicates pre-interpolation data created by copying.

At time t2, the sorting unit 13A simultaneously outputs the pre-interpolation data IN1_D1 to the filter 15-1, the pre-interpolation data IN2_D1 to the filter 15-2, and the pre-interpolation data IN3_D1 to the filter 15-3. At time t3, the sorting unit 13A simultaneously outputs the pre-interpolation data IN1_D2 to the filter 15-1, the pre-interpolation data IN2_D1 to the filter 15-2, and the pre-interpolation data IN3_D1 to the filter 15-3. At time t4, the sorting unit 13A simultaneously outputs the pre-interpolation data IN1_D2 to the filter 15-1, the pre-interpolation data IN2_D2 to the filter 15-2, and the pre-interpolation data IN3_D1 to the filter 15-3. At time t5, the sorting unit 13A simultaneously outputs the pre-interpolation data IN1_D2 to the filter 15-1, the pre-interpolation data IN2_D2 to the filter 15-2, and the pre-interpolation data IN3_D2 to the filter 15-3. At time t6, the sorting unit 13A simultaneously outputs the pre-interpolation data IN1_D3 to the filter 15-1, the pre-interpolation data IN2_D2 to the filter 15-2, and the pre-interpolation data IN3_D2 to the filter 15-3.

At time t7, the sorting unit 13A simultaneously outputs the pre-interpolation data IN1_D3 to the filter 15-1, the pre-interpolation data IN2_D3 to the filter 15-2, and the pre-interpolation data IN3_D2 to the filter 15-3. At time t8, the sorting unit 13A simultaneously outputs the pre-interpolation data IN1_D3 to the filter 15-1, the pre-interpolation data IN2_D3 to the filter 15-2, and the pre-interpolation data IN3_D3 to the filter 15-3. At time t9, the sorting unit 13A simultaneously outputs the pre-interpolation data IN1_D4 to the filter 15-1, the pre-interpolation data IN2_D3 to the filter 15-2, and the pre-interpolation data IN3_D3 to the filter 15-3.

Therefore, the filter 15-1 uses one pre-interpolation data IN1_D1, three pre-interpolation data IN1_D2, and one pre-interpolation IN1_D3 input at times t2 to t6, respectively, to obtain post-interpolation data at time t7. OUT1_D1 is generated and output to the output system OUT1. Since the filter 15-1 has the configuration shown in FIG. 2, the interpolated data OUT1_D1 generated by the filter 15-1 is represented by equation (1).
OUT1_D1 = IN1_D1×a + IN1_D2×(2b+c) + IN1_D3×a …(1)

Further, the filter 15-2 generates post-interpolation data OUT2_D1 at time t7 using the two pre-interpolation data IN2_D1 and the three pre-interpolation data IN2_D2 respectively input at times t2 to t6, and outputs the data to the output system. Output to OUT2. Since the filter 15-2 employs the configuration shown in FIG. 2, the interpolated data OUT2_D1 generated by the filter 15-2 is expressed by equation (2).
OUT2_D1 = IN2_D1×(a+b) + IN2_D2×(a+b+c) …(2)

Further, the filter 15-3 uses the three pre-interpolation data IN3_D1 and the two pre-interpolation data IN3_D2 that are input at times t2 to t6, respectively, to generate post-interpolation data OUT3_D1 at time t7, and output it to the output system. Output to OUT3. Since the filter 15-3 has the configuration shown in FIG. 2, the interpolated data OUT3_D1 generated by the filter 15-3 is represented by equation (3).
OUT3_D1 = IN3_D1×(a+b+c) + IN3_D2×(a+b) …(3)

Similarly, the filter 15-1 uses one pre-interpolation data IN1_D2, three pre-interpolation data IN1_D3, and one pre-interpolation IN1_D4 input at times t5 to t9, respectively, to obtain the formula ( 4) generates post-interpolation data OUT1_D2 and outputs it to the output system OUT1.
OUT1_D2 = IN1_D2×a + IN1_D3×(2b+c) + IN1_D4×a …(4)

Further, the filter 15-2 uses the two pre-interpolation data IN2_D2 and the three pre-interpolation data IN2_D3 that are input at times t5 to t9, respectively, to obtain post-interpolation data OUT2_D2 shown in equation (5) at time t10. is generated and output to the output system OUT2.
OUT2_D2 = IN2_D2×(a+b) + IN2_D3×(a+b+c) …(5)

In addition, the filter 15-3 uses the three pre-interpolation data IN3_D2 and the two pre-interpolation data IN3_D3 input at times t5 to t9, respectively, to obtain the post-interpolation data OUT3_D2 shown in Equation (6) at time t10. is generated and output to the output system OUT3.
OUT3_D2 = IN3_D2×(a+b+c) + IN3_D3×(a+b) …(6)

Since the sampling data output from the A/D converter 12 is interpolated by filtering with the filters 15-1, 15-2, and 15-3 as described above, all input systems of the input systems IN1, IN2, and IN3 The sampling timings of the sampling data corresponding to each of are aligned to the same timing.

[Comparative Example 2]
<Configuration of A/D conversion processing device>
FIG. 4 is a diagram showing a configuration example of an A/D conversion processing device of Comparative Example 2. As shown in FIG. In FIG. 4, the A/D conversion processing device 2 has a selection section 11B, an A/D converter 12, a distribution section 13B, a control section 14, and filters 16-1 to 16-4. The selection unit 11B, the A/D converter 12, and the allocation unit 13B operate under the control of the control unit 14. FIG.

Four input systems IN1 to IN4 are connected to the input side of the selector 11B, and the A/D converter 12 is connected to the output side of the selector 11B. An analog signal is input to each of the input systems IN1 to IN4. The selection unit 11B sequentially selects one of the input systems IN1 to IN4 and connects the selected input system to the A/D converter 12 . The selector 11B is implemented by, for example, a switching circuit.

The A/D converter 12 converts an analog signal input from the input system selected by the selection unit 11B from among the input systems IN1 to IN4 into a digital signal, and outputs the digital signal, which is sampling data, to the distribution unit 13B. do.

The distribution unit 13B distributes the sampling data input from the A/D converter 12 to the filters 16-1 to 16-4 corresponding to the input systems IN1 to IN4. The sorting unit 13B sends the converted sampling data of the analog signal of the input system IN1 to the filter 16-1, the converted sampling data of the analog signal of the input system IN2 to the filter 16-2, and the analog signal of the input system IN3. The converted sampling data is distributed to the filter 16-3, and the converted sampling data of the analog signal of the input system IN4 is distributed to the filter 16-4. The sorting unit 13B is realized by, for example, a switching circuit or an S/P (serial/parallel) converter.

By providing the A/D conversion processing device 2 with the selection unit 11B and the distribution unit 13B, the A/D conversion processing device 2 converts four analog signals input to each of the input systems IN1 to IN4 into one A The /D converter 12 enables time-division A/D conversion.

The filter 16-1 is provided corresponding to the input system IN1, performs filtering for interpolating the converted analog signal sampling data of the input system IN1, and outputs the filtered data to the output system OUT1. The filter 16-2 is provided corresponding to the input system IN2, performs filtering for interpolating the converted analog signal sampling data of the input system IN2, and outputs the filtered data to the output system OUT2. The filter 16-3 is provided corresponding to the input system IN3, performs filtering for interpolating the converted analog signal sampling data of the input system IN3, and outputs the filtered data to the output system OUT3. The filter 16-4 is provided corresponding to the input system IN4, performs filtering for interpolating the converted analog signal sampling data of the input system IN4, and outputs the filtered data to the output system OUT4. By interpolating the sampling data by the filters 16-1 to 16-4, it is possible to match the sampling timings of the sampling data corresponding to all the input systems IN1 to IN4 to the same timing. Each of the filters 16-1 to 16-4 is an FIR filter.

Hereinafter, the sampled data after the A/D conversion by the A/D converter 12 and before filtering by the filters 16-1 to 16-4 will be referred to as "pre-interpolation data", and the filters 16-1 to 16- The data after filtering in 4 is called "post-interpolation data".

Here, if the sampling frequency per input system is fs, the control unit 14 outputs a sampling clock of 4fs, which is four times the sampling frequency fs, to the A/D converter 12 . The A/D converter 12 converts the analog signals sequentially input from the input systems IN1 to IN4 into digital signals at sampling intervals of 1/(4fs) according to a sampling clock with a frequency of 4fs. In this case, the control unit 14 switches the connection state between the input systems IN1 to IN4 and the A/D converter 12 in the selection unit 11B at a cycle of 1/(4fs). Further, the distribution unit 13B distributes the sampling data input from the A/D converter 12 to the filters 16-1 to 16-4 under the control of the control unit 14 at a cycle of 1/(4 fs). conduct.

<Configuration of filter>
The four filters 16-1 to 16-4 in FIG. 4 have the same configuration as shown in FIG. 2, as in the first comparative example. FIG. 2 shows an example in which each of the filters 16-1 to 16-4 has five taps TA1 to TA5.

<Operation of A/D conversion processing device>
FIG. 5 is a diagram for explaining an operation example of the A/D conversion processing device of Comparative Example 2. FIG. In FIG. 5, IN1_D1 to IN1_D5 indicate pre-interpolation data input to the filter 16-1 (that is, pre-interpolation data after A/D conversion of the analog signal input from the input system IN1). IN2_D1 to IN2_D4 indicate pre-interpolation data input to the filter 16-2 (that is, pre-interpolation data after A/D conversion of the analog signal input from the input system IN2). IN3_D1 to IN3_D4 indicate pre-interpolation data input to the filter 16-3 (that is, pre-interpolation data after A/D conversion of the analog signal input from the input system IN3). IN4_D1 to IN4_D4 indicate pre-interpolation data input to the filter 16-4 (that is, pre-interpolation data after A/D conversion of the analog signal input from the input system IN4).

Pre-interpolation data IN1_D1 is input from A/D converter 12 to distribution unit 13B at time t0, pre-interpolation data IN2_D1 is input at time t1, pre-interpolation data IN3_D1 is input at time t2, and pre-interpolation data IN3_D1 is input at time t3. Pre-interpolation data IN4_D1 is input. Also, pre-interpolation data IN1_D2 at time t4, pre-interpolation data IN2_D2 at time t5, pre-interpolation data IN3_D2 at time t6, and pre-interpolation data IN4_D2 at time t7 are transferred from the A/D converter 12 to the sorting unit 13B. is entered. Also, pre-interpolation data IN1_D3 at time t8, pre-interpolation data IN2_D3 at time t9, pre-interpolation data IN3_D3 at time t10, and pre-interpolation data IN4_D3 at time t11 are transferred from the A/D converter 12 to the sorting unit 13B. is entered. In addition, pre-interpolation data IN1_D4 at time t12, pre-interpolation data IN2_D4 at time t13, pre-interpolation data IN3_D4 at time t14, and pre-interpolation data IN4_D4 at time t15 are transferred from the A/D converter 12 to the sorting unit 13B. is entered. Also, at time t16, pre-interpolation data IN1_D5 is input from the A/D converter 12 to the sorting section 13B.

The distribution unit 13B copies the pre-interpolation data input from the A/D converter 12 according to the number of input systems. In Comparative Example 2, since the number of input systems is four, IN1 to IN4, the distribution unit 13B copies each of the input pre-interpolation data three times in order to create four identical pre-interpolation data. do. In FIG. 5, unhatched data indicates copy source pre-interpolation data, and hatched data indicates pre-interpolation data created by copying.

At time t3, the sorting unit 13B transfers the pre-interpolation data IN1_D1 to the filter 16-1, the pre-interpolation data IN2_D1 to the filter 16-2, the pre-interpolation data IN3_D1 to the filter 16-3, and the pre-interpolation data IN4_D1. They are simultaneously output to the filter 16-4. Further, at time t4, the sorting unit 13B transfers the pre-interpolation data IN1_D2 to the filter 16-1, the pre-interpolation data IN2_D1 to the filter 16-2, the pre-interpolation data IN3_D1 to the filter 16-3, and the pre-interpolation data IN4_D1. They are simultaneously output to the filter 16-4. Further, at time t5, the sorting unit 13B transfers the pre-interpolation data IN1_D2 to the filter 16-1, the pre-interpolation data IN2_D2 to the filter 16-2, the pre-interpolation data IN3_D1 to the filter 16-3, and the pre-interpolation data IN4_D1. They are simultaneously output to the filter 16-4. Further, at time t6, the sorting unit 13B transfers the pre-interpolation data IN1_D2 to the filter 16-1, the pre-interpolation data IN2_D2 to the filter 16-2, the pre-interpolation data IN3_D2 to the filter 16-3, and the pre-interpolation data IN4_D1. They are simultaneously output to the filter 16-4. Further, at time t7, the sorting unit 13B transfers the pre-interpolation data IN1_D2 to the filter 16-1, the pre-interpolation data IN2_D2 to the filter 16-2, the pre-interpolation data IN3_D2 to the filter 16-3, and the pre-interpolation data IN4_D2. They are simultaneously output to the filter 16-4.

At time t8, the sorting unit 13B transfers the pre-interpolation data IN1_D3 to the filter 16-1, the pre-interpolation data IN2_D2 to the filter 16-2, the pre-interpolation data IN3_D2 to the filter 16-3, and the pre-interpolation data IN4_D2. They are simultaneously output to the filter 16-4. At time t9, the sorting unit 13B transfers the pre-interpolation data IN1_D3 to the filter 16-1, the pre-interpolation data IN2_D3 to the filter 16-2, the pre-interpolation data IN3_D2 to the filter 16-3, and the pre-interpolation data IN4_D2. They are simultaneously output to the filter 16-4. At time t10, the sorting unit 13B transfers the pre-interpolation data IN1_D3 to the filter 16-1, the pre-interpolation data IN2_D3 to the filter 16-2, the pre-interpolation data IN3_D3 to the filter 16-3, and the pre-interpolation data IN4_D2. They are simultaneously output to the filter 16-4. At time t11, the sorting unit 13B transfers the pre-interpolation data IN1_D3 to the filter 16-1, the pre-interpolation data IN2_D3 to the filter 16-2, the pre-interpolation data IN3_D3 to the filter 16-3, and the pre-interpolation data IN4_D3. They are simultaneously output to the filter 16-4.

Therefore, the filter 16-1 uses one pre-interpolation data IN1_D1 and four pre-interpolation data IN1_D2 input at times t3 to t7 to generate post-interpolation data OUT1_D1 at time t8, and outputs the data to the output system. Output to OUT1. Since the filter 16-1 has the configuration shown in FIG. 2, the interpolated data OUT1_D1 generated by the filter 16-1 is expressed by equation (7).
OUT1_D1 = IN1_D1×a + IN1_D2×(a+2b+c) …(7)

Further, the filter 16-2 generates post-interpolation data OUT2_D1 at time t8 using the two pre-interpolation data IN2_D1 and the three pre-interpolation data IN2_D2 respectively input at times t3 to t7, and outputs the data to the output system. Output to OUT2. Since the filter 16-2 has the configuration shown in FIG. 2, the interpolated data OUT2_D1 generated by the filter 16-2 is represented by equation (8).
OUT2_D1 = IN2_D1×(a+b) + IN2_D2×(a+b+c) …(8)

Further, the filter 16-3 generates post-interpolation data OUT3_D1 at time t8 using three pre-interpolation data IN3_D1 and two pre-interpolation data IN3_D2 that are input at times t3 to t7, respectively, and outputs the data to the output system. Output to OUT3. Since the filter 16-3 has the configuration shown in FIG. 2, the interpolated data OUT3_D1 generated by the filter 16-3 is represented by equation (9).
OUT3_D1 = IN3_D1×(a+b+c) + IN3_D2×(a+b) …(9)

Further, the filter 16-4 generates post-interpolation data OUT4_D1 at time t8 using four pre-interpolation data IN4_D1 and one pre-interpolation data IN4_D2 that are input at times t3 to t7, respectively, and outputs it to the output system. Output to OUT4. Since the filter 16-4 has the configuration shown in FIG. 2, the interpolated data OUT4_D1 generated by the filter 16-4 is represented by equation (10).
OUT4_D1 = IN4_D1×(a+2b+c) + IN4_D2×a …(10)

Similarly, the filter 16-1 uses one pre-interpolation data IN1_D2 and four pre-interpolation data IN1_D3 input at times t7 to t11, respectively, to obtain post-interpolation data shown in equation (11) at time t12. OUT1_D2 is generated and output to the output system OUT1.
OUT1_D2 = IN1_D2×a + IN1_D3×(a+2b+c) …(11)

In addition, the filter 16-2 uses the two pre-interpolation data IN2_D2 and the three pre-interpolation data IN2_D3 that are input at times t7 to t11, respectively, to obtain post-interpolation data OUT2_D2 shown in equation (12) at time t12. is generated and output to the output system OUT2.
OUT2_D2 = IN2_D2×(a+b) + IN2_D3×(a+b+c) …(12)

In addition, the filter 16-3 uses the three pre-interpolation data IN3_D2 and the two pre-interpolation data IN3_D3 that are input at times t7 to t11, respectively, to obtain post-interpolation data OUT3_D2 represented by Equation (13) at time t12. is generated and output to the output system OUT3.
OUT3_D2 = IN3_D2×(a+b+c) + IN3_D3×(a+b) …(13)

In addition, the filter 16-4 uses four pre-interpolation data IN4_D2 and one pre-interpolation data IN4_D3 that are input at times t7 to t11, respectively, to obtain post-interpolation data OUT4_D2 represented by equation (14) at time t12. is generated and output to the output system OUT4.
OUT4_D2 = IN4_D2×(a+2b+c) + IN4_D3×a …(14)

Since the sampling data output from the A/D converter 12 is interpolated by the filtering by the filters 16-1 to 16-4 as described above, the sampling data corresponding to each of all the input systems IN1 to IN4 is obtained. Data sampling timings are aligned to the same timing.

[Comparative Example 3]
<Configuration of A/D conversion processing device>
FIG. 6 is a diagram showing a configuration example of an A/D conversion processing device of Comparative Example 3. As shown in FIG. In FIG. 6, the A/D conversion processing device 3 has a selection section 11C, an A/D converter 12, a distribution section 13C, a control section 14, and filters 17-1 to 17-5. The selection unit 11C, the A/D converter 12, and the distribution unit 13C operate under the control of the control unit 14. FIG.

Five input systems IN1 to IN5 are connected to the input side of the selector 11C, and the A/D converter 12 is connected to the output side of the selector 11C. An analog signal is input to each of the input systems IN1 to IN5. The selector 11C sequentially selects one of the input systems IN1 to IN5 and connects the selected input system to the A/D converter 12. FIG. 11 C of selection parts are implement|achieved by the switching circuit, for example.

The A/D converter 12 converts an analog signal input from the input system selected by the selection unit 11C from among the input systems IN1 to IN5 into a digital signal, and outputs the digital signal, which is sampling data, to the distribution unit 13C. do.

The distribution unit 13C distributes the sampled data input from the A/D converter 12 to the filters 17-1 to 17-5 corresponding to the input systems IN1 to IN5. The sorting unit 13C sends the converted sampling data of the analog signal of the input system IN1 to the filter 17-1, the converted sampling data of the analog signal of the input system IN2 to the filter 17-2, and the analog signal of the input system IN3. to the filter 17-3, the converted sampling data of the analog signal of the input system IN4 to the filter 17-4, and the converted sampling data of the analog signal of the input system IN5 to the filter 17-5. Output each separately. 13 C of distribution parts are implement|achieved by the switching circuit or S/P (serial/parallel) converter, for example.

By providing the A/D conversion processing device 3 with the selection unit 11C and the distribution unit 13C, the A/D conversion processing device 2 converts five analog signals input to each of the input systems IN1 to IN5 into one A The /D converter 12 enables time-division A/D conversion.

The filter 17-1 is provided corresponding to the input system IN1, performs filtering for interpolating the converted analog signal sampling data of the input system IN1, and outputs the filtered data to the output system OUT1. The filter 17-2 is provided corresponding to the input system IN2, performs filtering for interpolating the converted analog signal sampling data of the input system IN2, and outputs the filtered data to the output system OUT2. The filter 17-3 is provided corresponding to the input system IN3, performs filtering for interpolating the converted analog signal sampling data of the input system IN3, and outputs the filtered data to the output system OUT3. The filter 17-4 is provided corresponding to the input system IN4, performs filtering for interpolating the converted analog signal sampling data of the input system IN4, and outputs the filtered data to the output system OUT4. The filter 17-5 is provided corresponding to the input system IN5, performs filtering for interpolating the converted analog signal sampling data of the input system IN5, and outputs the filtered data to the output system OUT5. By interpolating the sampling data by the filters 17-1 to 17-5, it is possible to match the sampling timings of the sampling data corresponding to all the input systems IN1 to IN5 to the same timing. Each of the filters 17-1 to 17-5 is an FIR filter.

Hereinafter, the sampled data after the A/D conversion by the A/D converter 12 and before filtering by the filters 17-1 to 17-5 will be referred to as "pre-interpolation data", and the filters 17-1 to 17- The data after filtering in 5 is called "post-interpolation data".

Here, when the sampling frequency per input system is fs, the control unit 14 outputs a sampling clock of 5 fs, which is five times the sampling frequency fs, to the A/D converter 12 . The A/D converter 12 converts analog signals sequentially input from the input systems IN1 to IN5 into digital signals at sampling intervals of 1/(5 fs) according to a sampling clock with a frequency of 5 fs. Further, in this case, the control unit 14 switches the connection state between the input systems IN1 to IN5 and the A/D converter 12 in the selection unit 11C at a cycle of 1/(5 fs). Further, the distribution unit 13C distributes the sampling data input from the A/D converter 12 to the filters 17-1 to 17-5 in accordance with the control from the control unit 14 at a cycle of 1/(5 fs). conduct.

<Configuration of filter>
FIG. 7 is a diagram illustrating a configuration example of a filter of Comparative Example 3. FIG. The five filters 17-1 to 17-5 in FIG. 6 have the same configuration as shown in FIG. FIG. 7 shows an example in which each of the filters 17-1 to 17-5 has seven taps TA1 to TA7.

7, the filters 17-1 to 17-5 have delayers 21-1 to 21-6, multipliers 24-1 to 24-7, and an adder 23. In FIG. Each of multipliers 24-1 to 24-7 is connected to each of taps TA1 to TA7.

The pre-interpolation data output from the distribution unit 13C is input to the delay element 21-6. The pre-interpolation data is delayed by one unit time in each of the delay elements 21-6 to 21-1, and then input to each of the multipliers 24-6 to 24-1.

Therefore, the multiplier 24 - 7 multiplies the pre-interpolation data with a delay of 0 (zero) by the coefficient a, and outputs the pre-interpolation data after the coefficient multiplication to the adder 23 . The multiplier 24 - 6 multiplies the pre-interpolation data delayed by one unit time by the coefficient b, and outputs the pre-interpolation data after the coefficient multiplication to the adder 23 . The multiplier 24 - 5 multiplies the pre-interpolation data delayed by two unit times by the coefficient c, and outputs the pre-interpolation data after the coefficient multiplication to the adder 23 . The multiplier 24 - 4 multiplies the pre-interpolation data delayed by three unit times by the coefficient d, and outputs the pre-interpolation data after the coefficient multiplication to the adder 23 . The multiplier 24 - 3 multiplies the pre-interpolation data delayed by 4 unit times by the coefficient c, and outputs the pre-interpolation data after the coefficient multiplication to the adder 23 . The multiplier 24 - 2 multiplies the pre-interpolation data delayed by 5 unit times by the coefficient b, and outputs the pre-interpolation data after the coefficient multiplication to the adder 23 . The multiplier 24 - 1 multiplies the pre-interpolation data delayed by 6 unit times by the coefficient a, and outputs the pre-interpolation data after the coefficient multiplication to the adder 23 .

The adder 23 obtains post-interpolation data by adding all pre-interpolation data after coefficient multiplication output from the multipliers 24-1 to 24-7.

<Operation of A/D conversion processing device>
FIG. 8 is a diagram for explaining an operation example of the A/D conversion processing device of Comparative Example 3. FIG. In FIG. 8, IN1_D1 to IN1_D4 indicate pre-interpolation data input to the filter 17-1 (that is, pre-interpolation data after A/D conversion of the analog signal input from the input system IN1). IN2_D1 to IN2_D4 indicate pre-interpolation data input to the filter 17-2 (that is, pre-interpolation data after A/D conversion of the analog signal input from the input system IN2). IN3_D1 to IN3_D4 indicate pre-interpolation data input to the filter 17-3 (that is, pre-interpolation data after A/D conversion of the analog signal input from the input system IN3). IN4_D1 to IN4_D4 indicate pre-interpolation data input to the filter 17-4 (that is, pre-interpolation data after A/D conversion of the analog signal input from the input system IN4). IN5_D1 to IN5_D4 indicate pre-interpolation data input to the filter 17-5 (that is, pre-interpolation data after A/D conversion of the analog signal input from the input system IN5).

Pre-interpolation data IN1_D1 is input from A/D converter 12 to distribution unit 13C at time t0, pre-interpolation data IN2_D1 is input at time t1, pre-interpolation data IN3_D1 is input at time t2, and pre-interpolation data IN3_D1 is input at time t3. Pre-interpolation data IN4_D1 is input, and pre-interpolation data IN5_D1 is input at time t5. Also, pre-interpolation data IN1_D2 at time t5, pre-interpolation data IN2_D2 at time t6, pre-interpolation data IN3_D2 at time t7, pre-interpolation data IN4_D2 at time t8, pre-interpolation data IN5_D2 at time t9, and A/D It is input from the converter 12 to the sorting section 13C. In addition, pre-interpolation data IN1_D3 at time t10, pre-interpolation data IN2_D3 at time t11, pre-interpolation data IN3_D3 at time t12, pre-interpolation data IN4_D3 at time t13, pre-interpolation data IN5_D3 at time t14, and A/D It is input from the converter 12 to the sorting section 13C. Also, pre-interpolation data IN1_D4 at time t15, pre-interpolation data IN2_D4 at time t16, pre-interpolation data IN3_D4 at time t17, pre-interpolation data IN4_D4 at time t18, pre-interpolation data IN5_D4 at time t19, and A/D It is input from the converter 12 to the sorting section 13C.

The distribution unit 13C copies the pre-interpolation data input from the A/D converter 12 according to the number of input systems. In Comparative Example 3, since the number of input systems is five, IN1 to IN5, the distribution unit 13C copies each of the input pre-interpolation data four times in order to create five identical pre-interpolation data. do. In FIG. 8, unhatched data indicates copy source pre-interpolation data, and hatched data indicates pre-interpolation data created by copying.

At time t4, the sorting unit 13C transfers the pre-interpolation data IN1_D1 to the filter 17-1, the pre-interpolation data IN2_D1 to the filter 17-2, the pre-interpolation data IN3_D1 to the filter 17-3, and the pre-interpolation data IN4_D1. The pre-interpolation data IN5_D1 is simultaneously output to the filter 17-4 and the filter 17-5. At time t5, the sorting unit 13C transfers the pre-interpolation data IN1_D2 to the filter 17-1, the pre-interpolation data IN2_D1 to the filter 17-2, the pre-interpolation data IN3_D1 to the filter 17-3, and the pre-interpolation data IN4_D1. The pre-interpolation data IN5_D1 is simultaneously output to the filter 17-4 and the filter 17-5. At time t6, the sorting unit 13C transfers the pre-interpolation data IN1_D2 to the filter 17-1, the pre-interpolation data IN2_D2 to the filter 17-2, the pre-interpolation data IN3_D1 to the filter 17-3, and the pre-interpolation data IN4_D1. The pre-interpolation data IN5_D1 is simultaneously output to the filter 17-4 and the filter 17-5. At time t7, the sorting unit 13C transfers the pre-interpolation data IN1_D2 to the filter 17-1, the pre-interpolation data IN2_D2 to the filter 17-2, the pre-interpolation data IN3_D2 to the filter 17-3, and the pre-interpolation data IN4_D1. The pre-interpolation data IN5_D1 is simultaneously output to the filter 17-4 and the filter 17-5. At time t8, the sorting unit 13C transfers the pre-interpolation data IN1_D2 to the filter 17-1, the pre-interpolation data IN2_D2 to the filter 17-2, the pre-interpolation data IN3_D2 to the filter 17-3, and the pre-interpolation data IN4_D2. The pre-interpolation data IN5_D1 is simultaneously output to the filter 17-4 and the filter 17-5. At time t9, the sorting unit 13C transfers the pre-interpolation data IN1_D2 to the filter 17-1, the pre-interpolation data IN2_D2 to the filter 17-2, the pre-interpolation data IN3_D2 to the filter 17-3, and the pre-interpolation data IN4_D2. The pre-interpolation data IN5_D2 is simultaneously output to the filter 17-4 and the filter 17-5. At time t10, the sorting unit 13C transfers the pre-interpolation data IN1_D3 to the filter 17-1, the pre-interpolation data IN2_D2 to the filter 17-2, the pre-interpolation data IN3_D2 to the filter 17-3, and the pre-interpolation data IN4_D2. The pre-interpolation data IN5_D2 is simultaneously output to the filter 17-4 and the filter 17-5.

At time t11, the sorting unit 13C transfers the pre-interpolation data IN1_D3 to the filter 17-1, the pre-interpolation data IN2_D3 to the filter 17-2, the pre-interpolation data IN3_D2 to the filter 17-3, and the pre-interpolation data IN4_D2. The pre-interpolation data IN5_D2 is simultaneously output to the filter 17-4 and the filter 17-5. At time t12, the sorting unit 13C transfers the pre-interpolation data IN1_D3 to the filter 17-1, the pre-interpolation data IN2_D3 to the filter 17-2, the pre-interpolation data IN3_D3 to the filter 17-3, and the pre-interpolation data IN4_D2. The pre-interpolation data IN5_D2 is simultaneously output to the filter 17-4 and the filter 17-5. At time t13, the sorting unit 13C transfers the pre-interpolation data IN1_D3 to the filter 17-1, the pre-interpolation data IN2_D3 to the filter 17-2, the pre-interpolation data IN3_D3 to the filter 17-3, and the pre-interpolation data IN4_D3. The pre-interpolation data IN5_D2 is simultaneously output to the filter 17-4 and the filter 17-5. At time t14, the sorting unit 13C transfers the pre-interpolation data IN1_D3 to the filter 17-1, the pre-interpolation data IN2_D3 to the filter 17-2, the pre-interpolation data IN3_D3 to the filter 17-3, and the pre-interpolation data IN4_D3. The pre-interpolation data IN5_D3 is simultaneously output to the filter 17-4 and the filter 17-5. At time t15, the sorting unit 13C transfers the pre-interpolation data IN1_D4 to the filter 17-1, the pre-interpolation data IN2_D3 to the filter 17-2, the pre-interpolation data IN3_D3 to the filter 17-3, and the pre-interpolation data IN4_D3. The pre-interpolation data IN5_D3 is simultaneously output to the filter 17-4 and the filter 17-5.

Therefore, the filter 17-1 uses one pre-interpolation data IN1_D1, five pre-interpolation data IN1_D2, and one pre-interpolation data IN1_D3 input at each of times t4 to t10, and at time t11, after interpolation Data OUT1_D1 is generated and output to the output system OUT1. Since the filter 17-1 has the configuration shown in FIG. 7, the interpolated data OUT1_D1 generated by the filter 17-1 is represented by equation (15).
OUT1_D1 = IN1_D1×a + IN1_D2×(2b+2c+d) + IN1_D3×a …(15)

Further, the filter 17-2 generates post-interpolation data OUT2_D1 at time t11 using the two pre-interpolation data IN2_D1 and the five pre-interpolation data IN2_D2 respectively input at times t4 to t10, and outputs the data to the output system. Output to OUT2. Since the filter 17-2 has the configuration shown in FIG. 7, the interpolated data OUT2_D1 generated by the filter 17-2 is represented by equation (16).
OUT2_D1 = IN2_D1×(a+b) + IN2_D2×(a+b+2c+d) …(16)

Further, the filter 17-3 uses the three pre-interpolation data IN3_D1 and the four pre-interpolation data IN3_D2 that are input at times t4 to t10, respectively, to generate post-interpolation data OUT3_D1 at time t11 and output it to the output system. Output to OUT3. Since the filter 17-3 has the configuration shown in FIG. 7, the interpolated data OUT3_D1 generated by the filter 17-3 is represented by equation (17).
OUT3_D1 = IN3_D1×(a+b+c) + IN3_D2×(a+b+c+d) …(17)

Further, the filter 17-4 generates post-interpolation data OUT4_D1 at time t11 using the four pre-interpolation data IN4_D1 and the three pre-interpolation data IN4_D2 input at times t4 to t10, respectively, and outputs the data to the output system. Output to OUT4. Since the filter 17-4 adopts the configuration shown in FIG. 7, the interpolated data OUT4_D1 generated by the filter 17-4 is represented by equation (18).
OUT4_D1 = IN4_D1×(a+b+c+d) + IN4_D2×(a+b+c) …(18)

Further, the filter 17-5 generates post-interpolation data OUT5_D1 at time t11 using the five pre-interpolation data IN5_D1 and the two pre-interpolation data IN5_D2 respectively input at times t4 to t10, and outputs the data to the output system. Output to OUT5. Since the filter 17-5 has the configuration shown in FIG. 7, the interpolated data OUT4_D1 generated by the filter 17-5 is represented by equation (19).
OUT5_D1 = IN5_D1×(a+b+2c+d) + IN5_D2×(a+b) …(19)

Similarly, the filter 17-1 uses one pre-interpolation data IN1_D2, five pre-interpolation data IN1_D3, and one pre-interpolation data IN1_D4 input at times t9 to t15, respectively, to obtain the formula Interpolated data OUT1_D2 shown in (20) is generated and output to the output system OUT1.
OUT1_D2 = IN1_D2×a + IN1_D3×(2b+2c+d) + IN1_D4×a …(20)

Further, the filter 17-2 uses the two pre-interpolation data IN2_D2 and the five pre-interpolation data IN2_D3 input at times t9 to t15, respectively, to obtain the post-interpolation data OUT2_D2 shown in Equation (21) at time t16. is generated and output to the output system OUT2.
OUT2_D2 = IN2_D2×(a+b) + IN2_D3×(a+b+2c+d) …(21)

Further, the filter 17-3 uses the three pre-interpolation data IN3_D2 and the four pre-interpolation data IN3_D3 that are input at times t9 to t15, respectively, to obtain post-interpolation data OUT3_D2 represented by Equation (22) at time t16. is generated and output to the output system OUT3.
OUT3_D2 = IN3_D2×(a+b+c) + IN3_D3×(a+b+c+d) …(22)

Further, the filter 17-4 uses the four pre-interpolation data IN4_D2 and the three pre-interpolation data IN4_D3 that are input at times t9 to t15, respectively, to obtain post-interpolation data OUT4_D2 represented by equation (23) at time t16. is generated and output to the output system OUT4.
OUT4_D2 = IN4_D2×(a+b+c+d) + IN4_D3×(a+b+c) …(23)

Further, the filter 17-5 uses the five pre-interpolation data IN5_D2 and the two pre-interpolation data IN5_D3 that are input at times t9 to t15, respectively, to obtain post-interpolation data OUT5_D2 shown in equation (24) at time t16. is generated and output to the output system OUT5.
OUT5_D2 = IN5_D2×(a+b+2c+d) + IN5_D3×(a+b) …(24)

Since the sampling data output from the A/D converter 12 is interpolated by the filtering by the filters 17-1 to 17-5 as described above, the sampling data corresponding to all the input systems IN1 to IN5 are obtained. Data sampling timings are aligned to the same timing.

[Example 1]
<Configuration of filter>
In Embodiment 1, the filters 15-1 to 15-3 (FIG. 1) adopt the configurations shown in FIGS. 9 to 11 instead of the configuration shown in FIG. 9 to 11 are diagrams showing configuration examples of the filter of the first embodiment. The filter 15-1 shown in FIG. 9 corresponds to the filter 15-1 shown in FIG. 1, the filter 15-2 shown in FIG. 10 corresponds to the filter 15-2 shown in FIG. 1, and the filter 15-3 shown in FIG. corresponds to the filter 15-3 shown in FIG.

That is, in each of formulas (1) and (4) in Comparative Example 1, multiplication is performed three times in generating post-interpolation data. Further, in each of formulas (2) and (5) in Comparative Example 1, multiplication is performed twice in generating post-interpolation data. Further, in each of formulas (3) and (6) in Comparative Example 1, multiplication is performed twice in generating post-interpolation data.

Therefore, the configuration of the filter 15-1 that generates post-interpolation data according to equations (1) and (4) can be replaced with the configuration shown in FIG. 9 instead of the configuration shown in FIG. In FIG. 9, the filter 15-1 has delay units 31-1, 31-2, multipliers 32-1, 32-2, 32-3, and an adder 33-1. Each of multipliers 32-1, 32-2 and 32-3 is connected to each of taps TA1, TA2 and TA3.

Of the pre-interpolation data output from the distribution unit 13A, the pre-interpolation data generated from the analog signal of the input system IN1 is input to the delay element 31-2. The pre-interpolation data is delayed by one unit time in each of the delay elements 31-2 and 31-1, and then input to each of the multipliers 32-2 and 32-1.

Therefore, the multiplier 32-3 multiplies the pre-interpolation data with a delay of 0 (zero) by the coefficient a, and outputs the pre-interpolation data after the coefficient multiplication to the adder 33-1. The multiplier 32-2 multiplies the pre-interpolation data delayed by one unit time by the coefficient 2b+c, and outputs the pre-interpolation data after the coefficient multiplication to the adder 33-1. The multiplier 32-1 multiplies the pre-interpolation data delayed by two unit times by the coefficient a, and outputs the pre-interpolation data after the coefficient multiplication to the adder 33-1.

The adder 33-1 obtains post-interpolation data by adding all the pre-interpolation data after coefficient multiplication output from the multipliers 32-1 to 32-3.

Therefore, as in Comparative Example 1, the interpolated data OUT1_D1 obtained by the adder 33-1 is expressed by Equation (1), and the interpolated data OUT1_D2 obtained by the adder 33-1 is expressed by Equation (4). be.

Also, the configuration of the filter 15-2 that generates post-interpolation data according to equations (2) and (5) can be replaced with the configuration shown in FIG. 10 instead of the configuration shown in FIG. In FIG. 10, the filter 15-2 has a delayer 31-3, multipliers 32-4 and 32-5, and an adder 33-2. Each of multipliers 32-4 and 32-5 is connected to each of taps TA1 and TA2.

Of the pre-interpolation data output from the distribution unit 13A, the pre-interpolation data generated from the analog signal of the input system IN2 is input to the delay element 31-3. The pre-interpolation data is delayed by one unit time in the delay element 31-3 and then input to the multiplier 32-4.

Therefore, the multiplier 32-5 multiplies the pre-interpolation data with a delay of 0 (zero) by the coefficient a+b+c, and outputs the pre-interpolation data after the coefficient multiplication to the adder 33-2. The multiplier 32-4 multiplies the pre-interpolation data delayed by one unit time by the coefficient a+b, and outputs the pre-interpolation data after the coefficient multiplication to the adder 33-2.

The adder 33-2 obtains post-interpolation data by adding all the pre-interpolation data after coefficient multiplication output from the multipliers 32-4 and 32-5.

Therefore, similarly to Comparative Example 1, the interpolated data OUT2_D1 obtained by the adder 33-2 is expressed by Equation (2), and the interpolated data OUT2_D2 obtained by the adder 33-2 is expressed by Equation (5). be.

Also, the configuration of the filter 15-3 that generates post-interpolation data according to equations (3) and (6) can be replaced with the configuration shown in FIG. 11 instead of the configuration shown in FIG. In FIG. 11, the filter 15-3 has a delayer 31-4, multipliers 32-6 and 32-7, and an adder 33-3. Each of multipliers 32-6 and 32-7 is connected to each of taps TA1 and TA2.

Of the pre-interpolation data output from the distribution unit 13A, the pre-interpolation data generated from the analog signal of the input system IN3 is input to the delay element 31-4. The pre-interpolation data is delayed by one unit time in the delay element 31-4 and then input to the multiplier 32-6.

Therefore, the multiplier 32-7 multiplies the pre-interpolation data with a delay of 0 (zero) by the coefficient a+b, and outputs the pre-interpolation data after the coefficient multiplication to the adder 33-3. The multiplier 32-6 multiplies the pre-interpolation data delayed by one unit time by the coefficient a+b+c, and outputs the pre-interpolation data after the coefficient multiplication to the adder 33-3.

The adder 33-3 obtains post-interpolation data by adding all the pre-interpolation data after coefficient multiplication output from the multipliers 32-6 and 32-7.

Therefore, as in Comparative Example 1, the interpolated data OUT3_D1 obtained by the adder 33-3 is expressed by Equation (3), and the interpolated data OUT3_D2 obtained by the adder 33-3 is expressed by Equation (6). be.

Here, according to Comparative Example 1, since each of the filters 15-1, 15-2, and 15-3 adopts the configuration shown in FIG. The total number of multipliers possessed by is "5×3=15". On the other hand, according to the first embodiment, the filter 15-1 has the configuration shown in FIG. 9, the filter 15-2 has the configuration shown in FIG. 10, and the filter 15-3 has the configuration shown in FIG. , filters 15-1, 15-2, and 15-3 have a total number of multipliers of "3+2+2=7". Therefore, each of the filters 15-1, 15-2, and 15-3 that generate the post-interpolation data OUT1_D1, OUT2_D1, OUT3_D1, OUT1_D2, OUT2_D2, and OUT3_D2 according to equations (1) to (6) has the configuration (comparison 9, 10, and 11 (Embodiment 1) instead of Example 1), the total number of multipliers possessed by the three filters 15-1, 15-2, and 15-3 is reduced to 15. It can be reduced from 1 to 7. Therefore, according to the first embodiment, the circuit scale of the A/D conversion processing device 1 can be reduced.

<Operation of A/D conversion processing device>
12A to 16C are diagrams for explaining an operation example of the A/D conversion processing device according to the first embodiment.

<When Comparative Example 1 adopts a 4-tap configuration>
In the A/D conversion processing device 1 (FIG. 1) having three input systems of input systems IN1, IN2, and IN3, each of the filters 15-1, 15-2, and 15-3 is in Comparative Example 1 (FIG. 2). When adopting a four-tap configuration of taps TA1 to TA4, the total number of multipliers possessed by the three filters 15-1, 15-2, and 15-3 is "4×3=12". Become. Here, let a be the coefficient of the taps TA1 and TA4, and b be the coefficient of the taps TA2 and TA3.

On the other hand, a filter having the same function as the 4-tap filter according to Comparative Example 1 is configured according to FIGS. 9 to 11, and as shown in FIG. When generating data, each of the interpolated data OUT1_D1, OUT2_D1, and OUT3_D1 is represented by equations (25), (26), and (27). Therefore, the total number of multipliers possessed by the three filters 15-1, 15-2 and 15-3 is "2+2+2=6".
OUT1_D1 = IN1_D1×a + IN1_D2×(a+2b) …(25)
OUT2_D1 = IN2_D1×(a+b) + IN2_D2×(a+b) …(26)
OUT3_D1 = IN3_D1×(a+2b) + IN3_D2×a …(27)

Further, a filter having the same function as the 4-tap filter modeled after Comparative Example 1 is configured as shown in FIGS. 9 to 11, and as shown in FIG. When generated, each of the interpolated data OUT1_D1, OUT2_D1, and OUT3_D1 is represented by equations (28), (29), and (30). Therefore, the total number of multipliers possessed by the three filters 15-1, 15-2 and 15-3 is "2+2+2=6".
OUT1_D1 = IN1_D2×(a+2b) + IN1_D3×a …(28)
OUT2_D1 = IN2_D1×a + IN2_D2×(a+2b) …(29)
OUT3_D1 = IN3_D1×(a+b) + IN3_D2×(a+b) …(30)

In addition, a filter having the same function as the 4-tap filter modeled after Comparative Example 1 is configured as shown in FIGS. 9 to 11, and as shown in FIG. When generated, each of the interpolated data OUT1_D1, OUT2_D1, and OUT3_D1 is represented by equations (31), (32), and (33). Therefore, the total number of multipliers possessed by the three filters 15-1, 15-2 and 15-3 is "2+2+2=6".
OUT1_D1 = IN1_D2×(a+b) + IN1_D3×(a+b) …(31)
OUT2_D1 = IN2_D2×(a+2b) + IN2_D3×a …(32)
OUT3_D1 = IN3_D1×a + IN3_D2×(a+2b) …(33)

That is, according to the first embodiment, in any case of FIGS. 12A to 12C, the three filters 15-1, 15-2, and 15-3 are arranged as compared with the case where the filter of the comparative example 1 is configured with four taps. The total number of multipliers the filter has can be reduced from twelve to six.

<When Comparative Example 1 adopts a 5-tap configuration>
In the A/D conversion processing device 1 (FIG. 1) having three input systems of input systems IN1, IN2, and IN3, each of the filters 15-1, 15-2, and 15-3 is in Comparative Example 1 (FIG. 2). When adopting a five-tap configuration of taps TA1 to TA5, the total number of multipliers possessed by the three filters 15-1, 15-2, and 15-3 is "5×3=15". Become. Here, let a be the coefficient of the taps TA1 and TA5, b be the coefficient of the taps TA2 and TA4, and c be the coefficient of the tap TA3.

On the other hand, a filter having the same function as the 5-tap filter following Comparative Example 1 is configured following FIGS. When generating data, each of the interpolated data OUT1_D1, OUT2_D1, and OUT3_D1 is represented by equations (34), (35), and (36). Therefore, the total number of multipliers of the three filters 15-1, 15-2, and 15-3 is "3+2+2=7".
OUT1_D1 = IN1_D1×a + IN1_D2×(2b+c) + IN1_D3×a …(34)
OUT2_D1 = IN2_D1×(a+b) + IN2_D2×(a+b+c) …(35)
OUT3_D1 = IN3_D1×(a+b+c) + IN3_D2×(a+b) …(36)

In addition, a filter having the same function as the 5-tap filter modeled after Comparative Example 1 is configured as shown in FIGS. 9 to 11, and as shown in FIG. When generated, each of the interpolated data OUT1_D1, OUT2_D1, and OUT3_D1 is represented by equations (37), (38), and (39). Therefore, the total number of multipliers possessed by the three filters 15-1, 15-2 and 15-3 is "2+3+2=7".
OUT1_D1 = IN1_D2×(a+b+c) + IN1_D3×(a+b) …(37)
OUT2_D1 = IN2_D1×a + IN2_D2×(2b+c) + IN2_D3×a …(38)
OUT3_D1 = IN3_D1×(a+b) + IN3_D2×(a+b+c) …(39)

Further, a filter having the same function as the 5-tap filter modeled after Comparative Example 1 is configured as shown in FIGS. 9 to 11, and as shown in FIG. When generated, each of the interpolated data OUT1_D1, OUT2_D1, and OUT3_D1 is represented by equations (40), (41), and (42). Therefore, the total number of multipliers possessed by the three filters 15-1, 15-2 and 15-3 is "2+2+3=7".
OUT1_D1 = IN1_D2×(a+b) + IN1_D3×(a+b+c) …(40)
OUT2_D1 = IN2_D2×(a+b+c) + IN2_D3×(a+b) …(41)
OUT3_D1 = IN3_D1×a + IN3_D2×(2b+c) + IN3_D3×a …(42)

That is, according to Example 1, in any of FIGS. The total number of multipliers the filter has can be reduced from 15 to 7.

<When Comparative Example 1 adopts a 6-tap configuration>
In the A/D conversion processing device 1 (FIG. 1) having three input systems of input systems IN1, IN2, and IN3, each of the filters 15-1, 15-2, and 15-3 is in Comparative Example 1 (FIG. 2). When adopting a six-tap configuration of taps TA1 to TA6, the total number of multipliers possessed by the three filters 15-1, 15-2, and 15-3 is "6×3=18". Become. Here, the coefficient of taps TA1 and TA6 is a, the coefficient of taps TA2 and TA5 is b, and the coefficient of taps TA3 and TA4 is c.

On the other hand, a filter having the same function as the 6-tap filter according to Comparative Example 1 is configured according to FIGS. 9 to 11, and as shown in FIG. When generating data, each of the interpolated data OUT1_D1, OUT2_D1, and OUT3_D1 is represented by equations (43), (44), and (45). Therefore, the total number of multipliers possessed by the three filters 15-1, 15-2 and 15-3 is "3+3+2=8".
OUT1_D1 = IN1_D1×a + IN1_D2×(b+2c) + IN1_D3×(a+b) …(43)
OUT2_D1 = IN2_D1×(a+b) + IN2_D2×(b+2c) + IN2_D3×a …(44)
OUT3_D1 = IN3_D1×(a+b+c) + IN3_D2×(a+b+c) …(45)

Further, a filter having the same function as the 6-tap filter according to Comparative Example 1 is configured according to FIGS. 9 to 11, and as shown in FIG. When generated, each of the interpolated data OUT1_D1, OUT2_D1, and OUT3_D1 is represented by equations (46), (47), and (48). Therefore, the total number of multipliers possessed by the three filters 15-1, 15-2 and 15-3 is "2+3+3=8".
OUT1_D1 = IN1_D2×(a+b+c) + IN1_D3×(a+b+c) …(46)
OUT2_D1 = IN2_D1×a + IN2_D2×(b+2c) + IN2_D3×(a+b) …(47)
OUT3_D1 = IN3_D1×(a+b) + IN3_D2×(b+2c) + IN3_D3×a …(48)

Further, a filter having the same function as the 6-tap filter according to Comparative Example 1 is configured according to FIGS. 9 to 11, and as shown in FIG. When generated, each of the interpolated data OUT1_D1, OUT2_D1, and OUT3_D1 is represented by equations (49), (50), and (51). Therefore, the total number of multipliers possessed by the three filters 15-1, 15-2 and 15-3 is "3+2+3=8".
OUT1_D1 = IN1_D2×(a+b) + IN1_D3×(b+2c) + IN1_D4×a …(49)
OUT2_D1 = IN2_D2×(a+b+c) + IN2_D3×(a+b+c) …(50)
OUT3_D1 = IN3_D1×a + IN3_D2×(b+2c) + IN3_D3×(a+b) …(51)

That is, according to Example 1, in any case of FIGS. The total number of multipliers the filter has can be reduced from 18 to 8.

<When Comparative Example 1 adopts a 7-tap configuration>
In the A/D conversion processing device 1 (FIG. 1) having three input systems of input systems IN1, IN2, and IN3, each of the filters 15-1, 15-2, and 15-3 is in Comparative Example 1 (FIG. 2). When adopting a 7-tap configuration of taps TA1 to TA7, the total number of multipliers possessed by the three filters 15-1, 15-2, and 15-3 is "7×3=21". Become. Here, the coefficient of taps TA1 and TA7 is a, the coefficient of taps TA2 and TA6 is b, the coefficient of taps TA3 and TA5 is c, and the coefficient of tap TA4 is d.

On the other hand, a filter having the same function as the 7-tap filter modeled after Comparative Example 1 is configured according to FIGS. When generating data, each of the interpolated data OUT1_D1, OUT2_D1, and OUT3_D1 is represented by equations (52), (53), and (54). Therefore, the total number of multipliers possessed by the three filters 15-1, 15-2 and 15-3 is "3+3+3=9".
OUT1_D1 = IN1_D1×a + IN1_D2×(b+c+d) + IN1_D3×(a+b+c) …(52)
OUT2_D1 = IN2_D1×(a+b) + IN2_D2×(2c+d) + IN2_D3×(a+b) …(53)
OUT3_D1 = IN3_D1×(a+b+c) + IN3_D2×(b+c+d) + IN3_D3×a …(54)

In addition, a filter having the same function as the 7-tap filter modeled after Comparative Example 1 is configured as shown in FIGS. 9 to 11, and as shown in FIG. When generated, each of the interpolated data OUT1_D1, OUT2_D1, and OUT3_D1 is represented by equations (55), (56), and (57). Therefore, the total number of multipliers possessed by the three filters 15-1, 15-2 and 15-3 is "3+3+3=9".
OUT1_D1 = IN1_D2×(a+b+c) + IN1_D3×(b+c+d) + IN1_D4×a …(55)
OUT2_D1 = IN2_D1×a + IN2_D2×(b+c+d) + IN2_D3×(a+b+c) …(56)
OUT3_D1 = IN3_D1×(a+b) + IN3_D2×(2c+d) + IN3_D3×(a+b) …(57)

In addition, a filter having the same function as the 7-tap filter according to Comparative Example 1 is configured according to FIGS. 9 to 11, and as shown in FIG. When generated, each of the interpolated data OUT1_D1, OUT2_D1, and OUT3_D1 is represented by equations (58), (59), and (60). Therefore, the total number of multipliers possessed by the three filters 15-1, 15-2 and 15-3 is "3+3+3=9".
OUT1_D1 = IN1_D2×(a+b) + IN1_D3×(2c+d) + IN1_D4×(a+b) …(58)
OUT2_D1 = IN2_D2×(a+b+c) + IN2_D3×(b+c+d) + IN2_D4×a …(59)
OUT3_D1 = IN3_D1×a + IN3_D2×(b+c+d) + IN3_D3×(a+b+c) …(60)

That is, according to Example 1, in any case of FIGS. The total number of multipliers the filter has can be reduced from 21 to 9.

<When Comparative Example 1 Adopts an 8-Tap Configuration>
In the A/D conversion processing device 1 (FIG. 1) having three input systems of input systems IN1, IN2, and IN3, each of the filters 15-1, 15-2, and 15-3 is in Comparative Example 1 (FIG. 2). When adopting an 8-tap configuration of taps TA1 to TA8, the total number of multipliers possessed by the three filters 15-1, 15-2, and 15-3 is "8×3=24". Become. Here, the coefficient of taps TA1 and TA8 is a, the coefficient of taps TA2 and TA7 is b, the coefficient of taps TA3 and TA6 is c, and the coefficient of taps TA4 and TA5 is d.

On the other hand, a filter having the same function as the 8-tap filter according to Comparative Example 1 is configured according to FIGS. 9 to 11, and as shown in FIG. When generating data, each of the interpolated data OUT1_D1, OUT2_D1, and OUT3_D1 is represented by equations (61), (62), and (63). Therefore, the total number of multipliers possessed by the three filters 15-1, 15-2 and 15-3 is "4+3+3=10".
OUT1_D1 = IN1_D1×a + IN1_D2×(b+c+d) + IN1_D3×(b+c+d) + IN1_D4×a …(61)
OUT2_D1 = IN2_D1×(a+b) + IN2_D2×(c+2d) + IN2_D3×(a+b+c) …(62)
OUT3_D1 = IN3_D1×(a+b+c) + IN3_D2×(c+2d) + IN3_D3×(a+b) …(63)

Further, a filter having the same function as the 8-tap filter according to Comparative Example 1 is configured according to FIGS. 9 to 11, and as shown in FIG. When generated, each of the interpolated data OUT1_D1, OUT2_D1, and OUT3_D1 is represented by equations (64), (65), and (66). Therefore, the total number of multipliers possessed by the three filters 15-1, 15-2 and 15-3 is "3+4+3=10".
OUT1_D1 = IN1_D2×(a+b+c) + IN1_D3×(c+2d) + IN1_D4×(a+b) …(64)
OUT2_D1 = IN2_D1×a + IN2_D2×(b+c+d) + IN2_D3×(b+c+d) + IN2_D4×a …(65)
OUT3_D1 = IN3_D1×(a+b) + IN3_D2×(c+2d) + IN3_D3×(a+b+c) …(66)

Further, a filter having the same function as the 8-tap filter modeled after Comparative Example 1 is configured as shown in FIGS. 9 to 11, and as shown in FIG. When generated, each of the interpolated data OUT1_D1, OUT2_D1, and OUT3_D1 is represented by equations (67), (68), and (69). Therefore, the total number of multipliers possessed by the three filters 15-1, 15-2 and 15-3 is "3+3+4=10".
OUT1_D1 = IN1_D2×(a+b) + IN1_D3×(c+2d) + IN1_D4×(a+b+c) …(67)
OUT2_D1 = IN2_D2×(a+b+c) + IN2_D3×(c+2d) + IN2_D4×(a+b) …(68)
OUT3_D1 = IN3_D1×a + IN3_D2×(b+c+d) + IN3_D3×(b+c+d) + IN3_D4×a …(69)

That is, according to Example 1, in any case of FIGS. The total number of multipliers the filter has can be reduced from 24 to 10.

As described above, in the first embodiment, the total number of multipliers included in the three filters 15-1 to 15-3 is reduced from 12 to 6, compared to the case where the filter of the comparative example 1 is configured with 4 taps. could be reduced to one. In addition, in the first embodiment, the total number of multipliers included in the three filters 15-1 to 15-3 is reduced from 15 to 7 compared to the case where the filter of the comparative example 1 is configured with 5 taps. We were able to. Further, in the first embodiment, the total number of multipliers included in the three filters 15-1 to 15-3 is reduced from 18 to 8 compared to the case where the filter of the comparative example 1 is configured with 6 taps. We were able to. Further, in the first embodiment, the total number of multipliers included in the three filters 15-1 to 15-3 is reduced from 21 to 9 compared to the filter of the comparative example 1 having 7 taps. We were able to. Further, in the first embodiment, the total number of multipliers included in the three filters 15-1 to 15-3 is reduced from 24 to 10 compared to the case where the filter of the comparative example 1 is configured with 8 taps. We were able to. Therefore, the number of filters that the A/D conversion processing device 1 of the first embodiment has (that is, the number of input systems that the A/D conversion processing device 1 of the first embodiment has) is "α", and A When the number of taps in each filter of the /D conversion processing device 1 is "n", the total number of multipliers of the three filters 15-1 to 15-3 of the first embodiment is "α+n-1 ” can be expressed as pcs.

Further, in the above, the case where the A/D conversion processing device 1 in Comparative Example 1 adopts the configuration of 4 taps, 5 taps, 6 taps, 7 taps, or 8 taps has been described as an example. The number of taps adopted by the A/D conversion processing device 1 in Comparative Example 1 is based on the accuracy required for interpolation processing by filtering in each of the filters 15-1, 15-2, and 15-3 in Comparative Example 1. It is determined.

[Example 2]
<Configuration of filter>
In the second embodiment, the filter 16-1 (FIG. 4) has the configuration shown in FIG. 17 instead of the configuration shown in FIG. 2, and the filter 16-2 (FIG. 4) has the configuration shown in FIG. , the configuration shown in FIG. 10 is adopted as in the first embodiment. Further, in the second embodiment, the filter 16-3 (FIG. 4) adopts the configuration shown in FIG. 11 as in the first embodiment instead of the configuration shown in FIG. , the configuration shown in FIG. 18 is adopted instead of the configuration shown in FIG. 17 and 18 are diagrams illustrating configuration examples of filters according to the second embodiment.

That is, in each of Equations (7) to (14) in Comparative Example 2, multiplication is performed twice in generating post-interpolation data.

Therefore, the configuration of the filter 16-1 that generates post-interpolation data in accordance with equations (7) and (11) can adopt the configuration shown in FIG. 17 instead of the configuration shown in FIG. In FIG. 17, the filter 16-1 has a delayer 31-5, multipliers 32-8 and 32-9, and an adder 33-5. Each of multipliers 32-8 and 32-9 is connected to each of taps TA1 and TA2.

Of the pre-interpolation data output from the distribution unit 13B, the pre-interpolation data generated from the analog signal of the input system IN1 is input to the delay element 31-5. The pre-interpolation data is delayed by one unit time in the delay element 31-5 and then input to the multiplier 32-8.

Therefore, the multiplier 32-9 multiplies the pre-interpolation data with a delay of 0 (zero) by the coefficient a+2b+c, and outputs the pre-interpolation data after the coefficient multiplication to the adder 33-5. The multiplier 32-8 multiplies the pre-interpolation data delayed by one unit time by the coefficient a, and outputs the pre-interpolation data after the coefficient multiplication to the adder 33-5.

The adder 33-5 obtains post-interpolation data by adding all the pre-interpolation data after coefficient multiplication output from the multipliers 32-8 and 32-9.

Therefore, similarly to Comparative Example 2, the interpolated data OUT1_D1 obtained by the adder 33-5 is expressed by Equation (7), and the interpolated data OUT1_D2 obtained by the adder 33-5 is expressed by Equation (11). be.

Also, the configuration of the filter 16-2 that generates post-interpolation data according to equations (8) and (12) can be replaced with the configuration shown in FIG. 10 instead of the configuration shown in FIG. In FIG. 10, the filter 16-2 has a delayer 31-3, multipliers 32-4 and 32-5, and an adder 33-2. Each of multipliers 32-4 and 32-5 is connected to each of taps TA1 and TA2.

Of the pre-interpolation data output from the distribution unit 13B, the pre-interpolation data generated from the analog signal of the input system IN2 is input to the delay element 31-3. The pre-interpolation data is delayed by one unit time in the delay element 31-3 and then input to the multiplier 32-4.

Therefore, the multiplier 32-5 multiplies the pre-interpolation data with a delay of 0 (zero) by the coefficient a+b+c, and outputs the pre-interpolation data after the coefficient multiplication to the adder 33-2. The multiplier 32-4 multiplies the pre-interpolation data delayed by one unit time by the coefficient a+b, and outputs the pre-interpolation data after the coefficient multiplication to the adder 33-2.

The adder 33-2 obtains post-interpolation data by adding all the pre-interpolation data after coefficient multiplication output from the multipliers 32-4 and 32-5.

Therefore, similarly to Comparative Example 2, the interpolated data OUT2_D1 obtained by the adder 33-2 is expressed by Equation (8), and the interpolated data OUT2_D2 obtained by the adder 33-2 is expressed by Equation (12). be.

Also, the configuration of the filter 16-3 that generates post-interpolation data according to equations (9) and (13) can be replaced with the configuration shown in FIG. 11 instead of the configuration shown in FIG. In FIG. 11, the filter 16-3 has a delayer 31-4, multipliers 32-6 and 32-7, and an adder 33-3. Each of multipliers 32-6 and 32-7 is connected to each of taps TA1 and TA2.

Of the pre-interpolation data output from the distribution unit 13B, the pre-interpolation data generated from the analog signal of the input system IN3 is input to the delay element 31-4. The pre-interpolation data is delayed by one unit time in the delay element 31-4 and then input to the multiplier 32-6.

Therefore, the multiplier 32-7 multiplies the pre-interpolation data with a delay of 0 (zero) by the coefficient a+b, and outputs the pre-interpolation data after the coefficient multiplication to the adder 33-3. The multiplier 32-6 multiplies the pre-interpolation data delayed by one unit time by the coefficient a+b+c, and outputs the pre-interpolation data after the coefficient multiplication to the adder 33-3.

The adder 33-3 obtains post-interpolation data by adding all the pre-interpolation data after coefficient multiplication output from the multipliers 32-6 and 32-7.

Therefore, similarly to Comparative Example 2, the interpolated data OUT3_D1 obtained by the adder 33-3 is expressed by Equation (9), and the interpolated data OUT3_D2 obtained by the adder 33-3 is expressed by Equation (13). be.

Further, the configuration of the filter 16-4 that generates post-interpolation data according to equations (10) and (14) can be replaced with the configuration shown in FIG. 18 instead of the configuration shown in FIG. In FIG. 18, the filter 16-4 has a delayer 31-6, multipliers 32-10 and 32-11, and an adder 33-4. Each of multipliers 32-10 and 32-11 is connected to each of taps TA1 and TA2.

Of the pre-interpolation data output from the distribution unit 13B, the pre-interpolation data generated from the analog signal of the input system IN4 is input to the delay element 31-6. The pre-interpolation data is delayed by one unit time in the delay element 31-6 and then input to the multiplier 32-10.

Therefore, the multiplier 32-11 multiplies the pre-interpolation data with a delay of 0 (zero) by the coefficient a, and outputs the pre-interpolation data after the coefficient multiplication to the adder 33-4. The multiplier 32-10 multiplies the pre-interpolation data delayed by one unit time by the coefficient a+2b+c, and outputs the pre-interpolation data after the coefficient multiplication to the adder 33-4.

The adder 33-4 obtains post-interpolation data by adding all the pre-interpolation data after coefficient multiplication output from the multipliers 32-10 and 32-11.

Therefore, similarly to Comparative Example 2, the interpolated data OUT4_D1 obtained by the adder 33-4 is expressed by Equation (10), and the interpolated data OUT4_D2 obtained by the adder 33-4 is expressed by Equation (14). be.

Here, according to Comparative Example 2, since each of the filters 16-1 to 16-4 adopts the configuration shown in FIG. , "5×4=20". On the other hand, according to the second embodiment, the filter 16-1 adopts the configuration shown in FIG. 17, the filter 16-2 adopts the configuration shown in FIG. 10, the filter 16-3 adopts the configuration shown in FIG. Filter 16-4 adopts the configuration shown in FIG. Therefore, in the second embodiment, the total number of multipliers of the four filters 16-1 to 16-4 is "2+2+2+2=8". Therefore, each of the filters 16-1 to 16-4 for generating the post-interpolation data OUT1_D1, OUT2_D1, OUT3_D1, OUT4_D1, OUT1_D2, OUT2_D2, OUT3_D2, OUT4_D2 according to the equations (7) to (14) has the configuration shown in FIG. 17, 10, 11, and 18 instead of example 2), the total number of multipliers possessed by the four filters 16-1 to 16-4 can be reduced from 20. can be reduced to eight. Therefore, according to the second embodiment, the circuit scale of the A/D conversion processing device 2 can be reduced.

<Operation of A/D conversion processing device>
19A to 23D are diagrams for explaining an operation example of the A/D conversion processing device of the second embodiment.

<When Comparative Example 2 adopts a 5-tap configuration>
In the A/D conversion processing device 2 (FIG. 4) having four input systems of input systems IN1 to IN4, each of the filters 16-1 to 16-4 follows the comparative example 2 (FIG. 2) and taps TA1 to TA5 , the total number of multipliers of the four filters 16-1 to 16-4 is "5×4=20". Here, let a be the coefficient of the taps TA1 and TA5, b be the coefficient of the taps TA2 and TA4, and c be the coefficient of the tap TA3.

On the other hand, a filter having the same function as the 5-tap filter modeled after Comparative Example 2 is configured according to FIGS. When the interpolated data is generated from the data, each of the interpolated data OUT1_D1, OUT2_D1, OUT3_D1, and OUT4_D1 is represented by equations (70) to (73). Therefore, the total number of multipliers of the four filters 16-1 to 16-4 is "2+2+2+2=8".
OUT1_D1 = IN1_D1×a + IN1_D2×(a+2b+c) …(70)
OUT2_D1 = IN2_D1×(a+b) + IN2_D2×(a+b+c) …(71)
OUT3_D1 = IN3_D1×(a+b+c) + IN3_D2×(a+b) …(72)
OUT4_D1 = IN4_D1×(a+2b+c) + IN4_D2×a …(73)

17, 10, 11, and 18, and as shown in FIG. 19B, from the data before interpolation from time t4 to t8 When generating post-interpolation data, each of post-interpolation data OUT1_D1, OUT2_D1, OUT3_D1, and OUT4_D1 is represented by equations (74) to (77). Therefore, the total number of multipliers of the four filters 16-1 to 16-4 is "2+2+2+2=8".
OUT1_D1 = IN1_D2×(a+2b+c) + IN1_D3×a …(74)
OUT2_D1 = IN2_D1×a + IN2_D2×(a+2b+c) …(75)
OUT3_D1 = IN3_D1×(a+b) + IN3_D2×(a+b+c) …(76)
OUT4_D1 = IN4_D1×(a+b+c) + IN4_D2×(a+b) …(77)

17, 10, 11, and 18, and as shown in FIG. When generating post-interpolation data, each of post-interpolation data OUT1_D1, OUT2_D1, OUT3_D1, and OUT4_D1 is represented by equations (78) to (81). Therefore, the total number of multipliers of the four filters 16-1 to 16-4 is "2+2+2+2=8".
OUT1_D1 = IN1_D2×(a+b+c) + IN1_D3×(a+b) …(78)
OUT2_D1 = IN2_D2×(a+2b+c) + IN2_D3×a …(79)
OUT3_D1 = IN3_D1×a + IN3_D2×(a+2b+c) …(80)
OUT4_D1 = IN4_D1×(a+b) + IN4_D2×(a+b+c) …(81)

17, 10, 11, and 18, and as shown in FIG. When generating post-interpolation data, each of post-interpolation data OUT1_D1, OUT2_D1, OUT3_D1, and OUT4_D1 is represented by equations (82) to (85). Therefore, the total number of multipliers of the four filters 16-1 to 16-4 is "2+2+2+2=8".
OUT1_D1 = IN1_D2×(a+b) + IN1_D3×(a+b+c) …(82)
OUT2_D1 = IN2_D2×(a+b+c) + IN2_D3×(a+b) …(83)
OUT3_D1 = IN3_D2×(a+2b+c) + IN3_D3×a …(84)
OUT4_D1 = IN4_D1×a + IN4_D2×(a+2b+c) …(85)

That is, according to the second embodiment, in any case of FIGS. 19A to 19D, the multiplication of the four filters 16-1 to 16-4 is greater than the case where the filter of the comparative example 2 is configured with 5 taps. The total number of vessels can be reduced from 20 to 8.

<When Comparative Example 2 adopts a 6-tap configuration>
In the A/D conversion processing device 2 (FIG. 4) having four input systems IN1 to IN4, each of the filters 16-1 to 16-4 follows the comparative example 2 (FIG. 2) and taps TA1 to TA6 , the total number of multipliers of the four filters 16-1 to 16-4 is "6×4=24". Here, the coefficient of taps TA1 and TA6 is a, the coefficient of taps TA2 and TA5 is b, and the coefficient of taps TA3 and TA4 is c.

On the other hand, a filter having the same function as the 6-tap filter according to Comparative Example 2 is configured according to FIGS. When the interpolated data is generated from the data, each of the interpolated data OUT1_D1, OUT2_D1, OUT3_D1, OUT4_D1 is represented by equations (86) to (89). Therefore, the total number of multipliers of the four filters 16-1 to 16-4 is "3+2+2+2=9".
OUT1_D1 = IN1_D1×a + IN1_D2×(2b+2c) + IN1_D3×a …(86)
OUT2_D1 = IN2_D1×(a+b) + IN2_D2×(a+b+2c) …(87)
OUT3_D1 = IN3_D1×(a+b+c) + IN3_D2×(a+b+c) …(88)
OUT4_D1 = IN4_D1×(a+b+2c) + IN4_D2×(a+b) …(89)

17, 10, 11, and 18, and as shown in FIG. When generating post-interpolation data, each of post-interpolation data OUT1_D1, OUT2_D1, OUT3_D1, and OUT4_D1 is represented by equations (90) to (93). Therefore, the total number of multipliers of the four filters 16-1 to 16-4 is "2+3+2+2=9".
OUT1_D1 = IN1_D2×(a+b+2c) + IN1_D3×(a+b) …(90)
OUT2_D1 = IN2_D1×a + IN2_D2×(2b+2c) + IN2_D3×a …(91)
OUT3_D1 = IN3_D1×(a+b) + IN3_D2×(a+b+2c) …(92)
OUT4_D1 = IN4_D1×(a+b+c) + IN4_D2×(a+b+c) …(93)

17, 10, 11, and 18, and, as shown in FIG. When generating post-interpolation data, each of post-interpolation data OUT1_D1, OUT2_D1, OUT3_D1, and OUT4_D1 is represented by equations (94) to (97). Therefore, the total number of multipliers of the four filters 16-1 to 16-4 is "2+2+3+2=9".
OUT1_D1 = IN1_D2×(a+b+c) + IN1_D3×(a+b+c) …(94)
OUT2_D1 = IN2_D2×(a+b+2c) + IN2_D3×(a+b) …(95)
OUT3_D1 = IN3_D1×a + IN3_D2×(2b+2c) + IN3_D3×a …(96)
OUT4_D1 = IN4_D1×(a+b) + IN4_D2×(a+b+2c) …(97)

17, 10, 11, and 18, and as shown in FIG. When generating post-interpolation data, each of post-interpolation data OUT1_D1, OUT2_D1, OUT3_D1, and OUT4_D1 is represented by equations (98) to (101). Therefore, the total number of multipliers of the four filters 16-1 to 16-4 is "2+2+2+3=9".
OUT1_D1 = IN1_D2×(a+b) + IN1_D3×(a+b+2c) …(98)
OUT2_D1 = IN2_D2×(a+b+c) + IN2_D3×(a+b+c) …(99)
OUT3_D1 = IN3_D2×(a+b+2c) + IN3_D3×(a+b) …(100)
OUT4_D1 = IN4_D1×a + IN4_D2×(2b+2c) + IN4_D3×a …(101)

That is, according to the second embodiment, in any case of FIGS. 20A to 20D, the multiplication of the four filters 16-1 to 16-4 is greater than the case where the filter of the comparative example 2 is configured with 6 taps. The total number of vessels can be reduced from 24 to 9.

<When Comparative Example 2 adopts a 7-tap configuration>
In the A/D conversion processing device 2 (FIG. 4) having four input systems IN1 to IN4, each of the filters 16-1 to 16-4 follows the comparative example 2 (FIG. 2) and taps TA1 to TA7 , the total number of multipliers of the four filters 16-1 to 16-4 is "7×4=28". Here, the coefficient of taps TA1 and TA7 is a, the coefficient of taps TA2 and TA6 is b, the coefficient of taps TA3 and TA5 is c, and the coefficient of tap TA4 is d.

On the other hand, a filter having the same function as the 7-tap filter according to Comparative Example 2 is configured according to FIGS. When the interpolated data is generated from the data, each of the interpolated data OUT1_D1, OUT2_D1, OUT3_D1, and OUT4_D1 is represented by equations (102) to (105). Therefore, the total number of multipliers of the four filters 16-1 to 16-4 is "3+3+2+2=10".
OUT1_D1 = IN1_D1×a + IN1_D2×(b+2c+d) + IN1_D3×(a+b) …(102)
OUT2_D1 = IN2_D1×(a+b) + IN2_D2×(b+2c+d) + IN2_D3×a …(103)
OUT3_D1 = IN3_D1×(a+b+c) + IN3_D2×(a+b+c+d) …(104)
OUT4_D1 = IN4_D1×(a+b+c+d) + IN4_D2×(a+b+c) …(105)

17, 10, 11, and 18, and as shown in FIG. When generating post-interpolation data, each of post-interpolation data OUT1_D1, OUT2_D1, OUT3_D1, and OUT4_D1 is represented by equations (106) to (109). Therefore, the total number of multipliers of the four filters 16-1 to 16-4 is "2+3+3+2=10".
OUT1_D1 = IN1_D2×(a+b+c+d) + IN1_D3×(a+b+c) …(106)
OUT2_D1 = IN2_D1×a + IN2_D2×(b+2c+d) + IN2_D3×(a+b) …(107)
OUT3_D1 = IN3_D1×(a+b) + IN3_D2×(b+2c+d) + IN3_D3×a …(108)
OUT4_D1 = IN4_D1×(a+b+c) + IN4_D2×(a+b+c+d) …(109)

17, 10, 11, and 18, and, as shown in FIG. When generating post-interpolation data, each of post-interpolation data OUT1_D1, OUT2_D1, OUT3_D1, and OUT4_D1 is represented by equations (110) to (113). Therefore, the total number of multipliers of the four filters 16-1 to 16-4 is "2+2+3+3=10".
OUT1_D1 = IN1_D2×(a+b+c) + IN1_D3×(a+b+c+d) …(110)
OUT2_D1 = IN2_D2×(a+b+c+d) + IN2_D3×(a+b+c) …(111)
OUT3_D1 = IN3_D1×a + IN3_D2×(b+2c+d) + IN3_D3×(a+b) …(112)
OUT4_D1 = IN4_D1×(a+b) + IN4_D2×(b+2c+d) + IN4_D3×a …(113)

17, 10, 11, and 18, and as shown in FIG. When generating post-interpolation data, each of post-interpolation data OUT1_D1, OUT2_D1, OUT3_D1, and OUT4_D1 is represented by equations (114) to (117). Therefore, the total number of multipliers of the four filters 16-1 to 16-4 is "3+2+2+3=10".
OUT1_D1 = IN1_D2×(a+b) + IN1_D3×(b+2c+d) + IN1_D4×a …(114)
OUT2_D1 = IN2_D2×(a+b+c) + IN2_D3×(a+b+c+d) …(115)
OUT3_D1 = IN3_D2×(a+b+c+d) + IN3_D3×(a+b+c) …(116)
OUT4_D1 = IN4_D1×a + IN4_D2×(b+2c+d) + IN4_D3×(a+b) …(117)

That is, according to the second embodiment, in any case of FIGS. 21A to 21D, the multiplication of the four filters 16-1 to 16-4 is greater than the case where the filter of the comparative example 2 is configured with 7 taps. The total number of vessels can be reduced from 28 to 10.

<Case in which Comparative Example 2 employs an 8-tap configuration>
In the A/D conversion processing device 2 (FIG. 4) having four input systems IN1 to IN4, each of the filters 16-1 to 16-4 follows the comparative example 2 (FIG. 2) and taps TA1 to TA8. , the total number of multipliers of the four filters 16-1 to 16-4 is "8×4=32". Here, the coefficient of taps TA1 and TA8 is a, the coefficient of taps TA2 and TA7 is b, the coefficient of taps TA3 and TA6 is c, and the coefficient of taps TA4 and TA5 is d.

On the other hand, a filter having the same function as the 8-tap filter according to Comparative Example 2 is configured according to FIGS. When generating post-interpolation data from data, each of post-interpolation data OUT1_D1, OUT2_D1, OUT3_D1, and OUT4_D1 is represented by equations (118) to (121). Therefore, the total number of multipliers of the four filters 16-1 to 16-4 is "3+3+3+2=11".
OUT1_D1 = IN1_D1×a + IN1_D2×(b+c+2d) + IN1_D3×(a+b+c) …(118)
OUT2_D1 = IN2_D1×(a+b) + IN2_D2×(2c+2d) + IN2_D3×(a+b) …(119)
OUT3_D1 = IN3_D1×(a+b+c) + IN3_D2×(b+c+2d) + IN3_D3×a …(120)
OUT4_D1 = IN4_D1×(a+b+c+d) + IN4_D2×(a+b+c+d) …(121)

17, 10, 11, and 18, a filter having the same function as the 8-tap filter in Comparative Example 2 is configured, and as shown in FIG. When generating post-interpolation data, each of post-interpolation data OUT1_D1, OUT2_D1, OUT3_D1, and OUT4_D1 is represented by equations (122) to (125). Therefore, the total number of multipliers possessed by the four filters 16-1 to 16-4 is "2+3+3+3=11".
OUT1_D1 = IN1_D2×(a+b+c+d) + IN1_D3×(a+b+c+d) …(122)
OUT2_D1 = IN2_D1×a + IN2_D2×(b+c+2d) + IN2_D3×(a+b+c) …(123)
OUT3_D1 = IN3_D1×(a+b) + IN3_D2×(2c+2d) + IN3_D3×(a+b) …(124)
OUT4_D1 = IN4_D1×(a+b+c) + IN4_D2×(b+c+2d) + IN4_D3×a …(125)

17, 10, 11, and 18, a filter having the same function as the 8-tap filter in Comparative Example 2 is configured, and as shown in FIG. When generating post-interpolation data, each of post-interpolation data OUT1_D1, OUT2_D1, OUT3_D1, and OUT4_D1 is represented by equations (126) to (129). Therefore, the total number of multipliers of the four filters 16-1 to 16-4 is "3+2+3+3=11".
OUT1_D1 = IN1_D2×(a+b+c) + IN1_D3×(b+c+2d) + IN1_D4×a …(126)
OUT2_D1 = IN2_D2×(a+b+c+d) + IN2_D3×(a+b+c+d) …(127)
OUT3_D1 = IN3_D1×a + IN3_D2×(b+c+2d) + IN3_D3×(a+b+c) …(128)
OUT4_D1 = IN4_D1×(a+b) + IN4_D2×(2c+2d) + IN4_D3×(a+b) …(129)

17, 10, 11, and 18, a filter having the same function as the 8-tap filter in Comparative Example 2 is configured, and as shown in FIG. When generating post-interpolation data, each of post-interpolation data OUT1_D1, OUT2_D1, OUT3_D1, and OUT4_D1 is represented by equations (130) to (133). Therefore, the total number of multipliers of the four filters 16-1 to 16-4 is "3+3+2+3=11".
OUT1_D1 = IN1_D2×(a+b) + IN1_D3×(2c+2d) + IN1_D4×(a+b) …(130)
OUT2_D1 = IN2_D2×(a+b+c) + IN2_D3×(b+c+2d) + IN2_D4×a …(131)
OUT3_D1 = IN3_D2×(a+b+c+d) + IN3_D3×(a+b+c+d) …(132)
OUT4_D1 = IN4_D1×a + IN4_D2×(b+c+2d) + IN4_D3×(a+b+c) …(133)

That is, according to the second embodiment, in any case of FIGS. 22A to 22D, the multiplication of the four filters 16-1 to 16-4 is greater than the case where the filter of the comparative example 2 is configured with 8 taps. The total number of vessels can be reduced from 32 to 11.

<When Comparative Example 2 adopts a 9-tap configuration>
In the A/D conversion processing device 2 (FIG. 4) having four input systems IN1 to IN4, each of the filters 16-1 to 16-4 follows the comparative example 2 (FIG. 2) and taps TA1 to TA9. , the total number of multipliers of the four filters 16-1 to 16-4 is "9×4=36". Here, the coefficient of taps TA1 and TA9 is a, the coefficient of taps TA2 and TA8 is b, the coefficient of taps TA3 and TA7 is c, the coefficient of taps TA4 and TA6 is d, and the coefficient of tap TA5 is e.

On the other hand, a filter having the same function as the 9-tap filter according to Comparative Example 2 is configured according to FIGS. When generating post-interpolation data from data, each of post-interpolation data OUT1_D1, OUT2_D1, OUT3_D1, and OUT4_D1 is represented by equations (134) to (137). Therefore, the total number of multipliers of the four filters 16-1 to 16-4 is "3+3+3+3=12".
OUT1_D1 = IN1_D1×a + IN1_D2×(b+c+d+e) + IN1_D3×(a+b+c+d) …(134)
OUT2_D1 = IN2_D1×(a+b) + IN2_D2×(c+2d+e) + IN2_D3×(a+b+c) …(135)
OUT3_D1 = IN3_D1×(a+b+c) + IN3_D2×(c+2d+e) + IN3_D3×(a+b) …(136)
OUT4_D1 = IN4_D1×(a+b+c+d) + IN4_D2×(b+c+d+e) + IN4_D3×a …(137)

17, 10, 11, and 18, and as shown in FIG. When generating post-interpolation data, each of post-interpolation data OUT1_D1, OUT2_D1, OUT3_D1, and OUT4_D1 is represented by equations (138) to (141). Therefore, the total number of multipliers of the four filters 16-1 to 16-4 is "3+3+3+3=12".
OUT1_D1 = IN1_D2×(a+b+c+d) + IN1_D3×(b+c+d+e) + IN1_D4×a …(138)
OUT2_D1 = IN2_D1×a + IN2_D2×(b+c+d+e) + IN2_D3×(a+b+c+d) …(139)
OUT3_D1 = IN3_D1×(a+b) + IN3_D2×(c+2d+e) + IN3_D3×(a+b+c) …(140)
OUT4_D1 = IN4_D1×(a+b+c) + IN4_D2×(c+2d+e) + IN4_D3×(a+b) …(141)

17, 10, 11, and 18, and, as shown in FIG. When generating post-interpolation data, each of post-interpolation data OUT1_D1, OUT2_D1, OUT3_D1, and OUT4_D1 is represented by equations (142) to (145). Therefore, the total number of multipliers of the four filters 16-1 to 16-4 is "3+3+3+3=12".
OUT1_D1 = IN1_D2×(a+b+c) + IN1_D3×(c+2d+e) + IN1_D4×(a+b) …(142)
OUT2_D1 = IN2_D2×(a+b+c+d) + IN2_D3×(b+c+d+e) + IN2_D4×a …(143)
OUT3_D1 = IN3_D1×a + IN3_D2×(b+c+d+e) + IN3_D3×(a+b+c+d) …(144)
OUT4_D1 = IN4_D1×(a+b) + IN4_D2×(c+2d+e) + IN4_D3×(a+b+c) …(145)

17, 10, 11, and 18, and as shown in FIG. When generating post-interpolation data, each of post-interpolation data OUT1_D1, OUT2_D1, OUT3_D1, and OUT4_D1 is represented by equations (146) to (149). Therefore, the total number of multipliers of the four filters 16-1 to 16-4 is "3+3+3+3=12".
OUT1_D1 = IN1_D2×(a+b) + IN1_D3×(c+2d+e) + IN1_D4×(a+b+c) …(146)
OUT2_D1 = IN2_D2×(a+b+c) + IN2_D3×(c+2d+e) + IN2_D4×(a+b) …(147)
OUT3_D1 = IN3_D2×(a+b+c+d) + IN3_D3×(b+c+d+e) + IN3_D4×a …(148)
OUT4_D1 = IN4_D1×a + IN4_D2×(b+c+d+e) + IN4_D3×(a+b+c+d) …(149)

That is, according to the second embodiment, in any case of FIGS. 23A to 23D, the multiplication of the four filters 16-1 to 16-4 is greater than the case where the filter of the comparative example 2 is configured with 9 taps. The total number of vessels can be reduced from 36 to 12.

As described above, in the second embodiment, the total number of multipliers included in the four filters 16-1 to 16-4 is reduced from 20 to 8, compared to the case where the filter of the comparative example 2 is configured with 5 taps. could be reduced to one. Moreover, in the second embodiment, the total number of multipliers included in the four filters 16-1 to 16-4 is reduced from 24 to 9 compared to the case where the filter of the comparative example 2 is configured with 6 taps. We were able to. Further, in the second embodiment, the total number of multipliers included in the four filters 16-1 to 16-4 is reduced from 28 to 10 compared to the filter of the comparative example 2 having 7 taps. We were able to. Further, in the second embodiment, the total number of multipliers included in the four filters 16-1 to 16-4 is reduced from 32 to 11 compared to the case where the filter of the comparative example 2 is configured with 8 taps. We were able to. Further, in the second embodiment, the total number of multipliers included in the four filters 16-1 to 16-4 is reduced from 36 to 12 compared to the case where the filter of the comparative example 2 is composed of 9 taps. We were able to. Therefore, the number of filters that the A/D conversion processing device 2 of the second embodiment has (that is, the number of input systems that the A/D conversion processing device 2 of the second embodiment has) is "α", and A When the number of taps in each filter of the /D conversion processing device 2 is "n", the total number of multipliers of the four filters 16-1 to 16-4 of the second embodiment is "α+n-1 ” can be expressed as pcs.

Also, in the above description, the case where the A/D conversion processing device 2 in Comparative Example 2 adopts the configuration of 5 taps, 6 taps, 7 taps, 8 taps, or 9 taps has been described as an example. The number of taps adopted by the A/D conversion processing device 2 in Comparative Example 2 is determined based on the accuracy required for interpolation processing by filtering in each of the filters 16-1 to 16-4 in Comparative Example 2. FIG.

[Example 3]
<Configuration of filter>
In the second embodiment, the filters 17-1 to 17-5 (FIG. 6) adopt configurations shown in FIGS. 24 to 28 instead of the configuration shown in FIG. 24 to 28 are diagrams showing configuration examples of filters according to the third embodiment. 24 corresponds to the filter 17-1 shown in FIG. 6, the filter 17-2 shown in FIG. 25 corresponds to the filter 17-2 shown in FIG. 6, and the filter 17-3 shown in FIG. corresponds to the filter 17-3 shown in FIG. 27 corresponds to the filter 17-4 shown in FIG. 6, and the filter 17-5 shown in FIG. 28 corresponds to the filter 17-5 shown in FIG.

That is, in each of Equations (15) and (20) in Comparative Example 3, multiplication is performed three times in generating post-interpolation data. Further, in each of Equations (16) and (21) in Comparative Example 3, multiplication is performed twice in generating post-interpolation data. Further, in each of Equations (17) and (22) in Comparative Example 3, multiplication is performed twice in generating post-interpolation data. Further, in each of formulas (18) and (23) in Comparative Example 3, multiplication is performed twice in generating post-interpolation data. Further, in each of Equations (19) and (24) in Comparative Example 3, multiplication is performed twice in generating post-interpolation data.

Therefore, the configuration of the filter 17-1 that generates post-interpolation data according to equations (15) and (20) can be replaced by the configuration shown in FIG. 24 instead of the configuration shown in FIG. In FIG. 24, the filter 17-1 has delayers 31-7, 31-8, multipliers 32-12, 32-13, 32-14, and an adder 33-8. Each of multipliers 32-12, 32-13 and 32-14 is connected to each of taps TA1, TA2 and TA3.

Of the pre-interpolation data output from the distribution unit 13C, the pre-interpolation data generated from the analog signal of the input system IN1 is input to the delay element 31-8. The pre-interpolation data is delayed by one unit time in each of the delay elements 31-8 and 31-7, and then input to each of the multipliers 32-13 and 32-12.

Therefore, the multiplier 32-14 multiplies the pre-interpolation data with a delay of 0 (zero) by the coefficient a, and outputs the pre-interpolation data after the coefficient multiplication to the adder 33-8. The multiplier 32-13 multiplies the pre-interpolation data delayed by one unit time by the coefficient 2b+2c+d, and outputs the pre-interpolation data after the coefficient multiplication to the adder 33-8. The multiplier 32-12 multiplies the pre-interpolation data delayed by two unit times by the coefficient a, and outputs the pre-interpolation data after the coefficient multiplication to the adder 33-8.

The adder 33-8 obtains post-interpolation data by adding all pre-interpolation data after coefficient multiplication output from the multipliers 32-12 to 32-14.

Therefore, similarly to Comparative Example 3, the interpolated data OUT1_D1 obtained by the adder 33-8 is expressed by Equation (15), and the interpolated data OUT1_D2 obtained by the adder 33-8 is expressed by Equation (20). be.

Further, the configuration of the filter 17-2 that generates post-interpolation data according to equations (16) and (21) can be replaced with the configuration shown in FIG. 25 instead of the configuration shown in FIG. In FIG. 25, the filter 17-2 has a delay device 31-9, multipliers 32-15 and 32-16, and an adder 33-9. Each of multipliers 32-15 and 32-16 is connected to each of taps TA1 and TA2.

Of the pre-interpolation data output from the distribution unit 13C, the pre-interpolation data generated from the analog signal of the input system IN2 is input to the delay element 31-9. The pre-interpolation data is delayed by one unit time in the delay element 31-9 and then input to the multiplier 32-15.

Therefore, the multiplier 32-16 multiplies the pre-interpolation data with a delay of 0 (zero) by the coefficient a+b+2c+d, and outputs the pre-interpolation data after the coefficient multiplication to the adder 33-9. The multiplier 32-15 multiplies the pre-interpolation data delayed by one unit time by the coefficient a+b, and outputs the pre-interpolation data after the coefficient multiplication to the adder 33-9.

The adder 33-9 obtains post-interpolation data by adding all pre-interpolation data after coefficient multiplication output from the multipliers 32-15 and 32-16.

Therefore, similarly to Comparative Example 3, the interpolated data OUT2_D1 obtained by the adder 33-9 is expressed by Equation (16), and the interpolated data OUT2_D2 obtained by the adder 33-9 is expressed by Equation (21). be.

Further, the configuration of the filter 17-3 that generates post-interpolation data according to equations (17) and (22) can be replaced with the configuration shown in FIG. 26 instead of the configuration shown in FIG. In FIG. 26, the filter 17-3 has a delay device 31-10, multipliers 32-17 and 32-18, and an adder 33-10. Each of multipliers 32-17 and 32-18 is connected to each of taps TA1 and TA2.

Of the pre-interpolation data output from the distribution unit 13C, the pre-interpolation data generated from the analog signal of the input system IN3 is input to the delay element 31-10. The pre-interpolation data is delayed by one unit time in the delay element 31-10 and then input to the multiplier 32-17.

Therefore, the multiplier 32-18 multiplies the pre-interpolation data with a delay of 0 (zero) by the coefficient a+b+c+d, and outputs the pre-interpolation data after the coefficient multiplication to the adder 33-10. The multiplier 32-17 multiplies the pre-interpolation data delayed by one unit time by the coefficient a+b+c, and outputs the pre-interpolation data after the coefficient multiplication to the adder 33-10.

The adder 33-10 obtains post-interpolation data by adding all pre-interpolation data after coefficient multiplication output from the multipliers 32-17 and 32-18.

Therefore, similarly to Comparative Example 3, the interpolated data OUT3_D1 obtained by the adder 33-10 is expressed by Equation (17), and the interpolated data OUT3_D2 obtained by the adder 33-10 is expressed by Equation (22). be.

Also, the configuration of the filter 17-4 that generates post-interpolation data according to equations (18) and (23) can be replaced with the configuration shown in FIG. 27 instead of the configuration shown in FIG. In FIG. 27, the filter 17-4 has a delay device 31-11, multipliers 32-19 and 32-20, and an adder 33-6. Each of multipliers 32-19 and 32-20 is connected to each of taps TA1 and TA2.

Of the pre-interpolation data output from the distribution unit 13C, the pre-interpolation data generated from the analog signal of the input system IN4 is input to the delay element 31-11. The pre-interpolation data is delayed by one unit time in the delay element 31-11 and then input to the multiplier 32-19.

Therefore, the multiplier 32-20 multiplies the pre-interpolation data with a delay of 0 (zero) by the coefficient a+b+c, and outputs the pre-interpolation data after the coefficient multiplication to the adder 33-6. The multiplier 32-19 multiplies the pre-interpolation data delayed by one unit time by the coefficient a+b+c+d, and outputs the pre-interpolation data after the coefficient multiplication to the adder 33-6.

The adder 33-6 obtains post-interpolation data by adding all the pre-interpolation data after coefficient multiplication output from the multipliers 32-19 and 32-20.

Therefore, similarly to Comparative Example 3, the interpolated data OUT4_D1 obtained by the adder 33-6 is expressed by Equation (18), and the interpolated data OUT4_D2 obtained by the adder 33-6 is expressed by Equation (23). be.

Further, the configuration of the filter 17-5 that generates post-interpolation data according to equations (19) and (24) can be replaced with the configuration shown in FIG. 28 instead of the configuration shown in FIG. In FIG. 28, the filter 17-5 has a delay device 31-12, multipliers 32-21 and 32-22, and an adder 33-7. Each of multipliers 32-21 and 32-22 is connected to each of taps TA1 and TA2.

Of the pre-interpolation data output from the distribution unit 13C, the pre-interpolation data generated from the analog signal of the input system IN5 is input to the delay element 31-12. The pre-interpolation data is delayed by one unit time in the delay element 31-12 and then input to the multiplier 32-21.

Therefore, the multiplier 32-22 multiplies the pre-interpolation data with a delay of 0 (zero) by the coefficient a+b, and outputs the pre-interpolation data after the coefficient multiplication to the adder 33-7. The multiplier 32-21 multiplies the pre-interpolation data delayed by one unit time by the coefficient a+b+2c+d, and outputs the pre-interpolation data after the coefficient multiplication to the adder 33-7.

The adder 33-7 obtains post-interpolation data by adding all pre-interpolation data after coefficient multiplication output from the multipliers 32-21 and 32-22.

Therefore, similarly to Comparative Example 3, the interpolated data OUT5_D1 obtained by the adder 33-7 is expressed by Equation (19), and the interpolated data OUT5_D2 obtained by the adder 33-7 is expressed by Equation (24). be.

Here, according to Comparative Example 3, since each of the filters 17-1 to 17-5 adopts the configuration shown in FIG. , "5×5=25". On the other hand, according to the third embodiment, the filter 17-1 adopts the configuration shown in FIG. 24, the filter 17-2 adopts the configuration shown in FIG. 25, the filter 17-3 adopts the configuration shown in FIG. The filter 17-4 has the configuration shown in FIG. 27, and the filter 17-5 has the configuration shown in FIG. Therefore, in the third embodiment, the total number of multipliers of the five filters 17-1 to 17-5 is "3+2+2+2+2=11". Therefore, each of the filters 17-1 to 17-5 that generate the interpolated data OUT1_D1, OUT2_D1, OUT3_D1, OUT4_D1, OUT5_D1, OUT1_D2, OUT2_D2, OUT3_D2, OUT4_D2, and OUT5_D2 according to equations (15) to (24) is shown in FIG. By adopting the configuration (embodiment 3) shown in FIGS. 24 to 28 instead of the configuration shown (comparative example 3), the total number of multipliers possessed by the five filters 17-1 to 17-5 can be reduced from 25. It can be reduced to 11. Therefore, according to the third embodiment, the circuit scale of the A/D conversion processing device 3 can be reduced.

<Operation of A/D conversion processing device>
29A to 33E are diagrams for explaining an operation example of the A/D conversion processing device of the third embodiment.

<When Comparative Example 3 adopts a 6-tap configuration>
In the A/D conversion processing device 3 (FIG. 6) having five input systems IN1 to IN5, each of the filters 17-1 to 17-5 follows the comparative example 3 (FIG. 7) and taps TA1 to TA6 , the total number of multipliers of the five filters 17-1 to 17-5 is "6×5=30". Here, the coefficient of taps TA1 and TA6 is a, the coefficient of taps TA2 and TA5 is b, and the coefficient of taps TA3 and TA4 is c.

On the other hand, a filter having the same function as the 6-tap filter according to Comparative Example 3 is configured according to FIGS. When generating data, each of the interpolated data OUT1_D1, OUT2_D1, OUT3_D1, OUT4_D1, and OUT5_D1 is represented by equations (150) to (154). Therefore, the total number of multipliers possessed by the five filters 17-1 to 17-5 is "2+2+2+2+2=10".
OUT1_D1 = IN1_D1×a + IN1_D2×(a+2b+2c) …(150)
OUT2_D1 = IN2_D1×(a+b) + IN2_D2×(a+b+2c) …(151)
OUT3_D1 = IN3_D1×(a+b+c) + IN3_D2×(a+b+c) …(152)
OUT4_D1 = IN4_D1×(a+b+2c) + IN4_D2×(a+b) …(153)
OUT5_D1 = IN5_D1×(a+2b+2c) + IN5_D2×a …(154)

In addition, a filter having the same function as the 6-tap filter according to Comparative Example 3 is configured according to FIGS. 24 to 28, and as shown in FIG. When generated, each of the interpolated data OUT1_D1, OUT2_D1, OUT3_D1, OUT4_D1, and OUT5_D1 is represented by equations (155) to (159). Therefore, the total number of multipliers possessed by the five filters 17-1 to 17-5 is "2+2+2+2+2=10".
OUT1_D1 = IN1_D2×(a+2b+2c) + IN1_D3×a …(155)
OUT2_D1 = IN2_D1×a + IN2_D2×(a+2b+2c) …(156)
OUT3_D1 = IN3_D1×(a+b) + IN3_D2×(a+b+2c) …(157)
OUT4_D1 = IN4_D1×(a+b+c) + IN4_D2×(a+b+c) …(158)
OUT5_D1 = IN5_D1×(a+b+2c) + IN5_D2×(a+b) …(159)

Further, a filter having the same function as the 6-tap filter according to Comparative Example 3 is configured according to FIGS. 24 to 28, and as shown in FIG. When generated, each of the interpolated data OUT1_D1, OUT2_D1, OUT3_D1, OUT4_D1, and OUT5_D1 is represented by equations (160) to (164). Therefore, the total number of multipliers possessed by the five filters 17-1 to 17-5 is "2+2+2+2+2=10".
OUT1_D1 = IN1_D2×(a+b+2c) + IN1_D3×(a+b) …(160)
OUT2_D1 = IN2_D2×(a+2b+2c) + IN2_D3×a …(161)
OUT3_D1 = IN3_D1×a + IN3_D2×(a+2b+2c) …(162)
OUT4_D1 = IN4_D1×(a+b) + IN4_D2×(a+b+2c) …(163)
OUT5_D1 = IN5_D1×(a+b+c) + IN5_D2×(a+b+c) …(164)

Further, a filter having the same function as the 6-tap filter according to Comparative Example 3 is configured according to FIGS. 24 to 28, and as shown in FIG. When generated, each of the interpolated data OUT1_D1, OUT2_D1, OUT3_D1, OUT4_D1, and OUT5_D1 is represented by equations (165) to (169). Therefore, the total number of multipliers possessed by the five filters 17-1 to 17-5 is "2+2+2+2+2=10".
OUT1_D1 = IN1_D2×(a+b+c) + IN1_D3×(a+b+c) …(165)
OUT2_D1 = IN2_D2×(a+b+2c) + IN2_D3×(a+b) …(166)
OUT3_D1 = IN3_D2×(a+2b+2c) + IN3_D3×a …(167)
OUT4_D1 = IN4_D1×a + IN4_D2×(a+2b+2c) …(168)
OUT5_D1 = IN5_D1×(a+b) + IN5_D2×(a+b+2c) …(169)

In addition, a filter having the same function as the 6-tap filter according to Comparative Example 3 is configured according to FIGS. 24 to 28, and as shown in FIG. When generated, each of the interpolated data OUT1_D1, OUT2_D1, OUT3_D1, OUT4_D1, and OUT5_D1 is represented by equations (170) to (174). Therefore, the total number of multipliers possessed by the five filters 17-1 to 17-5 is "2+2+2+2+2=10".
OUT1_D1 = IN1_D2×(a+b) + IN1_D3×(a+b+2c) …(170)
OUT2_D1 = IN2_D2×(a+b+c) + IN2_D3×(a+b+c) …(171)
OUT3_D1 = IN3_D2×(a+b+2c) + IN3_D3×(a+b) …(172)
OUT4_D1 = IN4_D2×(a+2b+2c) + IN4_D3×a …(173)
OUT5_D1 = IN5_D1×a + IN5_D2×(a+2b+2c) …(174)

That is, according to the third embodiment, in any case of FIGS. 29A to 29E, the multiplication of the five filters 17-1 to 17-5 is greater than the case where the filter of the comparative example 3 is configured with 6 taps. The total number of vessels can be reduced from 30 to 10.

<When Comparative Example 3 adopts a 7-tap configuration>
In the A/D conversion processing device 3 (FIG. 6) having five input systems IN1 to IN5, each of the filters 17-1 to 17-5 follows the comparative example 3 (FIG. 7) and taps TA1 to TA7 , the total number of multipliers of the five filters 17-1 to 17-5 is "7×5=35". Here, the coefficient of taps TA1 and TA7 is a, the coefficient of taps TA2 and TA6 is b, the coefficient of taps TA3 and TA5 is c, and the coefficient of tap TA4 is d.

On the other hand, a filter having the same function as the 7-tap filter according to Comparative Example 3 is configured according to FIGS. When generating data, each of the interpolated data OUT1_D1, OUT2_D1, OUT3_D1, OUT4_D1, and OUT5_D1 is represented by equations (175) to (179). Therefore, the total number of multipliers possessed by the five filters 17-1 to 17-5 is "3+2+2+2+2=11".
OUT1_D1 = IN1_D1×a + IN1_D2×(2b+2c+d) + IN1_D3×a …(175)
OUT2_D1 = IN2_D1×(a+b) + IN2_D2×(a+b+2c+d) …(176)
OUT3_D1 = IN3_D1×(a+b+c) + IN3_D2×(a+b+c+d) …(177)
OUT4_D1 = IN4_D1×(a+b+c+d) + IN4_D2×(a+b+c) …(178)
OUT5_D1 = IN5_D1×(a+b+2c+d) + IN5_D2×(a+b) …(179)

In addition, a filter having the same function as the 7-tap filter according to Comparative Example 3 is configured according to FIGS. 24 to 28, and as shown in FIG. When generated, each of the interpolated data OUT1_D1, OUT2_D1, OUT3_D1, OUT4_D1, and OUT5_D1 is represented by equations (180) to (184). Therefore, the total number of multipliers of the five filters 17-1 to 17-5 is "2+3+2+2+2=11".
OUT1_D1 = IN1_D2×(a+b+2c+d) + IN1_D3×(a+b) …(180)
OUT2_D1 = IN2_D1×a + IN2_D2×(2b+2c+d) + IN2_D3×a …(181)
OUT3_D1 = IN3_D1×(a+b) + IN3_D2×(a+b+2c+d) …(182)
OUT4_D1 = IN4_D1×(a+b+c) + IN4_D2×(a+b+c+d) …(183)
OUT5_D1 = IN5_D1×(a+b+c+d) + IN5_D2×(a+b+c) …(184)

In addition, a filter having the same function as the 7-tap filter according to Comparative Example 3 is configured according to FIGS. 24 to 28, and as shown in FIG. When generated, each of the interpolated data OUT1_D1, OUT2_D1, OUT3_D1, OUT4_D1, and OUT5_D1 is represented by equations (185) to (189). Therefore, the total number of multipliers of the five filters 17-1 to 17-5 is "2+2+3+2+2=11".
OUT1_D1 = IN1_D2×(a+b+c+d) + IN1_D3×(a+b+c) …(185)
OUT2_D1 = IN2_D2×(a+b+2c+d) + IN2_D3×(a+b) …(186)
OUT3_D1 = IN3_D1×a + IN3_D2×(2b+2c+d) + IN3_D3×a …(187)
OUT4_D1 = IN4_D1×(a+b) + IN4_D2×(a+b+2c+d) …(188)
OUT5_D1 = IN5_D1×(a+b+c) + IN5_D2×(a+b+c+d) …(189)

In addition, a filter having the same function as the 7-tap filter according to Comparative Example 3 is configured according to FIGS. 24 to 28, and as shown in FIG. When generated, each of the interpolated data OUT1_D1, OUT2_D1, OUT3_D1, OUT4_D1, and OUT5_D1 is represented by equations (190) to (194). Therefore, the total number of multipliers of the five filters 17-1 to 17-5 is "2+2+2+3+2=11".
OUT1_D1 = IN1_D2×(a+b+c) + IN1_D3×(a+b+c+d) …(190)
OUT2_D1 = IN2_D2×(a+b+c+d) + IN2_D3×(a+b+c) …(191)
OUT3_D1 = IN3_D2×(a+b+2c+d) + IN3_D3×(a+b) …(192)
OUT4_D1 = IN4_D1×a + IN4_D2×(2b+2c+d) + IN4_D3×a …(193)
OUT5_D1 = IN5_D1×(a+b) + IN5_D2×(a+b+2c+d) …(194)

In addition, a filter having the same function as the 7-tap filter according to Comparative Example 3 is configured according to FIGS. 24 to 28, and as shown in FIG. When generated, each of the interpolated data OUT1_D1, OUT2_D1, OUT3_D1, OUT4_D1, and OUT5_D1 is represented by equations (195) to (199). Therefore, the total number of multipliers possessed by the five filters 17-1 to 17-5 is "2+2+2+2+3=11".
OUT1_D1 = IN1_D2×(a+b) + IN1_D3×(a+b+2c+d) …(195)
OUT2_D1 = IN2_D2×(a+b+c) + IN2_D3×(a+b+c+d) …(196)
OUT3_D1 = IN3_D2×(a+b+c+d) + IN3_D3×(a+b+c) …(197)
OUT4_D1 = IN4_D2×(a+b+2c+d) + IN4_D3×(a+b) …(198)
OUT5_D1 = IN5_D1×a + IN5_D2×(2b+2c+d) + IN5_D3×a …(199)

That is, according to the third embodiment, in any case of FIGS. 30A to 30E, the multiplication of the five filters 17-1 to 17-5 is greater than the case where the filter of the comparative example 3 is configured with 7 taps. The total number of vessels can be reduced from 35 to 11.

<When Comparative Example 3 Adopts an 8-Tap Configuration>
In the A/D conversion processing device 3 (FIG. 6) having five input systems IN1 to IN5, each of the filters 17-1 to 17-5 follows the comparative example 3 (FIG. 7) and taps TA1 to TA8 , the total number of multipliers of the five filters 17-1 to 17-5 is "8×5=40". Here, the coefficient of taps TA1 and TA8 is a, the coefficient of taps TA2 and TA7 is b, the coefficient of taps TA3 and TA6 is c, and the coefficient of taps TA4 and TA5 is d.

On the other hand, a filter having the same function as the 8-tap filter according to Comparative Example 3 is configured according to FIGS. When generating data, each of the interpolated data OUT1_D1, OUT2_D1, OUT3_D1, OUT4_D1, and OUT5_D1 is represented by equations (200) to (204). Therefore, the total number of multipliers possessed by the five filters 17-1 to 17-5 is "3+3+2+2+2=12".
OUT1_D1 = IN1_D1×a + IN1_D2×(b+2c+2d) + IN1_D3×(a+b) …(200)
OUT2_D1 = IN2_D1×(a+b) + IN2_D2×(b+2c+2d) + IN2_D3×a …(201)
OUT3_D1 = IN3_D1×(a+b+c) + IN3_D2×(a+b+c+2d) …(202)
OUT4_D1 = IN4_D1×(a+b+c+d) + IN4_D2×(a+b+c+d) …(203)
OUT5_D1 = IN5_D1×(a+b+c+2d) + IN5_D2×(a+b+c) …(204)

Further, a filter having the same function as the 8-tap filter according to Comparative Example 3 is configured according to FIGS. 24 to 28, and as shown in FIG. When generated, each of the interpolated data OUT1_D1, OUT2_D1, OUT3_D1, OUT4_D1, and OUT5_D1 is represented by equations (205) to (209). Therefore, the total number of multipliers possessed by the five filters 17-1 to 17-5 is "2+3+3+2+2=12".
OUT1_D1 = IN1_D2×(a+b+c+2d) + IN1_D3×(a+b+c) …(205)
OUT2_D1 = IN2_D1×a + IN2_D2×(b+2c+2d) + IN2_D3×(a+b) …(206)
OUT3_D1 = IN3_D1×(a+b) + IN3_D2×(b+2c+2d) + IN3_D3×a …(207)
OUT4_D1 = IN4_D1×(a+b+c) + IN4_D2×(a+b+c+2d) …(208)
OUT5_D1 = IN5_D1×(a+b+c+d) + IN5_D2×(a+b+c+d) …(209)

In addition, a filter having the same function as the 8-tap filter modeled after Comparative Example 3 is configured as shown in FIGS. 24 to 28, and as shown in FIG. When generated, each of the interpolated data OUT1_D1, OUT2_D1, OUT3_D1, OUT4_D1, and OUT5_D1 is represented by equations (210) to (214). Therefore, the total number of multipliers possessed by the five filters 17-1 to 17-5 is "2+2+3+3+2=12".
OUT1_D1 = IN1_D2×(a+b+c+d) + IN1_D3×(a+b+c+d) …(210)
OUT2_D1 = IN2_D2×(a+b+c+2d) + IN2_D3×(a+b+c) …(211)
OUT3_D1 = IN3_D1×a + IN3_D2×(b+2c+2d) + IN3_D3×(a+b) …(212)
OUT4_D1 = IN4_D1×(a+b) + IN4_D2×(b+2c+2d) + IN4_D3×a …(213)
OUT5_D1 = IN5_D1×(a+b+c) + IN5_D2×(a+b+c+2d) …(214)

In addition, a filter having the same function as the 8-tap filter according to Comparative Example 3 is configured according to FIGS. 24 to 28, and as shown in FIG. When generated, each of the interpolated data OUT1_D1, OUT2_D1, OUT3_D1, OUT4_D1, and OUT5_D1 is represented by equations (215) to (219). Therefore, the total number of multipliers possessed by the five filters 17-1 to 17-5 is "2+2+2+3+3=12".
OUT1_D1 = IN1_D2×(a+b+c) + IN1_D3×(a+b+c+2d) …(215)
OUT2_D1 = IN2_D2×(a+b+c+d) + IN2_D3×(a+b+c+d) …(216)
OUT3_D1 = IN3_D2×(a+b+c+2d) + IN3_D3×(a+b+c) …(217)
OUT4_D1 = IN4_D1×a + IN4_D2×(b+2c+2d) + IN4_D3×(a+b) …(218)
OUT5_D1 = IN5_D1×(a+b) + IN5_D2×(b+2c+2d) + IN5_D3×a …(219)

In addition, a filter having the same function as the 8-tap filter according to Comparative Example 3 is configured according to FIGS. 24 to 28, and as shown in FIG. When generated, each of the interpolated data OUT1_D1, OUT2_D1, OUT3_D1, OUT4_D1, and OUT5_D1 is represented by equations (220) to (224). Therefore, the total number of multipliers possessed by the five filters 17-1 to 17-5 is "3+2+2+2+3=12".
OUT1_D1 = IN1_D2×(a+b) + IN1_D3×(b+2c+2d) + IN1_D4×a …(220)
OUT2_D1 = IN2_D2×(a+b+c) + IN2_D3×(a+b+c+2d) …(221)
OUT3_D1 = IN3_D2×(a+b+c+d) + IN3_D3×(a+b+c+d) …(222)
OUT4_D1 = IN4_D2×(a+b+c+2d) + IN4_D3×(a+b+c) …(223)
OUT5_D1 = IN5_D1×a + IN5_D2×(b+2c+2d) + IN5_D3×(a+b) …(224)

That is, according to the third embodiment, in any case of FIGS. 31A to 31E, the multiplication of the five filters 17-1 to 17-5 is greater than the case where the filter of the comparative example 3 is configured with 8 taps. The total number of vessels can be reduced from 40 to 12.

<When Comparative Example 3 adopts a 9-tap configuration>
In the A/D conversion processing device 3 (FIG. 6) having five input systems IN1 to IN5, each of the filters 17-1 to 17-5 follows the comparative example 3 (FIG. 7) and taps TA1 to TA9 , the total number of multipliers possessed by the five filters 17-1 to 17-5 is "9×5=45". Here, the coefficient of taps TA1 and TA9 is a, the coefficient of taps TA2 and TA8 is b, the coefficient of taps TA3 and TA7 is c, the coefficient of taps TA4 and TA6 is d, and the coefficient of tap TA5 is e.

On the other hand, a filter having the same function as the 9-tap filter according to Comparative Example 3 is configured according to FIGS. When generating data, each of the interpolated data OUT1_D1, OUT2_D1, OUT3_D1, OUT4_D1, and OUT5_D1 is represented by equations (225) to (229). Therefore, the total number of multipliers of the five filters 17-1 to 17-5 is "3+3+3+2+2=13".
OUT1_D1 = IN1_D1×a + IN1_D2×(b+c+2d+e) + IN1_D3×(a+b+c) …(225)
OUT2_D1 = IN2_D1×(a+b) + IN2_D2×(2c+2d+e) + IN2_D3×(a+b) …(226)
OUT3_D1 = IN3_D1×(a+b+c) + IN3_D2×(b+c+2d+e) + IN3_D3×a …(227)
OUT4_D1 = IN4_D1×(a+b+c+d) + IN4_D2×(a+b+c+d+e) …(228)
OUT5_D1 = IN5_D1×(a+b+c+d+e) + IN5_D2×(a+b+c+d) …(229)

Further, a filter having the same function as the 9-tap filter according to Comparative Example 3 is configured according to FIGS. 24 to 28, and as shown in FIG. When generated, each of the interpolated data OUT1_D1, OUT2_D1, OUT3_D1, OUT4_D1, and OUT5_D1 is represented by equations (230) to (234). Therefore, the total number of multipliers possessed by the five filters 17-1 to 17-5 is "2+3+3+3+2=13".
OUT1_D1 = IN1_D2×(a+b+c+d+e) + IN1_D3×(a+b+c+d) …(230)
OUT2_D1 = IN2_D1×a + IN2_D2×(b+c+2d+e) + IN2_D3×(a+b+c) …(231)
OUT3_D1 = IN3_D1×(a+b) + IN3_D2×(2c+2d+e) + IN3_D3×(a+b) …(232)
OUT4_D1 = IN4_D1×(a+b+c) + IN4_D2×(b+c+2d+e) + IN4_D3×a …(233)
OUT5_D1 = IN5_D1×(a+b+c+d) + IN5_D2×(a+b+c+d+e) …(234)

In addition, a filter having the same function as the 9-tap filter modeled after Comparative Example 3 is configured as shown in FIGS. 24 to 28, and as shown in FIG. When generated, each of the interpolated data OUT1_D1, OUT2_D1, OUT3_D1, OUT4_D1, and OUT5_D1 is represented by equations (235) to (239). Therefore, the total number of multipliers of the five filters 17-1 to 17-5 is "2+2+3+3+3=13".
OUT1_D1 = IN1_D2×(a+b+c+d) + IN1_D3×(a+b+c+d+e) …(235)
OUT2_D1 = IN2_D2×(a+b+c+d+e) + IN2_D3×(a+b+c+d) …(236)
OUT3_D1 = IN3_D1×a + IN3_D2×(b+c+2d+e) + IN3_D3×(a+b+c) …(237)
OUT4_D1 = IN4_D1×(a+b) + IN4_D2×(2c+2d+e) + IN4_D3×(a+b) …(238)
OUT5_D1 = IN5_D1×(a+b+c) + IN5_D2×(b+c+2d+e) + IN5_D3×a …(239)

In addition, a filter having the same function as the 9-tap filter modeled after Comparative Example 3 is configured as shown in FIGS. 24 to 28, and as shown in FIG. When generated, each of the interpolated data OUT1_D1, OUT2_D1, OUT3_D1, OUT4_D1, OUT5_D1 is represented by equations (240) to (244). Therefore, the total number of multipliers of the five filters 17-1 to 17-5 is "3+2+2+3+3=13".
OUT1_D1 = IN1_D2×(a+b+c) + IN1_D3×(b+c+2d+e) + IN1_D4×a …(240)
OUT2_D1 = IN2_D2×(a+b+c+d) + IN2_D3×(a+b+c+d+e) …(241)
OUT3_D1 = IN3_D2×(a+b+c+d+e) + IN3_D3×(a+b+c+d) …(242)
OUT4_D1 = IN4_D1×a + IN4_D2×(b+c+2d+e) + IN4_D3×(a+b+c) …(243)
OUT5_D1 = IN5_D1×(a+b) + IN5_D2×(2c+2d+e) + IN5_D3×(a+b) …(244)

In addition, a filter having the same function as the 9-tap filter according to Comparative Example 3 is configured according to FIGS. 24 to 28, and as shown in FIG. When generated, each of the interpolated data OUT1_D1, OUT2_D1, OUT3_D1, OUT4_D1, and OUT5_D1 is represented by equations (245) to (249). Therefore, the total number of multipliers possessed by the five filters 17-1 to 17-5 is "3+3+2+2+3=13".
OUT1_D1 = IN1_D2×(a+b) + IN1_D3×(2c+2d+e) + IN1_D4×(a+b) …(245)
OUT2_D1 = IN2_D2×(a+b+c) + IN2_D3×(b+c+2d+e) + IN2_D4×a …(246)
OUT3_D1 = IN3_D2×(a+b+c+d) + IN3_D3×(a+b+c+d+e) …(247)
OUT4_D1 = IN4_D2×(a+b+c+d+e) + IN4_D3×(a+b+c+d) …(248)
OUT5_D1 = IN5_D1×a + IN5_D2×(b+c+2d+e) + IN5_D3×(a+b+c) …(249)

That is, according to the third embodiment, in any case of FIGS. 32A to 32E, the multiplication of the five filters 17-1 to 17-5 is greater than the case where the filter of the comparative example 3 is configured with 9 taps. The total number of vessels can be reduced from 45 to 13.

<When Comparative Example 3 Adopts a 10-Tap Configuration>
In the A/D conversion processing device 3 (FIG. 6) having five input systems IN1 to IN5, each of the filters 17-1 to 17-5 follows the comparative example 3 (FIG. 7) and taps TA1 to TA10. , the total number of multipliers of the five filters 17-1 to 17-5 is "10×5=50". Here, the coefficient of taps TA1 and TA10 is a, the coefficient of taps TA2 and TA9 is b, the coefficient of taps TA3 and TA8 is c, the coefficient of taps TA4 and TA7 is d, and the coefficient of taps TA5 and TA6 is e.

On the other hand, a filter having the same function as the 10-tap filter according to Comparative Example 3 is configured according to FIGS. When generating data, each of the interpolated data OUT1_D1, OUT2_D1, OUT3_D1, OUT4_D1, and OUT5_D1 is represented by equations (250) to (254). Therefore, the total number of multipliers possessed by the five filters 17-1 to 17-5 is "3+3+3+3+2=14".
OUT1_D1 = IN1_D1×a + IN1_D2×(b+c+d+2e) + IN1_D3×(a+b+c+d) …(250)
OUT2_D1 = IN2_D1×(a+b) + IN2_D2×(c+2d+2e) + IN2_D3×(a+b+c) …(251)
OUT3_D1 = IN3_D1×(a+b+c) + IN3_D2×(c+2d+2e) + IN3_D3×(a+b) …(252)
OUT4_D1 = IN4_D1×(a+b+c+d) + IN4_D2×(b+c+d+2e) + IN4_D3×a …(253)
OUT5_D1 = IN5_D1×(a+b+c+d+e) + IN5_D2×(a+b+c+d+e) …(254)

Further, a filter having the same function as the 10-tap filter modeled after Comparative Example 3 is configured as shown in FIGS. 24 to 28, and as shown in FIG. When generated, each of the interpolated data OUT1_D1, OUT2_D1, OUT3_D1, OUT4_D1, and OUT5_D1 is represented by equations (255) to (259). Therefore, the total number of multipliers possessed by the five filters 17-1 to 17-5 is "2+3+3+3+3=14".
OUT1_D1 = IN1_D2×(a+b+c+d+e) + IN1_D3×(a+b+c+d+e) …(255)
OUT2_D1 = IN2_D1×a + IN2_D2×(b+c+d+2e) + IN2_D3×(a+b+c+d) …(256)
OUT3_D1 = IN3_D1×(a+b) + IN3_D2×(c+2d+2e) + IN3_D3×(a+b+c) …(257)
OUT4_D1 = IN4_D1×(a+b+c) + IN4_D2×(c+2d+2e) + IN4_D3×(a+b) …(258)
OUT5_D1 = IN5_D1×(a+b+c+d) + IN5_D2×(b+c+d+2e) + IN5_D3×a …(259)

Further, a filter having the same function as the 10-tap filter modeled after Comparative Example 3 is configured as shown in FIGS. 24 to 28, and as shown in FIG. When generated, each of the interpolated data OUT1_D1, OUT2_D1, OUT3_D1, OUT4_D1, OUT5_D1 is represented by equations (260) to (264). Therefore, the total number of multipliers possessed by the five filters 17-1 to 17-5 is "3+2+3+3+3=14".
OUT1_D1 = IN1_D2×(a+b+c+d) + IN1_D3×(b+c+d+2e) + IN1_D4×a …(260)
OUT2_D1 = IN2_D2×(a+b+c+d+e) + IN2_D3×(a+b+c+d+e) …(261)
OUT3_D1 = IN3_D1×a + IN3_D2×(b+c+d+2e) + IN3_D3×(a+b+c+d) …(262)
OUT4_D1 = IN4_D1×(a+b) + IN4_D2×(c+2d+2e) + IN4_D3×(a+b+c) …(263)
OUT5_D1 = IN5_D1×(a+b+c) + IN5_D2×(c+2d+2e) + IN5_D3×(a+b) …(264)

In addition, a filter having the same function as the 10-tap filter according to Comparative Example 3 is configured according to FIGS. 24 to 28, and as shown in FIG. When generated, each of the interpolated data OUT1_D1, OUT2_D1, OUT3_D1, OUT4_D1, and OUT5_D1 is represented by equations (265) to (269). Therefore, the total number of multipliers possessed by the five filters 17-1 to 17-5 is "3+3+2+3+3=14".
OUT1_D1 = IN1_D2×(a+b+c) + IN1_D3×(c+2d+2e) + IN1_D4×(a+b) …(265)
OUT2_D1 = IN2_D2×(a+b+c+d) + IN2_D3×(b+c+d+2e) + IN2_D4×a …(266)
OUT3_D1 = IN3_D2×(a+b+c+d+e) + IN3_D3×(a+b+c+d+e) …(267)
OUT4_D1 = IN4_D1×a + IN4_D2×(b+c+d+2e) + IN4_D3×(a+b+c+d) …(268)
OUT5_D1 = IN5_D1×(a+b) + IN5_D2×(c+2d+2e) + IN5_D3×(a+b+c) …(269)

In addition, a filter having the same function as the 10-tap filter according to Comparative Example 3 is configured according to FIGS. 24 to 28, and as shown in FIG. When generated, each of the interpolated data OUT1_D1, OUT2_D1, OUT3_D1, OUT4_D1, OUT5_D1 is represented by equations (270) to (274). Therefore, the total number of multipliers of the five filters 17-1 to 17-5 is "3+3+3+2+3=14".
OUT1_D1 = IN1_D2×(a+b) + IN1_D3×(c+2d+2e) + IN1_D4×(a+b+c) …(270)
OUT2_D1 = IN2_D2×(a+b+c) + IN2_D3×(c+2d+2e) + IN2_D4×(a+b) …(271)
OUT3_D1 = IN3_D2×(a+b+c+d) + IN3_D3×(b+c+d+2e) + IN3_D4×a …(272)
OUT4_D1 = IN4_D2×(a+b+c+d+e) + IN4_D3×(a+b+c+d+e) …(273)
OUT5_D1 = IN5_D1×a + IN5_D2×(b+c+d+2e) + IN5_D3×(a+b+c+d) …(274)

That is, according to Example 3, in any case of FIGS. 33A to 33E, compared to the case where the filter of Comparative Example 3 is configured with 10 taps, the multiplication of the five filters 17-1 to 17-5 has The total number of vessels can be reduced from 50 to 14.

As described above, in the third embodiment, the total number of multipliers included in the five filters 17-1 to 17-5 is reduced from 30 to 10, compared to the case where the filter of the comparative example 3 is configured with 6 taps. could be reduced to one. Further, in the third embodiment, the total number of multipliers included in the five filters 17-1 to 17-5 is reduced from 35 to 11 compared to the case where the filter of the comparative example 3 is configured with 7 taps. We were able to. Further, in the third embodiment, the total number of multipliers included in the five filters 17-1 to 17-5 is reduced from 40 to 12 compared to the case where the filter of the comparative example 3 is composed of 8 taps. We were able to. Further, in the third embodiment, the total number of multipliers included in the five filters 17-1 to 17-5 is reduced from 45 to 13 compared to the case where the filter of the comparative example 3 is composed of 9 taps. We were able to. Further, in the third embodiment, the total number of multipliers included in the five filters 17-1 to 17-5 is reduced from 50 to 14 compared to the filter of the comparative example 3 having 10 taps. We were able to. Therefore, the number of filters that the A/D conversion processing device 3 of Example 3 has (that is, the number of input systems that the A/D conversion processing device 3 of Example 3 has) is “α”, and A of Comparative Example 3 When the number of taps in each filter of the /D conversion processing device 3 is "n", the total number of multipliers in the five filters 17-1 to 17-5 of the third embodiment is "α+n-1 ” can be expressed as pcs.

Further, in the above, the case where the A/D conversion processing device 3 in Comparative Example 3 adopts the configuration of 6 taps, 7 taps, 8 taps, 9 taps, or 10 taps has been described as an example. The number of taps adopted by the A/D conversion processing device 3 in Comparative Example 3 is determined based on the accuracy required for interpolation processing by filtering in each of the filters 17-1 to 17-5 in Comparative Example 3. FIG.

[Example 4]
34 to 37 are diagrams showing an example of correspondence between taps and coefficients according to the fourth embodiment.

As described above, the filters 15-1 to 15-3, 16-1 to 16-4, 17-1 to 17-5 in the A/D conversion processing devices 1, 2, and 3 in Comparative Examples 1, 2, and 3 The number of taps taken by each (hereinafter referred to as the “number of comparison taps”) is determined based on the accuracy required for interpolation processing by filtering in each filter in Comparative Examples 1, 2, and 3. Then, the correspondence between the number of comparison taps (4 to 11) and the coefficients (k1 to k11) multiplied by the pre-interpolation data at each of the taps TA1 to TA11 of the number of comparison taps (hereinafter referred to as "first correspondence") ) is shown in FIG.

When the first correspondence is as shown in FIG. 34, the number of comparison taps (4 to 10) and each tap in each of the filters 15-1 to 15-3 are FIG. 35 shows the correspondence between the coefficients (k1 to k10) multiplied by the pre-interpolation data in TA1 to TA4.

Further, when the first correspondence relationship is as shown in FIG. 34, as can be seen from the description of the second embodiment above, the number of comparison taps (4 to 10) and the filters 16-1 to 16-4 FIG. 36 shows the correspondence between the taps TA1-TA4 and the coefficients (k1-k10) multiplied by the pre-interpolation data.

Further, when the first correspondence relationship is as shown in FIG. 34, as can be seen from the description of the third embodiment above, the number of comparison taps (4 to 11) and the filters in the filters 17-1 to 17-5 FIG. 37 shows the correspondence between the taps TA1-TA4 and the coefficients (k1-k11) multiplied by the pre-interpolation data.

1, 2, 3 A/D conversion processing devices 11A, 11B, 11C Selection unit 12 A/D converters 13A, 13B, 13C Distribution unit 14 Control units 15-1 to 15-3, 16-1 to 16-4 , 17-1 to 17-5 filters

Claims (3)

a selection unit that sequentially selects any one input system from α (where α is an integer equal to or greater than 3) input systems;
an A/D converter that converts an analog signal input from the input system selected by the selection unit into a digital signal;
a distribution unit that distributes the digital signal output from the A/D converter to each of the α input systems;
Interpolation for aligning the sampling timing of the digital signals corresponding to each of the α input systems by interpolating the digital signals provided corresponding to each of the α input systems and distributed by the distribution unit. α FIR filters for processing,
In the FIR filter, the number of taps determined based on the accuracy required for the interpolation process is the number of comparison taps. The total number of multipliers of the FIR filter of is α + n-1,
When the coefficients by which the digital signal is multiplied at the taps corresponding to the number of comparison taps are as shown in Table (1), the first, second, and third filters, which are FIR filters when α=3, have The coefficients multiplied by the digital signal at each tap are as shown in Table (2).
A/D conversion processor.

a selection unit that sequentially selects any one input system from α (where α is an integer equal to or greater than 3) input systems;
an A/D converter that converts an analog signal input from the input system selected by the selection unit into a digital signal;
a distribution unit that distributes the digital signal output from the A/D converter to each of the α input systems;
Interpolation for aligning the sampling timing of the digital signals corresponding to each of the α input systems by interpolating the digital signals provided corresponding to each of the α input systems and distributed by the distribution unit. α FIR filters for processing,
In the FIR filter, the number of taps determined based on the accuracy required for the interpolation process is the number of comparison taps. The total number of multipliers of the FIR filter of is α + n-1,
When the coefficients by which the digital signal is multiplied at the taps corresponding to the number of comparison taps are as shown in Table (1), the first filter, second filter, third filter, and third filter, which are FIR filters when α=4, are shown in Table (1). The coefficients multiplied by the digital signal at each tap of the 4 filters are as shown in Table (3).
A/D conversion processor.

a selection unit that sequentially selects any one input system from α (where α is an integer equal to or greater than 3) input systems;
an A/D converter that converts an analog signal input from the input system selected by the selection unit into a digital signal;
a distribution unit that distributes the digital signal output from the A/D converter to each of the α input systems;
Interpolation for aligning the sampling timing of the digital signals corresponding to each of the α input systems by interpolating the digital signals provided corresponding to each of the α input systems and distributed by the distribution unit. α FIR filters for processing,
In the FIR filter, the number of taps determined based on the accuracy required for the interpolation process is the number of comparison taps. The total number of multipliers of the FIR filter of is α + n-1,
When the coefficients by which the digital signal is multiplied at the taps corresponding to the number of comparison taps are as shown in Table (1), the first, second, third, and third filters are FIR filters when α=5. The coefficients by which the digital signal is multiplied at each tap of the 4th filter and the 5th filter are as shown in Table (4).
A/D conversion processor.

Images