JP7496704B2 - Inverter device, control method, motor drive device, and refrigeration and air conditioning equipment - Google Patents

Description

This disclosure relates to inverter technology, and more specifically to an inverter device, a control method for the inverter device, a motor drive device including the inverter device, and a refrigeration and air conditioning device including the motor drive device.

Conventionally, inverter circuits have been used to drive AC motors such as compressor motors and fan motors in air conditioners. The semiconductor switching elements that make up the inverter circuit are turned on (conducting) and off (non-conducting) in accordance with a pulse width modulation (PWM) signal from a controller, resulting in switching loss.

Regarding the reduction of switching loss, for example, the technology disclosed in Japanese Patent No. 5439352 (Patent Document 1) is known. Patent Document 1 discloses a configuration in which, when the relationship between the state of the IGBT in the previously calculated control cycle and the state of the IGBT in the currently calculated next control cycle becomes discontinuous, additional control is performed to turn the IGBT on or off in the next control cycle based on these states.

Patent document 2 also discloses a configuration in which an output voltage error correction means corrects the error in the calculated line voltage pulse width with the pulse width of a phase voltage signal of a phase other than the phase in which the minimum pulse width has been limited, and corrects the error in the line voltage pulse width resulting from the correction of the pulse width of this phase voltage signal with the pulse width of a phase voltage signal of a phase other than the phase in which the minimum pulse width has been limited and the phase in which the pulse width has been corrected.

Japanese Patent No. 5439352 Patent No. 6311401

This disclosure has been made in consideration of the above-mentioned conventional technology, and aims to provide an inverter device that reduces switching losses and suppresses output voltage errors.

In order to solve the above problems, the present disclosure provides an inverter device including an inverter circuit having a switching element and a controller that controls the inverter circuit, and having the following characteristics. In this inverter device, the controller includes a determination unit that determines whether the width of a signal section that constitutes a pulse signal train that controls the switching element falls below a reference value. The inverter device further includes a correction unit that erases a signal section whose width is determined to be below the reference value, and performs correction on pulses in the pulse signal train adjacent to the signal section to be erased, according to the width of the signal section to be erased.

Other problems and solutions disclosed in this application will be made clear in the detailed description and drawings.

The above configuration makes it possible to reduce switching losses and suppress output voltage errors in an inverter device.

FIG. 1 is a diagram showing the overall configuration of an inverter device according to a first embodiment. FIG. 2 is a diagram showing an internal configuration of a controller in the inverter device according to the first embodiment. FIG. 3 is a diagram showing the internal configuration of a pulse width modulation controller in the controller according to the first embodiment. FIG. 4 is a time chart illustrating how the inverter device according to the first embodiment generates a pulse width modulation signal. FIG. 5 is a diagram for explaining pulses that are the subject of pulse erasure and pulse width correction in a modulated wave and a pulse width modulated signal generated by an inverter device. FIG. 6 is a waveform diagram (case 1) illustrating a pulse erasure and pulse width correction method in the inverter device according to the first embodiment. FIG. 7 is a waveform diagram (case 2) illustrating a pulse erasure and pulse width correction method in the inverter device according to the first embodiment. FIG. 8 is a waveform diagram (case 3) illustrating a pulse erasure and pulse width correction method in the inverter device according to the first embodiment. FIG. 9 is a waveform diagram (case 4) illustrating the pulse erasure and pulse width correction method in the inverter device according to the first embodiment. FIG. 10 is a flowchart showing a control method executed by the inverter device according to the first embodiment. FIG. 11 is a configuration diagram of a motor drive device according to the second embodiment. FIG. 12 is a diagram showing the internal configuration of a controller of a motor drive device according to the second embodiment. FIG. 13 is a configuration diagram of a refrigeration and air conditioning device according to the third embodiment.

The following describes an embodiment of the present invention with reference to the drawings, but the embodiment of the present invention is not limited to the specific embodiment described below. In the drawings, the same reference numerals indicate the same or equivalent parts.

Embodiments of the present invention are directed to an inverter device, a control method for the inverter device, a motor drive device including the inverter device, and a refrigeration and air conditioning device equipped with the motor drive device. The inverter device according to an embodiment of the present invention is characterized in that, in a pulse signal train that controls switching elements constituting an inverter circuit, a signal section (e.g., an on-pulse section or an off-pulse section) whose width is below a reference value is erased, and at least one pulse (e.g., a preceding or following on-pulse or a preceding or following off-pulse) adjacent to the erased signal section in the pulse signal train is corrected according to the width of the erased signal section. This makes it possible to reduce switching losses and suppress output voltage errors, preferably over a wide operating range.

Below, we will explain, with more specific embodiments, an inverter device capable of reducing switching losses and suppressing output voltage errors, a control method for the inverter device, a motor drive device including the inverter device, and a refrigeration and air conditioning device equipped with the motor drive device.

First Embodiment
An inverter device 100 and a control method thereof according to a first embodiment of the present invention will be described below with reference to Figures 1 to 10. The first embodiment shown in Figures 1 to 10 corresponds to a grid-connected inverter device for a photovoltaic power generation facility or a storage battery and a control method thereof.

Figure 1 shows the overall configuration of an inverter device 100 according to a first embodiment of the present invention. The inverter device 100 shown in Figure 1 is connected to an AC power source 1 on its AC side, and to a DC load or DC power source (hereinafter referred to as "DC load/DC power source 10") on its DC side.

The inverter device 100 includes a noise filter 2 connected in series to the AC power source 1, a reactor 3, and an inverter circuit 4 connected to a DC load/DC power source 10. The inverter device 100 further includes a capacitor 5 connected between the positive and negative poles of the DC side of the inverter circuit 4, a voltage detection circuit 6 that detects the AC voltage of the AC power source 1, a voltage detection circuit 7 that detects the DC voltage between the positive and negative poles, a controller 8 that controls the pulse width modulation (hereinafter, pulse width modulation may be referred to as PWM (Pulse Width Modulation)) of the inverter circuit 4, and a current detection circuit 9 that detects the AC current of the AC power source 1.

The operation modes of the inverter circuit 4 are described below. The operation modes of the inverter circuit 4 include a rectification mode (AC/DC conversion mode) and a regeneration mode (DC/AC conversion mode). The rectification mode is a mode in which AC power is received from the AC power source 1 and DC power is supplied to the DC load/DC power source 10. The regeneration mode is a mode in which DC power from the DC load/DC power source 10 is inversely converted and AC power is output to the AC power source 1 (AC load). Switching between these two operation modes is achieved by a control signal from the controller 8. Examples of DC power sources used for the DC load/DC power source 10 include solar power generation equipment and storage batteries.

The AC power supply 1 shown in FIG. 1 is a three-phase AC power supply, and the inverter circuit 4 corresponds to the three-phase AC power supply 1 and is configured as a three-phase bridge circuit with six semiconductor switching elements 11 and diodes 12 connected in anti-parallel to each semiconductor switching element 11. The diodes 12 connected in anti-parallel to each switching element 11 are diodes for commutation operation when each switching element 11 is off.

Capacitor 5 is an element for suppressing ripple voltage and surge voltage of the DC voltage on the DC side of inverter circuit 4.

The controller 8 generates a pulse width modulation (PWM) signal for controlling the switching (on/off) of each semiconductor switching element 11 of the inverter circuit 4 based on the detection signals from the voltage detection circuit 6, the voltage detection circuit 7, and the current detection circuit 9. The controller 8 may be an arithmetic processing device such as a microcomputer or a DSP (Digital Signal Processor). The controller 8 also includes a sample-and-hold circuit and an A/D (Analog/Digital) conversion unit, and the input voltage and current detection signals are converted into digital signals.

The internal configuration of the controller 8 will be described below with reference to FIG. 2. FIG. 2 shows the internal configuration of the controller 8 in the inverter device 100. The controller 8 operates to generate a PWM signal for the inverter circuit 4 by the above-mentioned arithmetic processing device executing a predetermined program.

As shown in FIG. 2, the controller 8 includes a power supply phase calculator 21, a voltage controller 22, a three-phase/two-axis converter 23, a two-axis/three-phase converter 24, and a PWM controller 25.

The power supply phase calculator 21 receives the AC voltage detection signal detected by the voltage detection circuit 6, calculates the power supply voltage phase (θ _s ), and outputs the calculated power supply voltage phase (θ _s ) to each of the three-phase/two-axis converter 23 and the two-axis/three-phase converter 24.

The three-phase/two-axis converter 23 uses the AC current detection signals ( _Iu , _Iv ) for two phases of the three-phase AC system detected by the current detection circuit 9 and the power supply voltage phase ( _θs ) calculated by the power supply phase calculator 21 to calculate the d-axis current _Id and the q-axis current _Iq based on the following equations (1) and (2). The following equation (1) represents the calculation equation for the three-phase/two-axis conversion, and the following equation (2) represents the calculation equation for conversion to the rotating coordinate system.

The voltage controller 22 calculates the d-axis voltage command value V _d ^* and the q-axis voltage command value V _q ^* using proportional-integral (PI) control or the like so as to eliminate errors between the d-axis current command value I _{d *} and the q-axis current command value I _q ^* and the d-axis current detection value I _d and the q-axis current detection value ^{I q} _obtained by the three-phase/two-axis converter 23.

2 uses the d-axis voltage command value _Vd ^* and the q-axis voltage command value _Vq ^* , and the power supply voltage phase ( _θs ) calculated by the power supply phase calculator 21 to perform inverse conversion of the voltage commands based on the following equations (3) and (4), calculates three-phase voltage command values ( _Vu ^* , _Vv ^* , _Vw ^* ), and outputs them to the PWM controller 25. Note that the following equation (3) represents the calculation equation for conversion from the rotating coordinate system to the fixed coordinate system. Also, the following equation (4) represents the calculation equation for the two-axis/three-phase conversion.

The PWM controller 25 generates a PWM control signal based on the three-phase voltage command values ( _Vu ^* , _Vv ^* , _Vw ^* ) from the two-axis/three-phase converter 24, the DC voltage detection signal E _dc , and a carrier wave of a predetermined frequency, and causes each semiconductor switching element 11 of the inverter circuit 4 to perform switching operation, thereby controlling the output voltage of the inverter circuit 4.

The PWM control method in the PWM controller 25 is not particularly limited, but for example, a so-called triangular wave comparison method can be adopted, in which a triangular wave or sawtooth wave carrier wave signal is generated using the built-in functions of a microcomputer, and the output signal level is controlled by comparing it with the output of each register. Below, a more specific explanation will be given using the triangular wave comparison method using a triangular wave carrier wave signal.

However, the triangular wave comparison method using a triangular carrier wave signal is merely one example, and a sawtooth carrier wave signal may also be used. Also, from the standpoint of ease of implementation and reducing hardware costs, it is preferable to adopt the triangular wave comparison method, but this is not limiting.

Figure 3 shows the internal configuration of the PWM controller 25 in the controller 8. Note that Figure 3 also shows an example of the configuration of the PWM controller 25 inside the microcomputer. Note that the example configuration shown in Figure 3 is based on a triangular wave comparison method.

The PWM controller 25 uses a timer function to generate a triangular carrier wave signal in the carrier wave generator 35, and also generates peak/valley signals that indicate the timing of the peaks (the apexes of the upward convex parts) and valleys (the apexes of the downward convex parts).

The PWM controller 25 normalizes the three-phase voltage command values ( _Vu ^* , _Vv ^* , _Vw ^* ) from the two-axis/three-phase converter 24 in the modulated wave calculator 30 using the _DC voltage detection signal Edc, and converts them into modulated wave signals.

The PWM controller 25 performs correction processing on the modulated wave signal calculated by the modulated wave calculator 30 using the narrow pulse elimination corrector 31 to eliminate pulses in the PWM signal whose pulse section width is less than a predetermined standard.

The output of the narrow pulse elimination corrector 31 is input to a buffer register 32 and transferred to a comparison register 33 at the time of the peak or valley of the carrier wave according to the peak/valley signal. A comparator 34 compares the output of the comparison register 33 (modulated wave signal) with the carrier wave signal generated by a carrier wave generator 35 to generate a PWM signal.

Figure 4 explains how a PWM signal is generated in the inverter device 100. Figure 4 shows a time chart of register updates for a triangular wave and a voltage command for one phase. The modulated wave 41 from the narrow pulse elimination corrector 31 is input to the buffer register 32 at a predetermined timing, and is transferred to the comparison register 33 at the peak and valley of the carrier wave, the output of which becomes the modulated wave 42. The comparator 34 compares the modulated wave 42, which is the output from the comparison register 33, with the carrier wave 43 to generate the PWM signal 44.

The PWM signal 44 transitions from a HIGH state to a LOW state when the carrier wave signal crosses the level of the modulated wave 42 transferred to the comparison register 33 from bottom to top. On the other hand, the PWM signal 44 transitions from a LOW state to a HIGH state when the carrier wave crosses the level of the modulated wave 42 from top to bottom.

The processing performed by the narrow pulse elimination corrector 31 is explained in more detail below.

When the modulating wave 42 approaches the peak or valley of the carrier wave, the on and off intervals of the PWM signal 44 become narrower. Since the change in output voltage corresponding to a PWM signal with a narrow on and off interval is small, if such a narrow pulse interval in the PWM signal can be eliminated, it is expected that the number of switching operations of the semiconductor switching element 11 can be reduced and inverter losses can be reduced. On the other hand, if such a narrow pulse interval is simply eliminated, a small error may occur in the AC voltage of the inverter circuit 4, resulting in a current control error, etc., especially when the width of the pulse interval to be eliminated is to a certain extent.

Therefore, in order to correct the error in the narrow pulse section to be erased, this embodiment is configured to correct or adjust the width of other pulses in the PWM signal that are adjacent to the narrow pulse section to be erased.

Referring again to FIG. 3, a more detailed configuration of the narrow pulse elimination corrector 31 is shown. As shown in FIG. 3, the narrow pulse elimination corrector 31 includes a determination unit 36 and a correction unit 37.

The determination unit 36 determines whether the width of the signal section constituting the PWM signal, which is a pulse signal train that controls the switching element 11, falls below a predetermined standard. Signal sections that fall below the predetermined standard are eliminated by the correction unit 37, as described below. In the following explanation, a two-level inverter is used as an explanation, and the section in which the signal is in a HIGH state is referred to as an on-pulse section, and the section in which the signal is in a LOW state is referred to as an off-pulse section. Both the on-pulse section and the off-pulse section can be signal sections that are subject to the above judgment.

The above-mentioned predetermined standard for the width of the signal section may be, for example, a threshold value for the width, and the threshold value may be specified as a value for the predetermined width. For example, a value in the range of 5 to 30 μsec may be specified as the predetermined width. However, since the width of the pulse that is desired to be erased depends on factors such as the period of the carrier wave, it may also be specified as a value that is a predetermined percentage of the period of the carrier wave. For example, a value in the range of 5 to 15% may be specified as the predetermined percentage of the carrier period. If the carrier frequency is, for example, about 100 to 200 μsec, a predetermined width of 5 to 30 μsec is obtained, corresponding to a percentage in the range of 5 to 15%.

The correction unit 37 erases the on-pulse or off-pulse section whose width is determined by the determination unit 36 to be below the reference value, and performs correction on the pulses in the PWM signal adjacent to the on-pulse or off-pulse section to be erased according to the width of the on-pulse or off-pulse section to be erased.

Note that erasing the pulse section here can include erasing a section (on pulse) that includes a transition from a LOW state to a HIGH state and a transition from a HIGH state to a LOW state, resulting in a state in which there are no transitions at the LOW level during the section, and erasing a section (off pulse) that includes a transition from a HIGH state to a LOW state and a transition from a LOW state to a HIGH state, resulting in a state in which there are no transitions at the HIGH level during the section.

When an off-pulse section is to be erased, the neighboring pulse to be corrected can be an off-pulse adjacent to the off-pulse section to be erased, and the neighboring off-pulse is corrected to have a wider width. The neighboring off-pulse can also be an off-pulse that precedes or follows the off-pulse section to be erased. When an on-pulse section is to be erased, the neighboring pulse to be corrected can be an on-pulse adjacent to the on-pulse section to be erased, and the neighboring on-pulse is corrected to have a wider width. The neighboring on-pulse can also be an on-pulse that precedes or follows the on-pulse section to be erased.

In this embodiment, the judgment by the judgment unit 36 and the erasure of the pulse section in the PWM signal and the correction or adjustment of the width of the pulse section by the correction unit 37 are performed by the narrow pulse erasure corrector 31. The narrow pulse erasure corrector 31 does not input a PWM signal and apply corrections to it to erase the pulse section and adjust the pulse section width, but rather achieves the above-mentioned erasure of the narrow pulse and correction of adjacent pulses by applying corrections to the voltage command value of the modulated wave for generating the PWM signal.

That is, the judgment unit 36 makes the above judgment based on the relationship, more specifically the difference, between the level value of the modulated wave signal calculated by the modulated wave calculator 30 and the level value of the reference point (the apex of the crest or valley of the triangular wave) of the carrier wave signal generated by the carrier wave generator 35. The correction unit 37 realizes the elimination of the above-mentioned pulse section and correction of nearby pulses by modifying the value of the modulated wave signal calculated by the modulated wave calculator.

The judgment by the judgment unit 36 and the correction by the correction unit 37 can be performed using an arithmetic circuit based on information about two pulse periods in the PWM signal. Preferably, the controller 8 can stop the judgment by the judgment unit 36 and the erasure and correction by the correction unit 37 in response to an external command or a specified change in the power supply voltage.

Figure 5 explains the pulses to be processed in the modulated wave signal and PWM signal generated by the inverter device 100. Figure 5 shows a modulated wave 42, a carrier wave 43, and a PWM signal 44.

51 in FIG. 5 indicates the phase where the level of modulated wave 42 reaches a maximum value and starts to decrease, and shows a portion including a narrow off-pulse section followed by a wider off-pulse. 52 in FIG. 5 indicates the phase where the level of modulated wave 42 increases and reaches a maximum value, and shows a portion including a narrow off-pulse section followed by a wider off-pulse.

53 in FIG. 5 indicates the phase when the level of modulated wave 42 reaches a minimum value and starts to increase, and shows a portion including a narrow on-pulse section followed by a wider on-pulse. 54 in FIG. 5 indicates the phase when the level of modulated wave 42 decreases and reaches a minimum value, and shows a portion including a narrow on-pulse section followed by a wider on-pulse.

In this embodiment, the narrow pulse elimination corrector 31 eliminates the narrower pulse section that meets a predetermined criterion, and performs correction to widen the wider pulse.

Figures 6 to 9 explain in more detail the four cases described above regarding the pulse erasure and correction method in the inverter device according to the first embodiment. Figures 6 to 9 show waveform diagrams of the carrier wave, modulated wave, and PWM signal before and after correction processing in each case. In Figures 6 to 9, the upper row shows the waveform before correction processing, and the lower row shows the waveform after correction processing.

First, the first case will be described with reference to FIG. 6. In the first case, an off-pulse whose width falls below a predetermined standard is erased, and a correction is performed to widen the width of the subsequent off-pulse by the amount of the erased off-pulse.

As shown in the upper part of FIG. 6, the PWM signal 44 before correction processing has two consecutive off-pulses of width A and width B. Width A is narrower than a predetermined value, and the off-pulse of width A is erased. In addition, with the erasure, the off-pulse of width B is corrected (width is added) by the width A of the erased off-pulse. To correct the off-pulse of width B on the PWM signal 44, the narrow pulse erasure corrector 31 corrects the voltage command value for generating an off-pulse of width B in the modulated wave 42.

The waveform after correction processing is shown in the lower part of Figure 6. Figure 6 shows an off-pulse of width C after the off-pulse of width A has been erased and the off-pulse of width B has been corrected. The width of the off-pulse of width C after correction is the sum of widths A and B. Furthermore, from the perspective of maintaining the average output voltage, it is preferable to move the position of the off-pulse of width C to the weighted average position of the original off-pulse of width A and the off-pulse of width B. However, in order to achieve a similar effect without changing the carrier wave, as shown in the lower part of Figure 6, the rising edge of the off-pulse of width C is moved to a timing that coincides with the crest of the corresponding carrier wave.

Below, we will use a formula to explain how to adjust the modulated wave to erase a pulse section and correct a pulse adjacent to the pulse to be erased.

Here, the levels at each timing (peak-to-valley or valley-to-peak section) of modulated wave 42 before correction processing are Ma_up, Ma_dw, Mb_up and Mb_dw, the height of the apex of the carrier wave peak is Th, the height of the apex of the carrier wave valley is 0, and the level of the modulated wave corresponding to a predetermined width (a judgment value for whether a pulse is narrow) is _Tmin . First, it is judged whether width A or width B is narrower than the predetermined width using the following formulas (5) and (6).

If either the above formula (5) or formula (6) is satisfied, the erasure and correction processes are carried out. However, if both the above formula (5) and formula (6) are satisfied, the narrower off-pulse is erased and the wider off-pulse is widened for correction.

When erasing an off-pulse of width A and correcting the subsequent off-pulse of width B as in the first case shown in the upper part of Figure 6, the adjustment of each modulated wave is performed according to the following formula (7).

Figure 7 also shows a second case in which an off-pulse whose width falls below a predetermined standard is erased, and the width of the preceding off-pulse is widened by the amount of the erased off-pulse. In the case shown in Figure 7, an off-pulse of width B is erased, and an off-pulse of width A is widened, and the adjustment of each modulated wave is performed as shown in the following formula (8).

Below, the third and fourth cases of erasing an on-pulse will be described with reference to Figures 8 and 9. As shown in Figures 8 and 9, when the modulated wave 42 approaches the valley of the carrier wave 43, an on-pulse with a narrow width is generated. The third case in Figure 8 is a case in which an on-pulse whose width falls below a predetermined standard is erased, and a correction is made to widen the width of the subsequent on-pulse by the amount of the erased pulse. On the other hand, the fourth case in Figure 9 is a case in which an on-pulse whose width falls below a predetermined standard is erased, and a correction is made to widen the width of the preceding on-pulse by the amount of the erased pulse.

The judgment and erasure correction process for this narrow on-pulse uses the following formulas (9) and (10) to determine whether width A and width B are narrower than a predetermined width.

If either the above formula (9) or formula (10) is satisfied, the erasure and correction processes are carried out. However, if both the above formula (9) and formula (10) are satisfied, the narrower on-pulse is erased and the wider on-pulse is corrected to be wider.

When erasing the on-pulse of width A and correcting the on-pulse of width B as in the third case shown in the upper part of Figure 8, the adjustment of each modulated wave is performed according to the following formula (11).

In the case shown in FIG. 9, the on-pulse of width B is erased and the preceding on-pulse of width A is widened, and the adjustment of each modulated wave is performed according to the following formula (12).

The processing of the narrow pulse elimination corrector 31 uses modulated wave information for two periods of the carrier wave. For this purpose, for example, a buffer for modulated waves can be provided, and the previous modulated wave stored in the buffer and the modulated wave calculated this time can be used. At this time, since the modulated wave input to the buffer register is the previous value after processing, a delay of one carrier frequency may occur. If the effect of this processing delay cannot be ignored, the processing of the narrow pulse elimination corrector 31 can be temporarily stopped and the modulated wave calculated this time can be used as is, thereby suppressing the effect of the processing delay. Note that this corresponds to a case where the effect cannot be ignored, for example, when there is an external command that causes a large change or a predetermined change (e.g., a sudden change) in the power supply voltage.

Below, a control method for realizing the above-mentioned erasure of the narrow pulse and correction of adjacent pulses before and after it will be described with reference to FIG. 10. FIG. 10 is a flowchart showing the control method executed by the inverter device 100 according to the first embodiment.

The control shown in FIG. 10 starts from step S100. In step S101, the narrow pulse elimination corrector 31 acquires the levels of the modulated wave before correction processing (Ma_up, Ma_dw, Mb_up, and Mb_dw) as modulated wave information for two cycles of the carrier wave.

In step S102, the narrow pulse elimination corrector 31 determines whether the above formula (5) is satisfied. As described above, the above formula (5) is used to determine whether the modulated wave 42 is approaching the crest of the carrier wave in the first cycle and is an off-pulse having a width below the criterion. If the above formula (5) is satisfied in step S102, the process branches to step S103. In step S103, the narrow pulse elimination corrector 31 further determines whether the above formula (6) is satisfied. As described above, the above formula (6) is used to determine whether the modulated wave 42 is approaching the crest of the carrier wave in the second cycle and is an off-pulse having a width below the criterion.

If the above formula (6) is not satisfied in step S103, the process branches to step S105. On the other hand, if the above formula (6) is also satisfied in step S103, the process branches to step S104. This corresponds to the case where both the above formulas (5) and (6) are satisfied, and in step S104, the narrow pulse elimination corrector 31 determines whether the left side of the above formula (5) is smaller than the left side of the above formula (6) to obtain the narrower off-pulse. If it is determined in step S104 that the left side of the above formula (5) is smaller than the left side of the above formula (6), the process branches to step S105. In this case, the preceding off-pulse in the first period has a narrower width.

In step S105, the narrow pulse elimination corrector 31 corrects the levels of the modulated wave (Ma_up, Ma_dw, Mb_up, and Mb_dw) based on the above formula (7), and in step S115 outputs the corrected levels of the modulated wave (Ma_up', Ma_dw', Mb_up', and Mb_dw'), terminating the process. If the output of the modulated wave continues, the process is restarted from step S101 for the next cycle. In step S105, the preceding narrow off-pulse is eliminated, and the succeeding wide off-pulse is widened.

On the other hand, if the above formula (5) does not hold in step S102, the process branches to step S106. In step S106, the narrow pulse elimination corrector 31 determines whether or not the above formula (6) holds. If the above formula (6) holds in step S106, the process proceeds to step S107. Also, if it is determined in step S104 that the left side of the above formula (5) is not smaller than the left side of the above formula (6), the process branches to step S107.

In step S107, the narrow pulse elimination corrector 31 corrects the levels of the modulated wave (Ma_up, Ma_dw, Mb_up, and Mb_dw) based on the above formula (8), and in step S115 outputs the corrected levels of the modulated wave (Ma_up', Ma_dw', Mb_up', and Mb_dw'), terminating the process. In step S107, the trailing narrow off-pulse is eliminated, and the preceding wide off-pulse is widened.

On the other hand, if the above formula (6) does not hold in step S106, the process branches to step S108. In this case, it means that the modulated wave 42 is not approaching the peak of the carrier wave.

In step S108, the narrow pulse elimination corrector 31 determines whether the above formula (9) is satisfied. As described above, the above formula (9) is used to determine whether the modulated wave 42 is approaching the valley of the carrier wave in the first cycle and is an on-pulse having a width below the reference. If the above formula (9) is satisfied in step S108, the process branches to step S109. In step S109, the narrow pulse elimination corrector 31 further determines whether the above formula (10) is satisfied. As described above, the above formula (10) is used to determine whether the modulated wave 42 is approaching the valley of the carrier wave in the second cycle and is an on-pulse having a width below the reference.

If the above formula (10) is not satisfied in step S109, the process branches to step S112. On the other hand, if the above formula (10) is also satisfied in step S109, the process branches to step S110. This corresponds to the case where both the above formulas (9) and (10) are satisfied, and in step S110, the narrow pulse elimination corrector 31 determines whether the left side of the above formula (9) is smaller than the left side of the above formula (10),
If it is determined in step S110 that the left side of the above formula (9) is smaller than the left side of the above formula (10), the process branches to step S112. In this case, the preceding on-pulse in the first period has a narrower width.

In step S112, the narrow pulse elimination corrector 31 corrects the levels of the modulated wave (Ma_up, Ma_dw, Mb_up, and Mb_dw) based on the above formula (11), and in step S115 outputs the corrected levels of the modulated wave (Ma_up', Ma_dw', Mb_up', and Mb_dw'), terminating the process. In step S112, the preceding narrow on-pulse is eliminated, and the following wide on-pulse is widened.

If the above formula (9) is not satisfied in step S108, the process branches to step S111. In step S111, the narrow pulse elimination corrector 31 determines whether the above formula (10) is satisfied. If the above formula (10) is satisfied in step S111, the process proceeds to step S113. Also, if it is determined in step S110 that the left side of the above formula (9) is not smaller than the left side of the above formula (10), the process branches to step S113.

In step S113, the narrow pulse elimination corrector 31 corrects the levels of the modulated wave (Ma_up, Ma_dw, Mb_up, and Mb_dw) based on the above formula (12), returns to step S101, and in step S115 outputs the corrected levels of the modulated wave (Ma_up', Ma_dw', Mb_up', and Mb_dw'), terminating the process. In step S113, the trailing narrow on-pulse is eliminated, and the preceding wide on-pulse is widened.

On the other hand, if the above formula (10) does not hold in step S111, the level of the input modulated wave is used as the level of the output modulated wave (Ma_up', Ma_dw', Mb_up' and Mb_dw') in step S114, and this is output in step S115, ending the process. In this case, the modulated wave 42 is not approaching the valley of the carrier wave, and furthermore, since the flow shown in FIG. 10 branches off from step 106, it is not approaching the peak of the carrier wave either, so there is no need to correct the level of the modulated wave.

In an inverter circuit, in the region where the inverter modulation rate (ratio of inverter output voltage command to DC voltage) is high (>0.8), narrow pulses (for example, less than about 10 μs when the carrier frequency is 100-200 μs) frequently occur in the output voltage of each phase of the inverter. Eliminating such narrow pulses would reduce the switching loss of the inverter circuit, but it is desirable to prevent the occurrence of errors in the output voltage of the corresponding phase and prevent current distortion. Eliminating pulses of about 1 μs does not cause large errors in the output voltage, but eliminating pulses of about 10 μs would result in a change of about 10-5% if the carrier frequency is 100-200 μs, and the output voltage error cannot be ignored.

In the above-described embodiment, the narrow pulse elimination corrector 31 eliminates narrow pulses that are less than a predetermined threshold (e.g., 10 μs) that occur in the output voltage of each phase of the inverter, and performs correction according to the width of the eliminated pulse signal section for at least one pulse (e.g., an on pulse, an off pulse) adjacent to the signal section (e.g., an on pulse section or an off pulse section) involved in the elimination in the pulse signal train. By adding the narrow pulse elimination corrector 31, it is possible to reduce switching losses and suppress output voltage errors in the inverter circuit 4, preferably in a wide operating range.

In the embodiment described, a two-level inverter circuit has been described. However, in other embodiments, the invention may be applied to a multi-level inverter circuit, such as a three-level inverter circuit. In the case of a multi-level inverter circuit, a narrow pulse section of a specific level can also be detected as the target for erasure, and the width of other nearby pulses can be adjusted.

Second Embodiment
Hereinafter, a motor control device according to a second embodiment including the above-described inverter circuit will be described with reference to FIGS.

Figure 11 is a diagram showing the overall configuration of a motor drive device 200 according to the second embodiment. As shown in Figure 11, the motor drive device 200 is connected to an AC power supply 201 and a motor 210, and mainly includes a rectifier circuit 202, a smoothing capacitor 203, an inverter circuit 204, a current detection circuit 206, a DC voltage detection circuit 207, and a controller 208.

The rectifier circuit 202 is connected to the AC power source 201 and converts the AC voltage from the AC power source 201 into a DC voltage. The smoothing capacitor 203 is connected to the DC output terminal of the rectifier circuit 202 and smoothes the DC voltage output from the rectifier circuit 202. The inverter circuit 204 turns on and off semiconductor switching elements 211 such as IGBTs and power MOSs according to the PWM signal input from the controller 208, converts the DC voltage output from the smoothing capacitor 203 into an AC voltage, outputs it, and controls the rotation speed of the motor 210.

When power is supplied from a DC power source such as a storage battery instead of the AC power source 201, the rectifier circuit 202 may be omitted and the output of the DC power source may be input to the inverter circuit 204.

The current detection circuit 206 detects the DC current (bus current) of the inverter circuit 204 using a shunt resistor provided between the smoothing capacitor 203 and the inverter circuit 204. The DC voltage detection circuit 207 detects the DC voltage across the smoothing capacitor 203.

The controller 208 generates a PWM signal that controls the inverter circuit 204 based on the outputs of the current detection circuit 206 and the DC voltage detection circuit 207. The controller 208 can be implemented using a semiconductor computing element such as a microcomputer or a DSP (digital signal processor).

Figure 12 shows the internal configuration of the controller 208 of the motor drive device 200 according to the second embodiment. In Figure 12, the controller 208 calculates a voltage command signal to be applied to the motor 210 and generates a PWM control signal to control the inverter circuit 204. More specifically, the controller 208 includes a speed controller 220, a d-axis current command generator 221, a voltage controller 222, a two-axis/three-phase converter 223, a speed phase estimator 224, a three-phase/two-axis converter 225, a current reproduction calculator 226, and a PWM controller 227.

The current reproduction calculator 226 reproduces the output currents Iu, _Iv , and Iw of the inverter circuit 204 using the _bus current signal Ish output by the current detection circuit 206 and the three-phase voltage command values _Vu ^* , _Vv ^* , _{and Vw} ^* output by the two- _axis /three-phase converter 223. In FIG. 12, a method of reproducing the three-phase current from the bus current signal _Ish is adopted to reduce costs, but the AC current output from the inverter circuit 204 may be detected using a current detection means such as a current sensor. In this case, the three-phase current detected by the current detection means is input to the three-phase/two-axis converter 225. The voltage controller 222 related to motor control shown in FIG. 12 can adopt a known technique, and detailed description thereof will be omitted.

The PWM controller 227 has a configuration similar to that of the PWM controller 25 described in the first embodiment, and creates a PWM signal for the inverter circuit 204 using the three-phase command voltages ( _Vu ^* , _Vv ^* , _Vw ^* ) from the two-axis/three-phase converter 223 and the DC voltage detection signal E _dc from the DC voltage detection circuit 207.

As described in the first embodiment, the PWM controller 227 has an internal configuration similar to that shown in FIG. 3, and is configured to use the narrow pulse elimination corrector 31 to eliminate narrow off-pulses and on-pulses in the PWM signal and to correct adjacent pulses.

As described above, according to the second embodiment, it is possible to provide a motor drive device 200 that realizes a reduction in switching loss and suppression of output voltage error in the inverter circuit 204. Since the motor drive device 200 has a reduced switching loss, it is possible to reduce power consumption.

Third Embodiment
Hereinafter, a refrigeration and air conditioning device 300 according to a third embodiment including the above-mentioned inverter circuit will be described with reference to Fig. 13. Here, the refrigeration and air conditioning device (refrigeration and air conditioning device) is a general term for devices that use a refrigerant and a refrigeration cycle, such as air conditioners, refrigerators, freezers, etc. More specifically, examples of the refrigeration and air conditioning device may include air conditioners such as room air conditioners and gas engine heat pump air conditioners, heat source devices such as freezers and chilling units, commercial freezers such as showcases, refrigerator freezers, unit coolers, and ice makers, transportation refrigeration devices such as car air conditioners, and heat pump water heaters.

Figure 13 shows the configuration of a refrigeration and air conditioning device 300 in the third embodiment. The refrigeration and air conditioning device 300 is a device that adjusts the temperature of air, and is configured by connecting an indoor unit 300A and an outdoor unit 300B by a refrigerant pipe 306.

Here, the outdoor unit 300B is equipped with an outdoor heat exchanger 302 that exchanges heat between the refrigerant and air, a fan 304 that blows air to the outdoor heat exchanger 302, and a compressor 305 that compresses and circulates the refrigerant.

The compressor 305 also has a compressor motor 308 equipped with a permanent magnet synchronous motor inside. The compressor 305 is driven by driving the compressor motor 308 with the motor drive device 307. The motor drive device 307 converts the AC voltage of the AC power source into a DC voltage, provides the DC voltage to the motor drive inverter, and drives the compressor motor 308.

As the compressor 305, various types of compressors such as a rotary compressor or a scroll compressor can be used. The compressor 305 has an internal compression mechanism section, which is driven by a compressor motor 308. If the compression mechanism section is a scroll compressor, it is composed of a fixed scroll and an orbiting scroll. A compression chamber is formed between the scrolls as the orbiting scroll orbits relative to the fixed scroll.

By using the motor drive device 200 according to the second embodiment as the motor drive device 307, the switching loss of the inverter circuit can be reduced and the output voltage error can be suppressed, resulting in a more efficient refrigeration and air conditioning device that consumes less power.

As described above, the present disclosure makes it possible to provide an inverter device that reduces switching losses and suppresses output voltage errors, a control method for the inverter device, a motor drive device that includes the inverter device, and a refrigeration and air conditioning appliance that includes the motor drive device.

In the inverter device, motor drive device, and inverter circuit in the refrigeration and air conditioning equipment according to this embodiment, the number of switching times of the switching elements is reduced, and switching losses are reduced. In particular, in devices that operate for long periods near rated load conditions, such as air conditioner compressors, reducing losses in the motor drive inverter circuit can be advantageously used to improve the energy-saving performance of devices such as air conditioners.

In the conventional technology of Patent Document 1 described above, there is a possibility that output voltage errors and current distortions may occur. In contrast, according to the present embodiment, the pulse width is corrected in response to the erasure of the pulse, thereby suppressing the output voltage error. In addition, in the conventional technology of Patent Document 2, during overmodulation control, in a section where the voltage commands for two phases are stuck to the upper and lower limits, the voltage commands may not be corrected. In contrast, according to the present embodiment, the erasure of the pulse and the correction of the pulse width are performed within adjacent pulse sections of the same phase, so that switching losses can be reduced in a relatively wide operating range.

The embodiments of the present invention are not limited to the above-described embodiments, and may include various modified examples. For example, the above-described embodiments have been described in detail to make them easier to understand, and are not necessarily limited to those that include all of the configurations described. It is also possible to replace part of the configuration of one embodiment with the configuration of another embodiment, and it is also possible to add the configuration of another embodiment to the configuration of one embodiment. It is also possible to add, delete, or replace part of the configuration of each embodiment with other configurations.

In addition, some or all of the above configurations, functions, processing units, processing means, etc. may be realized in hardware, for example by designing them as integrated circuits. Furthermore, some or all of the above configurations, functions, etc. may be realized by computer-executable programs written in legacy programming languages such as assembler, C, C++, C#, Java (registered trademark), or object-oriented programming languages, in which a processor realizes each function, and information such as programs, tables, and files that realize each function may be stored in storage devices such as HDD (Hard Disk Drive), SSD (Solid State Drive), ROM, EEPROM, EPROM, and flash memory, flexible disks, CD-ROMs, CD-RWs, DVD-ROMs, DVD-RAMs, DVD-RWs, Blu-ray discs, SD (registered trademark) cards, and MOs, or distributed through telecommunication lines.

Furthermore, some or all of the above configurations, functions, etc. can be implemented on a programmable device (PD) such as a field programmable gate array (FPGA), and the circuit configuration data (bitstream data) to be downloaded to the PD to realize the above functional units on the PD, and data written in HDL (Hardware Description Language), VHDL (Very High Speed Integrated Circuits Hardware Description Language), Verilog-HDL, etc. for generating the circuit configuration data can be distributed on a recording medium. In addition, the control lines and information lines shown are those considered necessary for the explanation, and do not necessarily show all the control lines and information lines in the product. In reality, it can be considered that almost all the configurations are connected to each other. In addition, the formats of the various data exemplified in the above explanation can be configured, for example, in CSV (Comma-Separated Values), XML (eXtensible Markup Language), binary, etc., but are not necessarily limited to these.

100... inverter device, 1... AC power supply, 2... noise filter, 3... reactor, 4... inverter circuit, 5... capacitor, 6... voltage detection circuit, 7... voltage detection circuit, 8... controller, 9... current detection circuit, 10... DC load/DC power supply, 11... switching element, 12... diode, 21... power supply phase calculator, 22... voltage controller, 23... three-phase/two-axis converter, 24... two-axis/three-phase converter, 25... PWM controller, 30... modulated wave calculator, 31... narrow pulse elimination corrector, 32... buffer register, 33... comparison register, 34... comparator, 35... carrier wave generator, 36... judgment unit, 37... correction unit, 41... modulated wave, 42... modulated wave, 43... carrier wave, 44... PWM signal, 2 00...motor drive device, 201...AC power supply, 202...rectifier circuit, 203...smoothing capacitor, 204...inverter circuit, 206...current detection circuit, 207...DC voltage detection circuit, 208...controller, 210...motor, 211...switching element, 220...speed controller, 221...d-axis current command generator, 222...voltage controller, 223...two-axis/three-phase converter, 224...speed phase estimator, 225...three-phase/two-axis converter, 226...current reproduction calculator, 227...PWM controller, 300...refrigeration and air conditioning equipment, 300A...indoor unit, 300B...outdoor unit, 302...outdoor heat exchanger, 304...fan, 305...compressor, 306...refrigerant piping, 307...motor drive device, 308...compressor motor

Claims (13)

an inverter circuit including a switching element;
and a controller for controlling the inverter circuit,
a determination unit that controls the switching element and determines whether a width of a signal section constituting a pulse signal train based on a modulated wave signal and a carrier wave signal falls below a reference value;
a correction unit that erases a signal section whose width is determined to be below the reference, and that performs correction according to the width of the signal section to be erased by modifying multiple values of the modulated wave signal corresponding to multiple sections constituting one cycle of the carrier wave signal for pulses in the pulse signal train adjacent to the signal section to be erased. The inverter device according to claim 1, wherein the signal section is an on-pulse section or an off-pulse section. 3. The inverter device according to claim 1, wherein when the signal section is an off-pulse section, the neighboring pulse is an off-pulse preceding or following the signal section to be erased, and the correction is performed so that the width of the off-pulse is widened. The inverter device according to any one of claims 1 to 3, wherein when the signal section is an on-pulse section, the neighboring pulse is an on-pulse preceding or following the on-pulse section to be erased, and the width of the on-pulse is corrected to be wider. The inverter device according to any one of claims 1 to 4, characterized in that the controller uses a calculation circuit to perform the determination and the correction based on information relating to a section of at least two periods of the pulse signal train. The inverter device according to any one of claims 1 to 5, characterized in that the controller stops the determination by the determination unit and the erasure and correction by the correction unit in response to an external command or a predetermined change in the power supply voltage. The inverter device is
a modulated wave calculation unit that calculates the modulated wave signal;
a carrier wave generator for generating the carrier wave signal;
a comparator for comparing the modulated wave signal with the carrier wave signal;
the determination unit performs the determination based on a relationship between the value of the modulated wave signal calculated by the modulated wave calculation unit and a value of a peak or a valley of the carrier wave signal,
An inverter device as described in any one of claims 1 to 6, wherein the correction unit achieves the elimination of the signal section and the correction of the adjacent pulses by modifying the value of the modulated wave signal calculated by the modulated wave calculation unit. A motor drive device connected to an AC motor,
An inverter circuit including a switching element for converting a DC voltage into an AC voltage;
a current detection means for detecting an AC current output from the inverter circuit;
and a controller for controlling the inverter circuit, the controller comprising:
a determination unit that controls the switching element and determines whether a width of a signal section constituting a pulse signal train based on a modulated wave signal and a carrier wave signal falls below a reference value;
a correction unit that erases a signal section whose width is determined to be below the reference, and that performs correction according to the width of the signal section to be erased by modifying multiple values of the modulated wave signal corresponding to multiple sections that constitute one cycle of the carrier wave signal for pulses in the pulse signal train that are adjacent to the signal section to be erased. A refrigeration and air conditioning apparatus having a compressor,
The motor drive device according to claim 8 ,
and the AC motor built into the compressor. A control method for an inverter device including an inverter circuit having a switching element and a controller for controlling the inverter circuit, the controller comprising:
a step of determining whether or not a width of a signal section constituting a pulse signal train based on a modulated wave signal and a carrier wave signal, which controls the switching element, falls below a reference value;
a step of erasing a signal section whose width is determined to be below the reference, and correcting, for pulses in the pulse signal train adjacent to the signal section to be erased, a plurality of values of the modulated wave signal corresponding to a plurality of sections constituting one cycle of the carrier wave signal, thereby making a correction according to the width of the signal section to be erased. The control method according to claim 10, wherein when the signal section is an off-pulse section, the neighboring pulse is an off-pulse preceding or following the signal section to be erased, and the correction is performed so that the width of the off-pulse is widened. The control method according to claim 10 or 11, wherein, when the signal section is an on-pulse section, the neighboring pulse is an on-pulse preceding or following the on-pulse section to be erased, and the width of the on-pulse is corrected to be wider. The control method includes:
obtaining the calculated modulated wave signal;
a step of correcting the calculated value of the modulated wave signal;
and comparing the value of the corrected modulated wave signal with the value of the generated carrier wave signal,
In the determining step, a controller performs the determination based on a relationship between the acquired value of the modulated wave signal and a value of a peak or a valley of the carrier wave signal;
The control method according to any one of claims 10 to 12, characterized in that in the correction step, a controller realizes the erasure of the signal section and the correction of the neighboring pulses by modifying the value of the acquired modulated wave signal.