JP7432892B2 - power converter - Google Patents

Description

The present disclosure relates to a power conversion device that converts the voltage of power.

Power conditioners connected to storage batteries, solar cells, fuel cells, etc. use DC/DC converters and inverters. Highly efficient power conversion and compact design are desired for DC/DC converters and inverters. To achieve this, the DC/DC converter is configured with a flying capacitor circuit (four switching elements connected in series, and a flying capacitor connected in parallel to the second switching element and the third switching element) after the reactor. A multilevel power conversion device has been proposed in which the voltage at the connection point between the reactor and the flying capacitor circuit is set to three levels by connecting the reactor and the flying capacitor circuit (for example, see Patent Document 1).

A multilevel power conversion device can reduce the voltage applied to each switching element, thereby reducing switching loss and realizing highly efficient power conversion. By using three levels in the multilevel power conversion device using the flying capacitor circuit described above, the voltage applied to each switching element making up the flying capacitor circuit can be reduced to 1/2 of the DC bus voltage. .

As a result, it is possible to configure the inverter with relatively low voltage (e.g., 300V) switching elements instead of the relatively high voltage (e.g., 600V) switching elements used in the full bridge section of the inverter. Become. Switching elements with low breakdown voltages are cheaper than switching elements with high breakdown voltages, and have less conduction loss, switching loss, etc. during power conversion, contributing to higher efficiency.

Japanese Patent Application Publication No. 2013-192383

In MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) that are commonly used as inexpensive switching elements, parasitic diodes are used as freewheeling diodes. A parasitic diode has a large recovery loss and becomes a factor that increases switching loss.

The present disclosure has been made in view of these circumstances, and its purpose is to provide a low-cost, highly efficient power conversion device.

In order to solve the above problems, a power conversion device according to an aspect of the present disclosure is a power conversion device having a power conversion section in which a plurality of parallel switching elements, each of which has at least one switching element connected in parallel, are connected in series. A diode is formed or connected in antiparallel to each switching element, and among the plurality of parallel switching elements, a parallel switching element whose number of parallel switching elements is smaller than other parallel switching elements is included.

According to the present disclosure, a low-cost and highly efficient power conversion device can be realized.

1 is a diagram for explaining the configuration of a DC/DC conversion device according to Embodiment 1. FIG. FIG. 3 is a diagram summarizing the switching patterns of the first switching element to the eighth switching element of the DC/DC converter according to the first embodiment. FIGS. 3A to 3D are circuit diagrams showing current paths of each switching pattern during boost operation. FIGS. 4(a) to 4(d) are circuit diagrams showing current paths of each switching pattern during voltage step-down operation. 7 is a timing chart showing an example of a switching pattern of the first switching element to the eighth switching element when the boost ratio is twice or more. 7 is a timing chart showing an example of a switching pattern of the first switching element to the eighth switching element when the boost ratio is less than twice. FIGS. 7A to 7D are circuit diagrams (part 1) showing transitions of switching patterns when the boost ratio is twice or more. FIGS. 8A to 8D are circuit diagrams showing transitions of switching patterns when the boost ratio is twice or more (part 2). FIGS. 9A to 9D are circuit diagrams (part 1) showing transitions of switching patterns when the step-down ratio is twice or more. FIGS. 10A to 10D are circuit diagrams showing transitions of switching patterns when the step-down ratio is twice or more (part 2). FIGS. 11(a) to 11(d) are circuit diagrams showing transitions of switching patterns when the boost ratio is less than twice (Part 1). FIGS. 12(a) to 12(d) are circuit diagrams showing transitions of switching patterns when the boost ratio is less than twice (part 2). FIGS. 13(a) to 13(d) are circuit diagrams showing transitions of switching patterns when the step-down ratio is less than 2 times (part 1). FIGS. 14(a) to 14(d) are circuit diagrams showing transitions of switching patterns when the step-down ratio is less than 2 times (Part 2). FIG. 2 is a diagram for explaining the configuration of a DC/DC conversion device according to a comparative example of the first embodiment. 2 is a diagram for explaining the configuration of a DC/DC conversion device according to Example 1 of Embodiment 1. FIG. FIG. 3 is a diagram for explaining the configuration of a DC/DC converter according to Example 2 of Embodiment 1. FIG. FIG. 2 is a diagram for explaining the configuration of a DC/DC converter according to a modification of Example 1 of Embodiment 1. FIG. FIGS. 19(a) to 19(c) are diagrams showing configuration examples of flying capacitor circuits. FIG. 2 is a diagram showing an N (N is a natural number) stage flying capacitor circuit. FIG. 3 is a diagram for explaining the configuration of a DC/DC converter according to Example 1 of Embodiment 2. FIG. FIG. 3 is a diagram for explaining the configuration of a DC/DC converter according to Example 2 of Embodiment 2. FIG. FIG. 7 is a diagram for explaining the configuration of a DC/DC conversion device according to Example 1 of Embodiment 3; FIG. 7 is a diagram for explaining the configuration of a DC/DC converter according to Example 2 of Embodiment 3;

FIG. 1 is a diagram for explaining the configuration of a DC/DC conversion device 3 according to the first embodiment. The DC/DC converter 3 according to the first embodiment is a bidirectional buck-boost DC/DC converter. The DC/DC converter 3 can step up the DC power supplied from the second DC power supply 2 and supply it to the first DC power supply 1 . Further, the DC/DC converter 3 can step down the DC power supplied from the first DC power supply 1 and supply it to the second DC power supply 2 . In this specification, it is assumed that the second DC power supply 2 is a power supply with a lower voltage than the first DC power supply 1.

The second DC power source 2 is, for example, a storage battery, an electric double layer capacitor, or the like. The first DC power supply 1 corresponds to, for example, a DC bus to which a bidirectional DC/AC inverter is connected. The alternating current side of the bidirectional DC/AC inverter is connected to a commercial power system and an alternating current load for use in a power storage system. In electric vehicle applications, it is connected to a motor (with regeneration function). When used as a power storage system, a DC/DC converter for solar cells or a DC/DC converter for other storage batteries may be further connected to the DC bus.

The DC/DC converter 3 includes a DC/DC converter 30 and a controller 40. The DC/DC converter 30 includes an input capacitor C5, a reactor L1, a first flying capacitor circuit 31, a second flying capacitor circuit 32, a first divided capacitor C3, a second divided capacitor C4, and an output capacitor C6.

An input capacitor C5 is connected in parallel with the second DC power supply 2. An output capacitor C6 is connected in parallel with the first DC power supply 1. A first dividing capacitor C3 and a second dividing capacitor C4 are connected in series between the positive side bus and the negative side bus of the first DC power supply 1. The first dividing capacitor C3 and the second dividing capacitor C4 act as a snubber capacitor to divide the voltage E of the first DC power supply 1 into 1/2, and to suppress the surge voltage generated in the DC/DC converter 30. It has the effect of In this specification, the configuration before the input capacitor C5 is referred to as a low-voltage DC section, and the configuration after the first divided capacitor C3 and the second divided capacitor C4 is referred to as a high-voltage DC section.

The first flying capacitor circuit 31 and the second flying capacitor circuit 32 are connected in series in parallel with the high voltage side DC section. The reactor L1 is connected between the positive side terminal of the low voltage side DC section and the midpoint of the first flying capacitor circuit 31. The negative side terminal of the low voltage side DC section and the midpoint of the second flying capacitor circuit 32 are connected. The connection point between the first flying capacitor circuit 31 and the second flying capacitor circuit 32 is connected to the intermediate potential point M of the high voltage side DC section (the voltage dividing point between the first dividing capacitor C3 and the second dividing capacitor C4). Ru.

Note that the first dividing capacitor C3 and the second dividing capacitor C4 can be omitted, and in that case, the connection point between the first flying capacitor circuit 31 and the second flying capacitor circuit 32 is not necessarily in the middle of the high voltage side DC section. It does not need to be connected to potential point M.

The first flying capacitor circuit 31 includes a first switching element S1, a second switching element S2, a third switching element S3, a fourth switching element S4, and a first flying capacitor C1. The first switching element S1, the second switching element S2, the third switching element S3, and the fourth switching element S4 are connected in series, and are connected between the positive side bus of the high voltage DC section and the intermediate potential point M. The first flying capacitor C1 is connected between the connection point between the first switching element S1 and the second switching element S2 and the connection point between the third switching element S3 and the fourth switching element S4, and S1 - Charged and discharged by the fourth switching element S4.

At the midpoint of the first flying capacitor circuit 31, the voltage E [V] of the first DC power supply 1 applied to the upper terminal of the first switching element S1 and the lower terminal of the fourth switching element S4 are applied. A potential in the range between 1/2E[V] is generated. The first flying capacitor C1 is initially charged (precharged) to a voltage of 1/4E [V], and is repeatedly charged and discharged around the voltage of 1/4E [V]. Therefore, approximately three levels of potential, E[V], 3/4E[V], and 1/2E[V], are generated at the midpoint of the first flying capacitor circuit 31.

The second flying capacitor circuit 32 includes a fifth switching element S5, a sixth switching element S6, a seventh switching element S7, an eighth switching element S8, and a second flying capacitor C2. The fifth switching element S5, the sixth switching element S6, the seventh switching element S7, and the eighth switching element S8 are connected in series, and are connected between the intermediate potential point M of the high voltage DC section and the negative side bus. The second flying capacitor C2 is connected between the connection point between the fifth switching element S5 and the sixth switching element S6 and the connection point between the seventh switching element S7 and the eighth switching element S8, and S5 - Charged and discharged by the eighth switching element S8.

At the midpoint of the second flying capacitor circuit 32, 1/2E [V] is applied to the upper terminal of the fifth switching element S5, and 0 [V] is applied to the lower terminal of the eighth switching element S8. Potentials in the range between are generated. The second flying capacitor C2 is initially charged (precharged) to a voltage of 1/4E [V], and is repeatedly charged and discharged around the voltage of 1/4E [V]. Therefore, approximately three levels of potential are generated at the midpoint of the second flying capacitor circuit 32: 1/2E [V], 1/4E [V], and 0 [V].

A first diode D1 to an eighth diode D8 are formed/connected in antiparallel to the first switching element S1 to the eighth switching element S8, respectively.

It is preferable that switching elements having a breakdown voltage lower than the voltages of the first DC power supply 1 and the second DC power supply 2 are used as the first switching element S1 to the eighth switching element S8. Hereinafter, in this embodiment, an example will be assumed in which N-channel MOSFETs with a withstand voltage of 150 V are used as the first switching element S1 to the eighth switching element S8. In an N-channel MOSFET, a parasitic diode is formed from the source to the drain.

Although not shown in FIG. 1, a voltage sensor detects the voltage of the low-voltage DC section, a current sensor detects the current flowing to the reactor L1, a voltage sensor detects the voltage of the first flying capacitor C1, and a voltage sensor detects the voltage of the second flying capacitor C2. A voltage sensor that detects voltage and a voltage sensor that detects the voltage of the high-voltage DC section are provided, and their measured values are output to the control section 40.

The control unit 40 can control the first flying capacitor circuit 31 and the second flying capacitor circuit 32 to transmit DC power from the low-voltage DC section to the high-voltage DC section in a step-up operation. Further, DC power can be transmitted from the high voltage side DC section to the low voltage side DC section by step-down operation. More specifically, the control unit 40 supplies a drive signal (PWM (Pulse Width Modulation) signal) to the gate terminals of the first switching element S1 to the eighth switching element S8, thereby controlling the first switching element S1 to the eighth switching element S8. By controlling the switching element S8 on/off, power can be transmitted bidirectionally by step-up operation or step-down operation.

The configuration of the control unit 40 can be realized by cooperation of hardware resources and software resources, or by only hardware resources. Analog elements, microcomputers, DSPs, ROMs, RAMs, FPGAs, ASICs, and other LSIs can be used as hardware resources. Programs such as firmware can be used as software resources.

FIG. 2 is a diagram summarizing the switching patterns of the first switching element S1 to the eighth switching element S8 of the DC/DC converter 3 according to the first embodiment. In the switching pattern shown in FIG. 2, the set of the first switching element S1 and the eighth switching element S8 and the set of the fourth switching element S4 and the fifth switching element S5 have a complementary relationship. Further, the set of the second switching element S2 and the seventh switching element S7 and the set of the third switching element S3 and the sixth switching element S6 have a complementary relationship.

The control unit 40 performs a voltage step-up operation or a voltage step-down operation using four modes.
In mode a, the control unit 40 turns on the second switching element S2, the fourth switching element S4, the fifth switching element S5, and the seventh switching element S7, and turns on the first switching element S1, the third switching element S3, and the sixth switching element The switching element S6 and the eighth switching element S8 are controlled to be in the off state. In mode a, the voltage between the midpoint of the first flying capacitor circuit 31 and the midpoint of the second flying capacitor circuit 32 (that is, the input/output voltage V _L on the low voltage side of the flying capacitor section) is 1/2E.

In mode b, the control unit 40 turns on the first switching element S1, the third switching element S3, the sixth switching element S6, and the eighth switching element S8, and turns on the second switching element S2, the fourth switching element S4, and the fifth switching element S4. The switching element S5 and the seventh switching element S7 are controlled to be in the off state. In mode b, the input/output voltage _VL on the low voltage side of the flying capacitor section is 1/2E.

In mode c, the control unit 40 turns on the first switching element S1, the second switching element S2, the seventh switching element S7, and the eighth switching element S8, and turns on the third switching element S3, the fourth switching element S4, and the fifth switching element S4. The switching element S5 and the sixth switching element S6 are controlled to be in the off state. In mode c, the input/output voltage _VL on the low voltage side of the flying capacitor section is E.

In mode d, the control unit 40 turns on the third switching element S3, the fourth switching element S4, the fifth switching element S5, and the sixth switching element S6, and turns on the first switching element S1, the second switching element S2, and the seventh switching element S2. The switching element S7 and the eighth switching element S8 are controlled to be in the off state. In mode d, the input/output voltage _VL on the low voltage side of the flying capacitor section is zero.

FIGS. 3A to 3D are circuit diagrams showing current paths of each switching pattern during boost operation. FIGS. 4(a) to 4(d) are circuit diagrams showing current paths of each switching pattern during voltage step-down operation. Note that, to simplify the drawing, MOSFETs are drawn using simple switch symbols.

3(a) shows the current path of mode a during boost operation, FIG. 3(b) shows the current path of mode b during boost operation, and FIG. 3(c) shows the current path of mode c during boost operation. FIG. 3(d) shows the current path in mode d during boost operation. Similarly, FIG. 4(a) shows the current path in mode a during buck operation, FIG. 4(b) shows the current path in mode b during buck operation, and FIG. 4(c) shows the current path in mode b during buck operation. FIG. 4D shows the current path in mode d during step-down operation.

The direction of current is opposite during step-up operation and step-down operation. In mode a, as shown in FIG. 3(a), the first flying capacitor C1 and the second flying capacitor C2 are in the charging operation during the step-up operation, but as shown in FIG. The flying capacitor C1 and the second flying capacitor C2 are in a discharging operation. In mode b, as shown in FIG. 3(b), the first flying capacitor C1 and the second flying capacitor C2 are in a discharging operation during step-up operation, but as shown in FIG. 4(b), during step-down operation, the first flying capacitor C1 and second flying capacitor C2 The flying capacitor C1 and the second flying capacitor C2 are in a charging operation.

When transmitting power from the low-voltage DC section to the high-voltage DC section by step-up operation, the control unit 40 sets a current command value in the positive direction, and maintains the measured value of the current flowing through the reactor L1 at the current command value in the positive direction. The duty ratio (on time) of the first switching element S1 to the eighth switching element S8 is controlled so that the switching element S1 to the eighth switching element S8 is controlled. On the other hand, when transmitting power from the high-voltage DC section to the low-voltage DC section in step-down operation, the control unit 40 sets a current command value in the negative direction, and the measured value of the current flowing through the reactor L1 corresponds to the current command in the negative direction. The duty ratio (on time) of the first switching element S1 to the eighth switching element S8 is controlled so as to maintain the value.

Further, the control unit 40 transmits power using mode a, mode b, and mode c when the ratio between the voltage of the low voltage side DC section and the voltage of the high voltage side DC section is smaller than the set value. Further, when the ratio is larger than the set value, the control unit 40 transmits power using mode a, mode b, and mode d. Further, when the ratio matches the set value, the control unit 40 transmits power using mode a and mode b.

The voltage of the low-voltage side DC section and the voltage of the high-voltage side DC section are each measured by voltage sensors. The above set value is set according to the ratio of the voltage E of the first DC power supply 1 to the total voltage 1/2E of the voltage of the first flying capacitor C1 and the voltage of the second flying capacitor C2. In this embodiment, the above setting value is set to 2.

The control unit 40 generates a duty ratio so that the current command value and the measured value of the current flowing through the reactor L1 match, and the voltages of the first flying capacitor C1 and the second flying capacitor C2 are each 1/4E. . Specifically, the control unit 40 increases the duty ratio as the measured value of the current flowing through the reactor L1 is smaller than the current command value, and decreases the duty ratio as the measured value increases.

FIG. 5 is a timing chart showing an example of a switching pattern of the first switching element S1 to the eighth switching element S8 when the boost ratio is twice or more. FIG. 6 is a timing chart showing an example of a switching pattern of the first switching element S1 to the eighth switching element S8 when the boost ratio is less than twice. The control examples shown in FIGS. 5 and 6 show control examples using a double carrier drive method. The double carrier drive method uses two carrier signals (triangular waves in FIGS. 5 and 6) that are 180° out of phase. The duty ratio duty becomes a threshold value with which two carrier signals are compared. When the step-up ratio is 2 times or more, the duty ratio takes a value in the range of 0.5 to 1.0, and when the step-up ratio is less than 2 times, the duty ratio takes a value in the range of 0.0 to 0.5. Takes a value.

Based on the comparison result between the carrier signal indicated by the thick line and the duty ratio, the first gate signal is supplied to the first switching element S1 and the eighth switching element S8, and the fourth gate signal is supplied to the fourth switching element S4 and the fifth switching element S5. Generate a signal. Specifically, in a region where the bold carrier signal is higher than the duty ratio, the first gate signal is on and the fourth gate signal is off. In a region where the carrier signal indicated by the thick line is lower than the duty ratio, the first gate signal is turned off and the fourth gate signal is turned on. The first gate signal and the fourth gate signal have a complementary relationship. Note that when the first gate signal and the fourth gate signal are switched on and off, a dead time period is set in which the first gate signal and the fourth gate signal are simultaneously turned off.

Based on the comparison result between the thin line carrier signal and the duty ratio, the second gate signal is supplied to the second switching element S2 and the seventh switching element S7, and the third gate signal is supplied to the third switching element S3 and the sixth switching element S6. Generate a signal. Specifically, in a region where the thin line carrier signal is higher than the duty ratio, the second gate signal is turned on and the third gate signal is turned off. In a region where the thin line carrier signal is lower than the duty ratio, the second gate signal is turned off and the third gate signal is turned on. The second gate signal and the third gate signal have a complementary relationship. Note that when the second gate signal and the third gate signal are switched on and off, a dead time period is set in which the second gate signal and the third gate signal are simultaneously turned off.

When the boost ratio is twice or more, the control unit 40 alternately switches between mode a and mode b, and inserts mode d between switching between the two. That is, the control unit 40 switches the modes in the order of mode a → mode d → mode b → mode d → mode a → mode d → mode b → mode d... While the duty ratio does not change, the periods of mode a and mode b are equal, and the voltages of the first flying capacitor C1 and the second flying capacitor C2 are each maintained at 1/4E. When the boost ratio is twice or more, as the duty ratio increases, the period of mode d becomes longer with respect to the periods of mode a and mode b, and the amount of energy transferred increases.

When the boost ratio is less than twice, the control unit 40 alternately switches between mode a and mode b, and inserts mode c between switching between the two. That is, the control unit 40 switches the modes in the order of mode a→mode c→mode b→mode c→mode a→mode c→mode b→mode c... While the duty ratio does not change, the periods of mode a and mode b are equal, and the voltages of the first flying capacitor C1 and the second flying capacitor C2 are each maintained at 1/4E. When the boost ratio is less than 2 times, the higher the duty ratio is, the shorter the period of mode c is compared to the periods of modes a and b, and the amount of energy transferred increases.

If the step-up ratio ideally maintains 2 times, and the voltages of the first flying capacitor C1 and the second flying capacitor C2 ideally maintain 1/4E, the duty ratio duty maintains 0.5.

When the total voltage of the voltage of the first flying capacitor C1 and the voltage of the second flying capacitor C2 becomes less than 1/2E, the control unit 40 increases the time of the charging mode of mode a and mode b, and Bring the total voltage closer to 1/2E. On the other hand, when the total voltage of the voltage of the first flying capacitor C1 and the voltage of the second flying capacitor C2 exceeds 1/2E, the control unit 40 increases the time of the discharging mode between mode a and mode b. to bring the total voltage closer to 1/2E.

Note that the control unit 40 causes the DC/DC conversion unit 30 to perform normal step-up chopper operation by alternately switching between mode c and mode d without using the first flying capacitor C1 and the second flying capacitor C2. It is also possible to do so. In this case, switching of the operation mode based on the boost ratio does not occur.

Hereinafter, detailed switching patterns including dead time will be described for each of the step-up ratio of 2 times or more, the step-down ratio of 2 times or more, the step-up ratio of less than 2 times, and the step-down ratio of less than 2 times.

FIGS. 7A to 7D are circuit diagrams (part 1) showing transitions of switching patterns when the boost ratio is twice or more. FIGS. 8A to 8D are circuit diagrams showing transitions of switching patterns when the boost ratio is twice or more (part 2). When the boost ratio is twice or more, the control unit 40 changes mode d (FIG. 7(a))→dead time 1 (FIG. 7(b))→mode a (FIG. 7(c))→dead time 1 (FIG. 7(c)). 7(d)) → Mode d (Figure 8(a)) → Dead time 2 (Figure 8(b)) → Mode b (Figure 8(c)) → Dead time 2 (Figure 8(d)) in one cycle , change the switching pattern.

In dead time 1 when the boost ratio is twice or more, the control unit 40 simultaneously turns off the second switching element S2, the third switching element S3, the sixth switching element S6, and the seventh switching element S7. During dead time 1, the second switching element S2 and the seventh switching element S7 are in the off state, so the second switching element S2 and the seventh switching element S7 do not perform synchronous rectification, but the parasitic diode of the second switching element S2 and the seventh switching element S7. A current flows back through the parasitic diode of the switching element S7.

When switching from dead time 1 (FIG. 7(d)) to mode d (FIG. 8(a)), the third switching element S3 and the sixth switching element S6 are turned on. As a result, a reverse bias voltage is applied to the parasitic diode of the second switching element S2 and the parasitic diode of the seventh switching element S7 through which current was flowing in the forward direction, and a recovery current flows in the reverse direction (see R). As a result, the recovery current flows into the third switching element S3 and the sixth switching element S6, so the current flowing when the third switching element S3 and the sixth switching element S6 are turned on increases, and the current flowing when the third switching element S3 and the sixth switching element S6 are turned on increases. Switching loss of switching element S6 increases.

During dead time 2 when the boost ratio is twice or more, the control unit 40 simultaneously turns off the first switching element S1, the fourth switching element S4, the fifth switching element S5, and the eighth switching element S8. During dead time 2, the first switching element S1 and the eighth switching element S8 are in the off state, so the first switching element S1 and the eighth switching element S8 do not perform synchronous rectification, but the parasitic diode of the first switching element S1 and the eighth switching element S8. A current flows back through the parasitic diode of switching element S8.

When switching from dead time 2 (FIG. 8(d)) to mode d (FIG. 7(a)), the fourth switching element S4 and the fifth switching element S5 are turned on. As a result, a reverse bias voltage is applied to the parasitic diode of the first switching element S1 and the parasitic diode of the eighth switching element S8, through which current was flowing in the forward direction, and a recovery current flows in the reverse direction (see R). As a result, the recovery current flows into the fourth switching element S4 and the fifth switching element S5, so the current flowing when the fourth switching element S4 and the fifth switching element S5 are turned on increases, and the current flowing when the fourth switching element S4 and the fifth switching element S5 are turned on increases. Switching loss of switching element S5 increases.

FIGS. 9A to 9D are circuit diagrams (part 1) showing transitions of switching patterns when the step-down ratio is twice or more. FIGS. 10A to 10D are circuit diagrams showing transitions of switching patterns when the step-down ratio is twice or more (part 2). When the step-down ratio is twice or more, the control unit 40 changes mode d (FIG. 9(a))→dead time 1 (FIG. 9(b))→mode a (FIG. 9(c))→dead time 1 (FIG. 9(c)). 9(d)) → Mode d (Figure 10(a)) → Dead time 2 (Figure 10(b)) → Mode b (Figure 10(c)) → Dead time 2 (Figure 10(d)) in one cycle , change the switching pattern.

In dead time 1 when the step-down ratio is twice or more, the control unit 40 simultaneously turns off the second switching element S2, the third switching element S3, the sixth switching element S6, and the seventh switching element S7. In dead time 1, the third switching element S3 and the sixth switching element S6 are in the off state, so the third switching element S3 and the sixth switching element S6 do not perform synchronous rectification, but the parasitic diode of the third switching element S3 and the sixth switching element S6. A current flows back through the parasitic diode of the switching element S6.

When switching from dead time 1 (FIG. 9(b)) to mode a (FIG. 9(c)), the second switching element S2 and the seventh switching element S7 are turned on. As a result, a reverse bias voltage is applied to the parasitic diode of the third switching element S3 and the parasitic diode of the sixth switching element S6, through which current was flowing in the forward direction, and a recovery current flows in the reverse direction (see R). As a result, the recovery current flows into the second switching element S2 and the seventh switching element S7, so the current flowing when the second switching element S2 and the seventh switching element S7 are turned on increases, and the current flowing when the second switching element S2 and the seventh switching element S7 are turned on increases. Switching loss of switching element S7 increases.

During dead time 2 when the step-down ratio is twice or more, the control unit 40 simultaneously turns off the first switching element S1, the fourth switching element S4, the fifth switching element S5, and the eighth switching element S8. During dead time 2, the fourth switching element S4 and the fifth switching element S5 are in the off state, so the fourth switching element S4 and the fifth switching element S5 do not perform synchronous rectification, but the parasitic diode of the fourth switching element S4 and the fifth switching element S5. A current flows back through the parasitic diode of the switching element S5.

When switching from dead time 2 (FIG. 10(b)) to mode b (FIG. 10(c)), the first switching element S1 and the eighth switching element S8 are turned on. As a result, a reverse bias voltage is applied to the parasitic diode of the fourth switching element S4 and the parasitic diode of the fifth switching element S5, through which current was flowing in the forward direction, and a recovery current flows in the reverse direction (see R). As a result, the recovery current flows into the first switching element S1 and the eighth switching element S8, so the current flowing when the first switching element S1 and the eighth switching element S8 are turned on increases, and the current flowing when the first switching element S1 and the eighth switching element S8 are turned on increases. Switching loss of switching element S8 increases.

FIGS. 11(a) to 11(d) are circuit diagrams showing transitions of switching patterns when the boost ratio is less than twice (Part 1). FIGS. 12(a) to 12(d) are circuit diagrams showing transitions of switching patterns when the boost ratio is less than twice (part 2). When the boost ratio is less than twice, the control unit 40 changes mode c (FIG. 11(a))→dead time 1 (FIG. 11(b))→mode a (FIG. 11(c))→dead time 1 (FIG. 11(c)). 11(d)) → Mode c (Figure 12(a)) → Dead time 2 (Figure 12(b)) → Mode b (Figure 12(c)) → Dead time 2 (Figure 12(d)) in one cycle , change the switching pattern.

In dead time 1 when the boost ratio is less than twice, the control unit 40 simultaneously turns off the first switching element S1, the fourth switching element S4, the fifth switching element S5, and the eighth switching element S8. During dead time 1, the first switching element S1 and the eighth switching element S8 are in the off state, so the first switching element S1 and the eighth switching element S8 do not perform synchronous rectification, but the parasitic diode of the first switching element S1 and the eighth switching element S8. A current flows back through the parasitic diode of switching element S8.

When switching from dead time 1 (FIG. 11(b)) to mode a (FIG. 11(c)), the fourth switching element S4 and the fifth switching element S5 are turned on. As a result, a reverse bias voltage is applied to the parasitic diode of the first switching element S1 and the parasitic diode of the eighth switching element S8, through which current was flowing in the forward direction, and a recovery current flows in the reverse direction (see R). As a result, the recovery current flows into the fourth switching element S4 and the fifth switching element S5, so the current flowing when the fourth switching element S4 and the fifth switching element S5 are turned on increases, and the current flowing when the fourth switching element S4 and the fifth switching element S5 are turned on increases. Switching loss of switching element S5 increases.

During dead time 2 when the boost ratio is less than twice, the control unit 40 simultaneously turns off the second switching element S2, the third switching element S3, the sixth switching element S6, and the seventh switching element S7. During dead time 2, the second switching element S2 and the seventh switching element S7 are in the off state, so the second switching element S2 and the seventh switching element S7 do not perform synchronous rectification, but the parasitic diode of the second switching element S2 and the seventh switching element S7. A current flows back through the parasitic diode of the switching element S7.

When switching from dead time 2 (FIG. 12(b)) to mode b (FIG. 12(c)), the third switching element S3 and the sixth switching element S6 are turned on. As a result, a reverse bias voltage is applied to the parasitic diode of the second switching element S2 and the parasitic diode of the seventh switching element S7 through which current was flowing in the forward direction, and a recovery current flows in the reverse direction (see R). As a result, the recovery current flows into the third switching element S3 and the sixth switching element S6, so the current flowing when the third switching element S3 and the sixth switching element S6 are turned on increases, and the current flowing when the third switching element S3 and the sixth switching element S6 are turned on increases. Switching loss of switching element S6 increases.

FIGS. 13(a) to 13(d) are circuit diagrams showing transitions of switching patterns when the step-down ratio is less than 2 times (part 1). FIGS. 14(a) to 14(d) are circuit diagrams showing transitions of switching patterns when the step-down ratio is less than 2 times (Part 2). When the step-down ratio is less than twice, the control unit 40 changes mode c (FIG. 13(a))→dead time 1 (FIG. 13(b))→mode a (FIG. 13(c))→dead time 1 (FIG. 13(c)). 13(d)) → Mode c (Figure 14(a)) → Dead time 2 (Figure 14(b)) → Mode b (Figure 14(c)) → Dead time 2 (Figure 14(d)) in one cycle , change the switching pattern.

In dead time 1 when the step-down ratio is less than twice, the control unit 40 simultaneously turns off the first switching element S1, the fourth switching element S4, the fifth switching element S5, and the eighth switching element S8. During dead time 1, the fourth switching element S4 and the fifth switching element S5 are in the off state, so the fourth switching element S4 and the fifth switching element S5 do not perform synchronous rectification, but the parasitic diode of the fourth switching element S4 and the fifth switching element S5. A current flows back through the parasitic diode of the switching element S5.

When switching from dead time 1 (FIG. 13(d)) to mode c (FIG. 14(a)), the first switching element S1 and the eighth switching element S8 are turned on. As a result, a reverse bias voltage is applied to the parasitic diode of the fourth switching element S4 and the parasitic diode of the fifth switching element S5, through which current was flowing in the forward direction, and a recovery current flows in the reverse direction (see R). As a result, the recovery current flows into the first switching element S1 and the eighth switching element S8, so the current flowing when the first switching element S1 and the eighth switching element S8 are turned on increases, and the current flowing when the first switching element S1 and the eighth switching element S8 are turned on increases. Switching loss of switching element S8 increases.

During dead time 2 when the step-down ratio is less than twice, the control unit 40 simultaneously turns off the second switching element S2, the third switching element S3, the sixth switching element S6, and the seventh switching element S7. During dead time 2, the third switching element S3 and the sixth switching element S6 are in the off state, so the third switching element S3 and the sixth switching element S6 do not perform synchronous rectification, but the parasitic diode of the third switching element S3 and the sixth switching element S6. A current flows back through the parasitic diode of the switching element S6.

When switching from dead time 2 (FIG. 14(d)) to mode c (FIG. 13(a)), the second switching element S2 and the seventh switching element S7 are turned on. As a result, a reverse bias voltage is applied to the parasitic diode of the third switching element S3 and the parasitic diode of the sixth switching element S6, through which current was flowing in the forward direction, and a recovery current flows in the reverse direction (see R). As a result, the recovery current flows into the second switching element S2 and the seventh switching element S7, so the current flowing when the second switching element S2 and the seventh switching element S7 are turned on increases, and the current flowing when the second switching element S2 and the seventh switching element S7 are turned on increases. Switching loss of switching element S7 increases.

The recovery loss caused by the parasitic diode of the MOSFET used as a switching element is too large to be ignored, and reducing the recovery loss caused by the parasitic diode greatly contributes to improving the efficiency of the DC/DC converter 3 as a whole. Hereinafter, a circuit configuration that takes measures against recovery loss will be described.

FIG. 15 is a diagram for explaining the configuration of a DC/DC conversion device 3 according to a comparative example of the first embodiment. In the DC/DC converter 3 according to the comparative example of the first embodiment shown in FIG. 15, each of the first switching element S1 to the eighth switching element S8 of the DC/DC converter 3 shown in FIG. 1 is configured in three parallel configurations. has been done. Thereby, the current flowing through one switching element can be reduced to 1/3. Therefore, the allowable current of one switching element can be lowered, and the size of each switching element can be reduced. Furthermore, the amount of heat generated from one switching element can be reduced. Note that the number of parallel connections is not limited to three. By increasing the number of parallel elements, the amount of heat generated from one switching element can be further reduced. Hereinafter, the plurality of first switching elements S1a-S1c connected in parallel will be collectively referred to as first parallel switching elements S1a-S1c. The same applies to the second switching element S2 to the eighth switching element S8.

FIG. 16 is a diagram for explaining the configuration of the DC/DC converter 3 according to Example 1 of Embodiment 1. In the DC/DC converter 3 according to the first embodiment shown in FIG. 16, the first parallel switching elements S1a-S1b, the second parallel switching elements S2a-S2b, the seventh parallel switching elements S7a-S7b, and the eighth parallel switching element S8a - The number of parallel switching elements S8b is designed to be smaller than the number of parallel switching elements S3a-S3c, fourth parallel switching elements S4a-S4c, fifth parallel switching elements S5a-S5c, and sixth parallel switching elements S6a-S6c. There is. Specifically, the number of parallel connections in the former group is two, and the number of parallel connections in the latter group is three. Note that the number of parallel connections in the former group may be 1. Further, the number of parallel arrays in the latter group may be four or more.

FIG. 17 is a diagram for explaining the configuration of the DC/DC converter 3 according to Example 2 of Embodiment 1. In the DC/DC conversion device 3 according to Example 2 of Embodiment 1 shown in FIG. The number of parallel switching elements S6a-S6b is equal to the number of parallel switching elements S1a-S1c, second parallel switching elements S2a-S2c, seventh parallel switching elements S7a-S7c, and eighth parallel switching elements S8a-S8c. Designed for less. Specifically, the number of parallel connections in the former group is 3, and the number of parallel connections in the latter group is 2. Note that the number of parallel connections in the former group may be 4 or more. Further, the number of parallel connections in the latter group may be one.

In Example 1 of Embodiment 1 shown in FIG. 16, recovery loss during boost operation can be reduced. During boost operation, a recovery current is generated in the first switching element S1, the second switching element S2, the seventh switching element S7, and the eighth switching element S8 (FIG. 7(a), FIG. 8(a), FIG. 11(c)) , see FIG. 12(c)). On the other hand, in Example 1 of Embodiment 1, the first parallel switching elements S1a-S1b, the second parallel switching elements S2a-S2b, the seventh parallel switching elements S7a-S7b, and the eighth parallel switching elements S8a-S8b are By reducing the number of parallel circuits, the amount of recovery current can be reduced.

In Example 2 of Embodiment 1 shown in FIG. 17, recovery loss during voltage step-down operation can be reduced. During step-down operation, a recovery current is generated in the third switching element S3, the fourth switching element S4, the fifth switching element S5, and the sixth switching element S6 (FIG. 9(c), FIG. 10(c), FIG. 13(a)) , see FIG. 14(a)). On the other hand, in Example 2 of Embodiment 1, the third parallel switching elements S3a-S3b, the fourth parallel switching elements S4a-S4b, the fifth parallel switching elements S5a-S5b, and the sixth parallel switching elements S6a-S6b are By reducing the number of parallel circuits, the amount of recovery current can be reduced.

FIG. 18 is a diagram for explaining the configuration of the DC/DC converter 3 according to a modification of Example 1 of Embodiment 1. In the DC/DC converter 3 of Example 1 of Embodiment 1 shown in FIG. 16, the reactor L1 was connected between the positive terminal of the low voltage side DC section and the midpoint of the first flying capacitor circuit 31. In this regard, in the modification shown in FIG. 18, the first reactor L1 is connected between the positive terminal of the low voltage side DC section and the midpoint of the first flying capacitor circuit 31, and the A second reactor L2 is connected between the midpoints of the flying capacitor circuit 32. The first reactor L1 and the second reactor L2 may be configured as magnetically coupled reactors having a common core. In this case, during energization, the magnetic fluxes of the first reactor L1 and the second reactor L2 can be mutually strengthened.

Note that the reactor L1 may be connected between the negative terminal of the low-voltage DC section and the midpoint of the second flying capacitor circuit 32. In this way, the reactor L1 connects the positive side terminal of the low voltage side DC section and the middle point of the first flying capacitor circuit 31, and the path connecting the negative side terminal of the low voltage side DC section and the middle point of the second flying capacitor circuit 32. It is sufficient that it is inserted into at least one of the paths connecting the points. Although not shown, in the DC/DC converter 3 of Example 2 of Embodiment 1 shown in FIG. A reactor L2 may be connected.

FIGS. 19(a) to 19(c) are diagrams showing configuration examples of flying capacitor circuits. FIG. 19(a) shows a one-stage flying capacitor circuit. The flying capacitor circuit shown in FIG. 19(a) has the same circuit configuration as described in the first embodiment above.

FIG. 19(b) shows a two-stage flying capacitor circuit. The two-stage flying capacitor circuit includes six switching elements S12, S1, S2, S3, S4, and S42 connected in series, and two flying capacitors C11 and C12. The innermost flying capacitor C11 is connected in parallel to the two switching elements S2 and S3, and is controlled to maintain a voltage of 1/6E. The second flying capacitor C12 from the inside is connected in parallel to the four switching elements S1, S2, S3, and S4, and is controlled to maintain a voltage of 1/6E.

FIG. 19(c) shows a three-stage flying capacitor circuit. The three-stage flying capacitor circuit includes six switching elements S13, S12, S1, S2, S3, S4, S42, and S43 connected in series, and three flying capacitors C11, C12, and C13. The innermost flying capacitor C11 is connected in parallel to the two switching elements S2 and S3, and is controlled to maintain a voltage of 1/8E. The second flying capacitor C12 from the inside is connected in parallel to the four switching elements S1, S2, S3, and S4, and is controlled to maintain a voltage of 2/8E. The third flying capacitor C13 from the inside is connected in parallel to the six switching elements S12, S1, S2, S3, S4, and S42, and is controlled to maintain a voltage of 3/8E.

FIG. 20 shows a flying capacitor circuit with N stages (N is a natural number). In an N-stage flying capacitor circuit, (2N+2) switching elements S1n,..., S13, S12, S1, S2, S3, S4, S42, S43,..., S4n are connected in series, and N switching elements are connected in series. flying capacitors C11, C12, C13, . . . , C1n. The innermost flying capacitor C11 is connected in parallel to the two switching elements S2 and S3, and is controlled to maintain a voltage of 1/(2N+2)E. The second flying capacitor C12 from the inside is connected in parallel to the four switching elements S1, S2, S3, and S4, and is controlled to maintain a voltage of 2/(2N+2)E. The third flying capacitor C13 from the inside is connected in parallel to the six switching elements S12, S1, S2, S3, S4, and S42, and is controlled to maintain a voltage of 3/(2N+2)E. The outermost flying capacitor C1n is connected to 2N S1(n-1), ..., S13, S12, S1, S2, S3, S4, S42, S43, ..., S4(n-1). are connected in parallel and controlled to maintain a voltage of N/(2N+2)E.

The first flying capacitor circuit 31 and the second flying capacitor circuit 32 shown in FIG. 1 use the one-stage flying capacitor circuit shown in FIG. 19(a). When a one-stage flying capacitor circuit is used, voltages of three levels (E, 1/2E, 0) can be generated between the midpoint of the first flying capacitor circuit 31 and the midpoint of the second flying capacitor circuit 32. becomes possible. When the two-stage flying capacitor circuit shown in FIG. 19(b) is used, five levels (E, 2/3E, It becomes possible to generate a voltage of 1/2E, 1/3E, 0). When the three-stage flying capacitor circuit shown in FIG. 19(c) is used, seven levels (E, 3/4E, It becomes possible to generate voltages of 5/8E, 1/2E, 3/8E, 1/4E, 0). By using the N-stage flying capacitor circuit shown in FIG. 20, it is possible to generate a voltage at the (2N+1) level between the midpoint of the first flying capacitor circuit 31 and the midpoint of the second flying capacitor circuit 32. becomes.

As the number of stages of the flying capacitor circuit increases, switching elements that are inexpensive and have low breakdown voltage can be used, but the number of switching elements used increases. Therefore, the designer only has to consider the total cost and total conversion efficiency to determine the optimal number of stages of the flying capacitor circuit. Furthermore, in applications where the voltage of the high-voltage DC section exceeds 1000 V or 10000 V, it is effective to increase the number of stages of the flying capacitor circuit in order to lower the withstand voltage of each switching element.

In Embodiment 1, regardless of the number of stages of the flying capacitor circuit, the number of parallel switching elements including a switching element to which a diode to which the recovery current should be reduced is connected to the number of parallel switching elements connected to other parallel switching elements. Recovery loss can be reduced by designing the number to be smaller than the number.

FIG. 21 is a diagram for explaining the configuration of the DC/DC converter 3 according to Example 1 of Embodiment 2. The DC/DC converter 3 according to Example 1 of Embodiment 2 is a chopper-type buck-boost DC/DC converter. The DC/DC converter 30 according to Example 1 of the second embodiment includes an upper switching element S1 and a lower switching element S3. The lower switching element S3 is composed of parallel switching elements S3a and S3b in which two switching elements are connected in parallel.

When boosting the voltage, the control unit 40 always controls the upper switching element S1 to be off, and performs PWM control on the lower parallel switching elements S3a and S3b according to the boost ratio. During step-down, the control unit 40 always controls the lower parallel switching elements S3a-S3b to be off, and performs PWM control on the upper switching element S1 according to the step-down ratio.

The larger the boost ratio during boosting, the higher the duty ratio. That is, the on time of the lower parallel switching elements S3a-S3b becomes longer.

While the lower parallel switching elements S3a-S3b are off, a forward current flows through the diode D1 of the upper switching element S1. When the lower parallel switching elements S3a-S3b are turned on, a reverse bias voltage is applied to the diode D1 of the upper switching element S1 through which current was flowing in the forward direction, and a recovery current flows in the reverse direction. As a result, the recovery current flows into the lower parallel switching elements S3a-S3b, so the current flowing when the lower parallel switching elements S3a-S3b are turned on increases, resulting in switching loss of the lower parallel switching elements S3a-S3b. increases.

In contrast, in Example 1 of the second embodiment, the amount of recovery current can be reduced by reducing the number of upper switching elements S1 in parallel than the number of lower switching elements S3 in parallel.

The configuration of Example 1 of Embodiment 2 is a configuration that is more effective as the boost ratio increases. As the boost ratio increases, the current-time product of the lower switching element S3 becomes larger than the current-time product of the upper switching element S1. Therefore, the allowable current of the upper switching element S1 can be lower than the allowable current of the lower switching element S3. That is, the number of parallel switching elements S1 on the upper side can be smaller than the number of parallel switching elements S3 on the lower side.

FIG. 22 is a diagram for explaining the configuration of the DC/DC converter 3 according to Example 2 of Embodiment 2. The DC/DC converter 3 according to Example 2 of Embodiment 2 is also a chopper type buck-boost DC/DC converter. The DC/DC converter 30 according to Example 2 of the second embodiment includes an upper switching element S1 and a lower switching element S3. The upper switching element S1 is composed of parallel switching elements S1a and S1b in which two switching elements are connected in parallel.

When boosting the voltage, the control unit 40 always controls the upper parallel switching elements S1a-S1b to turn off, and performs PWM control on the lower switching element S3 according to the boost ratio. During step-down, the control unit 40 always controls the lower switching element S3 to be off, and performs PWM control on the upper parallel switching elements S1a-S1b according to the step-down ratio.

The smaller the step-down ratio during step-down, the higher the duty ratio. That is, the on time of the upper parallel switching elements S1a-S1b becomes longer.

While the upper parallel switching elements S1a-S1b are off, a forward current flows through the diode D3 of the lower switching element S3. When the upper parallel switching elements S1a-S1b are turned on, a reverse bias voltage is applied to the diode D3 of the lower switching element S3 through which current was flowing in the forward direction, and a recovery current flows in the reverse direction. As a result, the recovery current flows into the upper parallel switching elements S1a-S1b, so the current flowing when the upper parallel switching elements S1a-S1b are turned on increases, and the switching loss of the upper parallel switching elements S1a-S1b increases. .

On the other hand, in Example 2 of the second embodiment, the amount of recovery current can be reduced by reducing the number of lower switching elements S3 in parallel than the number of upper switching elements S1 in parallel.

The configuration of Example 2 of Embodiment 2 is a configuration that is more effective as the step-down ratio is smaller. The smaller the step-down ratio is, the larger the current-time product of the upper switching element S1 is than the current-time product of the lower switching element S3. Therefore, the allowable current of the lower switching element S3 can be lower than the allowable current of the upper switching element S1. That is, the number of parallel switching elements S3 on the lower side can be smaller than the number of parallel switching elements S1 on the upper side.

FIG. 23 is a diagram for explaining the configuration of the DC/DC converter 3 according to Example 1 of Embodiment 3. The DC/DC converter 3 according to Example 1 of Embodiment 3 is an interleaved chopper type buck-boost DC/DC converter. The DC/DC converter 30 according to Example 1 of the third embodiment includes an upper switching element S1 and a lower switching element S3 of the first phase, and an upper switching element S2 and a lower switching element of the second phase. Contains element S4. The lower switching element S3 of the first phase is composed of parallel switching elements S3a-S3b, in which two switching elements are connected in parallel. The lower switching element S4 of the second phase is also composed of parallel switching elements S4a and S4b in which two switching elements are connected in parallel.

During boosting, the control unit 40 always controls the upper switching elements S1 and S3 of the first and second phases to be off, and the lower parallel switching elements S3a-S3b, S4a-S4b of the first and second phases. is PWM controlled according to the boost ratio. In the interleaving method, the control unit 40 alternately turns on/off the lower parallel switching elements S3a-S3b of the first phase and the lower parallel switching elements S4a-S4b of the second phase with a phase shift of 180°. do. In the interleaving method, the current flowing through the output capacitor C6 can be reduced, so the capacitance of the output capacitor C6 can be reduced. The other explanations are the same as the chopper type buck-boost DC/DC converter shown in FIG.

FIG. 24 is a diagram for explaining the configuration of the DC/DC converter 3 according to Example 2 of Embodiment 3. The DC/DC converter 3 according to Example 2 of Embodiment 3 is an interleaved chopper type buck-boost DC/DC converter. The DC/DC converter 30 according to Example 2 of Embodiment 3 includes an upper switching element S1 and a lower switching element S3 of the first phase, and an upper switching element S2 and a lower switching element of the second phase. Contains element S4. The upper switching element S1 of the first phase is composed of parallel switching elements S1a and S1b in which two switching elements are connected in parallel. The upper switching element S2 of the second phase is also composed of parallel switching elements S2a and S2b in which two switching elements are connected in parallel.

During step-down, the control unit 40 always controls the lower switching elements S2 and S4 of the first and second phases to be off, and the upper parallel switching elements S1a-S1b, S3a-S3b of the first and second phases. PWM control is performed according to the step-down ratio. In the interleaving method, the control unit 40 alternately turns on/off the upper parallel switching elements S1a-S1b of the first phase and the upper parallel switching elements S3a-S3b of the second phase with a phase shift of 180°. The other explanations are the same as the chopper type buck-boost DC/DC converter shown in FIG.

The present disclosure has been described above based on the embodiments. It will be understood by those skilled in the art that the embodiments are illustrative, and that various modifications are possible to the combinations of each component and each treatment process, and that such modifications are also within the scope of the present disclosure. .

In the embodiments described above, an example has been described in which MOSFETs are used for the first switching element S1 to the eighth switching element S8. In this respect, the present disclosure is also applicable to the case of using a switching element such as an IGBT (Insulated Gate Bipolar Transistor) in which a parasitic diode is not formed. In this case as well, the recovery current flowing through the external diode can be reduced, and recovery loss can be reduced.

Note that the present disclosure is also applicable when using a switching element configured with a wide bandgap semiconductor using silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga2O3), diamond (C), etc. It is.

Note that the embodiment may be specified by the following items.

[Item 1]
A power conversion device (3) includes a power conversion unit (30) in which a plurality of parallel switching elements (S1) (S1-S8) are connected in series, in which at least one switching element (S1a-S1b) is connected in parallel. hand,
Diodes (D1a-D1b) are formed or connected in antiparallel to each switching element (S1a-S1b),
Among the plurality of parallel switching elements (S1-S8), a parallel switching element (S1) whose number of parallel switching elements is smaller than other parallel switching elements,
Power converter (3).
According to this, recovery loss due to the diode (D1a-D1b) can be reduced.
[Item 2]
The number of parallel switching elements (S1) including a switching element (S1a-S1b) in which diodes (D1a-D1b) to reduce the recovery current are formed or connected in antiparallel is greater than the number of other parallel switching elements in parallel. few,
The power conversion device (3) according to item 1.
According to this, recovery loss caused by the target diode (D1a-D1b) can be reduced.
[Item 3]
at least one reactor (L1) connected to the low-pressure side DC part;
A first flying capacitor circuit (31) and a second flying capacitor circuit (32) connected in series in parallel with the high voltage side DC section,
The positive side terminal of the low voltage side DC section and the midpoint of the first flying capacitor circuit (31) are electrically connected, and the negative side terminal of the low voltage side DC section and the middle point of the second flying capacitor circuit (32) are electrically connected. The midpoints are electrically connected,
The reactor (L1) has a path connecting the positive side terminal of the low voltage side DC section and the midpoint of the first flying capacitor circuit (31), and a path connecting the negative side terminal of the low voltage side DC section and the second flying capacitor circuit (31). inserted into at least one of the paths connecting the midpoints of the capacitor circuit (32),
The first flying capacitor circuit (31) and the second flying capacitor circuit (32) each include a plurality of the parallel switching elements (S1-S8) connected in series.
The power conversion device (3) according to item 1 or 2.
According to this, recovery loss of the diode in the multilevel power conversion device (3) using a flying capacitor can be reduced.
[Item 4]
The first flying capacitor circuit (31) includes:
A first parallel switching element (S1), a second parallel switching element (S2), a third parallel switching element (S3), and a fourth parallel switching element (S4) connected in series,
A connection between the connection point between the first parallel switching element (S1) and the second parallel switching element (S2) and the connection point between the third parallel switching element (S3) and the fourth parallel switching element (S4). a first flying capacitor (C1),
The second flying capacitor circuit (32) includes:
A fifth parallel switching element (S5), a sixth parallel switching element (S6), a seventh parallel switching element (S7), and an eighth parallel switching element (S8) connected in series,
A connection between the connection point between the fifth parallel switching element (S5) and the sixth parallel switching element (S6) and the connection point between the seventh parallel switching element (S7) and the eighth parallel switching element (S8). a second flying capacitor (C2),
The power conversion device (3) according to item 3.
According to this, recovery loss of the diode in the three-level power conversion device (3) using flying capacitors can be reduced.
[Item 5]
the number of parallel switching elements of the first parallel switching element (S1a-S1b), the second parallel switching element (S2a-S2b), the seventh parallel switching element (S7a-S7b), and the eighth parallel switching element (S8a-S8b); is the third parallel switching element (S3a-S3c), the fourth parallel switching element (S4a-S4c), the fifth parallel switching element (S5a-S5c), and the sixth parallel switching element (S6a-S6c). less than the number of parallel
The power conversion device (3) according to item 4.
According to this, recovery loss caused by the diodes (D1-D2, D7-D8) during boost operation can be reduced.
[Item 6]
the number of the third parallel switching elements (S3a-S3b), the fourth parallel switching elements (S4a-S4b), the fifth parallel switching elements (S5a-S5b), and the sixth parallel switching elements (S6a-S6b) in parallel; is the first parallel switching element (S1a-S1c), the second parallel switching element (S2a-S2c), the seventh parallel switching element (S7a-S7c), and the eighth parallel switching element (S8a-S8c). less than the number of parallel
The power conversion device (3) according to item 4.
According to this, it is possible to reduce recovery loss due to the diodes (D3-D6) during step-down operation.
[Item 7]
The first flying capacitor circuit (31) and the second flying capacitor circuit (32) are controlled to transfer power from the low-voltage side DC section to the high-voltage side DC section by step-up operation, and from the high-voltage side DC section to the further comprising a control unit (40) capable of performing at least one of power transmission by step-down operation to the low voltage side DC section,
The control unit (40) includes:
the second parallel switching element (S2), the fourth parallel switching element (S4), the fifth parallel switching element (S5), and the seventh parallel switching element (S7) are in an on state, and the first parallel switching element (S1), a first mode in which the third parallel switching element (S3), the sixth parallel switching element (S6), and the eighth parallel switching element (S8) are controlled to an OFF state;
The first parallel switching element (S1), the third parallel switching element (S3), the sixth parallel switching element (S6), and the eighth parallel switching element (S8) are in an on state, and the second parallel switching element (S2), a second mode in which the fourth parallel switching element (S4), the fifth parallel switching element (S5), and the seventh parallel switching element (S7) are controlled to an OFF state;
The first parallel switching element (S1), the second parallel switching element (S2), the seventh parallel switching element (S7), and the eighth parallel switching element (S8) are in an on state, and the third parallel switching element (S3), a third mode in which the fourth parallel switching element (S4), the fifth parallel switching element (S5), and the sixth parallel switching element (S6) are controlled to an OFF state;
The third parallel switching element (S3), the fourth parallel switching element (S4), the fifth parallel switching element (S5), and the sixth parallel switching element (S6) are in an on state, and the first parallel switching element (S1), a fourth mode in which the second parallel switching element (S2), the seventh parallel switching element (S7), and the eighth parallel switching element (S8) are controlled to an OFF state;
performing the step-up operation or the step-down operation using four modes;
The power conversion device (3) according to any one of items 4 to 6.
According to this, various controls can be performed by combining the four modes.
[Item 8]
The switching elements (S1-S8) are N-channel MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors),
The diodes (D1-D8) are parasitic diodes of the N-channel MOSFET,
The power conversion device (3) according to any one of items 1 to 7.
According to this, recovery loss due to freewheeling current flowing through the parasitic diode can be reduced.

1 First DC power supply, 2 Second DC power supply, 3 DC/DC converter, 30 DC/DC converter, 31, 32 Flying capacitor circuit, 40 Control unit, C1, C2 Flying capacitor, C3, C4 Split capacitor, C5 Input capacitor, C6 output capacitor, L1, L2 reactor, S1-S8 switching element, D1-D8 diode.

Claims (7)

at least one reactor connected to the low pressure side DC part;
A first flying capacitor circuit and a second flying capacitor circuit connected in series in parallel with the high voltage side DC section,
The first flying capacitor circuit and the second flying capacitor circuit each include a plurality of parallel switching elements connected in series,
The positive side terminal of the low voltage side DC section and the first midpoint of the series circuit of the plurality of parallel switching elements included in the first flying capacitor circuit are electrically connected, and the negative side terminal of the low voltage side DC section is electrically connected. and a second midpoint of a series circuit of the plurality of parallel switching elements included in the second flying capacitor circuit are electrically connected,
The reactor is connected to at least one of a path connecting between the positive side terminal of the low voltage side DC section and the first midpoint, and a path connecting between the negative side terminal of the low voltage side DC section and the second midpoint. inserted,
The parallel switching element has at least one switching element connected in parallel,
A diode is formed or connected in antiparallel to each switching element,
Among the plurality of parallel switching elements, including a parallel switching element whose number of parallel switching elements is smaller than other parallel switching elements,
Power converter. The number of parallel switching elements including a switching element in which diodes to reduce the recovery current are formed or connected in antiparallel is smaller than the number of other parallel switching elements.
The power conversion device according to claim 1. The first flying capacitor circuit includes:
A first parallel switching element, a second parallel switching element, a third parallel switching element, and a fourth parallel switching element connected in series,
a first flying capacitor connected between a connection point between the first parallel switching element and the second parallel switching element and a connection point between the third parallel switching element and the fourth parallel switching element;
The second flying capacitor circuit includes:
A fifth parallel switching element, a sixth parallel switching element, a seventh parallel switching element, and an eighth parallel switching element connected in series,
a second flying capacitor connected between a connection point between the fifth parallel switching element and the sixth parallel switching element and a connection point between the seventh parallel switching element and the eighth parallel switching element;
The power conversion device according to claim 1 . The number of parallel switching elements of the first parallel switching element, the second parallel switching element, the seventh parallel switching element, and the eighth parallel switching element is the third parallel switching element, the fourth parallel switching element, and the fifth parallel switching element. less than the number of parallel switching elements and the sixth parallel switching element;
The power conversion device according to claim 3 . The number of parallel switching elements of the third parallel switching element, the fourth parallel switching element, the fifth parallel switching element, and the sixth parallel switching element is the same as that of the first parallel switching element, the second parallel switching element, and the seventh parallel switching element. less than the number of parallel switching elements and the eighth parallel switching element;
The power conversion device according to claim 3 . The first flying capacitor circuit and the second flying capacitor circuit are controlled to transmit power from the low-voltage side DC section to the high-voltage side DC section by step-up operation, and from the high-voltage side DC section to the low-voltage side DC section. further comprising a control unit capable of executing at least one of power transmission in operation,
The control unit includes:
The second parallel switching element, the fourth parallel switching element, the fifth parallel switching element, and the seventh parallel switching element are turned on, and the first parallel switching element, the third parallel switching element, and the sixth parallel switching element are turned on. a first mode in which the switching element and the eighth parallel switching element are controlled to be in an off state;
The first parallel switching element, the third parallel switching element, the sixth parallel switching element, and the eighth parallel switching element are turned on, and the second parallel switching element, the fourth parallel switching element, and the fifth parallel switching element are turned on. a second mode of controlling the switching element and the seventh parallel switching element to an off state;
The first parallel switching element, the second parallel switching element, the seventh parallel switching element, and the eighth parallel switching element are turned on, and the third parallel switching element, the fourth parallel switching element, and the fifth parallel switching element are turned on. a third mode of controlling the switching element and the sixth parallel switching element to an off state;
The third parallel switching element, the fourth parallel switching element, the fifth parallel switching element, and the sixth parallel switching element are turned on, and the first parallel switching element, the second parallel switching element, and the seventh parallel switching element are turned on. a fourth mode of controlling the switching element and the eighth parallel switching element to an off state;
performing the step-up operation or the step-down operation using four modes;
The power conversion device according to any one of claims 3 to 5 . The switching element is an N-channel MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor),
the diode is a parasitic diode of the N-channel MOSFET;
The power conversion device according to any one of claims 1 to 6 .

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