JP7549474B2 - Semiconductor Device - Google Patents

Description

The present invention relates to a semiconductor device including a memory structure.

For example, the following Patent Document 1 is a document disclosing a semiconductor device equipped with a non-volatile memory. In the memory cell provided in the semiconductor device disclosed in Patent Document 1, a charge storage section is formed from above a resistance change section formed on the surface portion of the p-well region to the side wall of the gate electrode.

JP 2005-064295 A

In the memory cell disclosed in Patent Document 1, it is required to increase the amount of carriers (electrons and holes) captured in the charge storage portion, thereby increasing the amount of change in threshold voltage and current capability before and after writing.
SUMMARY OF THE PRESENT EMBODIMENTS Accordingly, one object of the present invention is to provide a semiconductor device in which a memory structure is arranged adjacent to a side of a planar gate structure, and in which the amount of carriers captured by the memory structure is increased.

One embodiment of the present invention provides a semiconductor device including: a semiconductor layer having a main surface; a source region and a drain region formed on a surface portion of the main surface of the semiconductor layer with a gap between them; a planar gate structure disposed between the source region and the drain region, the planar gate structure having a source sidewall portion facing the source region in a planar view and a drain sidewall portion facing the drain region in a planar view, the source sidewall portion having a first gate bend recessed toward the drain region; and a memory structure disposed adjacent to the source sidewall portion and the drain sidewall portion, the memory structure having a first memory bend along the first gate bend.

In this device, the memory structure is disposed adjacent to the source sidewall and drain sidewall of the planar gate structure. Carriers are primarily captured by the portion of the memory structure adjacent to the source sidewall. Therefore, if a wide portion is provided in the portion of the memory structure adjacent to the source sidewall, the amount of carriers captured by the memory structure can be increased.

Therefore, if the source sidewall of the planar gate structure has a first gate bend recessed toward the drain region, the width of the memory structure at the first memory bend can be made larger than the width of the memory structure in the portion other than the first memory bend. In other words, a wide portion can be provided in the portion of the memory structure adjacent to the source sidewall of the planar gate structure. This can increase the amount of carriers captured by the memory structure.

FIG. 1 is a plan view of a main portion of a semiconductor device according to a first embodiment of the present invention. FIG. 2 is a cross-sectional view taken along the line II-II shown in FIG. FIG. 3 is an enlarged view of region III shown in FIG. FIG. 4 is a cross-sectional view taken along the line IV-IV shown in FIG. FIG. 5 is an enlarged view of the V region shown in FIG. FIG. 6A is a schematic diagram for explaining the state of an electric circuit before a write operation of a memory structure provided in the semiconductor device. FIG. 6B is a schematic diagram for explaining a write operation of the memory structure. FIG. 6C is a schematic diagram for explaining the erase operation of the memory structure. FIG. 6D is a schematic diagram for explaining a read operation of the memory structure after the write operation. FIG. 6E is a schematic diagram for explaining a read operation of the memory structure after the erase operation. FIG. 7 is a graph showing the relationship between the gate potential and the drain-source current after the write operation and after the erase operation. FIG. 8A is a cross-sectional view for explaining an example of a method for manufacturing the semiconductor device. FIG. 8B is a cross-sectional view showing a step subsequent to that of FIG. 8A. FIG. 8C is a cross-sectional view showing a step subsequent to FIG. 8B. FIG. 8D is a cross-sectional view showing a step subsequent to FIG. 8C. FIG. 8E is a cross-sectional view showing a step subsequent to FIG. 8D. FIG. 8F is a cross-sectional view showing a step subsequent to FIG. 8E. FIG. 8G is a cross-sectional view showing a step subsequent to FIG. 8F. FIG. 8H is a cross-sectional view showing a step subsequent to FIG. 8G. FIG. 8I is a cross-sectional view showing a step subsequent to FIG. 8H. FIG. 8J is a cross-sectional view showing a step subsequent to FIG. 8I. FIG. 8K is a cross-sectional view showing a step subsequent to FIG. 8J. FIG. 8L is a cross-sectional view showing a step subsequent to FIG. 8K. FIG. 8M is a cross-sectional view showing a step subsequent to FIG. 8L. FIG. 8N is a cross-sectional view showing a step subsequent to FIG. 8M. FIG. 8O is a cross-sectional view showing a step subsequent to FIG. 8N. FIG. 8P is a cross-sectional view showing a step subsequent to that of FIG. 8O. FIG. 8Q is a cross-sectional view showing a step subsequent to FIG. 8P. FIG. 8R is a cross-sectional view showing a step subsequent to FIG. 8Q. FIG. 8S is a cross-sectional view showing a step subsequent to FIG. 8R. FIG. 8T is a cross-sectional view showing a step subsequent to FIG. 8S. FIG. 8U is a cross-sectional view showing a step subsequent to FIG. 8T. FIG. 8V is a cross-sectional view showing a step subsequent to FIG. 8U. FIG. 8W is a cross-sectional view showing a step subsequent to FIG. 8V. FIG. 8X is a cross-sectional view showing a step subsequent to FIG. 8W. FIG. 8Y is a cross-sectional view showing a step subsequent to that of FIG. 8X. FIG. 9 is a schematic diagram for explaining how the memory structure is formed by etching in the method for manufacturing the semiconductor device. FIG. 10A is a plan view of a main part of a semiconductor device according to a second embodiment of the present invention. FIG. 10B is an enlarged view of the XB region shown in FIG. 10A. FIG. 10C is an enlarged view of region XC shown in FIG. 10A. FIG. 11A is a plan view of a main part of a semiconductor device according to a third embodiment of the present invention. FIG. 11B is an enlarged view of region XIB shown in FIG. 11A. FIG. 12A is a plan view of a main part of a semiconductor device according to a fourth embodiment of the present invention. FIG. 12B is an enlarged view of region XIIB shown in FIG. 12A. FIG. 13A is a plan view of a main part of a semiconductor device according to a fifth embodiment of the present invention. FIG. 13B is an enlarged view of region XIIIB shown in FIG. 13A.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
First Embodiment
Fig. 1 is a plan view of a main portion of a semiconductor device 1 according to a first embodiment of the present invention. Fig. 2 is a cross-sectional view taken along line II-II shown in Fig. 1. Fig. 3 is an enlarged view of region III shown in Fig. 1. Fig. 4 is a cross-sectional view taken along line IV-IV shown in Fig. 1. Fig. 5 is an enlarged view of region V shown in Fig. 2. The configuration of the semiconductor device 1 will be described below with reference to Figs. 1 to 5.

1, a cover insulating film 51, an interlayer insulating film 65, a gate wiring 70, a source wiring 71, and a drain wiring 72, which will be described later, have been removed. The semiconductor device 1 is a non-volatile memory using a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The semiconductor device 1 includes a semiconductor layer 2. The semiconductor layer 2 is made of, for example, single crystal Si.
2 , the semiconductor layer 2 has a first main surface 3 on one side and a second main surface 4 on the other side. The semiconductor device 1 includes a p-type (first conductivity type) back gate region 20 formed in the semiconductor layer 2. The back gate region 20 is formed in the entire semiconductor layer 2.

The semiconductor device 1 includes a trench insulation structure 10 that defines a device region 6 in which a MOSFET is formed. The trench insulation structure 10 includes a trench 11 and an insulating filling 12. The trench 11 is formed by digging down the first main surface 3 toward the second main surface 4.
1 , the trench 11 is formed in a rectangular ring shape in a plan view seen from a normal direction Z of the first main surface 3 and the second main surface 4 (hereinafter simply referred to as a "plan view"), and defines a rectangular device region 6. A direction in which one side of the device region 6 extends in the plan view is defined as a first direction X. A direction perpendicular to both the first direction X and the normal direction Z is defined as a second direction Y.

Referring to FIG. 2, the trench 11 specifically includes an inner wall 13 on one side, an outer wall 14 on the other side, and a bottom wall 15 connecting the inner wall 13 and the outer wall 14. The inner wall 13 is formed in a rectangular ring shape in a plan view. The outer wall 14 is formed in a rectangular ring shape extending parallel to the inner wall 13 in a plan view. The outer wall 14 does not necessarily need to extend parallel to the inner wall 13, and may be formed in a shape different from the inner wall 13. The bottom wall 15 extends parallel to the first main surface 3. The bottom wall 15 may be formed in a curved shape toward the second main surface 4.

In this embodiment, the trench 11 is formed in a tapered shape with the opening width narrowing toward the bottom wall 15. The taper angle of the trench 11 may be greater than 90° and less than or equal to 125°. The taper angle is preferably greater than 90° and less than or equal to 100°. The taper angle of the trench 11 is the angle between the inner wall 13 (outer wall 14) of the trench 11 and the first major surface 3 in the semiconductor layer 2. Of course, the trench 11 may be formed perpendicular to the first major surface 3.

The depth of the trench 11 may be 0.1 μm or more and 1 μm or less. The width of the trench 11 is arbitrary. The width of the trench 11 may be 0.1 μm or more and 10 μm or less. The width of the trench 11 is defined by the width in a direction perpendicular to the direction in which the trench 11 extends in a plan view.
The insulating filling material 12 is buried in the trench 11. Any insulator may be used to form the insulating filling material 12. The insulating filling material 12 may include at least one of silicon oxide (SiO ₂ ) and silicon nitride (SiN). In this embodiment, the insulating filling material 12 is made of silicon oxide.

The insulating filling material 12 includes a buried portion 17 and a protruding portion 18. The buried portion 17 is located on the bottom wall 15 side of the trench 11 with respect to an opening end 16 of the trench 11. The protruding portion 18 protrudes from the buried portion 17 toward the side opposite to the bottom wall 15 side.
The semiconductor device 1 includes a well region 21 formed in a surface portion of the first main surface 3 in the device region 6. The well region 21 is a p-type (first conductivity type) impurity region. The p-type impurity concentration of the well region 21 exceeds the p-type impurity concentration of the back gate region 20. The p-type impurity concentration of the well region 21 is, for example, not less than 10×10 ¹² cm ⁻³ and not more than 10×10 ¹⁶ cm ⁻³ .

The bottom of the well region 21 is electrically connected to the back gate region 20. In this embodiment, the well region 21 is formed deeper than the trench 11 and partially covers the bottom wall 15 of the trench 11. Unlike this embodiment, the well region 21 is formed in a region on the first main surface 3 side of the bottom wall 15 of the trench 11, and the boundary between the well region 21 and the back gate region 20 may be located between the bottom wall 15 of the trench 11 and the first main surface 3.

The semiconductor device 1 includes a source region 22 and a drain region 23 formed in a surface layer portion of a first main surface 3 of a semiconductor layer 2 with a gap between them in a second direction Y. The source region 22 and the drain region 23 are n-type (second conductivity type) impurity regions formed in a surface portion of a well region 21. The n-type impurity concentrations of the source region 22 and the drain region 23 are, for example, not less than 10×10 ¹⁶ cm ⁻³ and not more than 10×10 ²⁰ cm ⁻³ .

A p-type (first conductivity type) channel region 24 is formed between the drain region 23 and the source region 22 in the surface portion of the device region 6. The channel region 24 forms a current path along the second direction Y between the source region 22 and the drain region 23.
The source region 22 has a bottom located on the first main surface 3 side with respect to the bottom of the well region 21. The drain region 23 has a bottom located on the first main surface 3 side with respect to the bottom of the well region 21.

The bottom of the source region 22 is flat without any step. More specifically, the source region 22 is in contact with the channel region 24, and no low-concentration source region having a lower n-type impurity concentration than the source region 22 is provided between the source region 22 and the channel region 24. Unlike the example shown in FIG. 2, a step may be provided at the bottom of the source region 22, and a low-concentration source region may be provided between the source region 22 and the channel region 24.

The bottom of the drain region 23 is flat without any steps. More specifically, the drain region 23 is in contact with the channel region 24, and no low-concentration drain region having a lower n-type impurity concentration than the drain region 23 is provided between the drain region 23 and the channel region 24. Unlike the example shown in FIG. 2, a low-concentration drain region may be provided between the drain region 23 and the channel region 24.

The semiconductor device 1 includes a planar gate structure 30 formed on the first major surface 3 in the device region 6 so as to face the channel region 24 .
1, the planar gate structure 30 is formed in a substantially L-shape in a plan view such that a bent portion 30C is located within the device region 6. In detail, the planar gate structure 30 includes a first straight portion 30A and a second straight portion 30B that is connected to the first straight portion 30A and intersects with the first straight portion 30A.

The first straight portion 30A and the second straight portion 30B are perpendicular to each other. The first straight portion 30A and the second straight portion 30B both extend in a direction different from the first direction X and the second direction Y. The first straight portion 30A extends at an angle of 45° with respect to the first direction X. The portion where the first straight portion 30A and the second straight portion 30B intersect is the bent portion 30C.
Unlike the example shown in FIG. 1, the first straight portion 30A and the second straight portion 30B are not perpendicular to each other, and the angle formed between the first straight portion 30A and the second straight portion 30B may be, for example, 60°.

The planar gate structure 30 has a source sidewall 37 and a drain sidewall 38 located in the device region 6. In a plan view, the source sidewall 37 faces the source region 22, and the drain sidewall 38 faces the drain region 23.
An end of the planar gate structure 30 in the first direction X reaches above the trench isolation structure 10. Unlike the example shown in Fig. 1, the end of the planar gate structure 30 in the first direction X may be located outside the trench isolation structure 10. The bent portion 30C of the planar gate structure 30 is located between the source region 22 and the drain region 23.

With reference to FIG. 2 , the planar gate structure 30 includes a gate insulating film 31 formed on the semiconductor layer 2 in the device region 6 , and a gate electrode 32 formed on the gate insulating film 31 .
The gate insulating film 31 is made of an oxide of the semiconductor layer 2. Specifically, the gate insulating film 31 is made of an oxide formed in a film shape by oxidizing the surface portion of the first main surface 3. That is, the gate insulating film 31 is made of a silicon oxide film ( _SiO2 film) formed along the first main surface 3. More specifically, the gate insulating film 31 is made of a thermal oxide of the semiconductor layer 2 formed in a film shape by thermally oxidizing the surface portion of the first main surface 3 of the semiconductor layer 2. That is, the gate insulating film 31 is made of a silicon thermal oxide film (thermal oxide film) formed along the first main surface 3.

Referring to FIG. 5, the gate insulating film 31 may have a thickness T1 of 7 nm or more and 13 nm or less. The thickness T1 of the gate insulating film 31 may be, for example, 10 nm. The gate insulating film 31 has a first surface 31a in contact with the first main surface 3 and a second surface 31b on the opposite side of the first surface 31a from the semiconductor layer 2. The first surface 31a and the second surface 31b may extend parallel to each other, and the gate insulating film 31 may have a substantially constant thickness. Both ends of the gate insulating film 31 in the first direction X are connected to the insulating filling 12 (see FIG. 4).

In the first main surface 3, recesses 33 are formed on both sides of the gate insulating film 31 to recess the first main surface 3 toward the second main surface 4. The recesses 33 may be formed in the entire area between the gate insulating film 31 and the protruding portion 18 of the insulating filling 12 in the device region 6.
The gate electrode 32 is made of conductive polysilicon. The gate electrode 32 is formed on the gate insulating film 31. The width (gate length) of the gate electrode 32 in the second direction Y may be 0.13 μm or more and 0.3 μm or less.

1 and 4, the gate electrode 32 crosses the opening end 16 of the trench 11 and reaches above the insulating filling 12. In detail, the gate electrode 32 includes a main body portion 35 facing the first main surface 3 in the device region 6 with the gate insulating film 31 therebetween, and an extension portion 36 facing the insulating filling 12 on the outer side of the device region 6.
The main body 35 is formed in the shape of a film extending along the gate insulating film 31 on the gate insulating film 31. The lead-out portion 36 is led out from the main body 35 onto the protruding portion 18 of the insulating filling 12.

1, the semiconductor device 1 includes a memory structure 40 capable of writing, erasing, and reading data. The memory structure 40 is disposed adjacent to the side of the planar gate structure 30 so as to cover the sidewall of the gate electrode 32. Therefore, the memory structure 40 is also called a sidewall structure.
Specifically, the memory structure 40 covers the sidewall of the main body portion 35 of the gate electrode 32 in the device region 6 , and covers the sidewall of the drawn-out portion 36 outside the device region 6 .

The memory structure 40 is disposed adjacent to the planar gate structure 30. In a plan view, the memory structure 40 is annular and surrounds the planar gate structure 30. The memory structure 40 is composed of a source side portion 40A and a drain side portion 40B located in the device region 6, and a pair of connecting portions 40C that connect the source side portion 40A and the drain side portion 40B.

The source side portion 40A is a portion located between the source region 22 and the planar gate structure 30 in a planar view. The drain side portion 40B is a portion located between the drain region 23 and the planar gate structure 30 in a planar view. Each coupling portion 40C is a portion of the memory structure 40 located on an insulating filling 12.
The memory structure 40 is disposed adjacent the source sidewall 37 and the drain sidewall 38 of the planar gate structure 30. In particular, a source side portion 40A of the memory structure 40 is disposed adjacent the source sidewall 37, and a drain side portion 40B of the memory structure 40 is disposed adjacent the drain sidewall 38.

Referring to FIG. 3, in the bent portion 30C, the drain sidewall portion 38 is the outer wall portion, and the source sidewall portion 37 is the inner wall portion. The source sidewall portion 37 has a first gate bent portion 100 recessed toward the drain region 23 side in the bent portion 30C, and a first gate non-bent portion 101 other than the first gate bent portion 100 in the bent portion 30C. The source side portion 40A of the memory structure 40 includes a first memory bent portion 110 along the first gate bent portion 100, and a first memory non-bent portion 111 along the first gate non-bent portion 101.

The source sidewall portion 37 of the planar gate structure 30 has a first source side edge 37a and a second source side edge 37b that extend linearly and face each other across the first memory bend 110 in a plan view, and an apex 37c where the first source side edge 37a and the second source side edge 37b intersect. The first gate bend 100 is provided on the apex 37c. It is preferable that the angle that the first source side edge 37a and the second source side edge 37b form within the memory structure 40 is 90° or less.

The source side portion 40A of the memory structure 40 has a third source side edge 120 extending parallel to the first source side edge 37a, a fourth source side edge 121 extending parallel to the second source side edge 37b, and an apex 122 where the third source side edge 120 and the fourth source side edge 121 intersect. The first memory bend 110 is the portion between the apex 122 of the source side portion 40A and the apex 37c of the source sidewall portion 37 in a plan view.

The width W1 of the source side portion 40A is the shortest distance between the end of the source side portion 40A on the source region 22 side and the source sidewall portion 37. The width W1 of the source side portion 40A differs between the first memory bent portion 110 and the first memory non-bent portion 111.
The width W1 (first bend width (third width) BW1) of the source side portion 40A in the first memory bend 110 is the shortest distance between the first gate bend 100 and the end of the first memory bend 110 on the source region 22 side. The first bend width BW1 is the distance between the top 37c of the source sidewall 37 and the top 122 of the source side portion 40A.

The width W1 (first non-bent portion width (first width) NW1) of the source side portion 40A in the first memory non-bent portion 111 is the shortest distance between the first gate non-bent portion 101 and the end portion on the source region 22 side in the first memory non-bent portion 111. The first non-bent portion width NW1 is the distance between the first source side edge 37a of the source sidewall portion 37 and the third source side edge 120 of the source side portion 40A, or the distance between the second source side edge 37b of the source sidewall portion 37 and the fourth source side edge 121 of the source side portion 40A. The first bent portion width BW1 is larger than the first non-bent portion width NW1.

The drain side wall 38, which is the outer wall, has a first side 130 (drain side gate non-bent portion) and a second side (drain side gate non-bent portion) 131 which extend linearly and face each other across the planar gate structure 30 in a planar view, and an apex (drain side gate bent portion) 132 where the first side 130 and the second side 131 intersect.
In a plan view, the drain side portion 40B has a third side 140 extending parallel to the first side 130, a fourth side 141 extending parallel to the second side 131, and an arc-shaped curved side 142 connecting the third side 140 and the fourth side 141. Therefore, the width (second width, fourth width) W2 of the drain side portion 40B is almost constant over the entire area of the drain side portion 40B. The width W2 of the drain side portion 40B is the shortest distance between the end of the drain side portion 40B on the drain region 23 side and the drain sidewall portion 38.

The width W2 of the drain side portion 40B is approximately equal to the first non-bent portion width NW1 and is smaller than the first bent portion width BW1. That is, the drain side portion 40B does not have a wide portion, and the source side portion 40A has the first memory bent portion 110 as a wide portion.
2, the memory structure 40 has an inner side surface 40a along the sidewall of the planar gate structure 30 and an outer side surface 40b curved to protrude toward the side opposite to the planar gate structure 30. The memory structure 40 includes an insulating film 41 formed on the channel region 24, a charge storage film 42 facing the channel region 24 with the insulating film 41 interposed therebetween, and an insulating spacer 43 formed on the charge storage film 42.

The insulating film 41 is made of an oxide of the semiconductor layer 2 and the gate electrode 32. Specifically, the insulating film 41 is made of an oxide formed in a film shape by oxidizing the surface portion of the semiconductor layer 2 and the sidewall of the gate electrode 32. The insulating film 41 is made of a silicon oxide film ( _SiO2 film) formed along the first main surface 3 and the side surface of the gate electrode 32. More specifically, the insulating film 41 is made of a thermal oxide formed in a film shape by thermally oxidizing the surface portion of the semiconductor layer 2 and the sidewall of the gate electrode 32. That is, the insulating film 41 is made of a silicon thermal oxide film formed along the first main surface 3 and the side surface of the gate electrode 32.

5, the insulating film 41 may have a thickness T2 of 5 nm or more and 10 nm or less. The thickness T2 of the insulating film 41 may be, for example, 8 nm. It is preferable that the insulating film 41 is thinner than the gate insulating film 31 (T2<T1).
The insulating film 41 has a first surface 41a in contact with the first main surface 3 of the semiconductor layer 2, a second surface 41b located on the opposite side of the semiconductor layer 2 from the first surface 41a, a third surface 41c in contact with the sidewall of the planar gate structure 30 (the sidewall of the gate electrode 32), and a fourth surface 41d located on the opposite side of the planar gate structure 30 from the third surface 41c.

The insulating film 41 includes a first insulating portion 46 extending along the first main surface 3 of the semiconductor layer 2 in the device region 6, and a second insulating portion 47 connected to the first insulating portion 46 and extending along the sidewall of the planar gate structure 30. The insulating film 41 may be formed in an L-shape in cross section by orthogonally connecting the first insulating portion 46 and the second insulating portion 47.
The width of the first insulating portion 46 in the first memory bend 110 is wider than the width of the first insulating portion 46 in locations other than the first memory bend 110 (the first memory non-bend portion 111 of the source side portion 40A and the drain side portion 40B) (see also Figure 3).

4, the insulating film 41 is made of oxides of the semiconductor layer 2 and the gate electrode 32, and is therefore not formed on the insulating filling material 12. Since the insulating film 41 is not formed on the insulating filling material 12, the first insulating portion 46 is not provided in the connecting portion 40C of the memory structure 40.
5, the insulating film 41 is formed on the first main surface 3 in the recess 33 and is adjacent to the gate insulating film 31. The first insulating portion 46 is located closer to the second main surface 4 than the gate insulating film 31. The first surface 41a of the insulating film 41 may be located closer to the second main surface 4 (see also FIG. 2) than the first surface 31a of the gate insulating film 31. The second surface 41b of the insulating film 41 may be formed flush with the first surface 31a of the gate insulating film 31.

The charge storage film 42 is made of an insulator different from the insulating film 41, for example, a silicon nitride film (SiN film). The charge storage film 42 is formed along the insulating film 41. The charge storage film 42 may have a thickness T3 of 10 nm or more and 50 nm or less. The thickness T3 of the charge storage film 42 may be, for example, 30 nm.
The charge storage film 42 has a ring shape surrounding the planar gate structure 30 in a plan view. That is, both ends of the charge storage film 42 in the first direction X are located outside the device region 6 (see also FIG. 4 ). In the example of FIG. 4 , the ends of the charge storage film 42 in the first direction X are located on the insulating filling 12.

The charge storage film 42 includes a first storage portion 48 formed on the first insulating portion 46 of the insulating film 41, and a second storage portion 49 connected to the first storage portion 48 and formed on the side of the second insulating portion 47. The charge storage film 42 may be formed in an L-shape in cross section by connecting the first storage portion 48 and the second storage portion 49 perpendicularly to each other.
The width of the first storage portion 48 in the first memory bend 110 is wider than the width of the first storage portion 48 in locations other than the first memory bend 110 (the first memory non-bend portion 111 of the source side portion 40A and the drain side portion 40B) (see also Figure 3).

The first accumulation portion 48 faces the insulating filling object 12 outside the device region 6 (see also FIG. 4). The first accumulation portion 48 faces the semiconductor layer 2 in the device region 6 with the first insulating portion 46 of the insulating film 41 therebetween. The second accumulation portion 49 faces the planar gate structure 30 with the second insulating portion 47 of the insulating film 41 therebetween (see also FIG. 4).
The source region 22 and the drain region 23 are formed in a self-aligned manner with respect to the memory structure 40. Therefore, the boundary between the source region 22 and the channel region 24, in a plan view, approximately coincides with the boundary between the outer side surface 40b of the memory structure 40 and the first main surface 3. Similarly, the boundary between the drain region 23 and the channel region 24, in a plan view, approximately coincides with the boundary between the outer side surface 40b of the memory structure 40 and the first main surface 3.

Strictly speaking, the boundary between the source region 22 and the channel region 24 is located slightly closer to the planar gate structure 30 than the boundary between the outer side surface 40b of the memory structure 40 and the first main surface 3. Similarly, the boundary between the drain region 23 and the channel region 24 is also located slightly closer to the planar gate structure 30 than the boundary between the outer side surface 40b of the memory structure 40 and the first main surface 3.
Therefore, the first accumulation portion 48 of the charge accumulation film 42 includes a first opposing portion 48A opposing the channel region 24 across the insulating film 41, and a second opposing portion 48B opposing the source region 22 and the drain region 23. The first opposing portion 48A is larger than the second opposing portion 48B in a plan view.

The charge storage film 42 has a recess 50 formed by a first storage portion 48 and a second storage portion 49. The recess 50 is provided on the opposite side of the first storage portion 48 to the first insulating portion 46 and on the opposite side of the second storage portion 49 to the second insulating portion 47.
The insulating spacer 43 is disposed adjacent to the charge storage film 42 in the recess 50. The insulating spacer 43 is made of, for example, silicon oxide. The insulating spacer 43 faces the insulating film 41 with the charge storage film 42 interposed therebetween.

The semiconductor device 1 further includes a coating insulating film 51 that covers the planar gate structure 30 and the memory structure 40. Both ends of the coating insulating film 51 in the second direction Y are located on the opposite side of the planar gate structure 30 from the memory structure 40. The coating insulating film 51 extends in the first direction X, and both ends of the coating insulating film 51 in the first direction X reach onto the insulating filling material 12 (see also FIG. 4). Therefore, the coating insulating film 51 covers the source region 22 and the drain region 23 in the device region 6, and covers the insulating filling material 12 outside the device region 6.

In detail, the covering insulating film 51 integrally has a first covering portion 52 that covers the gate electrode 32, a second covering portion 53 that covers the outer side surface 40b of the memory structure 40, a third covering portion 54 that covers the source region 22 and the drain region 23 in the device region 6, and a fourth covering portion 55 (see FIG. 4) that covers the protruding portion 18 of the insulating embedment 12 outside the device region 6.

The third covering portion 54 covers the source region 22 on the side of the source side portion 40A of the memory structure 40, and covers the drain region 23 on the side of the drain side portion 40B. The fourth covering portion 55 covers the insulating filling 12 on the side of the connecting portion 40C of the memory structure 40 (see FIG. 4). A through hole 52A is formed in the region of the first covering portion 52 that faces the trench insulating structure 10 across the gate electrode 32 (see FIG. 4).

2 and 4, semiconductor device 1 includes a gate silicide film 60, a source silicide film 61 and a drain silicide film 62.
4, the gate silicide film 60 is formed on a portion that constitutes the bottom of the through hole 52A on the surface of the gate electrode 32. The gate silicide film 60 is made of a polycide film that is formed integrally with the gate electrode 32.

Referring to FIG. 2, the source silicide film 61 and the drain silicide film 62 are made of silicide films formed integrally with the semiconductor layer 2. The source silicide film 61 is formed on the surface portion of the source region 22 on the side opposite the memory structure 40 with respect to the covering insulating film 51. The drain silicide film 62 is formed on the surface portion of the drain region 23 on the side opposite the memory structure 40 with respect to the covering insulating film 51.

The gate silicide film 60, the source silicide film 61 and the drain silicide film 62 may each include at least one of TiSi, _TiSi2 , NiSi, CoSi, _CoSi2 , _MoSi2 and _WSi2 .
The semiconductor device 1 includes an interlayer insulating film 65 covering the first main surface 3. The interlayer insulating film 65 includes at least one of an oxide film ( _SiO2 film) and a nitride film (SiN film). The interlayer insulating film 65 may have a single-layer structure made of an oxide film or a nitride film. The interlayer insulating film 65 may have a layered structure in which one or more oxide films and one or more nitride films are layered in any order. The interlayer insulating film 65 covers the trench insulating structure 10 and the device region 6 on the first main surface 3.

2 and 4, semiconductor device 1 includes a gate contact electrode 66, a source contact electrode 67 and a drain contact electrode 68 which penetrate interlayer insulating film 65.
4, the gate contact electrode 66 is electrically connected to the gate electrode 32 via the gate silicide film 60. Specifically, the gate contact electrode 66 is electrically connected to the gate electrode 32 and faces the insulating filling 12 with the gate electrode 32 interposed therebetween.

Unlike this embodiment, when the gate electrode 32 extends beyond the insulating filling material 12 , the gate contact electrode 66 may face the semiconductor layer 2 outside the insulating filling material 12 .
2, the source contact electrode 67 is electrically connected to the source region 22 via the source silicide film 61. The drain contact electrode 68 is electrically connected to the drain region 23 via the drain silicide film 62. In a plan view, the bent portion 30C is located between the source contact electrode 67 and the drain contact electrode 68 (see FIG. 1). Since the first gate bent portion 100 (see FIG. 3) is provided in the bent portion 30C, the first gate bent portion 100 (see FIG. 3) is also located between the source contact electrode 67 and the drain contact electrode 68 in a plan view.

Referring to FIG. 2 and FIG. 4, the gate contact electrode 66, the source contact electrode 67, and the drain contact electrode 68 are embedded in contact holes 69 formed in the interlayer insulating film 65. Each contact electrode (gate contact electrode 66, source contact electrode 67, and drain contact electrode 68) is formed of at least one of copper and tungsten.

A barrier electrode film (not shown) may be provided between each contact electrode and the inner wall of the contact hole 69. The barrier electrode film may have a single layer structure made of a Ti film or a TiN film. The barrier electrode film may have a layered structure including a Ti film and a TiN film layered in any order.
The semiconductor device 1 includes a gate wiring 70, a source wiring 71, and a drain wiring 72 formed on an interlayer insulating film 65. The gate wiring 70 is electrically connected to a gate contact electrode 66. The source wiring 71 is electrically connected to a source contact electrode 67. The drain wiring 72 is electrically connected to a drain contact electrode 68.

Each of the wirings (gate wiring 70, source wiring 71, and drain wiring 72) may include at least one of an Al film, an AlSiCu alloy film, an AlSi alloy film, and an AlCu alloy film.
A barrier wiring film (not shown) may be provided between each wiring and the interlayer insulating film 65. The barrier wiring film may have a single-layer structure made of a Ti film or a TiN film. The barrier wiring film may have a multilayer structure including a Ti film and a TiN film laminated in any order. The barrier wiring film may also be provided on each wiring.

6A to 7, each operation (write operation, erase operation, and read operation) of the memory structure 40 will be specifically described. In each operation, a reference potential is applied to the back gate region 20 connected to the well region 21.
Fig. 6A is a schematic diagram for explaining an initial state before a write operation of the memory structure 40. Fig. 6B is a schematic diagram for explaining a write operation of the memory structure 40.

As shown in FIG. 6A, the gate threshold voltage Vth before potentials are applied to the gate electrode 32, the source region 22, and the drain region 23 is defined as a first threshold voltage Vth1 (initial threshold voltage). The state before potentials are applied to the gate electrode 32, the source region 22, and the drain region 23 means a state in which the gate potential Vg, the source potential Vs, and the drain potential Vd are all 0V (Vg=Vs=Vd=0V). The gate potential Vg is the potential applied to the gate electrode 32. The source potential Vs is the potential applied to the source region 22. The drain potential Vd is the potential applied to the drain region 23.

As shown in FIG. 6B, the write operation is achieved by injecting electrons (hot electrons HE) generated by impact ionization in the vicinity of the source region 22 into the charge storage film 42 .
More specifically, during a write operation, a positive potential (e.g., 5 V) is applied to the gate electrode 32 and the source region 22 (Vg=Vs=5 V), and a reference potential is applied to the drain region 23 (Vd=0 V). This causes a drain-source current Ids to flow from the source region 22 to the drain region 23, concentrating an electric field in the vicinity of the source region 22. As a result, hot electrons HE are generated by impact ionization in the vicinity of the source region 22. The hot electrons HE are injected into the charge storage film 42 (see FIG. 5) of the memory structure 40.

The gate potential Vg and the source potential Vs in the write operation are not limited to 5V, and may be any potential selected from the range of 5V or more and 7V or less, for example.
The potential difference between the source region 22 and the gate electrode 32 is called the gate-source voltage Vgs. For example, when the gate potential Vg is 5 V and the source potential Vs is 5 V, the gate-source voltage Vgs is 0 V (Vgs=0 V).

The gate threshold voltage Vth increases due to the negative charge of the electrons injected into the charge storage film 42 by the write operation. Specifically, the gate threshold voltage Vth becomes a second threshold voltage Vth2 (see FIG. 6D described later) that is higher than the first threshold voltage Vth1 (Vth=Vth2, Vth2>Vth1).
6C is a schematic diagram for explaining the erase operation of the memory structure 40. As shown in FIG. 6C, the erase operation is achieved by injecting holes (hot holes HH) generated by the band-to-band tunneling phenomenon into the charge storage film 42.

In detail, during an erase operation, a negative potential (e.g., -5V) is applied to the gate electrode 32 (Vg = -5V), a positive potential (e.g., 5V) is applied to the source region 22 (Vs = 5V), and the drain region 23 is opened. In other words, a high voltage is applied between the source region 22 and the gate electrode 32. This causes a source-backgate current Isb to flow from the source region 22 to the backgate region 20 via the well region 21.

Therefore, hot holes HH are generated by the band-to-band tunneling phenomenon near the boundary between the well region 21 and the source region 22. The hot holes HH are injected into the charge storage film 42 of the memory structure 40 (see FIG. 2).
The gate potential Vg in the erase operation is not limited to −5 V, and may be any potential selected from the range of, for example, −7 V to −3 V. The source potential Vs in the erase operation is not limited to 5 V, and may be any potential selected from the range of 5 V to 7 V.

In an erase operation, when the gate potential Vg is -5V and the source potential Vs is 5V, the gate-source voltage Vgs is 10V (Vgs = 10V). For example, when the thickness T2 of the insulating film 41 is 8nm and the thickness T1 of the gate insulating film is 10nm, the insulating film 41 is thinner than the gate insulating film 31. Therefore, compared to a configuration in which the thicknesses of the insulating film 41 and the gate insulating film 31 are the same, the gate-source voltage Vgs is divided more efficiently in the charge storage film 42. Therefore, it is easier to concentrate an electric field near the source region 22, and it is easier to generate hot holes HH.

The gate threshold voltage Vth drops due to the positive charges of the holes injected into the charge storage film 42 by the erase operation. Specifically, the gate threshold voltage Vth returns from the second threshold voltage Vth2 to the first threshold voltage Vth1 (see FIG. 6E described later) (Vth=Vth1).
Next, the read operation of the memory structure 40 will be described. Fig. 6D is a schematic diagram for explaining the read operation after the write operation. Fig. 6E is a schematic diagram for explaining the read operation after the erase operation (i.e., the initial state). Fig. 7 is a graph showing the relationship between the gate potential Vg and the drain-source current Ids after the write operation and the erase operation.

During a read operation, a drain-source current Ids flows in the opposite direction to that of a write operation. The magnitude of the drain-source current Ids determines whether data has been written to the memory structure 40. Specifically, in a read operation after both a write operation and an erase operation, a positive potential (e.g., 1.5 V) is applied to the gate electrode 32, a positive potential (e.g., 0.5 V) is applied to the drain region 23, and a reference potential (Vs = 0 V) is applied to the source region 22.

When the gate potential Vg is 1.5 V and the drain potential Vd is 0.5 V, the potential difference between the drain region 23 and the gate electrode 32 (drain-gate voltage Vdg) is 1.0 V (Vg=1.5 V, Vd=0.5 V, Vdg=1.0 V).
The gate threshold voltage Vth (second threshold voltage Vth2) after the write operation is larger than the gate threshold voltage (first threshold voltage Vth1) after the erase operation. Therefore, as shown in FIG. 7, when the gate potential Vg is a predetermined read potential Vr (Vg=Vr) during reading, the drain-source current Ids2 in the read operation after the write operation is smaller than the drain-source current Ids1 in the read operation after the erase operation. This current difference ΔI (ΔI=Ids1-Ids2) can be used to determine whether data has been written to the memory structure 40.

The first threshold voltage Vth1 is, for example, 0.7 V or more and 2.0 V or less, and the second threshold voltage Vth2 is a voltage obtained by adding a potential to the first threshold voltage Vth1. For example, if the first threshold voltage Vth1 is 1.0 V, the second threshold voltage Vth2 is a higher voltage (1.2 V or more and 5 V or less). The read potential Vr is, for example, 1.5 V or more and 5.0 V or less.

In the first embodiment, the bottom of the source region 22 and the bottom of the drain region 23 are flat without any steps, and the source region 22 and the drain region 23 do not have low concentration regions (low concentration source region and low concentration drain region). Therefore, the charge storage film 42 faces the channel region 24. Therefore, hot carriers are likely to be generated. This allows hot electrons HE to be injected into the charge storage film 42 during a write operation, and allows hot holes HH to be drawn into the charge storage film 42 during an erase operation. Therefore, data can be written to the memory structure 40 and erased from the memory structure 40 repeatedly and efficiently.

Furthermore, by making the insulating film 41 thinner than the gate insulating film 31, the gate-source voltage Vgs can be efficiently divided by the charge storage film 42. Therefore, it is possible to easily draw the hot holes HH into the charge storage film 42.
In this embodiment, the memory structure 40 is covered with the insulating cover film 51. Therefore, the memory structure 40 can be prevented from being silicided.

In the first embodiment, the covering insulating film 51 partially covers the source region 22 and the drain region 23 on the side of the memory structure 40. The source silicide film 61 and the drain silicide film 62 are formed on the surface portions of the source region 22 and the drain region 23, respectively, on the side opposite the memory structure 40 with respect to the covering insulating film 51. Therefore, compared to a configuration in which the covering insulating film 51 does not cover the source region 22 and the drain region 23, the source silicide film 61 and the drain silicide film 62 can be kept away from the charge storage film 42. This makes it possible to suppress the outflow of electrons from the charge storage film 42.

In addition, in this first embodiment, the charge storage film 42 has a recess 50 on the opposite side of the planar gate structure 30 with respect to the first storage portion 48 and on the opposite side of the semiconductor layer 2 with respect to the second storage portion 49, and the insulating spacer 43 is disposed in the recess 50. Therefore, the charge storage film 42 is surrounded by the insulating film 41 and the insulating spacer 43, i.e., the insulator. Therefore, the gate-source voltage Vgs can be efficiently divided by the charge storage film 42.

Figures 8A to 8Y are cross-sectional views for explaining one example of a manufacturing method of the semiconductor device 1 shown in Figure 1. Figures 8A to 8Y are cross-sectional views of a region corresponding to Figure 2. Figures 8A to 8Y only show a manufacturing method of the device region 6 in which a MOSFET is formed.
First, referring to Fig. 8A, a semiconductor wafer 75 is prepared. The semiconductor wafer 75 serves as a base for the semiconductor layer 2. The semiconductor wafer 75 has a first wafer main surface 76 on one side and a second wafer main surface 77 on the other side. The first wafer main surface 76 and the second wafer main surface 77 correspond to the first main surface 3 and the second main surface 4 of the semiconductor layer 2, respectively (see Fig. 2).

Next, a resist mask 80 having a predetermined pattern is formed on the semiconductor wafer 75. The resist mask 80 exposes the region of the semiconductor wafer 75 where the trench 11 is to be formed, and covers the other regions.
8B, unnecessary portions of the first wafer main surface 76 are removed by etching through the resist mask 80. The etching may be a dry etching method (e.g., RIE method) and/or a wet etching method. The etching is preferably a dry etching method (e.g., RIE method).

As a result, trenches 11 that define the device regions 6 are formed in the first wafer main surface 76. The resist mask 80 is then removed. A detailed description of the trenches 11 is omitted here, as it has been described above.
8C , a base insulating film 81 that serves as a base for the insulating filling 12 is formed on the first wafer main surface 76. In this embodiment, the base insulating film 81 is made of silicon oxide. The base insulating film 81 may be formed by a CVD method. The base insulating film 81 fills the trench 11.

Next, referring to FIG. 8D, unnecessary portions of the base insulating film 81 are removed by an etching method. The base insulating film 81 is removed until the first wafer main surface 76 is exposed. The etching method may be a dry etching method (e.g., an RIE method) and/or a wet etching method. As a result, the insulating filling 12 located in the trench 11 is formed.

Next, referring to FIG. 8E, a first base film 82 that serves as a base for the gate insulating film 31 (see FIG. 2) is formed on the surface portion of the first wafer main surface 76 in the device region 6. The first base film 82 is made of an oxide of the semiconductor wafer 75. The first base film 82 is formed by oxidizing the surface portion of the first wafer main surface 76 into a film shape using an oxidation process. Specifically, the first base film 82 is formed by a thermal oxidation process.

According to the oxidation process (thermal oxidation process), a silicon oxide film (silicon thermal oxide film) is formed along the first wafer main surface 76. The thickness of the first base film 82 may be the same as the thickness T1 (see FIG. 5) of the gate insulating film 31, that is, 7 nm or more and 13 nm or less. The first base film 82 is integral with the insulating filling 12.
8F , a p-type well region 21 is formed in a surface portion of the first wafer main surface 76 in the device region 6. The well region 21 is formed by introducing p-type impurities into the surface portion of the first wafer main surface 76 by ion implantation via the gate insulating film 31. By forming the well region 21, a region in the semiconductor wafer 75 having a lower p-type impurity concentration than the well region 21 becomes the back gate region 20.

The introduction of p-type impurities into the first wafer main surface 76 may be performed at any timing. For example, the introduction of p-type impurities into the first wafer main surface 76 may be performed before the gate insulating film 31 is formed on the first wafer main surface 76. In that case, a sacrificial oxide film may be formed on the first wafer main surface 76, and the p-type impurities may be introduced into the first wafer main surface 76 through the sacrificial oxide film. Then, after the sacrificial oxide film is removed, the gate insulating film 31 is formed.

8G, the gate electrode 32 is formed on the first wafer main surface 76 so as to cover the first base film 82 and the insulating filling 12. In this embodiment, the gate electrode 32 is made of conductive polysilicon. The gate electrode 32 may be formed by a CVD method.
Next, referring to FIG. 8H, a resist mask 87 having a predetermined pattern is formed on the gate electrode 32. The resist mask 87 exposes unnecessary portions of the gate electrode 32 and covers the other regions. Next, the unnecessary portions of the gate electrode 32 are removed by etching through the resist mask 87. The etching may be a dry etching method (e.g., RIE method) and/or a wet etching method. The wet etching may be performed by supplying HF (hydrofluoric acid), for example. In this way, the gate electrode 32 is formed. Thereafter, as shown in FIG. 8I, the resist mask 87 is removed.

Next, referring to FIG. 8J, the first base film 82 is partially removed by etching to form the gate insulating film 31. This forms the planar gate structure 30. Due to the partial removal of the first base film 82, the first wafer main surface 76 recedes toward the second wafer main surface 77 on the side of the gate insulating film 31. Due to the receding of the first wafer main surface 76, a first recess 78 is formed on the side of the planar gate structure 30, which recesses the first wafer main surface 76 toward the second wafer main surface 77. In this way, due to the partial removal of the first base film 82, the gate insulating film 31 is formed and the first recess 78 is also formed. Due to the receding of the first wafer main surface 76, a part of the insulating filling 12 protrudes from the trench 11.

The etching method may be a dry etching method (for example, an RIE method) and/or a wet etching method. By partially removing the first base film 82, a planar gate structure 30 including a gate insulating film 31 and a gate electrode 32 is formed.
8K, a second base film 83 serving as a base for the insulating film 41 (see FIG. 2) is formed on the surface portion of the first wafer main surface 76 in the first recess 78 and on the surface portion of the gate electrode 32. The second base film 83 is made of oxides of the semiconductor wafer 75 and the gate electrode 32. The second base film 83 is formed by oxidizing the surface portion of the semiconductor wafer 75 in the device region 6 and the surface portion of the gate electrode 32 into a film shape by an oxidation process. Specifically, the second base film 83 is formed by a thermal oxidation process.

According to the oxidation process (thermal oxidation process), a silicon oxide film (silicon thermal oxide film) is formed along the first wafer main surface 76 and the gate electrode 32. The thickness of the second base film 83 may be the same as the thickness T2 of the insulating film 41 (see FIG. 5), that is, 5 nm or more and 10 nm or less.
Next, referring to FIG. 8L, a third base film 84, which is the base of the charge storage film 42, is formed on the first wafer main surface 76 so as to cover the second base film 83 and the insulating filling material 12. In this embodiment, the third base film 84 is made of silicon nitride. The third base film 84 may be formed by a CVD method. The thickness of the third base film 84 may be the same as the thickness T3 of the charge storage film 42 (see FIG. 5), that is, 10 nm or more and 50 nm or less.

Next, referring to FIG. 8M, a fourth base film 85, which serves as the base of the insulating spacer 43 (see FIG. 2), is formed on the first wafer main surface 76 so as to cover the third base film 84. In this embodiment, the fourth base film 85 is made of silicon oxide. The fourth base film 85 may be formed by a CVD method. The second base film 83, the third base film 84, and the fourth base film 85 are collectively referred to as the memory base film 86.

Next, referring to FIG. 8N, the memory base film 86 is partially removed by dry etching (for example, RIE method) so as to leave a portion covering the sidewall portion of the planar gate structure 30. In detail, when the memory base film 86 is etched, the memory base film 86 gradually becomes thinner throughout the device region 6. Eventually, the memory base film 86 disappears except for the portion adjacent to the planar gate structure 30, and the memory base film 86 remains in the portion adjacent to the planar gate structure 30. This forms the memory structure 40 consisting of the insulating film 41, the charge storage film 42, and the insulating spacer 43. In other words, the memory structure 40 is formed in a self-aligned manner with respect to the planar gate structure 30.

By partially removing the second base film 83, the first wafer main surface 76 is further recessed toward the second wafer main surface 77 on the side of the memory structure 40. By the first wafer main surface 76 being recessed toward the second wafer main surface 77, a second recess 79 deeper than the first recess 78 is formed on the side of the planar gate structure 30. The insulating film 41 is disposed on the first wafer main surface 76 within the second recess 79. The second recess 79 corresponds to the recess 33 (see FIG. 5). By the recession of the first wafer main surface 76, the amount of protrusion of the insulating filling 12 from the trench 11 increases.

Next, referring to FIG. 8O, an n-type drain region 23 and an n-type source region 22 are formed in the surface portion of the well region 21. In particular, the source region 22 is formed in the surface portion of the well region 21 on one side of the memory structure 40 by introducing an n-type impurity into the surface portion of the well region 21 by ion implantation using the memory structure 40 as a mask. The drain region 23 is formed in the surface portion of the well region 21 on the other side of the memory structure 40 by introducing an n-type impurity into the surface portion of the well region 21 by ion implantation using the memory structure 40 as a mask. In other words, the drain region 23 and the source region 22 are each formed in a self-aligned manner with respect to the memory structure 40.

8P, a coated insulating film 51 is formed on the device region 6 and the insulating filling 12. In this embodiment, the coated insulating film 51 is made of silicon oxide. The coated insulating film 51 may be formed by a CVD method.
8Q, a resist mask 89 having a predetermined pattern is formed on the coated insulating film 51. The resist mask 89 exposes unnecessary portions of the coated insulating film 51 and covers the other regions. Next, the unnecessary portions of the coated insulating film 51 are removed by an etching method using the resist mask 89.

Specifically, as shown in FIG. 8R, the covering insulating film 51 has a portion covering the planar gate structure 30 and the memory structure 40, and a portion covering the device region 6 on the side of the memory structure 40. At this time, the portion of the covering insulating film 51 covering the gate electrode 32 outside the device region 6 is removed to form a through hole 52A (see FIG. 4). The etching method may be a dry etching method (e.g., RIE method) and/or a wet etching method. The resist mask 89 is then removed.

Next, referring to FIG. 8S, a source silicide film 61 and a drain silicide film 62 are formed. In this process, a metal film 88 is first formed to cover the first wafer main surface 76 and the gate electrode 32 in the device region 6. The metal film 88 includes at least one of Ti, Ni, Co, Mo, and W. The metal film 88 may be formed by a sputtering method or a vapor deposition method.

Next, the gate electrode 32 and a portion of the first wafer main surface 76 in contact with the metal film 88 are silicided. The silicide may be performed by an annealing method (for example, an RTA (rapid thermal anneal) method). As a result, a drain silicide film 62 and a source silicide film 61 each including at least one of TiSi, TiSi ₂ , NiSi, CoSi, CoSi ₂ , MoSi ₂ and WSi ₂ are formed. When the drain silicide film 62 and the source silicide film 61 are formed, a gate silicide film 60 (see FIG. 4 ) is also formed. The metal film 88 is then removed.

8T, an interlayer insulating film 65 is formed on the first wafer main surface 76. The interlayer insulating film 65 includes at least one of an oxide film and a nitride film. The interlayer insulating film 65 may be formed by a CVD method. The interlayer insulating film 65 covers the trench insulating structure 10 and the planar gate structure 30 on the first wafer main surface 76.
Next, referring to FIG. 8U, a resist mask 93 having a predetermined pattern is formed on the interlayer insulating film 65. The resist mask 93 exposes regions in the interlayer insulating film 65 where a plurality of contact holes 69 are to be formed, and covers the other regions. Next, unnecessary portions of the interlayer insulating film 65 are removed by an etching method via the resist mask 93. The etching method may be a dry etching method (for example, an RIE method) and/or a wet etching method. As a result, a plurality of contact holes 69 are formed in the interlayer insulating film 65. The plurality of contact holes 69 are formed at positions corresponding to the gate electrode 32, the source region 22, and the drain region 23, respectively. The contact hole 69 corresponding to the gate electrode 32 communicates with the through hole 52A penetrating the coating insulating film 51. The resist mask 93 is then removed.

8V , a base contact electrode film 90 serving as a base for gate contact electrode 66, drain contact electrode 68, and source contact electrode 67 is formed on interlayer insulating film 65, filling a plurality of contact holes 69. Base contact electrode film 90 may be formed by sputtering or vapor deposition.
8W, unnecessary portions of base contact electrode film 90 are removed by an etching method. Base contact electrode film 90 is removed until interlayer insulating film 65 is exposed. The etching method may be a dry etching method (e.g., an RIE method) and/or a wet etching method. As a result, gate contact electrode 66 (see FIG. 4), source contact electrode 67, and drain contact electrode 68 are formed.

8X, a base wiring film 91 serving as a base for the gate wiring 70 (see FIG. 4), the source wiring 71, and the drain wiring 72 is formed on the interlayer insulating film 65. The base wiring film 91 may be formed by a sputtering method or a vapor deposition method.
8Y, a resist mask 92 having a predetermined pattern is formed on the base wiring film 91. The resist mask 92 covers regions of the interlayer insulating film 65 where the gate wiring 70, the drain wiring 72, and the source wiring 71 are to be formed, and leaves the other regions exposed.

Next, unnecessary portions of the base wiring film 91 are removed by etching through the resist mask 92. The etching may be a dry etching method (e.g., RIE method) and/or a wet etching method. As a result, the gate wiring 70 (see FIG. 4), the source wiring 71, and the drain wiring 72 are formed on the interlayer insulating film 65. The resist mask 92 is then removed. The semiconductor wafer 75 is then cut to cut out a plurality of semiconductor devices 1. Through the steps including those described above, the semiconductor device 1 is manufactured.

According to this manufacturing method, the memory structure 40 is formed in a self-aligned manner without using a resist mask, which makes it possible to form the memory structure 40 more efficiently than in a method of forming a memory structure using a resist mask.
Unlike the first embodiment, in a configuration in which the planar gate structure is formed linearly in a plan view, in order to increase the amount of carriers captured in the memory structure, it is necessary to increase the width of the memory structure. In order to increase the width of the memory structure, it is necessary to increase the thickness of the charge storage film and the oxide film, so it is difficult to form a wide memory structure by the above-mentioned manufacturing method.

According to the first embodiment, the source sidewall portion 37 of the planar gate structure 30 has a first gate bend portion 100 recessed toward the drain region 23. Therefore, by forming the memory structure 40 in a self-aligned manner, the first bend portion width BW1 can be made larger than the first non-bend portion width NW1 and the width W2 of the drain side portion 40B. In other words, a wide portion (first memory bend portion 110) can be provided in the portion of the memory structure 40 adjacent to the source sidewall portion 37 of the planar gate structure 30.

Therefore, the memory structure 40 can be formed in a self-aligned manner, while the amount of carriers captured in the memory structure 40 can be increased.
FIG. 9 is a schematic diagram for explaining how the memory structure 40 is formed by dry etching in the method for manufacturing the semiconductor device 1. As shown in FIG.
When the memory base film 86 is etched, exposed areas A1 in which the first wafer main surface 76 of the semiconductor wafer 75 is exposed are formed on both sides of the planar gate structure 30 .

Thereafter, as the etching progresses, the exposed region A1 expands toward the planar gate structure 30, and the covered region A2 covered by the memory base film 86 on the first wafer main surface 76 is reduced. Specifically, on both sides of the planar gate structure 30, the boundaries 95 between the covered region A2 and the exposed region A1 approach the planar gate structure 30.
The boundary 95 between the covered region A2 and the exposed region A1 has a pair of straight portions 96 extending parallel to each of the first straight portion 30A and the second straight portion 30B of the planar gate structure 30, and a curved connecting portion 97 connecting the pair of straight portions 96 to each other.

The covered region A2 on one side of the planar gate structure 30 is sandwiched between the first straight portion 30A and the second straight portion 30B of the planar gate structure 30 in a planar view. Therefore, as the etching progresses, the curvature of the connection portion 97 at the boundary 95 between the covered region A2 and the exposed region A1 decreases. After the etching is completed, the connection portion 97 disappears and an apex 98 is formed where a pair of straight portions 96 intersect.

The covering region A2 on the other side of the planar gate structure 30 is not sandwiched between the first straight portion 30A and the second straight portion 30B of the planar gate structure 30 in a plan view. Therefore, even after the etching is completed, the connection portion 97 of the boundary 95 between the covering region A2 and the exposed region A1 is maintained.
In this way, by providing the first gate bend 100 on the source sidewall 37 of the planar gate structure 30, a first memory bend 110 as a wide portion can be formed in a self-aligned manner in the source side portion 40A of the memory structure 40.

Second Embodiment
Fig. 10A is a plan view of a main part of a semiconductor device 1P according to a second embodiment of the present invention. Fig. 10B is an enlarged view of an XB region shown in Fig. 10A. Fig. 10C is an enlarged view of an XC region shown in Fig. 10A. In Figs. 10A to 10C, configurations equivalent to those shown in Figs. 1 to 9 described above are given the same reference numerals as in Fig. 1 and the like, and descriptions thereof will be omitted.

The semiconductor device 1P according to the second embodiment differs mainly from the semiconductor device 1 according to the first embodiment in that the planar gate structure 30P according to the second embodiment is formed in a zigzag shape in a planar view.
The semiconductor device 1P according to the second embodiment has a cross-sectional shape similar to that of the semiconductor device 1 according to the first embodiment (see FIGS. 2, 4, and 5), and therefore a detailed description thereof will be omitted. The planar gate structure 30P and memory structure 40P according to the second embodiment have configurations similar to those of the planar gate structure 30 and memory structure 40 according to the first embodiment, respectively. The semiconductor device 1P according to the second embodiment can be manufactured by the same manufacturing method as that of the semiconductor device 1 according to the first embodiment, and therefore a detailed description thereof will be omitted.

10A , the planar gate structure 30P has a shape in which two substantially L-shaped portions of the planar gate structure 30 according to the first embodiment are arranged side by side in the first direction X. In the planar gate structure 30P according to the second embodiment, first straight line portions 30A and second straight line portions 30B are alternately arranged along the first direction X.
The first linear direction L1 in which each first linear portion 30A extends and the second linear direction L2 in which each second linear portion 30B extends do not coincide with the first direction X and the second direction Y. The first linear direction L1 and the second linear direction L2 are perpendicular to each other. In the example of FIG. 10A, the first linear direction L1 is inclined at 45° with respect to the first direction X, and the second linear direction L2 is perpendicular to the first linear direction L1. Unlike the example of FIG. 10A, the directions in which the multiple first linear portions 30A extend may be different from each other, and the directions in which the multiple second linear portions 30B extend may be different from each other.

The planar gate structure 30P has multiple bent portions 30C. The multiple bent portions 30C are located between the source region 22 and the drain region 23. The multiple bent portions 30C have multiple first bent portions 30CA in which the source sidewall portion 37 is bent so as to recess toward the drain region 23, and one or more second bent portions 30CB in which the drain sidewall portion 38 is bent so as to recess toward the source region 22.

In the first bent portion 30CA, the drain sidewall portion 38 is an outer wall portion, and the source sidewall portion 37 is an inner wall portion. In the second bent portion 30CB, the source sidewall portion 37 is an outer wall portion, and the drain sidewall portion 38 is an inner wall portion.
The number of first bent portions 30CA is greater than the number of second bent portions 30CB. In the example of Fig. 10A, two first bent portions 30CA are provided, and one second bent portion 30CB is provided.

A plurality of source contact electrodes 67 may be connected to the source region 22 according to the second embodiment. The plurality of source contact electrodes 67 may be arranged at equal intervals in the first direction X. Similarly, a plurality of drain contact electrodes 68 may be connected to the drain region 23 according to the second embodiment. The plurality of drain contact electrodes 68 may be arranged at equal intervals in the first direction X. The plurality of source contact electrodes 67 may each face the plurality of drain contact electrodes 68 in the second direction Y.

A gate contact electrode 66 is connected to an end of the planar gate structure 30P in the first direction X. The end of the planar gate structure 30P in the first direction X reaches onto the trench isolation structure 10. Unlike this embodiment, the end of the planar gate structure 30P in the first direction X may be located outside the trench isolation structure 10.
The memory structure 40P according to the second embodiment is annular in plan view surrounding the planar gate structure 30P. Like the memory structure 40 according to the first embodiment, the memory structure 40P according to the second embodiment is composed of a source side portion 40A, a drain side portion 40B, and a pair of coupling portions 40C.

As shown in FIG. 10B, the source sidewall portion 37 of the planar gate structure 30P has a first gate bend portion 100 recessed toward the drain region 23 in each first bend portion 30CA, and a first gate non-bend portion 101 other than the first gate bend portion 100 in each first bend portion 30CA. In this embodiment, multiple first gate bend portions 100 (two in the example of FIG. 10A) are provided.

The source side portion 40A of the memory structure 40P includes a first memory bend 110 along each of the first gate bends 100 and a first memory non-bend portion 111 along each of the first gate non-bend portions 101. The first memory bends 110 are provided in the same number as the first gate bends 100.
The source sidewall 37 of the planar gate structure 30P has a first source side edge 37a and a second source side edge 37b that extend linearly and face each other across the first memory bend 110 in a plan view, and an apex 37c where the first source side edge 37a and the second source side edge 37b intersect. The first gate bend 100 is provided on the apex 37c. The angle that the first source side edge 37a and the second source side edge 37b make in the memory structure 40 is preferably 90° or less.

The source side portion 40A of the memory structure 40P has a third source side edge 120 extending parallel to the first source side edge 37a, a fourth source side edge 121 extending parallel to the second source side edge 37b, and an apex 122 where the third source side edge 120 and the fourth source side edge 121 intersect. The first memory bend 110 is the portion between the apex 122 of the source side portion 40A and the apex 37c of the source sidewall portion 37 in a plan view.

The width W1 of the source side portion 40A is the shortest distance between the end of the source side portion 40A on the source region 22 side and the source sidewall portion 37. The width W1 of the source side portion 40A differs between the first memory bent portion 110 and the first memory non-bent portion 111.
The width W1 (first bend width BW1) of the source side portion 40A in the first memory bend 110 is the shortest distance between the first gate bend 100 and the end of the first memory bend 110 on the source region 22 side. The first bend width BW1 is the distance between the top 37c of the source sidewall 37 and the top 122 of the source side portion 40A.

The width W1 (first non-bending portion width NW1) of the source side portion 40A in the first memory non-bending portion 111 is the shortest distance between the first gate non-bending portion 101 and the end of the first memory non-bending portion 111 on the source region 22 side. The first non-bending portion width BW1 is larger than the first non-bending portion width NW1. The first non-bending portion width NW1 is the distance between the first source side edge 37a of the source side wall portion 37 and the third source side edge 120 of the source side portion 40A, or the distance between the second source side edge 37b of the source side wall portion 37 and the fourth source side edge 121 of the source side portion 40A.

The width W2 of the drain side portion 40B adjacent to the first bent portion 30CA is approximately equal to the first non-bent portion width NW1 and is smaller than the first bent portion width BW1. That is, the drain side portion 40B does not have a wide portion, and the source side portion 40A has the first memory bent portion 110 as a wide portion.
10C, the drain sidewall 38 of the planar gate structure 30P has a second gate bend 150 recessed toward the source region 22 at the second bend 30CB, and a second gate non-bend 151 other than the second gate bend 150 at the second bend 30CB. In the example of FIG. 10A, the number of second gate bends 150 is one. Therefore, the number of first gate bends 100 is greater than the number of second gate bends 150.

The drain side portion 40B of the memory structure 40P includes a second memory bend 160 along the second gate bend 150 and a second memory non-bend 161 along the second gate non-bend 151. The second memory bends 160 are provided in the same number as the second gate bends 150. Therefore, the number of the first memory bends 110 is greater than the number of the second memory bends 160.
The drain sidewall 38 of the planar gate structure 30P has a first drain side edge 38a and a second drain side edge 38b that extend linearly and face each other across the second memory bend 160 in a plan view, and an apex 38c where the first drain side edge 38a and the second drain side edge 38b intersect. The second gate bend 150 is provided on the apex 38c. The angle that the first drain side edge 38a and the second drain side edge 38b form in the memory structure 40 is preferably 90° or less.

The drain side portion 40B of the memory structure 40P has, in a plan view, a third drain side edge 170 extending parallel to the first drain side edge 38a, a fourth drain side edge 171 extending parallel to the second drain side edge 38b, and an apex 172 where the third drain side edge 170 and the fourth drain side edge 171 intersect. The second memory bend 160 is, in a plan view, a portion between the apex 172 of the drain side portion 40B and the second gate bend 150.

The width W2 of the drain side portion 40B is the shortest distance between the end of the drain side portion 40B on the drain region 23 side and the drain sidewall portion 38. The width W2 of the drain side portion 40B in the second memory bend 160 (second bend width BW2) is the shortest distance between the second gate bend 150 and the end of the second memory bend 160 on the drain region 23 side. The second bend width BW2 is the distance between the top 38c of the drain sidewall portion 38 and the top 172 of the drain side portion 40B.

The width W2 (second non-bent portion width NW2) of the drain side portion 40B in the second memory non-bent portion 161 is the shortest distance between the second gate non-bent portion 151 and the end of the second memory non-bent portion 161 on the drain region 23 side. The second non-bent portion width NW2 is the distance between the first drain side edge 38a of the drain side wall portion 38 and the third drain side edge 170 of the drain side portion 40B, or the distance between the second source side edge 37b of the drain side wall portion 38 and the fourth drain side edge 171 of the drain side portion 40B. The second bent portion width BW2 is larger than the second non-bent portion width NW2.

The width W1 of the portion of the source side portion 40A adjacent to the second bent portion 30CB is approximately equal to the second non-bent portion width NW2 and is smaller than the second bent portion width BW2. That is, the drain side portion 40B is provided with the second memory bent portion 160 as a wide portion.
According to the second embodiment, the same effect as that of the first embodiment can be obtained. According to the second embodiment, the first memory bent portion 110 as the wide portion can be provided at a plurality of positions. Therefore, the amount of carriers captured by the memory structure 40P can be further increased.

Third Embodiment
Fig. 11A is a plan view of a main part of a semiconductor device 1Q according to a third embodiment of the present invention. Fig. 11B is an enlarged view of an XIIB region shown in Fig. 11A. In Fig. 11A and Fig. 11B, the same reference numerals as in Fig. 1 and the like are used to designate configurations equivalent to those shown in Fig. 1 to Fig. 10C, and descriptions thereof will be omitted.

The semiconductor device 1Q according to the third embodiment differs from the semiconductor device 1 according to the first embodiment mainly in that the planar gate structure 30Q according to the third embodiment has a linear portion 200 that extends linearly in the first direction X between the source region 22 and the drain region 23, and multiple (three in the example of FIG. 11A) tapered triangular portions 201 that protrude from the linear portion 200 toward the source region 22. The multiple triangular portions 201 are aligned along the first direction X.

The semiconductor device 1Q according to the third embodiment has a cross-sectional shape similar to that of the semiconductor device 1 according to the first embodiment (see Figures 2, 4, and 5), and therefore a detailed description thereof will be omitted. The planar gate structure 30Q and memory structure 40Q according to the third embodiment have configurations similar to those of the planar gate structure 30 and memory structure 40 according to the first embodiment, respectively. The semiconductor device 1Q according to the third embodiment can be manufactured by the same manufacturing method as that of the semiconductor device 1 according to the first embodiment, and therefore a detailed description thereof will be omitted.

An end of the planar gate structure 30Q in the first direction X reaches above the trench isolation structure 10. Unlike this embodiment, the end of the planar gate structure 30Q in the first direction X may be located outside the trench isolation structure 10.
The memory structure 40Q according to the third embodiment has an annular shape surrounding the planar gate structure 30Q in a planar view. Like the memory structure 40 according to the first embodiment, the memory structure 40Q is composed of a source side portion 40A, a drain side portion 40B, and a pair of coupling portions 40C.

The source sidewall portion 37 of the planar gate structure 30Q has multiple (two in the example of FIG. 11A ) tapered triangular portions 205 recessed toward the drain region 23 between adjacent triangular portions 201 in the first direction X.
11B, the triangular portion 205 has a first gate bent portion 100 recessed toward the drain region 23, and a first gate non-bent portion 101 other than the first gate bent portion 100. In this embodiment, a plurality of first gate bent portions 100 (two in the example of FIG. 11A) are provided.

The source side portion 40A of the memory structure 40Q includes a first memory bend 110 along each of the first gate bends 100 and a first memory non-bend 111 along each of the first gate non-bends 101. The first memory bends 110 are provided in the same number as the first gate bends 100.
The source sidewall 37 of the planar gate structure 30Q has a first source side edge 37a and a second source side edge 37b that extend linearly and face each other across the first memory bend 110 in a plan view, and an apex 37c where the first source side edge 37a and the second source side edge 37b intersect. In this embodiment, the apex 37c constitutes the apex of the triangular portion 205 on the drain region 23 side, and the first source side edge 37a and the second source side edge 37b constitute a pair of linear portions that form the apex 37c. That is, the first gate bend 100 is provided at the apex of the triangular portion 205 on the drain region 23 side.

The source side portion 40A of the memory structure 40Q has, in a plan view, a third source side edge 120 extending parallel to the first source side edge 37a, a fourth source side edge 121 extending parallel to the second source side edge 37b, and an apex 122 where the third source side edge 120 and the fourth source side edge 121 intersect. The first memory bend 110 is, in a plan view, the portion between the apex 122 of the source side portion 40A and the first gate bend 100.

The width W1 (first bend width BW1) of the source side portion 40A in the first memory bend 110 is the shortest distance between the first gate bend 100 and the end of the first memory bend 110 on the source region 22 side. The first bend width BW1 is the distance between the top 37c of the source sidewall 37 and the top 122 of the source side portion 40A.
The width W1 (first non-bent portion width NW1) of the source side portion 40A in the first memory non-bent portion 111 is the shortest distance between the first gate non-bent portion 101 and the end portion on the source region 22 side in the first memory non-bent portion 111. The first non-bent portion width NW1 is the distance between the first source side edge 37a of the source sidewall portion 37 and the third source side edge 120 of the source side portion 40A, or the distance between the second source side edge 37b of the source sidewall portion 37 and the fourth source side edge 121 of the source side portion 40A. The first bent portion width BW1 is larger than the first non-bent portion width NW1.

The drain sidewall portion 38 of the planar gate structure 30Q is linear along the first direction X. Therefore, the drain side portion 40B of the memory structure 40Q is also formed linearly along the first direction X. The drain side portion 40B has a constant width W2 regardless of its position in the first direction X.
The first bent portion width BW1 is larger than the first non-bent portion width NW1. The width W2 of the drain side portion 40B is approximately equal to the first non-bent portion width NW1 and is smaller than the first bent portion width BW1. That is, the source side portion 40A is provided with the first memory bent portion 110 as a wide portion.

According to the third embodiment, the same effect as that of the first embodiment can be obtained. According to the third embodiment, the first memory bent portion 110 as the wide portion can be provided at a plurality of locations. Therefore, the amount of carriers captured by the memory structure 40Q can be further increased.
Fourth Embodiment
Fig. 12A is a plan view of a main part of a semiconductor device 1R according to a fourth embodiment of the present invention. Fig. 12B is an enlarged view of an XIIB region shown in Fig. 12A. In Fig. 12A and Fig. 12B, the same reference numerals as in Fig. 1 and the like are used for configurations equivalent to those shown in Fig. 1 to Fig. 11B described above, and descriptions thereof will be omitted.

The semiconductor device 1R according to the fourth embodiment is mainly different from the semiconductor device 1 according to the first embodiment in that the planar gate structure 30R according to the fourth embodiment has a linear portion 200 that extends linearly in the first direction X between the source region 22 and the drain region 23, and a plurality of (four in the example of FIG. 12A ) square portions 202 that protrude from the linear portion 200 toward the source region 22. The multiple square portions 202 are aligned along the first direction X. A gap is provided between adjacent square portions 202.

The semiconductor device 1R according to the fourth embodiment has a cross-sectional shape similar to that of the semiconductor device 1 according to the first embodiment (see Figures 2, 4, and 5), and therefore a detailed description thereof will be omitted. The planar gate structure 30R and memory structure 40R according to the fourth embodiment have configurations similar to those of the planar gate structure 30 and memory structure 40 according to the first embodiment, respectively. The semiconductor device 1R according to the fourth embodiment can be manufactured by the same manufacturing method as that of the semiconductor device 1 according to the first embodiment, and therefore a detailed description thereof will be omitted.

An end of the planar gate structure 30R in the first direction X reaches the trench isolation structure 10. Unlike this embodiment, an end of the planar gate structure 30R in the first direction X may be located outside the trench isolation structure 10.
The memory structure 40R according to the fourth embodiment is annular in plan view surrounding the planar gate structure 30R. Like the memory structure 40 according to the first embodiment, the memory structure 40R is composed of a source side portion 40A, a drain side portion 40B, and a pair of coupling portions 40C.

The source sidewall portion 37 of the planar gate structure 30R has a plurality of (three in the example of FIG. 12A) square portions 206 recessed toward the drain region 23 between the square portions 202 adjacent in the first direction X.
Between the rectangular portions 206, there are a first gate bent portion 100 recessed toward the drain region 23, and a first gate non-bent portion 101 other than the first gate bent portion 100. In this embodiment, a plurality of first gate bent portions 100 (three in the example of FIG. 12A ) are provided.

12B , the source side portion 40A of the memory structure 40R includes a first memory bend 110 along each of the first gate bends 100 and a first memory non-bend 111 along each of the first gate non-bends 101. The first memory bends 110 are provided in the same number as the first gate bends 100.
In a plan view, the source sidewall portion 37 of the planar gate structure 30R has a pair of first source side edges 37a extending in the second direction Y toward the drain region 23, a second source side edge 37b connecting the first source side edges 37a and extending in the first direction X, and an apex 37c where each of the first source side edges 37a and the second source side edge 37b intersect. The first source side edges 37a and the second source side edges 37b face each other with the first memory bend portion 110 therebetween.

In this embodiment, the apex 37c constitutes two apexes of the rectangular portion 206 on the drain region 23 side, and the pair of the first source side edge 37a and the second source side edge 37b constitute three linear portions that form the two apexes 37c. That is, the first gate bend 100 is provided at the two apexes of the rectangular portion 206 on the drain region 23 side.
The source side portion 40A of the memory structure 40R has, in a plan view, a pair of third source sides 120 extending parallel to each of the pair of first source sides 37a, a fourth source side 121 extending parallel to the second source side 37b, and an apex 122 where each of the third source sides 120 intersects with the fourth source side 121. The first memory bend 110 is a portion between the apex 122 of the source side portion 40A and the first gate bend 100 in a plan view.

The width W1 (first bend width BW1) of the source side portion 40A in the first memory bend 110 is the shortest distance between the first gate bend 100 and the end of the first memory bend 110 on the source region 22 side. The first bend width BW1 is the distance between the top 37c of the source sidewall 37 and the top 122 of the source side portion 40A.
The width W1 (first non-bent portion width NW1) of the source side portion 40A in the first memory non-bent portion 111 is the shortest distance between the first gate non-bent portion 101 and the end portion on the source region 22 side in the first memory non-bent portion 111. The first non-bent portion width NW1 is the distance between the first source side edge 37a of the source sidewall portion 37 and the third source side edge 120 of the source side portion 40A, or the distance between the second source side edge 37b of the source sidewall portion 37 and the fourth source side edge 121 of the source side portion 40A. The first bent portion width BW1 is larger than the first non-bent portion width NW1.

The drain sidewall portion 38 of the planar gate structure 30R is linear along the first direction X. Therefore, the drain side portion 40B of the memory structure 40R is also formed linearly along the first direction X. The drain side portion 40B has a constant width W2 regardless of its position in the first direction X.
The first bent portion width BW1 is larger than the first non-bent portion width NW1. The width W2 of the drain side portion 40B is approximately equal to the first non-bent portion width NW1 and smaller than the first bent portion width BW1. That is, the drain side portion 40B does not have a wide portion, and the source side portion 40A has the first memory bent portion 110 as a wide portion.

The fourth embodiment provides the same effect as the first embodiment. According to the fourth embodiment, the first memory bend portion 110 as the wide portion can be provided in multiple locations. The amount of carriers captured by the memory structure 40R can be further increased. Furthermore, since two first memory bend portions 110 can be provided in each square portion 206, the amount of carriers captured by the memory structure 40R can be further increased.

Fifth Embodiment
Fig. 13A is a plan view of a main part of a semiconductor device 1S according to a fifth embodiment of the present invention. Fig. 13B is an enlarged view of a region XIIIA shown in Fig. 13A. In Fig. 13A and Fig. 13B, the same reference numerals as in Fig. 1 and the like are used for configurations equivalent to those shown in Fig. 1 to Fig. 12B described above, and descriptions thereof will be omitted.

The main difference between the semiconductor device 1S of the fifth embodiment and the semiconductor device 1 of the first embodiment is that the planar gate structure 30S of the fifth embodiment is formed in an approximately square ring shape in a planar view.
The semiconductor device 1S according to the fifth embodiment has a cross-sectional shape similar to that of the semiconductor device 1 according to the first embodiment (see FIGS. 2, 4, and 5), and therefore a detailed description thereof will be omitted. The planar gate structure 30S and memory structure 40S according to the fifth embodiment have configurations similar to those of the planar gate structure 30 and memory structure 40 according to the first embodiment, respectively. The semiconductor device 1S according to the fifth embodiment can be manufactured by the same manufacturing method as that of the semiconductor device 1 according to the first embodiment, and therefore a detailed description thereof will be omitted.

The planar gate structure 30S includes four straight portions 250 and four bent portions 251 where the straight portions 250 intersect with each other. The four bent portions 251 include two first bent portions 251A located within the device region 6 and two second bent portions 251B located outside the device region 6. The second bent portions 251B are located on the trench insulation structure 10. A gate contact electrode 66 is connected to one of the two second bent portions 251B.

In the semiconductor device 1S according to the fifth embodiment, the source region 22 is located inside the planar gate structure 30S, and the drain region 23 is located on both outsides of the planar gate structure 30S.
The planar gate structure 30S has a pair of source sidewalls 37 and a pair of drain sidewalls 38 located in the device region 6. The pair of source sidewalls 37 face the source region 22 from both sides in the second direction Y, and the pair of drain sidewalls 38 face the pair of drain regions 23, respectively.

The memory structure 40S provided in the semiconductor device 1S of the fifth embodiment includes an inner memory structure 260 having an approximately square ring shape arranged adjacent to the inner wall portion of the planar gate structure 30S, and an outer memory structure 261 having an approximately square ring shape arranged adjacent to the outer wall portion of the planar gate structure 30S.
The inner memory structure 260 includes a pair of source side portions 260A located between the source region 22 and the planar gate structure 30S in the device region 6, and a pair of connecting portions 260B connecting the source side portions 260A to each other. Each source side portion 260A is located between the source region 22 and the planar gate structure 30S.

The outer memory structure 261 includes a pair of drain side portions 261A located in the device region 6 and a pair of connecting portions 261B connecting the drain side portions 261A to each other. Each drain side portion 261A is located between the planar gate structure 30S and the corresponding drain region 23.
13B , the source sidewall 37 of the planar gate structure 30S has, at each first bent portion 251A, a first gate bent portion 100 recessed toward the drain region 23 and a first gate non-bent portion 101 other than the first gate bent portion 100. The source side portion 260A includes a first memory bent portion 110 aligned with the corresponding first gate bent portion 100 and a first memory non-bent portion 111 aligned with the corresponding first gate non-bent portion 101.

Each source sidewall portion 37 of the planar gate structure 30 has a first source side edge 37a and a second source side edge 37b that extend linearly and face each other across the first memory bend portion 110 in a planar view, and an apex 37c where the first source side edge 37a and the second source side edge 37b intersect.
Each source side portion 260A of the inner memory structure 260 has a third source side edge 120 extending parallel to the first source side edge 37a in a plan view, a fourth source side edge 121 extending parallel to the second source side edge 37b in a plan view, and an apex 122 where the third source side edge 120 and the fourth source side edge 121 intersect. The first memory bend 110 is a portion between the apex 37c of the source side portion 260A and the first gate bend 100 in a plan view.

The width W1 of each source side portion 260A is the shortest distance between the end of the source side portion 260A on the source region 22 side and the source sidewall portion 37.
The width W1 (first bend width BW1) of the source side portion 260A in the first memory bend 110 is the shortest distance between the first gate bend 100 and the end of the first memory bend 110 on the source region 22 side. The first bend width BW1 is the distance between the top 37c of the source sidewall 37 and the top 122 of the source side portion 260A.

The width W1 (first non-bending portion width NW1) of the source side portion 260A in the first memory non-bending portion 111 is the shortest distance between the first gate non-bending portion 101 and the end of the first memory non-bending portion 111 on the source region 22 side. The first non-bending portion width NW1 is the distance between the first source side edge 37a of the source side wall portion 37 and the third source side edge 120 of the source side portion 40A, or the distance between the second source side edge 37b of the source side wall portion 37 and the fourth source side edge 121 of the source side portion 40A.

The first bent portion width BW1 is larger than the first non-bent portion width NW1. The width W2 of the drain side portion 261A is approximately equal to the first non-bent portion width NW1 and is smaller than the first bent portion width BW1. That is, the drain side portion 261A does not have a wide portion, and the source side portion 260A has the first memory bent portion 110 as a wide portion.
According to the fifth embodiment, the same effect as that of the first embodiment can be obtained. According to the fifth embodiment, the first memory bent portion 110 as the wide portion can be provided at a plurality of locations. Therefore, the amount of carriers captured by the memory structure 40S can be further increased.

The present invention is not limited to the above-described embodiment, and can be embodied in other forms.
For example, in the second embodiment described above, the more the number of first bent portions 30CA, the more the amount of carriers captured, so the more the first bent portions 30CA are provided than the second bent portions 30CB. However, even in a configuration in which the number of second bent portions 30CB is greater than the number of first bent portions 30CA, the amount of carriers captured by the memory structure 40P can be increased as long as at least one first bent portion 30CA is provided.

In each of the above-described embodiments, an n-type (first polarity type) MOSFET is formed, which includes a p-type well region 21, an n-type source region 22, and an n-type drain region 23. However, unlike the above-described embodiments, a p-type (second polarity type) MOSFET may be formed, which includes an n-type well region 21, a p-type source region 22, and a p-type drain region 23.
The cross-sectional structures of the memory structures 40, 40P, 40Q, 40R, and 40S are not necessarily limited to those shown in Figures 2, 4, and 5. That is, the insulating film 41, the charge storage film 42, and the insulating spacer 43 do not need to be provided, and it is sufficient that the memory structures are configured to be able to store charges.

Various other modifications may be made within the scope of the claims.

1: Semiconductor device 1P: Semiconductor device 1Q: Semiconductor device 1R: Semiconductor device 1S: Semiconductor device 2: Semiconductor layer 3: First main surface 21: Well region 22: Source region 23: Drain region 24: Channel region 30: Planar gate structure 30P: Planar gate structure 30Q: Planar gate structure 30R: Planar gate structure 30S: Planar gate structure 31: Gate insulating film 32: Gate electrode 33: Recess 37: Source side wall portion 37a: First source side edge 37b: Second source side edge 37c: Top portion 38: Drain side wall portion 38a: First drain side edge 38b: Second drain side edge 38c: Top portion 40: Memory structure 41: Insulating film 42: Charge storage film 67: Source contact electrode 68: Drain contact electrode 100: First gate bend portion 101 : First gate non-bending portion 110 : First memory non-bending portion 111 : First memory non-bending portion 150 : Second gate non-bending portion 151 : Second gate non-bending portion 160 : Second memory non-bending portion 161 : Second memory non-bending portion 205 : Triangular portion 206 : Square portion BW1 : First bent portion width BW2 : Second bent portion width NW1 : First non-bending portion width NW2 : Second non-bending portion width T1 : Thickness T2 : Thickness

Claims (17)

a semiconductor layer having a primary surface;
a source region and a drain region formed in a surface portion of the main surface of the semiconductor layer and spaced apart from each other;
a planar gate structure disposed between the source region and the drain region, the planar gate structure having a source sidewall portion facing the source region in a planar view and a drain sidewall portion facing the drain region in a planar view, the source sidewall portion having a first gate bent portion recessed toward the drain region and a first gate non-bent portion other than the first gate bent portion, and the drain sidewall portion having a drain side gate bent portion recessed toward the drain region and a drain side non-bent portion other than the drain side gate bent portion;
a memory structure having a source side portion adjacent to the source sidewall portion , the memory structure having a first memory bend along the first gate bend and a first memory non-bend along the first gate non-bend, and a drain side portion adjacent to the drain sidewall portion, the memory structure having a drain side bend along the drain side gate bend and a drain side non-bend along the drain side gate non-bend ,
a first width of the first memory non-bending portion of the source side portion is the same as a second width of the drain side non-bending portion of the drain side portion;
a third width of the first memory bend at the source side portion is greater than a fourth width of the drain side bend at the drain side portion . The semiconductor device according to claim 1 , wherein the third width is greater than the first width . the third width is a shortest distance between the first gate bent portion and an end of the first memory bent portion on the source region side;
the first width is a shortest distance between the first gate non-bending portion and an end of the first memory non-bending portion on the source region side,
the second width is a shortest distance between the drain-side gate non-bent portion and an end portion of the drain-side non-bent portion on the drain region side,
3. The semiconductor device according to claim 1 , wherein the fourth width is a shortest distance between the drain side gate bent portion and an end of the drain side bent portion on the drain region side . the source sidewall portion has a first source side edge and a second source side edge which face each other across the first memory bent portion in a plan view and extend linearly;
4. The semiconductor device according to claim 1, wherein the first gate bent portion is provided at an apex where the first source side and the second source side intersect. a semiconductor layer having a primary surface;
a source region and a drain region formed in a surface portion of the main surface of the semiconductor layer and spaced apart from each other;
a planar gate structure disposed between the source region and the drain region, the planar gate structure having a source sidewall portion facing the source region in a plan view and a drain sidewall portion facing the drain region in a plan view, the source sidewall portion having a first gate bent portion recessed toward the drain region;
a memory structure disposed adjacent the source sidewall and the drain sidewall, the memory structure having a first memory bend along the first gate bend;
the source sidewall portion has a tapered triangular portion recessed toward the drain region in a plan view,
The first gate bent portion is provided at an apex of the triangular portion on the drain region side . a semiconductor layer having a primary surface;
a source region and a drain region formed in a surface portion of the main surface of the semiconductor layer and spaced apart from each other;
a planar gate structure disposed between the source region and the drain region, the planar gate structure having a source sidewall portion facing the source region in a plan view and a drain sidewall portion facing the drain region in a plan view, the source sidewall portion having a first gate bent portion recessed toward the drain region;
a memory structure disposed adjacent the source sidewall and the drain sidewall, the memory structure having a first memory bend along the first gate bend;
the source sidewall portion has a rectangular portion recessed toward the drain region in a plan view,
The first gate bent portion is provided at an apex of the rectangular portion on the drain region side . a source contact electrode electrically connected to the source region;
a drain contact electrode electrically connected to the drain region;
The semiconductor device of any one of claims 1 to 6, wherein the first gate bend is located between the source contact electrode and the drain contact electrode. a semiconductor layer having a primary surface;
a source region and a drain region formed in a surface portion of the main surface of the semiconductor layer and spaced apart from each other;
a planar gate structure disposed between the source region and the drain region, the planar gate structure having a source sidewall portion facing the source region in a plan view and a drain sidewall portion facing the drain region in a plan view, the source sidewall portion having a first gate bent portion recessed toward the drain region;
a memory structure disposed adjacent said source sidewall and said drain sidewall, said memory structure having a first memory bend along said first gate bend;
the drain sidewall portion has a second gate bent portion recessed toward the source region;
the memory structure having a second memory bend along the second gate bend;
A semiconductor device, wherein the number of the first gate bends is greater than the number of the second gate bends. the drain sidewall portion further includes a second gate non-bent portion other than the second gate bent portion,
the memory structure further comprising a second memory non-bend portion along the second gate non-bend portion;
The semiconductor device according to claim 8 , wherein a width of said memory structure in said second memory bent portion is greater than a width of said memory structure in said second memory non-bent portion. a width of the memory structure at the second memory bend is a shortest distance between the second gate bend and an end of the second memory bend opposite the second gate bend;
The width of the memory structure at the second memory non-bending portion is the second gate non-bending portion and
10. The semiconductor device according to claim 9, wherein the distance is the shortest distance between an end of said second memory non-bent portion on a side opposite to said second gate non-bent portion. the drain sidewall portion has a first drain side edge and a second drain side edge which face each other across the second memory bend portion in a plan view and extend linearly;
11. The semiconductor device according to claim 8, wherein the second gate bent portion is an apex where the first drain side and the second drain side intersect. a first conductivity type well region formed in a surface portion of the main surface of the semiconductor layer,
the source region and the drain region are impurity regions of a second conductivity type formed in a surface portion of the well region,
the planar gate structure faces a channel region of a first conductivity type between the source region and the drain region;
12. The semiconductor device according to claim 1, wherein the memory structure includes an insulating film formed on the channel region, and a charge storage film facing the channel region with the insulating film interposed therebetween. The semiconductor device according to claim 12, wherein the planar gate structure includes a gate insulating film formed on the main surface of the semiconductor layer and a gate electrode formed on the gate insulating film. The semiconductor device according to claim 13, wherein the thickness of the insulating film is smaller than the thickness of the gate insulating film. a recess for recessing the main surface of the semiconductor layer is provided on a side of the gate insulating film;
15. The semiconductor device according to claim 13, wherein the insulating film is formed on the main surface of the semiconductor layer in the recess so as to be adjacent to the gate insulating film. The semiconductor device according to any one of claims 12 to 15, wherein the charge storage film is an insulator different from the insulating film. 17. The semiconductor device according to claim 16, wherein the charge storage film is made of SiN and the insulating film is made of _SiO2 .

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