JP7505868B2 - Semiconductor device mounting parts - Google Patents

Description

The present invention relates to a semiconductor device mounting component manufactured using a new substrate for forming via wiring.

In the field of mobile terminals and information appliances, multi-layer substrate structures incorporating semiconductor chips have become necessary to meet the demands of smaller, lighter, more sophisticated devices, as well as higher speeds and frequencies. As a technology for creating such multi-layer substrate structures incorporating semiconductor chips, the fan-out wafer-level package (FO-WLP), which forms a rewiring layer outside the semiconductor chip area to meet the demands of high-density wiring, has been attracting attention.

As an example of such FO-WLP, a method (chip-first) has been proposed in which semiconductor chips cut from a wafer are first prepared and integrated in a spaced arrangement (hereafter referred to as a "pseudo wafer"), a redistribution layer is formed on this pseudo wafer, and after the redistribution layer is formed, the pseudo wafer is cut to obtain individual packages (see Patent Document 1).

In addition, one of the mass-produced FO-WLPs is a method called InFO (Integrated Fan-Out) (see Patent Document 2). In this method, a columnar electrical connector 108 is provided on an internal wiring layer 104 provided on a support substrate 102 (FIG. 1B), a first semiconductor chip 110 having an electrical connector 112 is placed with its active surface facing up on the internal wiring layer 104 between the electrical connectors 108 (FIG. 1C), the electrical connector 108 and the semiconductor chip 110 are molded with a molding material 114, and after hardening (FIG. 1D), the molding material 114 is polished to expose the upper end surface 108A of the electrical connector 108 and the upper end surface 112A of the electrical connector 112 of the semiconductor chip 110, and the electrical connectors 108 and 112 are made into through-molded vias (FIG. 1E). Next, an internal wiring layer (rewiring layer) 116 is provided that connects to the electrical connectors 108 and 112, which are through-molding vias, and an electrical connector 118 is formed on top of this (FIG. 1F), and a second semiconductor chip 120 is mounted on top of this (FIG. 1G).

In this method, the columnar electrical connector 108 and the electrical connector 112 on the semiconductor chip 110 must be molded together and then the top end surface must be exposed by polishing, which becomes more difficult as the wiring density increases, and also makes it difficult to connect to the rewiring layer. In addition, the height of the columnar electrical connector 108 is limited to about 150 to 200 μm, and manufacturing may be difficult if the semiconductor chip 110 is tall. Furthermore, when multiple semiconductor chips are initially mounted, if the heights of the semiconductor chips differ, it is necessary to make the electrical connector of one of the semiconductor chips columnar, which is a problem that is difficult to deal with.

JP 2013-58520 A US Patent Application Publication No. 2018/0138089

The present invention aims to solve the above-mentioned problems by providing a new substrate for forming via wiring that does not require the preparation of columnar electrical connectors in advance and allows semiconductor chips of different heights to be mounted simultaneously, and to provide a semiconductor device mounting component manufactured using the same.

The first aspect of the present invention is a semiconductor device mounting component comprising a component receiving laminate in which a first layer made of a first insulating layer and a second layer laminated on the first layer are laminated, and a via for forming a via wiring is formed in the first layer and the second layer, penetrating only the first layer and the second layer without misalignment; at least one component having a connection terminal that is bonded to the first layer or the second layer of the component receiving laminate and faces the via for forming a via wiring; a third layer made of a mold resin that embeds the component; and a via wiring whose one end is connected to the connection terminal of the component and whose other end is drawn to the opposite side of the component receiving laminate through the via for forming a via wiring, and whose total thickness of the first layer and the second layer of the component receiving laminate is selected from the range of 15 μm to 70 μm.

A second aspect of the present invention is a semiconductor device mounting component according to the first aspect, characterized in that the first insulating layer of the first layer is made of an epoxy-based sealing material.

The third aspect of the present invention is a semiconductor device mounting component according to the first or second aspect, characterized in that the component includes at least one semiconductor chip having a connection terminal, and at least one semiconductor chip or passive component whose height, which is a dimension in the thickness direction of the component receiving laminate, differs from that of the semiconductor chip.

The fourth aspect of the present invention is a semiconductor device mounting component according to any one of the first to third aspects, characterized in that the second layer is made of a second insulating layer and the component is bonded to the second layer.

The fifth aspect of the present invention is the semiconductor device mounting component of the fourth aspect, characterized in that the via wiring is drawn from the connection terminal of the component to the opposite side of the component receiving laminate through a through hole provided in a rewiring insulating layer provided in the via for forming the via wiring.

The sixth aspect of the present invention is a semiconductor device mounting component according to the fourth or fifth aspect, characterized in that the second layer is made of a low-fluidity adhesive.

The seventh aspect of the present invention is a semiconductor device mounting component according to any one of the first to third aspects, characterized in that the second layer is made of a metal layer, the component is bonded to the first layer, the via wiring is drawn out from the connection terminal of the component through a through hole provided in a rewiring insulating layer provided in the via for forming the via wiring, a second through hole that exposes the metal layer is provided in the rewiring insulating layer and the first layer, and a second wiring that connects to the metal layer is provided in the second through hole.

The eighth aspect of the present invention is the semiconductor device mounting component of the seventh aspect, characterized in that the metal layer is copper foil.

The ninth aspect of the present invention is a semiconductor device mounting component according to any one of the first to eighth aspects, characterized in that one connection terminal of the component is arranged corresponding to one of the vias for forming the via wiring, a photosensitive resin layer is provided that covers a first via wiring provided through the via for forming the via wiring, a through hole is provided in the photosensitive resin layer at a position facing the first via wiring, and a wiring layer is provided on the photosensitive resin layer, the wiring layer including a second via wiring formed in the through hole that connects to the first via wiring.

The tenth aspect of the present invention is a semiconductor device mounting component according to any one of the first to eighth aspects, characterized in that one of the vias for forming via wiring is arranged to correspond to a plurality of connection terminals of the component, the photosensitive resin layer of the via for forming via wiring has a plurality of through holes that face the plurality of connection terminals, and the via wiring is provided in each through hole.

The eleventh aspect of the present invention is a semiconductor device mounting component according to the tenth aspect, characterized in that the component is an area pad type semiconductor chip in which a plurality of connection terminals are arranged in a predetermined area in the center, the via for forming the via wiring is formed in a shape corresponding to the predetermined area, the photosensitive resin layer is formed so as to fill the via for forming the via wiring, a plurality of the through holes are formed facing the plurality of connection terminals, and the via wiring is provided in each through hole.

The twelfth aspect of the present invention is a semiconductor device mounting component according to the tenth aspect, characterized in that the component is a peripheral pad type semiconductor chip in which a plurality of connection terminals are arranged in a predetermined peripheral portion surrounding a central portion, the via for forming the via wiring is formed in a shape corresponding to the predetermined peripheral portion surrounding the central portion, the photosensitive resin layer is formed so as to fill the via for forming the via wiring, a plurality of the through holes are formed facing the plurality of connection terminals, and the via wiring is provided in each through hole.

The thirteenth aspect of the present invention is a semiconductor device mounting component according to any one of the first to eighth aspects, characterized in that a rewiring layer is provided on the surface to which the via wiring is drawn, with rewiring formed through a photosensitive resin layer.

The fourteenth aspect of the present invention is the semiconductor device mounting component according to the thirteenth aspect, characterized in that the rewiring layer is provided in three or four or more layers.

The fifteenth aspect of the present invention is a semiconductor device mounting component according to the thirteenth aspect, characterized in that the rewiring layer is two or three layers, the component receiving laminate is further provided thereon, and a further rewiring layer is provided thereon.

The sixteenth aspect of the present invention is a semiconductor device mounting component according to the thirteenth aspect, characterized in that the component further comprises the component receiving laminate on the outermost layer of the rewiring layer.

The seventeenth aspect of the present invention is a semiconductor device mounting component according to any one of the tenth to thirteenth aspects, characterized in that the component is a semiconductor chip on which the rewiring layer is provided in two or three layers by eWLP.

As described above, the present invention can provide a semiconductor device mounting component manufactured using a via wiring formation substrate that does not require the preparation of columnar electrical connectors in advance and can simultaneously mount semiconductor chips of different heights.

1 is a cross-sectional view of a via wiring formation substrate according to a first embodiment of the present invention; 1A to 1C are cross-sectional views showing a manufacturing process of a via wiring formation substrate according to a first embodiment of the present invention. 1A to 1C are cross-sectional views showing a manufacturing process of a via wiring formation substrate according to a first embodiment of the present invention FIG. 4 is a cross-sectional view of a via wiring formation substrate according to a second embodiment of the present invention. FIG. 11 is a cross-sectional view of a via wiring formation substrate according to a third embodiment of the present invention. 10A to 10C are cross-sectional views showing a manufacturing process of a via wiring formation substrate according to a third embodiment of the present invention. 1A-1D are cross-sectional views illustrating a manufacturing process of a semiconductor chip having a copper PAD and an adhesive layer. 3A to 3C are cross-sectional views showing a manufacturing process of a via wiring formation substrate according to the first embodiment. 5A to 5C are cross-sectional views showing the effect of the mounting process according to the first embodiment. 1A-1D are cross-sectional views illustrating a manufacturing process of a semiconductor chip having a copper PAD and an adhesive layer. 10A to 10C are cross-sectional views showing a mounting process according to the second embodiment. 1 is a cross-sectional view showing a comparison between a semiconductor chip mounting component of the present invention and a conventional eWLP structure. FIG. 11 is a cross-sectional view showing a modified example of the semiconductor chip mounting component of the present invention. FIG. 11 is a cross-sectional view showing a modified example of the semiconductor chip mounting component of the present invention. FIG. 11 is a cross-sectional view showing a modified example of the semiconductor chip mounting component of the present invention. FIG. 11 is a cross-sectional view showing a modified example of the semiconductor chip mounting component of the present invention. FIG. 11 is a cross-sectional view showing a modified example of the semiconductor chip mounting component of the present invention. FIG. 11 is a cross-sectional view showing a modified example of the semiconductor chip mounting component of the present invention. FIG. 11 is a cross-sectional view showing a modified example of the semiconductor chip mounting component of the present invention. FIG. 11 is a cross-sectional view showing a modified example of the semiconductor chip mounting component of the present invention. FIG. 11 is a cross-sectional view showing a modified example of the semiconductor chip mounting component of the present invention. FIG. 11 is a cross-sectional view showing a modified example of the semiconductor chip mounting component of the present invention.

The present invention will now be described in further detail.
First, a via wiring forming substrate used for manufacturing a semiconductor device mounting part of the present invention will be described.

(Substrate embodiment 1)
FIG. 1 is a cross-sectional view of a via wiring forming substrate according to this embodiment, and FIGS. 2 and 3 are cross-sectional views showing a manufacturing process of the via wiring forming substrate.

As shown in these drawings, the via wiring forming substrate 1 comprises a support substrate 11, a peelable adhesive layer 12 provided on one side of the support substrate 11, a first insulating layer 13 provided on the peelable adhesive layer 12, and a second insulating layer 14 provided on the first insulating layer 13, and a plurality of vias 15 for forming via wiring are formed, penetrating only the first insulating layer 13 and the second insulating layer 14.

The vias 15 for forming via wiring are holes for forming via wiring, and are formed, for example, to match the positions of the connection terminals of the semiconductor chip to be mounted on the FO-WLP to be manufactured, and the positions of the via wiring to be provided around the mounted semiconductor chip.

The via 15 for forming via wiring penetrates only the first insulating layer 13 and the second insulating layer 14 without affecting the support substrate 11 and the peelable adhesive layer 12 provided on one side of the support substrate 11, and is provided penetrating the first insulating layer 13 and the second insulating layer 14 without misalignment. Here, penetrating without misalignment refers to a state in which the via 15a penetrating the first insulating layer 13 of the via 15 for forming via wiring and the via 15b penetrating the second insulating layer 14 are formed integrally and continuously without misalignment.

The first insulating layer 13 and the second insulating layer 14 cannot stand on their own and must be supported by the support substrate 11. Furthermore, the first insulating layer 13 and the second insulating layer 14 are made of different materials and have different mechanical properties and processing properties, and therefore cannot be formed by drilling or laser processing. A via 15 for forming via wiring that penetrates only the first insulating layer 13 and the second insulating layer 14 supported by such a support substrate 11 can be formed by a novel photolithography process as described below.

The vias 15 for forming via wiring are formed with the same precision as those formed by a photolithography process on the first insulating layer 13 and the second insulating layer 14 while they are supported on the support substrate 11, so they have good positional precision and can be formed with a finer hole diameter and pitch than drilling. The vias 15 for forming via wiring are straight vias with a diameter of 15 μm to 70 μm, and have a positional precision equivalent to photolithography precision. Specifically, for example, it is ±5 μm or less.

The first insulating layer 13 and the second insulating layer 14 cannot stand on their own and must be supported by the support substrate 11. Furthermore, the vias 15 for forming via wiring cannot be formed by drilling or laser processing the first insulating layer 13 and the second insulating layer 14 alone. Even if they are formed by drilling, the diameter is limited to about 75 μm, and the processing accuracy is ±5 μm, so through holes of 70 μm or less cannot be formed, and the positional accuracy is about ±10 μm. Furthermore, laser processing results in tapered holes, and straight holes cannot be formed. Furthermore, there is a possibility that the support substrate 11 will be damaged, which will hinder repeated use of the support substrate 11.

Here, the total thickness of the first insulating layer 13 and the second insulating layer 14 is selected from the range of 15 μm to 70 μm. The thickness of the first insulating layer 13 is selected from the range of 5 μm to 50 μm, and the thickness of the second insulating layer 14 is selected from the range of 3 μm to 35 μm. A laminate of such a thickness cannot stand on its own and cannot be handled in the mounting process, so it must be subjected to the mounting process together with a support substrate. The thickness of each of the first insulating layer 13 and the second insulating layer 14 may be selected from the ranges mentioned above.

In addition, the vias 15 for forming via wiring are formed by etching the metal layer and the plated metal using the resist formed by the photolithography process, so unlike mechanical processing, there is an advantage that even if the number of vias is large, there is no significant increase in cost. Also, unlike drill processing or laser processing, it is not affected by the processability of the first insulating layer 13 and the second insulating layer 14, and can be formed with high precision using the precision of the photolithography process, and conversely, there is a large degree of freedom in selecting the material for the first insulating layer 13 and the second insulating layer 14.

The hole diameter and minimum pitch of the vias 15 for forming via wiring are assumed to be in a very small area where drilling is difficult, but may be in an area where drilling is possible. The hole diameter of the vias 15 for forming via wiring is, for example, 15 μm to 70 μm, preferably 20 μm to 50 μm, and the minimum pitch is 50 μm to 200 μm.

The support substrate 11 is a substrate used temporarily to improve handling in the manufacturing process, and is reusable. It is sufficient to use a material that has mechanical strength, a small thermal expansion coefficient, high dimensional stability, and resistance to the etching solution used in the photolithography process. Furthermore, if the peelable adhesive layer 12 is peeled off by irradiation with light, it must be transparent to the wavelength used, but if it is peeled off by heating, it does not need to be transparent. For example, a glass plate, a metal plate, a resin plate, etc. can be used as the support substrate 11, with a glass plate being preferred.

The peelable adhesive layer 12 does not peel off during the manufacturing process, but can be peeled off when necessary by irradiation with light or heat. There are no particular limitations on the adhesive as long as it has this function, but for example, JV Peel Tape SELFA-SE (manufactured by Sekisui Chemical Co., Ltd.) can be used as an adhesive that can be peeled off by irradiation with ultraviolet (UV) light. In addition, an example of an adhesive that can be peeled off by heating is one that contains a foaming agent that expands when heated to a certain temperature.

The first insulating layer 13 can be formed of a thermosetting resin with a low thermal expansion coefficient, such as an epoxy resin, filled with an inorganic filler such as silica, and in particular an epoxy-based sealing resin can be used. In any case, it is not a photosensitive resist resin that can be partially exposed to light through a mask and the unexposed parts can be developed and removed, but is made of an insulating material that has durability that can be used as a structure for a wiring board. Therefore, through holes cannot be formed directly in the first insulating layer 13 by etching using photolithography.

Since the second insulating layer 14 exists on the first insulating layer 13, even when the semiconductor chip is mounted, there is no direct contact with the active surface of the semiconductor chip, so it is not necessary to use a low-impurity, halogen-free material. However, since the vias 15 for forming via wiring are formed at a fine pitch, it is preferable to use a thermosetting resin material filled with micro-fillers. The maximum particle size of the filler is preferably about 5 μm to 30 μm.

The second insulating layer 14 uses a thermosetting or thermoplastic resin material that does not contain filler or has a smaller amount of filler than the first insulating layer 13 and has a lower elastic modulus than the first insulating layer 13. This is to make the second insulating layer 14, which is provided as an upper layer of the first insulating layer 13 and to which the semiconductor chip is directly bonded, less elastic than the first insulating layer 13. In addition, since the second insulating layer 14 comes into direct contact with the active surface of the semiconductor chip to be mounted, a low-impurity, halogen-free material is used.

As a resin material having such characteristics, an adhesive resin with lower fluidity than general adhesives can be used, and for example, an adhesive resin layer can be made using an adhesive resin such as an epoxy resin, a phenolic resin, or a polyimide resin.

By providing such a second insulating layer 14, as described below, when the semiconductor chip is bonded to the second insulating layer 14 and then molded, the semiconductor chip is adhered to the second insulating layer 14, which has a lower elasticity than when directly bonded to the first insulating layer 13, and thus has the advantage that cracks are less likely to occur. Conversely, if the semiconductor chip is directly bonded to the first insulating layer 13 and then molded, the first insulating layer 13 is too rigid and there is a risk of cracks occurring, and the configuration of the present invention described above solves such problems.

Such an adhesive resin layer can be formed by printing the adhesive resin or by attaching a sheet of the adhesive resin.

As described below, the second insulating layer 14 is the surface that is bonded to the active surface of the semiconductor chip, and needs to have appropriate fluidity to follow the unevenness of the active surface. However, if the fluidity is too high, it will seep into the vias 15 for forming via wiring, so it is preferable to use a resin with appropriate elasticity and fluidity. In this embodiment, the second insulating layer 14 is a non-flow adhesive layer (NFA) that has lower fluidity than general adhesives. In this case, for example, a commercially available low-elasticity die bonding film, such as the HS series (manufactured by Hitachi Chemical Co., Ltd.), can be used.

As shown in the manufacturing process described below, the vias 15 for forming via wiring can be formed with the same hole diameter and pitch as vias formed by photolithography, but the depth (aspect ratio) and uniformity of the hole diameter in the depth direction are better than those processed directly into the first insulating layer 13 and the second insulating layer 14 by the photolithography process. Since the support substrate 11 exists, it is impossible to form them by laser processing or drilling, but even if processing is possible without the support substrate, it is possible to form vias with finer hole diameters and pitches than vias formed by these processes, and the depth (aspect ratio) and uniformity of the hole diameter in the depth direction are good.

The vias 15 for forming via wiring are formed to match the terminal arrangement and dimensions of the semiconductor chip to be mounted and the arrangement and dimensions of the columnar via wiring to be provided around them. Since multiple vias with different hole diameters are patterned and arranged, the hole diameter and pitch are not generally limited, but the hole diameter is 15 μm to 70 μm, preferably 20 μm to 50 μm, and the minimum pitch is 50 μm to 200 μm, preferably 50 μm to 120 μm, and more preferably 50 μm to 100 μm.

An example of a manufacturing process for the via wiring formation substrate 1 will be described below with reference to FIGS.
First, a first support substrate 21 made of glass, for example, is prepared (FIG. 2(a)), and a first peelable adhesive layer 22 is provided on one side of the substrate (FIG. 2(b)). The first peelable adhesive layer 22 may be formed by coating or by attaching a sheet-like adhesive layer, but in this example, a UV peelable tape SELFA HW (manufactured by Sekisui Chemical Co., Ltd.) was attached.

Next, a first metal layer 23 and a second metal layer 24 are provided on the first peelable adhesive layer 22 (FIG. 2(c)). The first metal layer 23 and the second metal layer 24 have different etching characteristics so that in the subsequent process, the first metal layer 23 serves as an etching stop layer and only the second metal layer 24 is etched. In addition, in relation to the resist layer that serves as a mask, it is preferable for the metal layer to be etched with an acidic etching solution.

The metals forming the first metal layer 23 and the second metal layer 24 may be selected from titanium (Ti), silver (Ag), aluminum (Al), tin (Sn), nickel (Ni), copper (Cu), etc. The etching solution for Ti is, for example, NH ₄ FHF-H ₂ O ₂ , the etching solution for Ag is, for example, CH ₃ COOH-H ₂ O ₂ , the etching solution for Al is, for example, HCl, the etching solution for Sn is, for example, NH ₄ FHF-H ₂ O ₂ , and the etching solution for Ni is, for example, HCl. For example, when any of these metals is used for one of them, etching solutions that can etch these and Cu as an etching stop layer include FeCl ₃ , Cu(NH ₃ ) ₂ , and H ₂ SO ₄ -H ₂ O ₂ .

Combinations of metals forming the first metal layer 23 and the second metal layer 24 include, but are not limited to, Ti-Cu, Ag-Cu, Al-Cu, Sn-Cu, Ni-Cu, Ni-Ti, Ni-Sn, Al-Ti, Al-Sn, Ti-Ag, Al-Ag, An-Ag, Ni-Ag, etc.

The method for forming the first metal layer 23 and the second metal layer 24 is not particularly limited, and may include film formation using various vapor phase methods, film formation using a plating method, or a method of attaching a foil or sheet, but from the standpoint of work efficiency, it is preferable to attach a commercially available two-layer metal sheet.

In this example, a two-layer metal foil is applied, with the first metal layer 23 being nickel and the second metal layer 24 being copper. In this example, the thickness of the nickel in the first metal layer 23 is 0.5 μm, and the thickness of the copper in the second metal layer 24 is 12 μm. The thickness of the first metal layer 23 is not particularly limited, but should be about 0.5 μm to 5 μm. Any thickness greater than this would be wasted. On the other hand, the thickness of the second metal layer 24 is approximately equivalent to the thickness of the second insulating layer 14 of the via wiring formation substrate 1, and therefore must be selected according to the required thickness of the second insulating layer 14. Although it depends on the application of the via wiring formation substrate 1, it is about 5 μm to 40 μm, preferably about 5 μm to 35 μm.

In this specification, for example, when simply referring to nickel or copper, this includes those containing desired added elements or unavoidable trace elements, and those containing desired added elements or trace elements may also be referred to as nickel alloys or copper alloys.

Next, a resist layer 25 is formed on the second metal layer 24, and an opening 26 penetrating the resist layer 25 is formed by photoresist patterning in a conventional manner (FIG. 2(d)). The thickness of the resist layer 25 affects the thickness of the first insulating layer 13 of the via wiring forming substrate 1, although not directly, and the patterning characteristics, i.e., the shape of the opening 26 (hole diameter and verticality), are transferred to the shape of the via wiring forming via 15. Therefore, the resist resin forming the resist layer 25 may be either positive type or negative type, but it is preferable to select a resist resin that satisfies the above-mentioned required characteristics. A preferable resist resin is the RY series for forming Photec PKG substrate circuits (manufactured by Hitachi Chemical Co., Ltd.). Here, the thickness of the resist layer 25 is 35 μm, and the diameter of the opening 26 is 30 μm.

The exposure was performed by irradiating UV at 100 to 300 mJ/cm ² and developing by spraying a 1% Na ₂ CO ₃ solution for 30 seconds, thereby performing patterning.

Next, using the patterned resist layer 25 as a mask, only the second metal layer 24 made of Cu in the opening 26 is etched (FIG. 2(e)). In this example, by using _FeCl3 , Cu( _NH3 ) ₂ , or _{H2SO4 -H2O2 as an} etching solution, only the second metal layer 24 can be etched using the first metal layer 23 made of Ti as an etching stop layer.

Next, the first metal layer 23 made of Ni exposed in the opening 26 is used as an electrode to form a metal pillar 27 made of nickel in the opening 26 (FIG. 2(f)). In this example, the thickness of the metal pillar 27 is set to 20 μm.

In this example, the metal pillars 27 are nickel, but there are no particular limitations as long as the metal is resistant to etching when the second metal layer 24 is etched away in the process described below, and the metal may be the same as or different from the first metal layer 23.

The metal pillars 27 were formed by electroplating, but the method is not limited to plating as long as it can completely fill the openings 26.

Next, the resist layer 25 is peeled off (FIG. 2(g)), a first molding resin 28 that will become the first insulating layer 13 is applied (FIG. 2(h)), and then the first molding resin 28 is polished to expose the top surface of the metal column 27 covered with the first molding resin 28 (FIG. 2(i)).

The first molding resin 28 may be made of the resin material that will become the first insulating layer 13 described above, and the thickness should be such that the metal column 27 is covered. The method of applying the first molding resin 28 is not particularly limited, but it can be performed by vacuum printing, film lamination, compression molding using a mold, etc. In this example, Nagase Chemtec Corporation's R4212 molding resin is used, and the compression molding is performed under molding conditions of 120°C for 10 minutes, and post-cure conditions of 150°C for 1 hour, resulting in the first molding resin 28.

In addition, polishing to expose the top surface of the metal pillar 27 can be performed using a general polishing machine such as a diamond bit.

Next, a second support substrate 30 is provided on the first mold resin 28 with the upper surfaces of the metal columns 27 exposed, via a second peelable adhesive layer 29 (FIG. 3(a)). The second support substrate 30 and the second peelable adhesive layer 29 respectively become the support substrate 11 and the peelable adhesive layer 12 of the via wiring formation substrate 1. The second peelable adhesive layer 29 may be formed by coating or by attaching a sheet-like adhesive layer, but here, a UV peelable tape (SELFA-HW, manufactured by Sekisui Chemical Co., Ltd.) is attached, and the second support substrate 30 is a glass plate.

Next, the whole is turned over, and the first removable adhesive layer 22 is peeled off to remove the first support substrate 21 (FIG. 3(b)), and then the first metal layer 23 on the uppermost surface is removed (FIG. 3(c)). The first metal layer 23 may be removed by etching, polishing, or etching followed by polishing. When etching is performed, a hydrochloric acid solution, sulfuric acid, or _sulfuric acid perhydrate ( _H2SO4 - _H2O2 ) can be used as _the etching solution.

Next, the second metal layer 24 is removed to expose the upper ends of the metal columns 27 (FIG. 3D). The second metal layer 24 is removed by etching. In this case, FeCl ₃ , Cu(NH ₃ ) ₂ , H ₂ SO ₄ —H ₂ O ₂ or the like can be used as an etching solution.

Next, a second resin layer 31 that will become the second insulating layer 14 is provided so as to cover the upper end of the metal column 27 (FIG. 3(e)), and then the second resin layer 31 is polished so as to expose the upper end surface of the metal column 27 (FIG. 3(f)). Here, the second resin layer 31 may be made of the material of the second insulating layer 14. Polishing to expose the upper surface of the metal column 27 can be performed using a general polishing machine such as a diamond bit.

Next, the metal pillar 27 is removed by etching to form a via 32 for forming a via wiring, which will become the via 15 for forming a via wiring of the via wiring formation substrate 1 (FIG. 3(g)). This results in a via wiring formation substrate 1 having a first insulating layer 13 and a second insulating layer 14 on the support substrate 11 and the peelable adhesive layer 12, and a via 15 for forming a via wiring that penetrates only the first insulating layer 13 and the second insulating layer 14.

(Substrate embodiment 2)
FIG. 4 shows a cross-sectional view of a via wiring formation substrate according to this embodiment.
As shown in Figure 4, the via wiring formation substrate 1A comprises a support substrate 11, a peelable adhesive layer 12 provided on one side of the support substrate 11, a first insulating layer 13 provided on the peelable adhesive layer 12, and a second insulating layer 14A provided on the first insulating layer 13, and a plurality of vias 15 for forming via wiring are formed which penetrate the first insulating layer 13 and the second insulating layer 14A.

The via wiring formation substrate 1A is similar to that of the first embodiment except that the second insulating layer 14A is not a non-flow adhesive layer (NFA) but contains no filler or has a smaller amount of filler than the first insulating layer 13, and uses a thermosetting or thermoplastic resin material with a lower elastic modulus than the first insulating layer 13. The manufacturing process is also the same, so duplicated explanations will be omitted. Specifically, the second insulating layer 14A uses HS-270 (DAF) manufactured by Hitachi Chemical Co., Ltd., and is laminated at 80°C to 200°C and bonded at 120°C to 160°C under a pressure of 0.02 MPa to 0.2 MPa for 30 seconds.

The resin material used for the second insulating layer 14 may be a photosensitive resin such as the photosensitive polyimide resin used for the rewiring layer, or a thermosetting resin.

(Substrate embodiment 3)
FIG. 5 shows a cross-sectional view of a via wiring formation substrate according to this embodiment.

As shown in FIG. 5, the via wiring forming substrate 1B comprises a support substrate 11, a peelable adhesive layer 12 provided on one side of the support substrate 11, and a metal layer 16 and an insulating layer 17 provided on the peelable adhesive layer 12, and a plurality of vias 18 for forming via wiring are formed, penetrating only the metal layer 16 and the insulating layer 17.

In either case, the vias 18 for forming via wiring are holes for forming via wiring, and are formed, for example, to match the positions of the connection terminals of the semiconductor chip to be mounted on the FO-WLP to be manufactured, and the positions of the via wiring to be provided around the mounted semiconductor chip.

The insulating layer 17 can be made of a thermosetting resin material with a low thermal expansion coefficient, such as epoxy resin, filled with an inorganic filler such as silica, and in particular an epoxy-based sealing resin can be used. In any case, it is not a photosensitive resist resin that can be partially exposed to light through a mask and the unexposed parts developed and removed, but is made of an insulating material that has durability that can be used as a structure for a wiring board. Therefore, it is not possible to directly form through-holes in the insulating layer 17 by etching using photolithography.

In addition, since the insulating layer 17 may come into direct contact with the active surface of the semiconductor chip, it is preferable to use a low-impurity, halogen-free material, and since the vias 18 for forming via wiring are formed at a fine pitch, it is preferable to use a resin material filled with fine fillers. The maximum particle size of the filler is preferably about 5 μm to 30 μm.

The vias 18 for forming via wiring are provided penetrating only the metal layer 16 and the insulating layer 17 without affecting the support substrate 11 and the peelable adhesive layer 12.

Here, the via 18 for forming the via wiring is a straight via with a diameter of 15 μm to 70 μm, and the positional accuracy is photolithography accuracy. Specifically, for example, it is ±5 μm or less.

The metal layer 16 and the insulating layer 17 cannot stand on their own and must be supported by the support substrate 11. Furthermore, the vias 18 for forming via wiring cannot be formed by drilling or laser processing only the metal layer 16 and the insulating layer 17. Even if they are formed by drilling, the diameter is up to about 75 μm and the processing accuracy is ±5 μm, so through holes of 70 μm or less cannot be formed, and the positional accuracy is about ±10 μm. Furthermore, laser processing results in tapered holes, and straight holes cannot be formed. Such vias 18 for forming via wiring that penetrate only the metal layer 16 and the insulating layer 17 supported by the support substrate 11 can be formed by the following new process.

Here, the total thickness of the metal layer 16 and the insulating layer 17 is selected from the range of 15 μm to 70 μm. The thickness of the metal layer 16 is selected from the range of 1 μm to 20 μm, and the thickness of the insulating layer 17 is selected from the range of 5 μm to 50 μm. A laminate with such a thickness cannot stand on its own and cannot be handled in the mounting process, so it needs to be subjected to the mounting process together with a support substrate. The thicknesses of the first insulating layer 13 and the second insulating layer 14 may be selected from the ranges mentioned above.
In addition, since the metal layer 16 can be used as a ground wiring, a shielding layer for the semiconductor chip, and a heat spreading layer for heat dissipation of the semiconductor chip, the thickness can be set taking into consideration the electrical conductivity and thermal conductivity required for each function.

The support substrate 11 is a substrate used temporarily to improve handling in the manufacturing process, and is reusable. It is sufficient to use a material that has mechanical strength, a small thermal expansion coefficient, high dimensional stability, and resistance to the etching solution used in the following process. Furthermore, if the peelable adhesive layer 12 is peeled off by irradiation with light, it must be transparent to the wavelength used, but if it is peeled off by heating, it does not need to be transparent. For example, a glass plate, a metal plate, a resin plate, etc. can be used as the support substrate 11, with a glass plate being preferred.

The peelable adhesive layer 12 does not peel off during the manufacturing process, but can be peeled off when necessary by irradiation with light or heating. There are no particular limitations on the type of adhesive as long as it has this function, but for example, UV peelable tape SELFA-HW (manufactured by Sekisui Chemical Co., Ltd.) can be used as an adhesive that can be peeled off by irradiation with ultraviolet (UV) light. In addition, an example of an adhesive that can be peeled off by heating is one that contains a foaming agent that expands when heated to a specified temperature.

As described above, the insulating layer 17 can be formed from a molding resin in which a filler is added to a thermosetting resin such as an epoxy resin, and in particular, an epoxy-based sealing resin can be used.

As shown in the manufacturing process described below, the vias 18 for forming via wiring can be formed with the same precision of hole diameter and pitch as vias formed by photolithography, but the depth (aspect ratio) and uniformity of the hole diameter in the depth direction are better than those processed directly into the insulating layer 17 by the photolithography process. That is, even if the insulating layer 17 is photosensitive and via processing can be performed directly by exposure and development, the hole diameter is likely to vary due to the influence of the filler, which causes differences in light refraction and light transmittance and large variations in coating thickness. However, according to the process of the present invention, the vias formed in the high-resolution resist can be transferred via metal pillars, so that the vias can be formed with the same precision of hole diameter and pitch as vias formed by photolithography. Since the support substrate 11 is present, it is impossible to form them by laser processing or drilling. However, even if processing were possible without the support substrate, it would be possible to create vias with finer diameters and pitches than those created by these processes, and the hole diameter would be uniform throughout the depth (aspect ratio) and depth direction.

The vias 18 for forming via wiring are formed to match the terminal arrangement and dimensions of the semiconductor chip to be mounted and the arrangement and dimensions of the columnar via wiring to be provided around them, and since multiple vias with different hole diameters are patterned and arranged, the hole diameter and pitch are not generally limited, but the hole diameter is 15 μm to 70 μm, preferably 20 μm to 50 μm, and the minimum pitch is 50 μm to 200 μm, preferably 50 μm to 120 μm, and more preferably 50 μm to 100 μm.

An example of the manufacturing process for the via wiring formation substrate 1B is described below with reference to FIG.

First, a support substrate 121 made of glass, for example, is prepared (FIG. 6(a)), and a peelable adhesive layer 122 is provided on one side of the support substrate (FIG. 6(b)). The peelable adhesive layer 122 may be formed by coating or by attaching a sheet-like adhesive layer, but in this example, a UV peelable tape SELFA-HW (manufactured by Sekisui Chemical Co., Ltd.) was attached.

Next, a metal layer 123 is provided on the peelable adhesive layer 122 (FIG. 6(c)). In view of its relationship with the resist layer that serves as a mask, the metal layer 123 is preferably one that can be etched with an acidic etching solution.

The metal forming the metal layer 123 may be selected from titanium (Ti), silver (Ag), aluminum (Al), tin (Sn), nickel (Ni), copper (Cu), etc., with copper being preferred.

The method for forming the metal layer 123 is not particularly limited, and may include film formation using various vapor phase methods, film formation using plating methods, or a method of attaching a foil or sheet, but from the standpoint of work efficiency, it is preferable to attach a commercially available metal foil.

In this example, a metal foil made of Cu is applied as the metal layer 123. In this example, the thickness of the Cu in the metal layer 123 is 0.5 μm.

Next, a resist layer 125 is formed on the metal layer 123, and openings 126 penetrating the resist layer 125 are formed in a predetermined pattern by photoresist patterning in a conventional manner (FIG. 6(d)). The thickness of the resist layer 125 affects the thickness of the insulating layer 17 of the via wiring formation substrate 1, although not directly, and the patterning characteristics, i.e., the shape of the opening 126 (hole diameter and verticality), are transferred to the shape of the via wiring formation via 18. Therefore, the resist resin forming the resist layer 125 may be either positive or negative, but it is preferable to select a resist resin that satisfies the above-mentioned required characteristics. A preferable resist resin is the RY series for forming Photec PKG substrate circuits (manufactured by Hitachi Chemical Co., Ltd.).

Next, using the patterned resist layer 125 as a mask and the metal layer 123 made of Ni exposed in the opening 126 as an electrode, a metal pillar 127 made of copper is formed in the opening 126 (FIG. 6(e)). In this example, the thickness of the metal pillar 127 is set to 25 μm. The thickness of the metal pillar 127 is directly related to the depth of the via 18 for forming the via wiring described above, so the thickness of the metal pillar 127 is determined according to the required depth.
In this example, the metal pillars 127 are made of copper, the same as the metal layer 123, but they may be made of the same metal as the metal layer 123 or a different metal.
Moreover, although the metal pillars 127 are formed by electroplating, the method is not limited to plating as long as it can completely fill the openings 126. However, forming the metal pillars 127 by electroplating is the most efficient and low-cost method.

Next, the resist layer 125 is peeled off (FIG. 6(f)), a molded resin 128 that will become the insulating layer 17 is applied (FIG. 6(g)), and then the molded resin 128 is polished to expose the top surface, which is the first end surface of the metal column 127 covered with the molded resin 128 (FIG. 6(h)).

The mold resin 128 may be made of the resin material that will become the insulating layer 17 described above, and the thickness is set to a level that covers the metal column 127. The method of applying the mold resin 128 is not particularly limited, and it may be performed by vacuum printing, film lamination, compression molding using a mold, or the like. In this example, the mold resin 128 is made by using Nagase Chemtec Corporation's R4212 mold resin, and is hardened by compression molding under molding conditions of 120°C for 10 minutes and post-cure conditions of 150°C for 1 hour.
Moreover, polishing to expose the upper surface of the metal pillar 127 can be performed using a general polishing machine such as a diamond bit.

Next, the metal pillar 127 and the metal layer 123 are removed by etching to form a via wiring formation via 129 that will become the via wiring formation via 18 of the via wiring formation substrate 1 (FIG. 6(i)). This results in a via wiring formation substrate 1B (see FIG. 5) having the metal layer 16 and the insulating layer 17 on the support substrate 11 and the peelable adhesive layer 12, and having the via wiring formation via 18 that penetrates only the metal layer 16 and the insulating layer 17.

(Embodiment 1)
An example of a process for mounting a semiconductor chip on the via wiring formation substrate 1 will be described below with reference to the drawings.

First, an example of a method for manufacturing a semiconductor chip having a copper pad will be described with reference to FIG.
As shown in Fig. 7(a), a semiconductor chip 50 having an aluminum pad 51 is prepared, and a seed metal layer 55 is provided thereon (Fig. 7(b)). Next, a photosensitive resin layer 56 is provided (Fig. 7(c)), and an opening 56a is formed above the aluminum pad 51 by exposure, development, and patterning (Fig. 7(d)). A copper pad 52 is formed by electroplating on the seed metal layer 55 in the opening 56a (Fig. 7(e)). The photosensitive resin layer 56 is removed (Fig. 7(f)). The seed metal layer 55 is removed by soft etching to obtain a semiconductor chip 50 having a copper pad 52 (Fig. 7(g)).

The method of providing the copper PAD 52 is not limited to the above-mentioned method. For example, the copper PAD 52 is not limited to being formed by copper plating, but can also be formed by sputtering a seed metal onto the aluminum PAD 51, providing a copper paste, and metallizing it, or by providing a copper paste directly onto the aluminum PAD 51 and metallizing it. In any case, this represents a significant reduction in the process compared to the InFO columnar electrical connector described in the prior art.

Next, the process of mounting the semiconductor chip 50 having such a copper PAD 52 on the via wiring forming substrate 1 of the present invention will be described. The via wiring forming substrate 1 of the present invention has a first insulating layer 13 and a second insulating layer 14 on the support substrate 11 and the peelable adhesive layer 12, and has a via wiring forming via 15 that penetrates only the first insulating layer 13 and the second insulating layer 14, but the first insulating layer 13 is made of an epoxy molding resin, and the second insulating layer 14 is made of a non-flow adhesive layer (NFA).

The vias 15 for forming via wiring, which penetrate only the first insulating layer 13 and the second insulating layer 14, are formed to match the positions of the connection terminals of the semiconductor chip 50.

With the copper pads 52 aligned with the vias 15 for forming via wiring, the semiconductor chips 50 are bonded onto the second insulating layer 14, which is the NFA (Figure 8(a)). Specifically, in accordance with the usual method, each semiconductor chip 50 is temporarily bonded while being pressurized and heated, and then the entire chip is positioned while being pressurized and heated for permanent bonding.

Next, a molded resin layer 41 is provided so as to embed the semiconductor chip 50 (FIG. 8(b)). The molded resin layer 41 can be formed of a molded resin in which a filler is filled in a thermosetting resin such as an epoxy resin, and in particular, an epoxy-based sealing resin can be used. Since the molded resin layer 41 comes into direct contact with the active surface of the semiconductor chip 50, it is necessary to use a low-impurity, halogen-free material. Note that since processing is not performed at a fine pitch, it may contain a larger filler than the resin material used for the first insulating layer 13. For example, a thermosetting resin containing a filler with a maximum particle size of 5 μm to 50 μm can be used.

After providing the molded resin layer 41, a support substrate may be provided via a peelable adhesive layer. This support substrate is intended to improve handling after the support substrate 11 is peeled off in the next process, and is peeled off in the final process to produce the product, but in either case it is not shown in the figures.

Next, the support substrate 11 is peeled off via the peelable adhesive layer 12 (Figure 8(c)). If UV peelable tape SELFA-HW (manufactured by Sekisui Chemical Co., Ltd.) is used as the peelable adhesive layer 12, the support substrate 11 can be peeled off by UV irradiation.

Next, the via wiring 59 is formed in the via 15 for forming the via wiring by electroplating (FIG. 8(d)). Specifically, after providing a chemical copper seed or a sputter seed in the via 15 for forming the via wiring, the via wiring 59 is formed by electroplating. The wiring layer formed on the surface of the insulating layer 13 is patterned to a predetermined size to form the via wiring 59.

Here, the formation of the via wiring 59 is not limited to electroplating, and for example, a conductive paste containing copper may be filled into the via wiring formation via 15 to form the via wiring 59.

The via wiring 59 can also be formed by a pattern plating method. In the pattern plating method, after providing a copper seed layer, a plating resist layer is patterned, and then the via wiring 59 is formed in the via 15 for forming the via wiring by pattern electroplating through the plating resist layer, the plating resist is peeled off, and the seed layer other than the layer under the via wiring 59 is removed by soft etching to form the via wiring 59.
When the via wiring 59 is formed by this pattern plating method, it is not necessary to change the aluminum pad 51 of the semiconductor chip 50 to the copper pad 52, and the semiconductor chip 50 can be mounted with the aluminum pad 51 as it is.

Next, as shown in FIG. 8(e), multiple rewiring layers 70 (three layers in the figure) are formed by a standard method on the insulating layer 13 on which the via wiring 59 is formed, to form the semiconductor chip mounted component 3. The semiconductor chip mounted component 3 is the semiconductor component mounted component of this embodiment.

By using the via wiring forming substrate 1 of the present invention, the via wiring forming vias 15 can be formed with high precision to match semiconductor chips and functional components with high density connection terminals, making it easy to mount various semiconductor chips and functional components. In addition, in this case, after the joining terminal side is adhered to the via wiring forming substrate 1, multiple semiconductor chips 50 and functional components are molded, so there is an advantage that multiple semiconductor chips 50 and functional components can be easily mounted even if they have different heights.

Such an example of mounting is shown in Figure 9. Figure 9(a) shows a case where semiconductor chips 501 and 502 of different heights are mounted on the via wiring formation substrate 1 of the present invention, and Figure 9(b) shows a case where the semiconductor chip 501 and passive component 510 are mounted. In either case, the terminal side of the semiconductor chips 501, 502 or the passive component 510 is adhered to the via wiring formation substrate 1 of the present invention, so the semiconductor chips 501, 502 and the passive component 510 do not pose a problem.

On the other hand, in the InFO described in the prior art, the columnar electrical connector 108 and the electrical connector 112 on the semiconductor chip 110 must be molded together, and then the top surface must be exposed by polishing, which becomes more difficult as the wiring density increases, and also makes it difficult to connect to the rewiring layer. In addition, the height of the columnar electrical connector 108 is limited to approximately 150 μm to 200 μm, and manufacturing may be difficult if the semiconductor chip 110 is tall. Furthermore, when multiple semiconductor chips are initially mounted, if the heights of the semiconductor chips differ, it is necessary to lengthen the columnar electrical connector of one of the semiconductor chips, which is a problem that is difficult to deal with.

In addition, when the via wiring formation substrate 1 of the present invention is used, the relatively rigid first insulating layer 13 exists between the rewiring layer 70 and the semiconductor chip 50, so that even if multiple layers of the rewiring layer 70 are provided on the first insulating layer 13, cracks are unlikely to occur in the rewiring layer 70. In addition, the relatively rigid first insulating layer 13 and the semiconductor chip 50 are interposed between the second insulating layer 14, which has a lower elasticity than the first insulating layer 13, so that even if multiple layers of the rewiring layer 70 are provided on the first insulating layer 13, cracks are unlikely to occur in the rewiring layer 70.

(Embodiment 2)
Next, an example of a process for mounting a semiconductor chip on the via wiring formation substrate 1A will be described with reference to the drawings.

The second insulating layer 14A on the surface of the via wiring formation substrate 1A is not a non-flow adhesive layer (NFA), so it is necessary to provide an NFA on the semiconductor chip.

This process will be described with reference to FIG.
As shown in Figure 10, a semiconductor chip 50 having a copper PAD 52 manufactured by the process shown in Figure 9 is prepared, and then an adhesive layer 61 is provided to cover the copper PAD 52 using a non-flow adhesive with relatively low fluidity (Figure 10(a)), and then the top of the copper PAD 52 is exposed by a polishing process to obtain a semiconductor chip 50A having an adhesive layer 61 (Figure 10(b)).

Next, a process for mounting the semiconductor chip 50A on the via wiring formation substrate 1A will be described.
With the copper pad 52 aligned with the via 15 for forming a via wiring, the semiconductor chip 50A is adhered to the second insulating layer 14A with an adhesive layer 61 (FIG. 11A).

Next, a molded resin layer 41 is provided so as to embed the semiconductor chip 50A (FIG. 11(b)). The molded resin layer 41 is the same as that used in the process of FIG. 8.

After providing the molded resin layer 41, a support substrate may be provided via a peelable adhesive layer. This support substrate is intended to improve handling after the support substrate 11 is peeled off in the next process, and is peeled off in the final process to produce the product, but in either case it is not shown in the figures.

Next, the support substrate 11 is peeled off via the peelable adhesive layer 12 (FIG. 11(c)). That is, when UV peelable tape SELFA-HW (manufactured by Sekisui Chemical Co., Ltd.) is used as the peelable adhesive layer 12, the support substrate 11 can be peeled off by UV irradiation.

Next, via wiring is formed in the via 15 for forming via wiring by electroplating. Specifically, a seed layer 57 made of a chemical copper seed or a sputter seed is provided in the via 15 for forming via wiring (FIG. 11(d)), and then a wiring layer 58 including the via wiring is formed by electroplating (FIG. 11(e)). The wiring layer 58 formed on the surface of the insulating layer 13 is patterned to a predetermined size to form a via wiring 59 (FIG. 11(f)).

Next, as shown in FIG. 11(g), a plurality of rewiring layers 70 (three layers in the figure) are formed by a conventional method on the second insulating layer 14A on which the via wiring 59 is formed, to form a semiconductor chip mounting component 3A having via wiring 91 on the surface. The semiconductor chip mounting component 3A is the semiconductor device mounting component of this embodiment. The rewiring layer 70 is composed of a rewiring insulating layer, via wiring penetrating the rewiring insulating layer, and a wiring pattern provided on the rewiring insulating layer. The rewiring insulating layer is made of a photosensitive resin such as a photosensitive polyimide resin or a thermosetting resin. When a non-photosensitive resin is used, patterning such as through-hole formation is performed by laser processing or the like.

Other Embodiments
FIG. 12 shows a comparison between the semiconductor chip mounting components 3 of the present invention manufactured in the first and second embodiments and a conventional eWLP (Embedded Wafer Level Package) structure.

In the conventional eWLP structure of FIG. 12(b), the rewiring layer 700 is provided directly on the molded resin layer 410 that molds the semiconductor chip 50. On the other hand, in the semiconductor chip mounting component 3 of the present invention shown in FIG. 12(a), the relatively low elasticity second insulating layer 14 and the relatively high elasticity and rigidity first insulating layer 13 are arranged from the molded resin layer 41 side between the molded resin layer 41 and the rewiring layer 70, which has the effect of making it difficult for cracks to occur in the rewiring layer 70.

The via wiring formation substrates 1 and 1A of embodiments 1 and 2 can be used for various purposes in addition to the standard usage methods of embodiments 3 and 4.

For example, as shown in FIG. 13(a), a second insulating layer 14 and a first insulating layer 13 may be provided between the multiple rewiring layers 70 of the semiconductor chip mounting component 3 of the third and fourth embodiments using a via wiring forming substrate 1. A via wiring 92 is provided on the top surface. In this case, cracks in the rewiring layer 70 can be prevented, making it possible to stack a larger number of rewiring layers 70 than in the past. For example, it is said that there is a risk of cracks occurring when three to four or more rewiring layers 70 are stacked, but by providing a component receiving laminate consisting of the second insulating layer 14 and the first insulating layer 13 in the middle, there is an advantage in that the occurrence of cracks can be prevented, particularly due to the presence of the rigid first insulating layer 13.

In addition, making the redistribution layer 70 multi-layered has the advantage that the pitch of the via wiring can be expanded. In the case of FIG. 13(a), for example, if the pitch P1 of the semiconductor chip 50 is about 40 μm to 100 μm, the pitch P2 on the top surface can be expanded to about 300 μm to 500 μm.

As shown in FIG. 13(b), there is also a method of using the via wiring forming substrate 1 to provide the second insulating layer 14 and the first insulating layer 13 on the surface of the semiconductor chip mounting component 3 of the third and fourth embodiments. This can be provided as a substitute for the solder resist that is usually provided on the surface of the mounting component. This method of use is possible because the component receiving laminate can be made very thin and the through-holes have good positional accuracy, so that it can be used for fine wiring structures in the same way as photosensitive solder resist. This cannot be achieved by mechanical processing such as drilling and laser processing. Furthermore, the presence of the rigid first insulating layer 13 on the surface has the effect of preventing cracks in the rewiring layer 70. The via 15 for via wiring formation is used for connection to the via wiring 91.

Furthermore, the via wiring formation substrates 1 and 1A of the first and second embodiments can be used in addition to conventional mounting structures.

For example, as shown in FIG. 14(a), a second insulating layer 14 and a first insulating layer 13 may be provided between multiple rewiring layers 700 of a conventional eWLP 500 (see FIG. 14(b)) using a via wiring forming substrate 1, and a via wiring 93 may be provided through the rewiring layer 70 on the first insulating layer 13.

Also, as shown in FIG. 14(b), a second insulating layer 14 and a first insulating layer 13 may be provided on the surface of the eWLP 500 using a via wiring forming substrate 1 to form a via wiring 94, or as shown in FIG. 14(c), a second insulating layer 14 and a first insulating layer 13 may be provided on the surface of the eWLP 500 using a via wiring forming substrate 1, and the via wiring forming via 15 may be used for connecting to the wiring terminal of the eWLP 500.

Furthermore, the via wiring formation substrates 1 and 1A of the first and second embodiments can also be used to mount, for example, eWLP500 (see FIG. 14(b)) instead of mounting a semiconductor chip.

An example of this manufacturing process is shown in Figure 15. As shown in Figure 15(a), an eWLP500 is prepared, and as shown in Figure 15(b), the eWLP500 is mounted and bonded onto a via wiring formation substrate 1.

Next, similar to the embodiment described above, the eWLP500 is molded with a molded resin layer 41 (Figure 15 (c)).

After providing the molded resin layer 41, a support substrate may be provided via a peelable adhesive layer. This support substrate is intended to improve handling after the support substrate 11 is peeled off in the next process, and is peeled off in the final process to produce the product, but in either case it is not shown in the figures.

Next, the support substrate 11 is peeled off via the peelable adhesive layer 12 (FIG. 15(d)), and then the via wiring 95 is formed in the via 15 for forming the via wiring by electroplating or the like (FIG. 15(e)). Next, as shown in FIG. 15(f), a plurality of rewiring layers 70 (three layers in the figure) are formed by a conventional method on the insulating layer 13 on which the via wiring 95 is formed, resulting in a semiconductor chip mounting component having a via wiring 97 on the top surface.

Above, various semiconductor component mounting parts have been described while explaining the semiconductor component mounting process. In each case, the via 15 for forming via wiring corresponds one-to-one to the copper pad 52, and the via wiring 59 fills the entire via wiring via 15, but this is not limited to the above.

The structural features of the above-mentioned example are summarized in FIG. 16. As shown in FIG. 16(a), a via 15 for via wiring is formed corresponding to one copper PAD 52 of a semiconductor chip 50 molded by a molded resin layer 41, and a via wiring 59 is provided to fill the via wiring via 15. In this case, generally, as shown in FIG. 16(b), a rewiring insulating layer 81 made of a photosensitive resin or a thermosetting resin is formed on the first insulating layer 13 including the via wiring 59, and a via wiring 83 connected to the via wiring 59 is formed in a through hole 82 formed in a position facing the via wiring 59 of the rewiring insulating layer 81. In reality, a wiring (not shown) that connects to the via wiring 83 is formed on the rewiring insulating layer 81, constituting the rewiring layer 80.

Figure 17 shows another example in which the via 15 for forming via wiring and the copper pad 52 correspond one-to-one. As shown in Figure 17 (a), a rewiring insulating layer 81A is formed on the periphery of the via 15 for forming via wiring and on the first insulating layer 13, and a through hole 82A is provided in the part of the rewiring insulating layer 81A facing the copper pad 52. Then, as shown in Figure 17 (b), a via wiring 83A that connects to the copper pad 52 is provided in the through hole 82A provided in the rewiring insulating layer 81A in the via 15 for forming via wiring. Note that in reality, a wiring (not shown) that connects to the via wiring 83A is formed on the rewiring insulating layer 81A, constituting the rewiring layer 80A.

16 and 17 show a case where the vias 15 for forming via wiring and the copper pads 52 correspond one to one, but FIGS. 18 and 19 show an example where there is a one to multiple correspondence.
18 and 19, the semiconductor chip molded by the mold resin layer 41 is an area pad type semiconductor chip 51A, and the via 15A for forming via wiring is formed in a shape corresponding to a rectangular area 53 provided with a plurality of area pad type copper pads 52. Fig. 18 shows a state in which a rewiring insulating layer has been formed, and Fig. 19 shows a state in which wiring has been formed, where (a) is a plan view and (b) corresponds to the b-b' cross section of (a).

As shown in these drawings, a rewiring insulating layer 81B is provided on the first insulating layer 15 including a via 15A for via wiring corresponding to the rectangular area 53, and through holes 82B are provided in the rewiring insulating layer 81B at positions facing each of the multiple copper pads 52. Then, a via wiring 83B that connects to the copper pad 52 is provided in the through hole 82B, and wiring 84B that rewires the via wiring 83B is provided to form a rewiring layer 80B. This is an example of a semiconductor device mounting component of the present invention.

20 and 21 show another example in which the vias 15 for forming via wirings and the copper pads 52 correspond to each other in a one-to-multiple correspondence.
20 and 21 show that the semiconductor chip molded by the mold resin layer 41 is a peripheral pad type semiconductor chip 51B, and the vias 15B for forming via wiring are formed in a shape corresponding to a rectangular doughnut-shaped peripheral area 54 in which a plurality of peripheral pad type copper pads 52 are provided. Fig. 20 shows a state in which a rewiring insulating layer has been formed, and Fig. 21 shows a state in which wiring has been formed, with (a) being a plan view, and (b) and (c) corresponding to the b-b' cross section and the c-c' cross section of (a).

As shown in these drawings, a rewiring insulating layer 81C is provided on the first insulating layer 15 including vias 15B for via wiring corresponding to the rectangular doughnut-shaped peripheral area 54, and through holes 82C are provided in the rewiring insulating layer 81C at positions facing each of the multiple copper pads 52. Then, via wiring 83C connecting to the copper pad 52 is provided in the through holes 82C, and wiring 84C for rewiring the via wiring 83C is provided to form a rewiring layer 80C. This is an example of a semiconductor device mounting component of the present invention.

Figure 22 shows a mounting process for an example of a semiconductor component mounting part of the present invention. This example shows a semiconductor component mounting part using via wiring formation substrate 1B (see Figure 5) of substrate embodiment 3.

22(a) shows a state in which the semiconductor chip 50A having the adhesive layer 61 of FIG. 10 is adhered to the via wiring forming substrate 1B, the semiconductor chip 50A is molded with the molded resin layer 41, and then the support substrate 1 is peeled off, and the semiconductor chip 50A is mounted on the component mounting laminate. Next, as shown in FIG. 22(b), a rewiring insulating layer 81D is provided on the metal layer 17 including the via forming via 18, and as shown in FIG. 22(c), a through hole 82D exposing the copper PAD 52 and a ground through hole 85D exposing the metal layer 17 are formed at a position opposite the copper PAD 52. Then, as shown in FIG. 22(d), a via wiring 83D connecting to the copper PAD 52 and a wiring 84D rewiring the via wiring 83 are formed in the through hole 82D, and further, a ground wiring 86D connecting to the metal layer 17 is provided in the ground through hole 85D. This forms a rewiring layer 80D that includes a second wiring 86D that connects to the metal layer 17.

In such semiconductor component mounting components, the metal layer 17 can be used as a ground wiring, a shielding layer for the semiconductor chip, and a heat spread layer for dissipating heat from the semiconductor chip.

REFERENCE SIGNS LIST 1, 1A Substrate for forming via wiring 11, 21, 30 Support substrate 12, 22, 29 Peelable adhesive layer 13, 28 First insulating layer 14, 31 Second insulating layer 15, 15A, 15B Via for forming via wiring 27 Metal pillar 28 Molding resin 50 Semiconductor chip 51 Aluminum PAD
52 Copper PAD
61 adhesive layer 41 molded resin layer 70, 70A, 70B, 80, 80A to 80D rewiring layer 81, 81A to 81D rewiring insulating layer

Claims (21)

a component receiving laminate in which a first layer made of a first insulating layer and a second layer laminated on the first layer are laminated, and a via for forming a via wiring is formed in the first layer and the second layer so as to penetrate only the first layer and the second layer without misalignment;
At least one component is bonded to the first layer or the second layer of the component receiving laminate and has a connection terminal facing the via for forming the via wiring;
a third layer made of a molding resin in which the component is embedded;
a via wiring having one end connected to the connection terminal of the component and the other end drawn out to the opposite side of the component receiving laminate through the via for forming the via wiring,
the opening of the via for forming a via wiring on the component side is larger than the size of the connection terminal,
A semiconductor device mounting component, characterized in that the total thickness of the first layer and the second layer of the component receiving laminate is selected from the range of 15 μm to 70 μm. The semiconductor device mounting component according to claim 1, characterized in that the first insulating layer of the first layer is made of an epoxy-based sealing material. The semiconductor device mounting component according to claim 1 or 2, characterized in that the component includes at least one semiconductor chip having a connection terminal, and at least one semiconductor chip or passive component whose height, which is a dimension in the thickness direction of the component receiving laminate, differs from that of the semiconductor chip. The semiconductor device mounting component according to any one of claims 1 to 3, characterized in that the second layer is made of a second insulating layer, and the component is bonded to the second layer. The semiconductor device mounting component according to claim 4, characterized in that the via wiring is pulled out from the connection terminal of the component to the opposite side of the component receiving laminate through a through hole provided in a rewiring insulating layer provided within the via for forming the via wiring. The semiconductor device mounting component according to claim 4 or 5, characterized in that the second layer is made of a low-fluidity adhesive. A semiconductor device mounting component as described in any one of claims 1 to 6, characterized in that one connection terminal of the component is arranged corresponding to one of the vias for forming the via wiring, a photosensitive resin layer is provided to cover a first via wiring provided through the via for forming the via wiring, a through hole is provided in the photosensitive resin layer at a position opposite to the first via wiring, and a wiring layer is provided on the photosensitive resin layer, the wiring layer including a second via wiring formed in the through hole connected to the first via wiring. A semiconductor device mounting component as described in any one of claims 1 to 6, characterized in that one of the vias for forming via wiring is arranged to correspond to a plurality of connection terminals of the component, a photosensitive resin layer is provided to cover a first via wiring provided through the via for forming via wiring, a plurality of through holes facing the plurality of connection terminals are formed in the photosensitive resin layer of the via for forming via wiring, and the via wiring is provided in each of the through holes . The semiconductor device mounting component according to claim 8, characterized in that the component is an area pad type semiconductor chip having a plurality of connection terminals arranged in a predetermined area in the center, the via for forming the via wiring is formed in a shape corresponding to the predetermined area, the photosensitive resin layer is formed so as to fill the via for forming the via wiring, a plurality of the through holes are formed facing the plurality of connection terminals, and the via wiring is provided in each of the through holes . The semiconductor device mounting component of claim 8, characterized in that the component is a peripheral pad type semiconductor chip in which a plurality of connection terminals are arranged on a predetermined peripheral portion surrounding a central portion, the via for forming the via wiring is formed in a shape corresponding to the predetermined peripheral portion surrounding the central portion, the photosensitive resin layer is formed so as to fill the via for forming the via wiring, a plurality of the through holes are formed facing the plurality of connection terminals, and the via wiring is provided in each of the through holes . 7. The semiconductor device mounting component according to claim 1 , further comprising a rewiring layer formed on a surface to which the via wiring is drawn, the rewiring being formed via a photosensitive resin layer. 12. The semiconductor device mounting component according to claim 11 , wherein the rewiring layers are provided in three or four or more layers. 12. The semiconductor device mounting component according to claim 11 , wherein the rewiring layer is two or three layers, the component receiving laminate is further provided thereon, and a further rewiring layer is further provided thereon. 12. The semiconductor device mounting component according to claim 11 , wherein the component further comprises a component receiving laminate on the outermost layer of the rewiring layer. 12. The semiconductor device mounting component according to claim 8 , wherein the component is a semiconductor chip having two or three rewiring layers provided thereon by eWLP. The semiconductor device mounting component according to any one of claims 1 to 3, characterized in that the second layer is made of a metal layer, the component is bonded to the first layer, the via wiring is drawn out from the connection terminal of the component through a through hole provided in a rewiring insulating layer provided in the via for forming the via wiring, a second through hole exposing the metal layer is provided in the rewiring insulating layer and the first layer, and a second wiring connecting to the metal layer is provided in the second through hole. 17. The semiconductor device mounting component of claim 16 , wherein the metal layer is a copper foil. a component receiving laminate in which a first layer made of a first insulating layer and a second layer laminated on the first layer are laminated, and a via for forming a via wiring is formed in the first layer and the second layer so as to penetrate only the first layer and the second layer without misalignment;
At least one component is bonded to the first layer or the second layer of the component receiving laminate and has a connection terminal facing the via for forming the via wiring;
a third layer made of a molding resin in which the component is embedded;
a via wiring having one end connected to the connection terminal of the component and the other end drawn out to the opposite side of the component receiving laminate through the via for forming the via wiring,
a total thickness of the first layer and the second layer of the component receiving laminate is selected from a range of 15 μm to 70 μm;
A semiconductor device mounting component characterized in that the second layer is made of a metal layer, the component is bonded to the first layer, the via wiring is pulled out from the connection terminal of the component through a through hole provided in a rewiring insulating layer provided in the via for forming the via wiring, a second through hole exposing the metal layer is provided in the rewiring insulating layer and the first layer, and a second wiring connecting to the metal layer is provided in the second through hole. 20. The semiconductor device mounting component according to claim 18, wherein said first insulating layer of said first layer is made of an epoxy-based sealing material. The semiconductor device mounting component according to claim 18 or 19, characterized in that the component includes at least one semiconductor chip having a connection terminal, and at least one semiconductor chip or passive component having a height, which is a dimension in the thickness direction of the component receiving laminate, that differs from that of the semiconductor chip. 21. The semiconductor device mounting component according to claim 18, wherein the metal layer is a copper foil.