JP7516974B2 - DEVICE FOR ELECTRONIC APPLICATION, CONTROL METHOD FOR ELECTRONIC APPLICATION DEVICE, AND CONTROL PROGRAM FOR ELECTRONIC APPLICATION DEVICE - Google Patents

Description

The present invention relates to a device for electronic equipment, a control method for an electronic equipment device, and a control program for an electronic equipment device.

In recent years, semiconductor devices that have a CPU (Central Processing Unit) interface and modules that can be accessed by the CPU are used in various electronic devices. One example of an electronic device is an image forming device such as a copy machine.

When a fault occurs in such electronic devices, the conventional method for analyzing the fault is to use a debugging device such as an In Circuit Emulator (ICE). The debugging device can be used to trace the access contents of the CPU or to set desired values in registers, making it possible to determine the cause of the fault.

However, when using a debugging device to identify the cause of a fault, the debugging device must be brought to the analysis location and connected to the electronic device being analyzed, which requires time-consuming preparations before analysis. Furthermore, if the CPU is built into a device mounted on the electronic device, it is not possible to connect the debugging device to the CPU interface, making analysis using the debugging device impossible.

To solve this problem, a method is known in which accesses from the CPU to a register are monitored, log information of detected register accesses is created, and the created log is stored in an internal memory so that it can be output to the outside (see, for example, Patent Document 1).

There is also known a computing device that has a processor, a main memory device that stores the processor's operation log, and a log collection device that is connected to the processor via a PCI (Peripheral Component Interconnect) Express bus. The log collection device has a watchdog timer that monitors a signal output from the processor at a predetermined interval, a DMAC (Direct Memory Access Controller), and a storage unit.

When the log collection device detects by the watchdog timer that the processor is inoperable, it uses the DMAC to quickly transfer the operation log stored in the main memory to the storage unit. This makes it possible to obtain the operation log even if the processor is inoperable (see, for example, Patent Document 2).

However, the log collection device does not collect PCI Express link information as a log. Therefore, if the DMAC cannot collect the operation log from the main memory device, the log collection device cannot determine whether the cause is a PCI Express link down. In order to collect PCI Express link information as a log, it is necessary to connect a debugging device to an external terminal capable of outputting link information, etc., and analyze the link information collected by the debugging device, which is very time-consuming.

The disclosed technology has been developed in consideration of the above-mentioned problems, and aims to easily determine, by referring to logs, whether the communication interface is the cause of a failure to communicate with the processor.

In order to solve the above technical problems, one embodiment of the present invention is a device for electronic equipment, characterized in that it comprises a communication interface connected to a processor and having a plurality of operating states, a state detection unit that detects transitions of the plurality of operating states and link information indicating a connection state between the processor and the communication interface at the time of detecting the transition, an access detection unit that detects access to a storage unit by the processor, and a log generation unit that generates a log including the transition information and the link information indicating the transition detected by the state detection unit, and generates a log including access information indicating the access detected by the access detection unit.

If communication with the processor is not possible, you can easily determine whether the communication interface is the cause by referring to the log.

1 is a block diagram showing an example of an electronic device according to a first embodiment of the present invention. 2 is a flow diagram showing an example of an operation of the debug controller of FIG. 1; 10 is a flow diagram illustrating another example of the operation of the debug controller of FIG. 1. FIG. 11 is a block diagram showing an example of an electronic device according to a second embodiment of the present invention. FIG. 11 is an explanatory diagram illustrating an example of a format of a PCIe link state log. FIG. 13 is a block diagram showing an example of a format of a log of register accesses. FIG. 11 is a block diagram showing an example of an electronic device according to a third embodiment of the present invention. FIG. 13 is a block diagram showing an example of an electronic device according to a fourth embodiment of the present invention.

The following describes the embodiments with reference to the drawings. Note that in each drawing, the same components are given the same reference numerals, and duplicate explanations may be omitted. Below, reference numerals indicating signals are also used to indicate signal lines.

First Embodiment
Fig. 1 is a block diagram showing an example of an electronic device according to a first embodiment. The electronic device 100 shown in Fig. 1 is connected to a CPU 200 via a PCI Express bus and a PCI Express root complex 300. PCI Express is also called PCIe. The CPU 200 and the electronic device 100 can communicate with each other via the PCIe bus. The CPU 200 is an example of a processor.

The electronic device device 100 has a PCIe physical layer interface (PHY) 10, a PCIe endpoint 20, and a debug controller 30. The PHY 10 receives control signals, data signals, etc. from the CPU 200 via the root complex 300 and the PCIe bus, and transfers the received signals to the endpoint 20. Note that in FIG. 1, the endpoint 20 is connected only to the debug controller 30, but in reality, it can be connected to various devices. The PHY 10 is an example of a communication interface and an example of a PCI Express interface.

The endpoint 20 manages the PCIe link, detects errors, etc. The endpoint 20 outputs LTSSM information indicating the state of the LTSSM (Link Training and Status State Machine), link information indicating the state of the PCIe link, and a register access signal issued by the CPU 200. The link information is information indicating the connection state between the CPU 200 and the PHY 10. The LTSSM information and the link information are supplied to the debug controller 30. The register access signal is supplied to the debug controller 30 and to the outside of the electronic device 100.

The register access signal output from the CPU 200 is used, for example, to access registers included in various functional modules (not shown) mounted in the system SYS. The registers are an example of a storage unit. The various functional modules may be mounted in the electronic device 100. The various functional modules switch operating modes, etc., depending on the setting value of the register. The CPU 200 can use the register access signal not only to set values in the registers, but also to read values set in the registers.

The debug controller 30 has a state detection unit 31, a register access detection unit 32, an arbitration unit 33, a log generation unit 34, and a log retention unit 35. The state detection unit 31, the register access detection unit 32, the arbitration unit 33, and the log generation unit 34 may be realized by hardware or by software. When realized by software, the state detection unit 31, the register access detection unit 32, the arbitration unit 33, and the log generation unit 34 are realized by a control program executed by a computer such as a CPU (not shown) mounted on the debug controller 30. Then, the control program is executed to realize a control method for the electronic device 100.

The state detection unit 31 detects a transition of the LTSSM state based on the LTSSM information, and outputs change information including link information and transition information indicating the detected transition to the arbitration unit 33. The LTSMM state is an example of a plurality of operating states that the LTSSM can take. For example, when the state detection unit 31 detects changes in both the LTSSM state and the LTSSM substate, it outputs change information including link information and transition information including information on the state before the transition and information on the state after the transition to the arbitration unit 33.

The register access detection unit 32 detects the occurrence of a register access based on a register access signal output from the endpoint 20. When the register access detection unit 32 detects the occurrence of a register access, it outputs access information indicating the address, data, read/write type, etc. included in the register access signal to the arbitration unit 33. The register access detection unit 32 is an example of an access detection unit that detects access to a register by the CPU 200.

The arbitration unit 33 outputs the received change information to the log generation unit 34, and outputs the received access information to the log generation unit 34. When the arbitration unit 33 receives change information and access information simultaneously, it performs an arbitration process to determine the order in which to output them to the log generation unit 34, and outputs the change information and access information to the log generation unit 34 sequentially according to the order determined by the arbitration process. For example, when the arbitration unit 33 receives change information and access information in the same reception cycle, it determines that they were received simultaneously and performs arbitration processing.

The log generation unit 34 generates a log that records the change information or access information received from the arbitration unit 33 in the order in which it is received from the arbitration unit 33. Therefore, the order determined by the arbitration unit 33 through the arbitration process is also the order in which the logs are generated. For example, the log generation unit 34 generates a log that includes each state and link information before and after the transition of the LTSSM received from the arbitration unit 33. The log generation unit 34 also generates a log that includes access information indicating register access received from the arbitration unit 33. The log generation unit 34 stores the generated logs in the log storage unit 35.

For example, the information stored in the log storage unit 35 can be read from outside the debug controller 30 via a serial interface (not shown) or the like. The log storage unit 35 may be provided outside the debug controller 30. Note that an enable signal that enables the operation of the debug controller 30 may be supplied to the debug controller 30 from outside the electronic device 100 in order to operate the debug controller 30 only during debugging and stop it at other times.

By providing the debug controller 30 in the electronic device 100, it is possible to record as a log not only the changes in the state of the LTSSM during link-up of the PCIe link, but also the link state of the PCIe link, not only after link-up of the PCIe link. As a result, it is possible to record as a log the behavior of the PCIe link during link-up, and it is possible to debug malfunctions during link-up. For example, it is possible to easily identify the cause when the PCIe link does not link up.

As a result, when communication between the CPU 200 and the electronic device device 100 is not possible, it is easy to determine whether the cause is the PCIe interface by referring to the log. Therefore, developers of the system SYS including the CPU 200 and the electronic device device 100 can debug whether the operation of the PCIe link is normal based on the generated log.

Furthermore, it is possible to check the state of the LTSSM when the system SYS is started (i.e., when the PCIe link is linked up) without having to prepare a debugging device to constantly monitor changes in the state of the LTSSM. As a result, debugging the system SYS can be made easier than before.

FIG. 2 is a flow diagram showing an example of the operation of the debug controller 30 in FIG. 1. The flow shown in FIG. 2 is started, for example, when the electronic device 100 is started and the PCIe starts linking up. Note that since the debug controller 30 is mounted on the electronic device 100, the flow shown in FIG. 3 may be started together with the start of the electronic device 100.

First, in step S10, the debug controller 30 detects whether or not an LTSSM state transition has occurred using the state detection unit 31. If an LTSSM state transition has occurred, the debug controller 30 performs step S12. The debug controller 30 repeats the determination in step S10 until an LTSSM state transition has occurred. Note that the debug controller 30 performs step S12 if the state detection unit 31 detects transitions to both the LTSSM state and the LTSSM substate in step S10.

In step S12, the debug controller 30 records the states and link information before and after the transition of the LTSSM by the log generation unit 34. Next, in step S14, the debug controller 30 generates a log including the recorded information by the log generation unit 34, and ends the operation shown in FIG. 2. For example, the log generated by the log generation unit 34 is held in the log holding unit 35.

As shown in FIG. 2, the debug controller 30 can detect changes in the LTSSM state immediately after the start of PCIe link-up and record them together with the link information. In other words, the debug controller 30 can record any malfunctions that occur during link-up as a log.

FIG. 3 is a flow diagram showing another example of the operation of the debug controller 30 of FIG. 2. The flow shown in FIG. 3 is started, for example, when the CPU 200 is started. Note that, if the electronic device 100 is mounted on the same board as the CPU 200 and started at the same time as the CPU 200, for example, the flow shown in FIG. 3 may be started together with the start-up of the electronic device 100.

First, in step S20, the debug controller 30 determines whether or not the CPU 200 has performed a register access based on the register access signal. If a register access has been performed, the debug controller 30 performs step S22. The debug controller 30 repeats the determination of step S20 until a register access is performed.

In step S22, the debug controller 30 records the address, data, and read/write type of the register access performed by the CPU 200. Next, in step S24, the debug controller 30 causes the log generation unit 34 to generate a log including the recorded information, and ends the operation shown in FIG. 3. For example, the log generated by the log generation unit 34 is held in the log holding unit 35.

As described above, in the first embodiment, the debug controller 30 is provided in the electronic device 100. Therefore, it is possible to record, as a log, not only after the PCIe link is linked up, but also the change in the state of the LTSSM during the link up and the link state of the PCIe link. As a result, it is possible to record, as a log, the behavior of the PCIe link during the link up, and it is possible to debug a malfunction during the link up. For example, it is possible to easily identify the cause when the PCIe link does not link up.

As a result, when communication between the CPU 200 and the electronic device device 100 is not possible, it is easy to determine whether the cause is the PCIe interface by referring to the log. Therefore, developers of the system SYS including the CPU 200 and the electronic device device 100 can debug whether the operation of the PCIe link is normal based on the generated log.

Furthermore, it is possible to check the state of the LTSSM when the system SYS is started (i.e., when the PCIe link is linked up) without having to prepare a debugging device to constantly monitor changes in the state of the LTSSM. As a result, debugging the system SYS can be made easier than before.

Second Embodiment
Fig. 4 is a block diagram showing an example of an electronic device according to a second embodiment of the present invention. The same elements as those in Fig. 1 are given the same reference numerals, and detailed description will be omitted. The electronic device 100 shown in Fig. 4 has a debug controller 30A instead of the debug controller 30 in Fig. 1. Other configurations and functions of the electronic device 100 are the same as those in Fig. 1.

The debug controller 30A has an arbitration unit 33A instead of the arbitration unit 33 in FIG. 1. In addition, the debug controller 30A adds a time count unit 36 to the debug controller 30 in FIG. 1. The time count unit 36 outputs a count value CNT to the arbitration unit 33A. The other configurations and functions of the debug controller 30A are the same as those of the debug controller 30 in FIG. 1. The state detection unit 31, the register access detection unit 32, the arbitration unit 33A, and the log generation unit 34 may be realized by hardware or software, similar to the debug controller 30 in FIG. 1.

The time counting unit 36 starts operation when the electronic device 100 is started up, counts time, and outputs the counted time to the arbitration unit 33A as a count value CNT. For example, the time counting unit 36 counts the number of clocks of a clock signal (not shown) as time based on a reset signal that is released when the electronic device 100 is started up. The clock signal supplied to the time counting unit 36 may be a clock signal that operates the electronic device 100, or may be a clock signal obtained by dividing the frequency of the clock signal that operates the electronic device 100. The time counting unit 36 is an example of a timer. The count value CNT output by the time counting unit 36 is an example of time information.

When the arbitration unit 33A receives change information or access information including transition information and link information, it adds the count value CNT being counted by the time count unit 36 to the change information or access information. When the arbitration unit 33A receives change information and access information simultaneously, it adds the same count value CNT to the change information and access information. Then, the arbitration unit 33A outputs the change information with the count value CNT added or the access information with the count value CNT added to the log generation unit 34.

For example, the log generating unit 34 receives the change information and the access information, each having the same count value CNT added thereto, at different times, and generates the respective logs. Therefore, for example, when a log including change information and a log including access information are generated in this order, it is possible to determine from the count value CNT whether the LTSSM state transition and the register access occurred in the order in which the logs were generated, or whether they occurred simultaneously. As a result, developers of the system SYS including the CPU 200 and the electronic device device 100 can accurately grasp the operation of the PCIe link based on the log including the count value CNT, thereby improving debugging efficiency.

Figure 5 is an explanatory diagram showing an example of the format of a log of the PCIe link state. The log generation unit 34 generates the change information received and recorded from the arbitration unit 33A as a log in the format shown in Figure 5. The log has an 8-byte area for each piece of change information (the upper byte is byte 7 and the lower byte is byte 0).

The 5-byte area from byte 7 to byte 3 stores the 40-bit count value CNT counted by the time count unit 36 in FIG. 4 as count information time_cnt[39:0]. Power management information Powerdown[1:0] is stored in bits 5 to 4 of byte 2. Amplitude information txswing of the transmission signal is stored in bit 3 of byte 2. "0" in the amplitude information txswing indicates full swing, and "1" in the amplitude information txswing indicates half swing (low voltage specification).

Bit 2 of byte 2 stores the waveform information txdeemph. A "1" in the waveform information txdeemph indicates the selection of de-emphasis, and a "0" in the waveform information txdeemph indicates the selection of Coefficient. Bit 1 of byte 2 stores the transfer rate information link_spd.

A "0" in the transfer rate information link_spd indicates GEN1 (PCI Express 1.1), and a "1" in the transfer rate information link_spd indicates GEN2 (PCI Express 2.0). Bit 0 of byte 2 stores the link up information dl_up. A "0" in the link up information dl_up indicates a communication unavailable state, and a "1" in the link up information dl_up indicates a communication available state (i.e., a link up state).

Bits 7 to 4 of byte 1 store state information ltssm_before before the LTSSM transition. Bits 2 to 0 of byte 1 store sub-state information ltssm_st_before before the LTSSM transition. Bits 7 to 4 of byte 0 store state information ltssm_after after the LTSSM transition. Bits 2 to 0 of byte 0 store sub-state information ltssm_st_after after the LTSSM transition. Note that "0" is stored in bits that do not store any of the above information.

Figure 6 is a block diagram showing an example of the format of a register access log. The log generation unit 34 generates the access information received and recorded from the arbitration unit 33A as a log in the format shown in Figure 6. The log has an area of 16 bytes (upper byte group and lower byte group) for each piece of access information.

The most significant bit of the upper byte group and the lower byte group stores identification information num[0] for identifying the upper byte group and the lower byte group. The identification information num of the upper byte group stores "1", and the identification information num of the lower byte group stores "0". The five-byte area from byte 4 to byte 0 of the upper byte group stores the count value CNT as 40-bit count information time_cnt[39:0].

Bit 6 of byte 7 of the lower byte group stores the read/write information rw for register access. A "0" in the read/write information rw indicates a read access, and a "1" in the read/write information rw indicates a write access. Bit 5 of byte 7 to bit 0 of byte 4 of the lower byte group store 30-bit address information addr[29:0] indicating the access address. Bytes 3 to 0 of the lower byte group store data information data[31:0] indicating the data. "0" is stored in other areas of the upper byte group and the lower byte group.

As described above, the second embodiment can achieve the same effects as the first embodiment. Furthermore, in the second embodiment, when the arbitration unit 33A receives change information or access information, it adds a count value CNT to the change information or access information, and the log generation unit 34 generates a log in which a log is added to each of the change information and the access information. This makes it possible to determine, based on the count value CNT, whether the LTSSM state transition and the register access occurred in the order in which the logs were generated or simultaneously. As a result, system SYS developers and the like can accurately grasp the operation of the PCIe link when debugging the system SYS, thereby improving debugging efficiency.

Third Embodiment
Fig. 7 is a block diagram showing an example of an electronic device according to a third embodiment of the present invention. The same elements as those in Figs. 1 and 4 are given the same reference numerals, and detailed description thereof will be omitted. The electronic device 100 shown in Fig. 7 has a debug controller 30B instead of the debug controller 30 in Fig. 1. Other configurations and functions of the electronic device 100 are the same as those in Fig. 1.

In this embodiment, the system SYS including the CPU 200 and the electronic device device 100 has a large-capacity memory 400 and a data bus DB that connects the large-capacity memory 400 and the electronic device device 100. A signal line that transmits a register access signal output by the endpoint 20 is connected to the data bus DB. The large-capacity memory 400 is an example of an external memory that can store logs generated by the log generation unit 34.

The debug controller 30B adds a time count unit 36, a memory interface unit 37, an internal memory 38, and a DMA transfer unit 39 to the debug controller 30 in FIG. 1. The debug controller 30B also has an arbitration unit 33B instead of the arbitration unit 33 in FIG. 1, and a log generation unit 34B instead of the log generation unit 34. The state detection unit 31, the register access detection unit 32, the arbitration unit 33B, and the log generation unit 34B may be realized by hardware or software, similar to the debug controller 30 in FIG. 1.

The memory interface unit 37 is connected to the arbitration unit 33B, the built-in memory 38, and the log generation unit 34B. The log generation unit 34B is connected to the memory interface unit 37 and the DMA transfer unit 39. For example, the built-in memory 38 is a dual-port memory having a write port WP and a read port RP. The DMA transfer unit 39 is connected to the large-capacity memory 400 via the data bus DB, and can transfer data, etc. to the large-capacity memory 400 at high speed without placing a load on the CPU 200. The time count unit 36, like the time count unit 36 shown in FIG. 4, counts the time from the start of the electronic device 100 and outputs the counted time to the arbitration unit 33B as a count value CNT.

The arbitration unit 33B has a function of storing the change information and access information in the built-in memory 38 via the memory interface unit 37. For example, due to initialization processing such as formatting at the time of starting up the system SYS, there are cases where the large-capacity memory 400 cannot be immediately accessed via the data bus DB. During the period when the large-capacity memory 400 cannot be accessed, the arbitration unit 33B outputs a write request to the memory interface unit 37 to write at least one of the change information received from the state detection unit 31 and the access information received from the register access detection unit 32 to the built-in memory 38.

The memory interface unit 37 generates a write command including at least one of the change information and the access information based on the received write request, and outputs the generated write command to the write port WP of the built-in memory 38. At least one of the change information and the access information is then written to the built-in memory 38. As a result, even when the change information or the access information cannot be stored in the large-capacity memory 400, such as when the system SYS is started, the change information or the access information that occurs during the start-up of the system SYS can be retained without loss.

On the other hand, assume that the startup of the system SYS is complete, the data bus DB is available, and the DMA transfer unit 39 is able to write information from the debug controller 30B to the large-capacity memory 400. In this case, the log generation unit 34B receives a signal from the DMA transfer unit 39 indicating that DMA transfer to the data bus DB is now possible. The log generation unit 34B also outputs a read request to the memory interface unit 37 to read from the built-in memory 38 the change information and access information held in the built-in memory 38.

The memory interface unit 37 generates a read command based on the received read request, outputs it to the read port RP of the built-in memory 38, and reads the change information and access information from the built-in memory 38. The memory interface unit 37 outputs the change information and access information read from the built-in memory 38 to the log generation unit 34B as a response to the read request.

After the startup of the system SYS is completed, the arbitration unit 33B arbitrates the change information received from the state detection unit 31 and the access information received from the register access detection unit 32, and then outputs the information to the log generation unit 34B via the memory interface unit 37. The log generation unit 34B outputs the change information and access information received from the memory interface unit 37 to the DMA transfer unit 39 together with a transfer request to the large-capacity memory 400. The DMA transfer unit 39 DMA transfers the received change information and access information to the large-capacity memory 400 via the data bus DB.

In this embodiment, the change information and access information that occurs during startup of the system SYS and the change information and access information that occurs after startup of the system SYS are transferred to the large-capacity memory 400 in no particular order. However, because the arbitration unit 33B adds a count value CNT to the change information and access information, it is possible to determine the order of occurrence of the change information and access information that were written in no particular order to the large-capacity memory 400 by referring to the count value CNT.

By DMA transfer, the change information and access information written to the large-capacity memory 400 can be read out via a serial interface or the like that can access the data bus DB. Therefore, when debugging the system SYS, developers of the system SYS can read out a log including change information to which the count value CNT has been added and a log including access information to which the count value CNT has been added from the large-capacity memory 400. The change information and access information read out from the large-capacity memory 400 includes information that has occurred while the system SYS was booting up, so developers can accurately grasp the operation of the PCIe link and improve debugging efficiency.

As described above, the third embodiment can also provide the same effects as the first and second embodiments. Furthermore, in the third embodiment, the debug controller 30B is provided with a memory interface unit 37 and an internal memory 38. As a result, even when change information or access information cannot be stored in the large-capacity memory 400, such as when the system SYS is started, the change information or access information generated during the start-up of the system SYS can be stored in the internal memory 38 without loss.

After the large-capacity memory 400 becomes accessible, the change information and access information transferred from the built-in memory 38 to the large-capacity memory 400 include the count value CNT. Therefore, by referring to the count value CNT included in the log written in random order to the large-capacity memory 400, it is possible to determine the order of the occurrence time of the LTSSM state transition indicated by the change information and the occurrence time of the register access indicated by the access information.

Fourth Embodiment
Fig. 8 is a block diagram showing an example of an electronic device according to a fourth embodiment of the present invention. The same elements as those in Figs. 1, 4 and 7 are given the same reference numerals, and detailed description is omitted. The electronic device 100 shown in Fig. 8 has a debug controller 30C instead of the debug controller 30B in Fig. 7. Other configurations and functions of the electronic device 100 and the configuration of the system SYS including the CPU 200 and the electronic device 100 are the same as those in Fig. 7.

The debug controller 30C has an arbitration unit 33C instead of the arbitration unit 33B of the debug controller 30B of FIG. 7, and has a log generation unit 34C instead of the log generation unit 34B of the debug controller 30B of FIG. 7. The debug controller 30C also has a memory interface unit 37C instead of the memory interface unit 37 of FIG. 7. The state detection unit 31, the register access detection unit 32, the arbitration unit 33C, and the log generation unit 34C may be realized by hardware or software, similar to the debug controller 30 of FIG. 1. The built-in memory 38 may be a single-port memory.

The memory interface unit 37C is connected to the arbitration unit 33C and the built-in memory 38. The log generation unit 34C is connected to the arbitration unit 33C and the DMA transfer unit 39.

The arbitration unit 33C has a function of storing the change information and access information in the built-in memory 38 via the memory interface unit 37C. The arbitration unit 33C also has a function of reading the change information and access information stored in the built-in memory 38 from the built-in memory 38 via the memory interface unit 37C. Furthermore, the arbitration unit 33C has a function of outputting the change information and access information to the log generation unit 34, similar to the arbitration unit 33 in FIG. 1.

Similar to the arbitration unit 33B shown in FIG. 7, the arbitration unit 33C outputs a write request to the memory interface unit 37C to write at least one of the change information and the access information to the built-in memory 38. The memory interface unit 37C generates a write command including at least one of the change information and the access information based on the received write request, and outputs the generated write command to the write port WP of the built-in memory 38. Then, at least one of the change information and the access information is written to the built-in memory 38.

On the other hand, when the startup of the system SYS is completed and the large-capacity memory 400 becomes accessible, the arbitration unit 33C outputs a read request to the memory interface unit 37C to read from the built-in memory 38 the change information and access information held in the built-in memory 38. The memory interface unit 37C generates a read command based on the received read request and outputs it to the built-in memory 38, reading the change information and access information from the built-in memory 38. The memory interface unit 37C outputs the change information and access information read from the built-in memory 38 to the arbitration unit 33C as a response to the read request.

The arbitration unit 33C outputs the change information and access information received from the memory interface unit 37C to the log generation unit 34C. After the startup of the system SYS is completed, the arbitration unit 33C arbitrates the change information received from the state detection unit 31 and the access information received from the register access detection unit 32, and then outputs the information to the log generation unit 34C.

Like the log generation unit 34B shown in FIG. 7, the log generation unit 34C outputs the change information and access information received from the arbitration unit 33C to the DMA transfer unit 39 toward the large-capacity memory 400. The DMA transfer unit 39 DMA-transfers the received change information and access information to the large-capacity memory 400 via the data bus DB.

As described above, the fourth embodiment can achieve the same effects as the first to third embodiments.

The present invention has been described above based on each embodiment, but the present invention is not limited to the requirements shown in the above embodiments. These points can be changed without departing from the spirit of the present invention, and can be appropriately determined according to the application form.

10 Physical Layer Interface (PHY)
20 endpoint 30, 30A, 30B, 30C debug controller 31 state detection unit 32 register access detection unit 33, 33A, 33B, 33C arbitration unit 34, 34B, 34C log generation unit 35 log retention unit 36 time count unit 37, 37C memory interface unit 38 built-in memory 39 DMA transfer unit 100 electronic device device 200 CPU
300 Root Complex CNT Count Value DB Data Bus SYS System

Patent No. 6127766 JP 2014-182676 A

Claims (6)

a communication interface coupled to the processor and having a plurality of operating states;
a state detection unit that detects transitions of the plurality of operation states and link information indicating a connection state between the processor and the communication interface at the time of detecting the transition;
an access detection unit that detects an access to a storage unit by the processor;
a log generating unit that generates a log including transition information indicating the transition detected by the state detecting unit and the link information, and that generates a log including access information indicating the access detected by the access detecting unit;
A device for electronic equipment comprising: an arbitration unit that determines an order of logs to be generated by the log generation unit when the detection of the transition by the state detection unit and the detection of the access by the access detection unit occur simultaneously;
A timer that outputs time information indicating a time,
the arbitration unit outputs the time information at the time of detection of the transition to the log generation unit together with the transition information and the link information, and outputs the time information at the time of detection of the access to the log generation unit together with the access information indicating the access;
The electronic device according to claim 1 , wherein the log generating unit generates a log in which the time information is added to the transition information, the link information, and the access information. an internal memory capable of storing the transition information, the link information, and the access information;
an external memory connected to the outside of the electronic device and capable of storing the log generated by the log generating unit;
The arbitration unit is
storing the transition information, the link information, and the access information in the internal memory during a period when the external memory is inaccessible;
When the external memory becomes accessible, the transition information, the link information, and the access information are read from the internal memory, and output to the log generating unit;
The electronic device according to claim 2 , wherein the log generating unit outputs the generated log to the external memory. the communication interface is a PCI Express interface,
4. The electronic device according to claim 1, wherein the state detection unit detects a transition of a status of a link training status state machine. 1. A method for controlling an electronic device having a communication interface connected to a processor and having a plurality of operating states, comprising:
detecting transitions of the plurality of operation states and link information indicating a connection state between the processor and the communication interface at the time of detecting the transitions;
Detecting an access of a storage unit by the processor;
A method for controlling a device for an electronic device, comprising: generating a log including transition information indicating the detected transition and the link information; and generating a log including access information indicating the detected access. A control program for an electronic device having a communication interface connected to a processor and having a plurality of operating states, comprising:
detecting transitions of the plurality of operation states and link information indicating a connection state between the processor and the communication interface at the time of detecting the transitions;
Detecting an access of a storage unit by the processor;
A control program for an electronic device, comprising: causing a computer to execute a process of generating a log including transition information indicating the detected transition and the link information; and generating a log including access information indicating the detected access.

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