JP7528875B2 - Vehicle Electronic Control Unit - Google Patents

Description

This disclosure relates to an electronic control device for a vehicle that controls devices mounted on the vehicle.

Patent document 1 discloses an electronic device that includes a CPU, RAM, DMA controller, etc., and is configured so that when the DMA controller receives a start signal from a timer that measures the pulse width of a pulse signal, the timer transfers the measurement result to the RAM.

In this electronic device, when the start signal is input a predetermined number of times, the DMA controller transfers the pulse width measurement results and then outputs an interrupt signal to the CPU. The CPU then uses the interrupt signal to save the data transferred from the DMA controller to a buffer and diagnoses the RAM for abnormalities.

Patent No. 5924195

In the above electronic device, if you want to transfer data corresponding to multiple activation signals within a specific period from the DMA controller, it is a good idea to input an interrupt signal to the CPU from the DMA controller or a timer at the start and end of the specific period. In other words, the CPU can execute interrupt processing in response to the interrupt signal, and this interrupt processing will start data transfer from the DMA controller at the start timing and stop the data transfer at the end timing.

However, because the processing executed by the CPU may be delayed by other interrupt processing with a higher priority, if the DMA controller is operated as described above, the period during which data is transferred from the DMA controller may deviate from the desired data transfer period. As a result, problems may occur in which some of the data to be transferred is missing, or unnecessary data may be mixed into some of the transferred data.

One aspect of the present disclosure is to enable a CPU in a vehicle electronic control device equipped with a DMA controller to accurately obtain data for a desired period via the DMA controller.

An electronic control device for a vehicle according to one aspect of the present disclosure includes a CPU (12), a DMA controller (20), a RAM (16), a timer (18), and a data input unit (22) within a microcomputer.

The CPU sets the start timing for the data input unit to start data transfer in the timer, and causes the timer to output a first interrupt signal at the start timing. In addition, when the CPU receives the first interrupt signal output from the timer, it sets the end timing for ending data transfer in the timer, and causes the timer to output a second interrupt signal at the end timing.

Meanwhile, the DMA controller starts transferring data from the data input unit to the RAM in synchronization with the first output synchronized with the timer, and ends the data transfer in synchronization with the second output synchronized with the timer.

In this manner, according to the vehicle electronic control device disclosed herein, the DMA controller starts data transfer in synchronization with the output from the timer, and ends data transfer in synchronization with the output from the timer.

Therefore, data is transferred from the data input unit to the RAM without delay during the data transfer period defined by the start and end timings. And because the data transferred to the RAM is data that is transferred without being affected by delays in interrupt processing, the CPU can use that data to properly control the vehicle.

Next, a vehicle electronic control device according to another aspect of the present disclosure includes a CPU, a DMA controller, a RAM, a timer, and a data input unit, similar to the above.
Then, the CPU sets the start timing for starting data transfer from the data input unit in a timer, and causes the timer to output an interrupt signal at the start timing.

Moreover, the DMA controller starts transferring data from the data input section to the RAM in synchronization with the output synchronized with the timer.
Therefore, in this vehicle electronic control unit as well, data transfer can be started without being affected by delays in interrupt processing.

When the CPU receives an interrupt signal output from the timer, it periodically determines whether the amount of data transferred from the data input unit to the RAM has reached a preset number. When the amount of data reaches the preset number, it ends the data transfer by the DMA controller.

Thus, the end timing of the data transfer will be affected by delays in interrupt processing, but because the CPU does not acquire more than the set amount of data, it can acquire data for the desired period without being affected by delays in interrupt processing.

1 is a block diagram showing an overall configuration of a vehicle electronic control device according to a first embodiment; FIG. 1 is an explanatory diagram illustrating a problem caused by a delay in interrupt processing in a CPU. 1 is an explanatory diagram illustrating a flow in which an analog waveform is input from a sensor to an A/D converter and the data is transferred to a RAM; 4 is a time chart illustrating a data transfer operation by a DMA controller. 4 is a flowchart showing a processing procedure of a CPU and a DMA controller. 10 is a flowchart showing a processing procedure of a CPU and a DMA controller according to a second embodiment. 10 is a time chart illustrating a data transfer operation by a DMA controller according to a second embodiment. FIG. 13 is an explanatory diagram of a modified example in which a CPU is configured to acquire data taking into account a delay time caused by an A/D converter.

Hereinafter, embodiments of the present disclosure will be described with reference to the drawings.
[First embodiment]
As shown in FIG. 1, a vehicle electronic control unit (hereinafter, referred to as ECU) 4 of this embodiment is a device that controls the fuel injection amount, ignition timing, etc. of an engine 2 mounted on a vehicle.

The ECU 4 includes a microcomputer (hereinafter, MCU) 10 as a control unit that performs processing to control the engine 2. The MCU 10 includes a CPU 12, a ROM 14, a RAM 16, a timer 18, and a DMA controller (hereinafter, DMAC) 20.

The microcomputer 10 also includes an input section 22 that receives detection signals from various sensors provided in the engine 2, and an output section 24 that outputs control signals to the fuel injection device and ignition device of the engine 2. The above-mentioned sections within the microcomputer 10 are connected to each other via a bus 26.

The input section 22 is provided with an A/D converter 30 .
The A/D converter 30 is used for A/D conversion of input signals (i.e., analog voltages) from sensors, and in this embodiment, converts detection signals from a knock sensor that detects vibrations of the engine 2 into digital data.

The A/D converter 30 may also perform A/D conversion of the output from a sensor that outputs an analog voltage as a detection signal, such as a temperature sensor that detects the temperature of the engine 2 or the intake air, or an intake air pressure sensor that detects the pressure of the intake air.

The A/D converter 30 is configured to repeatedly A/D convert the detection signal from the knock sensor, for example, in synchronization with the rotation signal output from the rotation sensor at each predetermined rotation angle of the engine 2. Then, the DMAC 20 transfers the data A/D converted by the A/D converter 30 to the RAM 16. The A/D converter 30 may be configured to A/D convert the detection signal at regular intervals.

During the data transfer period set by the CPU 12 in synchronization with the rotation of the engine 2, the DMAC 20 sequentially transfers the multiple pieces of data A/D converted by the A/D converter 30 to the RAM 16.

The data transfer period is preset to a period from BTDC 60° CA to ATDC 60° CA in terms of the crank angle of the engine 2, for example, so that knock determination can be performed based on the detection signal from the knock sensor.

In order to have the DMAC 20 perform data transfer during the data transfer period, the CPU 12 sets the transfer period in the timer 18, and the timer 18 generates an interrupt to the CPU 12 at the start or end of the transfer.

Then, during the interrupt processing of the CPU 12, it instructs the DMAC 20 to start and end the transfer. The DMAC 20 can transfer data from the A/D converter 30 to the RAM 16 during the data transfer period according to the instructions output from the CPU 12.

However, in this case, as shown in FIG. 2, the interrupt processing executed by the CPU 12 at the start and end of the data transfer period may be delayed by other interrupt processing with a higher priority.

This interrupt processing delay may result in a delay in the command to DMAC20 to start the data transfer, causing the first data in the data transfer period to be missing, or a delay in the command to DMAC20 to end the data transfer, causing unnecessary data to be mixed in at the end of the transferred data.

Therefore, in this embodiment, as shown in Figures 3 and 4, the CPU 12 sequentially sets the start timing and end timing of the data transfer period in the timer 18, and causes the timer 18 to generate a first interrupt signal and a second interrupt signal at each of these timings.

The timer 18 may be, for example, a counter that measures time by counting pulse signals output at regular intervals from a pulse generator. In this embodiment, since the transferred data is A/D converted by the A/D converter 30 for each predetermined rotation angle of the engine 2, which is the object of control, a counter that counts up for each predetermined rotation angle of the engine 2 is used for the timer 18.

Next, the DMAC 20 starts transferring data from the register 32 of the A/D converter 30 to the RAM 16 in synchronization with an output synchronized with the timer 18 (hereinafter, the synchronous output), and ends the data transfer in synchronization with the next synchronous output from the timer 18.

In other words, as shown in FIG. 4, the timer 18 outputs a signal whose level is inverted at a set timing by the counter's output compare function as a signal synchronized with the timer 18. Then, the DMAC 20 starts and ends data transfer according to the change in the level of this output signal.

Therefore, data transfer by the DMAC 20 is not delayed by delays in interrupt processing executed by the CPU 12, and the DMAC 20 can transfer data A/D converted by the A/D converter 30 to the RAM 16 for the desired data transfer period.

The register 32 temporarily holds the A/D conversion result by the A/D converter 30. In other words, the A/D converter 30 writes the A/D conversion result to the register 32 every time it A/D converts the detection signal from the sensor 40. During the data transfer period, the DMAC 20 sequentially transfers the data written to the register 32 to the RAM 16.

On the other hand, when the CPU 12 receives a first interrupt signal output from the timer 18 at the timing of starting the data transfer, the CPU 12 sets the end timing in the timer 18 through interrupt processing. Also, when the CPU 12 receives a second interrupt signal output from the timer 18 at the timing of ending the data transfer, the CPU 12 uses the interrupt processing to carry out processing using the transferred data.

As a result, the CPU 12 can obtain all data transferred from the DMAC 20 to the RAM 16 during the data transfer period for the correct period. In addition, the data transferred from the DMAC 20 during the next data transfer period can be written to the buffer area of the RAM 16.

Next, the above-mentioned operation of the CPU 12 and the operation of the DMAC 20 will be described with reference to the flowchart shown in FIG.
As shown in FIG. 5, in S100, the CPU 12 sets the start timing of the data transfer period, more specifically, the count value until the start timing, in the timer 18, and permits the DMAC 20 to start the data transfer in synchronization with the synchronous output from the timer 18.

In S100, when the start timing of the data transfer period is set in the timer 18, the timer 18 counts the pulse output synchronized with the rotation of the engine 2 until the start timing is reached. Then, as shown in FIG. 4, when the count value of the timer 18 matches the count value of the start timing, the output signal is inverted and a first interrupt signal is generated.

This first interrupt signal causes the CPU 12 to execute the interrupt process of S110. In the interrupt process of S110, the end timing of the data transfer period is set in the timer 18.

Meanwhile, in S200, the DMAC 20 receives an enable signal from the CPU 12, enabling it to start data transfer in synchronization with the synchronous output from the timer 18. Then, it waits for the synchronous output from the timer 18 to change from OFF to ON, and when the synchronous output from the timer 18 changes from OFF to ON, in S210 it starts data transfer by transferring the A/D conversion result stored in the register 32 to the RAM 16.

Next, in S110, the CPU 12 sets the end timing of the data transfer period in the timer 18. The timer 18 counts the rotation angle of the engine 2 until the end timing is reached, and when the end timing is reached, it inverts the synchronous output and generates a second interrupt signal.

In response to this second interrupt signal, the CPU 12 executes the interrupt process of S120.
In the interrupt process of S120, the process is carried out using the data that has been transferred from the register 32 during the data transfer period and that has been stored in the buffer area of the RAM 16.

In addition, in the interrupt process of S 120 , the DMAC 20 is prohibited from starting a data transfer in synchronization with the synchronous output from the timer 18 .
In addition, since the data transferred from the register 32 and stored in the RAM 16 is vibration data obtained from the knock sensor within a specified rotation angle range of the engine 2, the CPU 12 uses that data to make a knock judgment on the engine 2 and control the ignition timing of the engine 2.

Meanwhile, when DMAC 20 starts data transfer of the A/D conversion result in S210, it waits for the synchronous output from timer 18 to change from ON to OFF. Then, when the synchronous output from timer 18 changes from ON to OFF, it stops data transfer of the A/D conversion result in S220 and proceeds to S230.

In S230, the CPU 12 sends a command in the interrupt process of S120 to prohibit the start of data transfer in synchronization with the synchronous output from the timer 18, and in accordance with the prohibition command, prohibits the start of data transfer in synchronization with the synchronous output from the timer 18.

As described above, in the ECU 4 of this embodiment, the DMAC 20 provided in the microcontroller 10 starts data transfer in synchronization with the first synchronous output from the timer 18, and ends data transfer in synchronization with the second synchronous output from the timer 18.

As a result, during the data transfer period, all data A/D converted by the A/D converter 30 is transferred from the register 32 of the A/D converter 30 to the RAM 16, and the CPU 12 can obtain the data without being affected by delays in interrupt processing.

Therefore, delays in the interrupt processing of the CPU 12 do not result in some of the data used by the CPU 12 for engine control being lost or unnecessary data being mixed in, and the CPU 12 can appropriately control the engine 2 based on the data obtained from the DMAC 20.

[Second embodiment]
In the first embodiment, the period during which the DMAC 20 transfers data is set in advance, and the CPU 12 causes the timer 18 to generate an interrupt signal at both the start and end of the data transfer period.

However, the timing for ending the data transfer does not necessarily need to be specified. For example, the data transfer may be ended when the CPU 12 detects the number of pieces of data acquired after the DMAC 20 starts the data transfer and the number reaches a preset number.

Hereinafter, a vehicle electronic control device configured to operate in this manner will be described as a second embodiment of the present disclosure.
The vehicle electronic control device of this embodiment is configured similarly to the ECU 4 of the first embodiment, and differs from the first embodiment only in the operations of the CPU 12 and the DMAC 20 of the microcomputer 10. Therefore, in this embodiment, the operations of the CPU 12 and the DMAC 20 will be described, and descriptions of parts common to the first embodiment will be omitted.

As shown in FIG. 6, in the same manner as in the first embodiment, in S100, the CPU 12 sets the start timing of the data transfer period in the timer 18 and permits the DMAC 20 to start data transfer in synchronization with the synchronous output from the timer 18. Then, when an interrupt signal is output from the timer 18, in S130, the DMAC 20 is prohibited from starting data transfer in synchronization with the output from the timer 18.

Meanwhile, by receiving permission from the CPU 12 in S200, the DMAC 20 becomes able to start data transfer in synchronization with the synchronous output from the timer 18. Therefore, the DMAC 20 waits for the synchronous output from the timer 18 to invert, and when the synchronous output from the timer 18 is inverted, in S230, the DMAC 20 starts data transfer by transferring the A/D conversion result stored in the register 32 to the RAM 16.

When the DMAC 20 starts data transfer in this way, the CPU 12 sends a command in the process of S130 to prohibit the start of data transfer in synchronization with the synchronous output from the timer 18.

Therefore, when the DMAC 20 starts data transfer in S230, it waits in S240 for a command to prohibit the start of data transfer to be sent from the CPU 12, and when the command is sent, it prohibits the start of data transfer in synchronization with the synchronous output from the timer 18.

The process of S240 is executed after the data transfer is started in S230, so the data transfer from the DMAC 20 continues until a command to stop the data transfer is received from the CPU 12 in the following S250. Then, when the DMAC 20 receives a command to stop the data transfer from the CPU 12 in S250, it stops the data transfer.

Next, after executing the process of S130, the CPU 12 proceeds to S140, and in the periodic process executed at a predetermined interval as shown in FIG. 7, it determines whether the amount of data transferred from the register 32 to the RAM 16 by the DMAC 20 has reached a preset number.

Then, if it is determined in the periodic processing of S140 that the amount of data transferred from register 32 to RAM 16 has not reached the set amount, the process returns to S140 and the amount of data is determined again in the next periodic processing.

On the other hand, if it is determined in S140 that the amount of data transferred from the register 32 to the RAM 16 has reached the set amount, the CPU 12 proceeds to S150 and outputs a data transfer stop command to the DMAC 20. As a result, data transfer to the RAM 16 by the DMAC 20 is stopped.

In this manner, in this embodiment, the data transfer by the DMAC 20 from the register 32 to the RAM 16 continues from the start of the data transfer period until the number of transferred data reaches the set number. Therefore, the data transfer period is determined by the number of data transferred from the register 32 to the RAM 16.

However, even in this case, the data transfer by the DMAC 20 is started without delay from the start timing, and the CPU 12 can obtain the desired number of data, as specified by the set number, after the data transfer starts.
Therefore, similar to the first embodiment, the CPU 12 can acquire the data A/D converted by the A/D converter 30 during the desired data transfer period for an accurate period of time, and use that data to properly perform engine control.

[Modification]
Next, in the above embodiment, the CPU 12 is described as saving all data transferred from the DMAC 20 during a data transfer period in a predetermined storage area of the RAM 16 .

However, since it takes time for the detection signal to be A/D converted in the A/D converter 30, the A/D conversion result of the detection signal is transferred from the DMAC 20 with a delay of this time (hereinafter, A/D conversion delay time) from the actual detection timing of the sensor.

Therefore, in this modified example, the CPU 12 transfers data from the register 32 to the RAM 16, taking into account this A/D conversion delay time.
8, the CPU 12 discards data transferred from the register 32 to the RAM 16 during the A/D conversion delay time from the start timing of the data transfer period. Also, the CPU 12 extends the data transfer period by the A/D conversion delay time.

As a result, according to this modified example, it becomes possible to obtain the detection signal data detected by the sensor within the desired data transfer period without being affected by the delay time required for A/D conversion in the A/D converter 30.

In the first embodiment, to extend the data transfer period by the delay time of the A/D conversion, the data transfer period is set to include the A/D conversion delay time, and the end timing is determined.

In addition, in the second embodiment, to extend the data transfer period by the A/D conversion delay time, the number used for the determination in S150 of FIG. 6 can be set to the number of data that should have been acquired plus the number of data that corresponds to the A/D conversion delay time.

Although the embodiments and modifications of the present disclosure have been described above, the present disclosure is not limited to the above-described embodiments and modifications, and can be implemented in various forms.
For example, in the above embodiment, the ECU 4 has been described as controlling the engine 2 mounted on the vehicle, but the vehicle electronic control device of the present disclosure may also control equipment other than the engine provided in the vehicle's drive system, such as an automatic transmission.

The electronic control device for a vehicle disclosed herein may also control devices installed in the braking system of the vehicle, such as a braking device, or may control on-board equipment other than the drive and braking system of the vehicle, such as an air conditioning device.

In the above embodiment, the DMAC 20 has been described as transferring data that has been A/D converted by the A/D converter 30 as a data input unit to the RAM 16, but the data transferred by the DMAC is not limited to A/D converted data. In other words, the data that the DMAC transfers to the RAM may be any data used by the vehicle electronic control unit, such as data input from another electronic control unit or a communication device.

Furthermore, multiple functions possessed by one component in the above embodiments may be realized by multiple components, or one function possessed by one component may be realized by multiple components. Further, multiple functions possessed by multiple components may be realized by one component, or one function realized by multiple components may be realized by one component. Further, part of the configuration of the above embodiments may be omitted. Further, at least part of the configuration of the above embodiments may be added to or substituted for the configuration of another of the above embodiments.

2...ECU, 10...microcomputer, 12...CPU, 16...RAM, 18...timer, 20...DMAC, 22...input section.

Claims (5)

The device comprises a CPU (12), a DMA controller (20), a RAM (16), a timer (18), and a data input unit (22);
the CPU is configured to set a start timing for starting transfer of data input to the data input unit in the timer, and cause the timer to output a first interrupt signal at the start timing, and upon receiving the first interrupt signal output from the timer, execute an interrupt process for setting an end timing for ending the data transfer in the timer, and cause the timer to output a second interrupt signal at the end timing;
The DMA controller is configured to start a transfer of the data from the data input unit to the RAM in synchronization with a first output synchronized with the timer, and to end the transfer of the data in synchronization with a second output synchronized with the timer. The device comprises a CPU (12), a DMA controller (20), a RAM (16), a timer (18), and a data input unit (22);
the CPU is configured to set a start timing for starting transfer of data input to the data input unit in the timer and to cause the timer to output an interrupt signal at the start timing;
the DMA controller is configured to initiate a transfer of the data from the data input to the RAM in synchronization with an output synchronized with the timer;
Furthermore, when the CPU receives the interrupt signal output from the timer, it determines in a periodic process whether the number of data transferred from the data input unit to the RAM has reached a preset number, and when the number of data has reached the preset number, it terminates the data transfer by the DMA controller. 3. The vehicle electronic control device according to claim 1,
The timer is a counter that counts in synchronization with the rotation of a controlled object. The vehicle electronic control device according to any one of claims 1 to 3,
The data input unit includes an A/D converter (30) that converts an input signal into digital data at a predetermined period, and the DMA controller is configured to transfer data resulting from the A/D conversion by the A/D converter from a register (32) that stores the data to the RAM. 5. The vehicle electronic control device according to claim 4,
The CPU is configured to discard, during the data transfer period, the data transferred to the RAM during a delay time of A/D conversion by the A/D converter, and to extend the data transfer period by the delay time.

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