JP7614829B2 - Multi-Display - Google Patents

Description

The present invention relates to a multi-display.

For example, organic EL display devices (organic EL displays) that use organic electroluminescence (EL) elements are highly luminous and self-luminous, can be driven at a low DC voltage, have high response speeds, and emit light from a solid organic film. As a result, they have excellent display performance and can be made thin, lightweight, and consume less power. For these reasons, they are expected to replace liquid crystal display devices in the future (see, for example, Patent Document 1 below).

Specifically, an organic EL display device has a display panel including a display area in which a plurality of pixels are arranged in a matrix on a surface. The display panel includes a plurality of scanning lines (gate lines), a plurality of signal lines (data lines), and a plurality of power lines (power lines) arranged in the horizontal and vertical directions on the surface of the display area, and a pixel circuit that constitutes the above-mentioned pixels is provided in each area partitioned by the plurality of scanning lines and the plurality of signal lines.

The display panel has a pixel circuit that includes an organic EL element, which is a light-emitting element, a capacitor, which is a storage capacitance, and two thin film transistor (TFT) elements, which are switching elements. In the display panel, the potential (image data) of the signal line is stored in the storage capacitance connected to the signal line via the selection TFT element through the switching operation of the selection TFT element connected to the scan line. In addition, depending on the potential of the storage capacitance, a drive current flows through the organic EL element connected to the power line via the drive TFT element. This makes it possible to cause the organic EL element to emit light (light up).

The display panel also has a peripheral area called a bezel (frame) that surrounds the periphery of the display area. In the peripheral area, a number of connection parts corresponding to a number of scanning lines and a number of signal lines that are drawn out to the outside of the display area are arranged in the horizontal and vertical directions of the peripheral area. The multiple scanning lines and multiple signal lines are electrically connected to an external drive circuit (driver) via a flexible printed circuit board (FPC) that is connected to the multiple connection parts.

In a multi-display, multiple display panels are arranged on a surface to display a single screen. However, in a multi-display, each display panel is divided and driven separately, so a driver is required for each display panel. For this reason, a multi-display has the problem of increased costs due to the increased number of drivers.

JP 2013-105148 A

The present invention has been proposed in light of the above-mentioned conventional circumstances, and aims to provide a multi-display that makes it possible to reduce the number of drivers that drive the display panel units when multiple display panel units are arranged to form a single display screen.

In order to achieve the above object, the present invention provides the following means.
[1] A display device comprising a plurality of display panel units each including a display area in which a plurality of pixels are arranged side by side within a plane;
a multi-display in which adjacent ones of the plurality of display panel units are butted against each other, so that display areas of the plurality of display panel units form a single display screen,
a connecting member that connects adjacent ones of the plurality of display panel units to each other,
the connecting member has a connection wiring that electrically connects the adjacent display panel units,
The display panel unit includes a pixel circuit substrate on which a plurality of pixel circuits constituting the plurality of pixels are provided;
a plurality of first wirings arranged on one surface side of the pixel circuit substrate and electrically connected to each of the plurality of pixel circuits;
a plurality of contact plugs arranged in a thickness direction of the pixel circuit substrate and electrically connected to the plurality of first wirings,
a plurality of second wirings arranged on the other surface side of the pixel circuit substrate and electrically connected to each of the plurality of contact plugs;
a plurality of connection portions disposed on the other surface side of the pixel circuit substrate and electrically connected to the plurality of second wirings,
the plurality of connection portions are provided in a region overlapping with the display region in a plan view,
the pixel circuit substrate includes a plurality of scanning lines arranged in one direction intersecting within a plane of the display area, and a plurality of signal lines arranged in another direction intersecting within the plane of the display area,
the pixel circuit is provided for each area partitioned by the plurality of scanning lines and the plurality of signal lines;
the first wiring, the contact plug, and the second wiring are provided corresponding to the scanning lines and the signal lines, respectively;
the plurality of connection portions are provided in a line row corresponding to each of the plurality of scanning lines and the plurality of signal lines,
the plurality of scanning lines are electrically connected to a first flexible printed wiring board via the plurality of connection portions;
the plurality of signal lines are electrically connected to a second flexible printed wiring board via the plurality of connection portions;
A multi-display characterized in that the connecting member has a first opening through which the first flexible printed wiring board is pulled out, and a second opening through which the second flexible printed wiring board is pulled out .
[2] The multi-display according to [1], wherein the display panel units are stretchable and have a shape formed by developing a curved surface into a flat surface, and each of the display areas forms a single curved display screen by butting adjacent display panel units together while curving them.
[3] The multi-display according to [2], wherein the plurality of display panel units have shapes that match each other.
[4] The multi-display according to any one of [1] to [3], further comprising a support member that supports the plurality of display panel units in a state in which the display panel units are arranged in a plane.
[5] The multi-display according to [4], wherein the connecting member is constituted by the supporting member .
[ 6 ] The plurality of scanning lines are electrically connected to a scanning line driving circuit via the first flexible printed wiring board,
The multi-display described in any one of [1] to [5], characterized in that the multiple signal lines are electrically connected to a signal line driving circuit via the second flexible printed wiring board.

As described above, according to the present invention, it is possible to provide a multi-display that makes it possible to reduce the number of drivers that drive the display panel units when multiple display panel units are arranged to form a single display screen.

1 is a perspective view showing a configuration of a multi-display according to a first embodiment of the present invention. In the configuration of the multi-display shown in FIG. 1, (A) is a plan view in which a plurality of display panel units are developed, and (B) is a perspective view showing a support member. FIG. 2 is a cross-sectional view showing a configuration of the multi-display shown in FIG. FIG. 2 is a circuit diagram showing a configuration of a display panel unit. FIG. 2 is a circuit diagram showing a configuration of a pixel circuit. 2 is a cross-sectional view showing a configuration of a main part of a display panel unit. FIG. FIG. 2 is a cross-sectional view showing a configuration of a pixel circuit substrate. FIG. 2 is a perspective plan view showing a configuration of a pixel circuit substrate. 1A to 1C are cross-sectional views illustrating a process for manufacturing a pixel circuit substrate. 1A to 1C are cross-sectional views illustrating a process for manufacturing a pixel circuit substrate. 1A to 1C are cross-sectional views illustrating a process for manufacturing a pixel circuit substrate. 1A to 1C are cross-sectional views illustrating a process for manufacturing a pixel circuit substrate. 1A to 1C are cross-sectional views illustrating a process for manufacturing a pixel circuit substrate. 1A to 1C are cross-sectional views illustrating a process for manufacturing a pixel circuit substrate. 1A to 1C are cross-sectional views illustrating a process for manufacturing a pixel circuit substrate. 1A to 1C are cross-sectional views illustrating a process for manufacturing a pixel circuit substrate. FIG. 2 is a perspective view illustrating a process for producing a multi-display. FIG. 11 is a plan view showing a plurality of display panel units constituting a multi-display according to a second embodiment of the present invention, in which the display panel units are expanded. FIG. 19 is a cross-sectional view showing the configuration of the multi-display shown in FIG. 18. FIG. 11 is a plan view showing a configuration of a multi-display according to a third embodiment of the present invention. FIG. 21 is a cross-sectional view showing the configuration of the multi-display shown in FIG. 20. 4 is a cross-sectional view showing a configuration of a pixel circuit substrate and a connecting member. FIG. FIG. 2 is a perspective plan view showing the configuration of a pixel circuit substrate and connection wiring. FIG. 13 is a cross-sectional view showing a configuration of a multi-display according to a fourth embodiment of the present invention. FIG. 13 is a perspective view showing a configuration of a multi-display according to a fifth embodiment of the present invention. In the configuration of the multi-display shown in FIG. 25, (A) is a plan view showing a plurality of display panel units developed, and (B) is a perspective view showing a support member. FIG. 26 is a cross-sectional view showing the configuration of the multi-display shown in FIG. 25. FIG. 13 is a plan view showing the configuration of a multi-display according to a sixth embodiment of the present invention. FIG. 29 is a cross-sectional view showing the configuration of the multi-display shown in FIG. 28. FIG. 29 is a cross-sectional view showing another configuration of the multi-display shown in FIG. 28.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.
In addition, the drawings used in the following description may show characteristic parts in a schematic manner for the sake of convenience in order to make the characteristics easier to understand, and the number of components and dimensional ratios are not necessarily the same as in reality. Furthermore, the materials, dimensions, etc. exemplified in the following description are merely examples, and the present invention is not necessarily limited to them, and can be appropriately changed and implemented within the scope of the present invention.

(First embodiment)
First, as a first embodiment of the present invention, a multi-display 1A shown in, for example, FIGS. 1 to 8 will be described.

FIG. 1 is a perspective view showing the configuration of multi-display 1A. FIG. 2 shows the configuration of multi-display 1A, with (A) being a plan view of multiple display panel units 2 unfolded, and (B) being a perspective view showing support member 50. FIG. 3 is a cross-sectional view showing the configuration of multi-display 1A. FIG. 4 is a circuit diagram showing the configuration of display panel unit 2. FIG. 5 is a circuit diagram showing the configuration of pixel circuit 3. FIG. 6 is a cross-sectional view of a main part showing the configuration of display panel unit 2. FIG. 7 is a cross-sectional view showing the configuration of pixel circuit board 4. FIG. 8 is a perspective plan view showing the configuration of pixel circuit board 4.

As shown in Figures 1, 2, and 3, the multi-display 1A of this embodiment includes a plurality of display panel units 2 including a display area E in which a plurality of pixels P are arranged side by side within a plane, and a support member 50 that supports the plurality of display panel units 2 in a curved state.

The multiple display panel units 2 are stretchable and have a shape obtained by expanding a curved surface onto a flat surface. In other words, when the curved surfaces of the multiple display panel units 2 are expanded onto a flat surface, they have a shape that is divided so that a contour line is drawn along the boundary line between adjacent display panel units.

In the multi-display 1A, the display panel units 2 are attached to one side of the support member 50 with adjacent display panel units 2 curved and butted against each other. As a result, the display areas E of the display panel units 2 form a single curved display screen S.

In this embodiment, a hemispherical (dome) three-dimensional (3D) multi-display 1A is configured. The inner surface of this multi-display 1A configures a spherical concave display screen S. The multiple display panel units 2 have a boat-shaped cone shape (non-rectangular shape) that is a hemisphere expanded onto a plane using, for example, a fracture projection method (in this embodiment, a boat-shaped polycone projection method).

The multiple display panel units 2 have the same shape and are arranged side by side in one direction (the vertical direction in FIG. 2(A)), with adjacent ones being connected to each other.

The support member 50 is made of a transparent resin material such as an acrylic resin and is formed in a hemispherical shape to match the three-dimensional shape of the multi-display 1A. The multiple display panel units 2 are attached to one surface (outer surface) of the support member 50 via a first adhesive layer 51. As a result, the support member 50 supports the multiple display panel units 2 in a hemispherically curved state. Note that FIG. 3 shows the cross-sectional shape of the multi-display 1A when it is in a planar shape.

The first adhesive layer 51 is made of a transparent adhesive material, such as an epoxy resin adhesive.

An anti-reflection layer 52 is disposed on the other surface (inner surface) of the support member 50. The anti-reflection layer 52 is located on the front surface side of each display panel unit 2 and prevents reflection of external light, and is composed of a film-like circular polarizing plate.

The anti-reflection layer 52 is attached to the surface (inner surface) of the support member 50 opposite each display panel unit 2 via a second adhesive layer 53. The second adhesive layer 53 is made of the same material as the first adhesive layer 51.

The display panel unit 2 is an organic EL display device (organic EL display) that uses organic EL elements to display color.

Specifically, the display panel unit 2 has a pixel circuit substrate 4 on which pixel circuits 3 that constitute pixels P are provided, as shown in Figures 4, 5, and 6.

The pixel circuit board 4 includes a plurality of scanning lines 5 arranged in one direction (vertical direction in FIGS. 4 and 5) that intersects within the plane of the display area E, and a plurality of signal lines 6 and a plurality of power lines 7 arranged in another direction (horizontal direction in FIGS. 4 and 5) that intersects within the plane of the display area E. The pixel circuit board 4 has a structure in which a pixel circuit 3 is provided for each area partitioned by the plurality of scanning lines 5, the plurality of signal lines 6, and the plurality of power lines 7.

The display panel unit 2 also has a structure in which a plurality of pixels (called "subpixels") P corresponding to at least the three primary colors of red (R), green (G), and blue (B) are grouped into one pixel unit (called a "pixel") Pu, and these pixel units Pu are periodically arranged within the plane.

In this embodiment, one pixel unit Pu is formed by arranging a pixel P corresponding to red (R), a pixel P corresponding to green (G), and a pixel P corresponding to blue (B) periodically in another direction. Also, in this embodiment, pixel units Pu that are rectangular in plan view are arranged in a matrix on the surface of a display area E that is non-rectangular in plan view, thereby forming a display panel unit 2 that is non-rectangular in plan view.

The pixel unit Pu is not necessarily limited to the above-mentioned configuration, and can be configured, for example, with four pixels P, including the pixels P corresponding to red (R), green (G), and blue (B) and a pixel P corresponding to white (W). Also, it is not limited to a configuration in which a plurality of pixels P corresponding to the above-mentioned color display is arranged, and it is also possible to have a configuration in which a plurality of pixels P corresponding to monochrome display is arranged.

As shown in Figures 5 and 7, the pixel circuit 3 includes an organic EL element 8, which is a light-emitting element, a capacitor 9, which is a storage capacitance C, and two TFT elements (a selection TFT element 10 and a drive TFT element 11), which are switching elements.

The organic EL element 8 has a structure in which a pixel electrode 13, an organic functional layer 14, and a common electrode 15 are sequentially laminated on one surface (front surface in FIG. 7) of a substrate 12 that constitutes the pixel circuit board 4. In other words, the organic EL element 8 has a structure in which the organic functional layer 14 is sandwiched between the pixel electrode 13, which is the positive electrode (+), and the common electrode 15, which is the negative electrode (-).

The substrate 12 is made of a flexible substrate such as a plastic substrate. In this embodiment, a film-like plastic substrate having a thickness of, for example, 10 μm or less is used as the substrate 12. The plastic substrate is made of a resin material such as polyimide.

The substrate 12 is not necessarily limited to the configuration using the flexible substrate described above, but can also be configured using a rigid substrate such as a glass substrate.

The pixel electrodes 13 are provided corresponding to each of the plurality of pixels P. The pixel electrodes 13 are made of a metal electrode material such as aluminum (Al). The pixel electrodes 13 are formed on an interlayer insulating layer 16 that covers a surface on which the two TFT elements 10 and 11 described below are formed. The interlayer insulating layer 16 is made of, for example, silicon oxide (SiO _x ). The pixel electrodes 13 are electrically connected to the source electrode 11s side of the driving TFT element 11.

The organic functional layer 14 has a structure (called a "heterostructure") in which, for example, a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, and an electron injection layer are stacked in this order. A bank layer 17 is provided on the interlayer insulating layer 16, except on the surface of the pixel electrode 13. The bank layer 17 is made of, for example, a coating-type organic insulating material. The organic functional layer 14 is embedded inside the bank layer 17.

The common electrode 15 constitutes a single solid electrode common to multiple pixels P. The common electrode 15 is made of a transparent electrode material such as indium tin oxide (ITO). The common electrode 15 is formed so as to cover the surface on which the organic functional layer 14 and the bank layer 17 are formed. In addition, a protective layer 18 is formed on the common electrode 15 so as to cover the entire surface of the substrate 12. The protective layer 18 is made of, for example, a coating-type organic insulating material.

The common electrode 15 is electrically connected to a GND line 19. The GND line 19 is provided on the surface of a gate insulating layer 20 that constitutes two TFT elements 10 and 11 described later. The GND line 19 is electrically connected to the common electrode 15 via a contact plug 21a that penetrates the interlayer insulating layer 16, a contact electrode 21b formed on the interlayer insulating layer 16, and a contact plug 21c that penetrates the bank layer 17.

In the organic EL element 8, holes injected and transported from the pixel electrode 13 side through the hole injection layer and hole transport layer, and electrons injected and transported from the common electrode side through the electron injection layer and electron transport layer recombine in the light-emitting layer, making it possible to emit light.

The organic EL element 8 has a top emission structure in which light is extracted from one side of the substrate 12 (hereinafter, one side of the substrate 12 will be referred to as the "front side" and the other side of the substrate 12 will be referred to as the "back side").

When a color display is performed using the organic EL element 8, a configuration is used in which an organic EL element that emits white light is combined with color filters corresponding to red (R), green (G), and blue (B). Alternatively, a configuration may be used in which organic EL elements that emit red light, green light, and blue light are combined.

The storage capacitance C is provided such that one end of the capacitor 9 is electrically connected to the source electrode 10s of the selection TFT element 10 and the gate electrode 11g of the drive TFT element 11, and the other end of the capacitor 9 is electrically connected to the source electrode 11s of the drive TFT element 11.

The two TFT elements 10, 11 are provided side by side on a substrate 12. The two TFT elements 10, 11 use an oxide semiconductor such as an oxide of indium (In)-tin (Sn)-zinc (Zn) (InSnZnO). The oxide semiconductor may be an oxide containing at least one metal element such as In, gallium (Ga), Zn, Sn, or Al, or may be polycrystalline silicon, amorphous silicon, or an organic semiconductor. The gate insulating layer 20 uses, for example, silicon oxide (SiO _x ).

The selection TFT element 10 is provided with a gate electrode 10g electrically connected to the scanning line 5, a drain electrode 10d electrically connected to the signal line 6, and a source electrode 10s electrically connected to the gate electrode 11g of the drive TFT element 11 and one end of the storage capacitance C (capacitor 9).

The driving TFT element 11 is provided with a gate electrode 10g electrically connected to the source electrode 10s of the selection TFT element 10 and the storage capacitance C (one end of the capacitor 9), a drain electrode 11d electrically connected to the power line 7, and a source electrode 11s electrically connected to the pixel electrode 13 and the other end of the storage capacitance C (capacitor 9).

In the display panel unit 2, the potential (image data) of the signal line 6 is held in the holding capacitance C via the selection TFT element 10 by the switching operation of the selection TFT element 10. Also, depending on the potential of the holding capacitance C, a driving current flows from the power line 7 to the organic EL element 8 via the driving TFT element 11. This makes it possible to cause the organic EL element 8 to emit light (light up).

As shown in Figures 6, 7 and 8, the pixel circuit substrate 4 of this embodiment has a plurality of first wirings 31 arranged on the front side of the substrate 12, a plurality of contact plugs 32 arranged in the thickness direction of the substrate 12, a plurality of second wirings 33 arranged on the rear side of the substrate 12, and a plurality of connection portions 34 arranged on the rear side of the substrate 12.

The multiple first wirings 31 are electrically connected to each of the multiple pixel circuits 3. The multiple contact plugs 32 are electrically connected to each of the multiple first wirings 31. The multiple second wirings 33 are electrically connected to each of the multiple contact plugs 32. That is, the first wirings 31 and the second wirings 33 are electrically connected via the contact plugs 32.

The first wiring 31 and the second wiring 33 are formed in a linear pattern using a conductive material such as copper, aluminum, molybdenum, or chromium. The contact plug 32 is formed by embedding a conductive material such as copper, aluminum, molybdenum, or chromium, such as a coating type of silver (Ag) paste, in a contact hole penetrating the substrate 12.

The first wiring 31, the contact plug 32, and the second wiring 33 are provided corresponding to each of the multiple scanning lines 5. That is, each scanning line 5 is routed from the front side to the back side of the substrate 12 by the first wiring 31, the contact plug 32, and the second wiring 33.

The first wiring 31, the contact plug 32, and the second wiring 33 are provided corresponding to each of the multiple signal lines 6. That is, each signal line 6 is routed from the front side to the back side of the substrate 12 by the first wiring 31, the contact plug 32, and the second wiring 33.

The multiple connection parts 34 electrically connect each of the multiple second wirings 33 to each of the multiple terminals provided on one end side of the flexible printed circuit board (FPC) 35.

The connection portion 34 is formed by using a connection material such as anisotropic conductive film (ACF) or anisotropic conductive paste (ACP) to cross between the second wirings 33, and while maintaining insulation between the second wirings 33, the connection portion 34 is made conductive at the positions where it overlaps with each of the second wirings 33, thereby electrically connecting each of the second wirings 33 to each terminal of the FPC 35 and bonding the FPC 35 to the pixel circuit board 4.

The multiple scanning lines 5 are electrically connected to the FPC 35 (hereinafter, referred to as the "first flexible printed circuit board (FPC) 35A" as needed) via multiple connection parts 34 (hereinafter, referred to as the "first connection parts 34A" as needed).

The first connection parts 34A are arranged in one direction (vertical direction in FIG. 8) for each line row corresponding to each of the multiple scanning lines 5. The first FPC 35A is provided with a scanning line driving circuit (gate driver) 36 including, for example, a shift register and a level shifter. The multiple scanning lines 5 are electrically connected to the gate driver 36 via the first FPC 35A. The gate driver 36 sequentially supplies scanning signals to the multiple scanning lines 5, and switches the driving of the selection TFT elements 10 in response to the scanning signals.

The multiple signal lines 6 are electrically connected to the FPC 35 (hereinafter, referred to as the "second flexible printed circuit board (FPC) 35B" as needed) via multiple connection parts 34 (hereinafter, referred to as the "second connection parts 34B" as needed).

The second connection parts 34B are arranged in the other direction (horizontal direction in FIG. 8) for each line row corresponding to each of the multiple signal lines 6. The second FPC 35B is provided with a signal line drive circuit (data driver) 37 including, for example, a shift register, a level shifter, a video line, and an analog switch. The multiple signal lines 6 are electrically connected to the data driver 37 via this second FPC 35B. The data driver 37 supplies image data to the multiple signal lines 6.

In the area that overlaps with the display area E of the pixel circuit substrate 4 in a planar view, a plurality of contact plugs 32 (hereinafter, distinguished as "first contact plugs 32A" as necessary) are arranged in one direction (the vertical direction in FIG. 8) for each line row corresponding to each of the plurality of scanning lines 5.

The multiple first contact plugs 32A are electrically connected to one end of each second wiring 33 (hereinafter, as necessary, distinguished as "first back surface wiring 33A"). On the other hand, the multiple first connection parts 34A are electrically connected to the other end of each first back surface wiring 33A.

In addition, within the region that overlaps with the display region E of the pixel circuit substrate 4 in a planar view, a plurality of contact plugs 32 (hereinafter, distinguished as "second contact plugs 32B" as necessary) are arranged in another direction (horizontal direction in FIG. 8) for each line row corresponding to each of the plurality of signal lines 6.

The multiple second contact plugs 32B are electrically connected to one end of each second wiring 33 (hereinafter, as necessary, they are distinguished as "second back surface wiring 33B"). On the other hand, the multiple second connection parts 34B are electrically connected to the other end of each second back surface wiring 33B.

The first wiring 31, the contact plug 32, and the second wiring 33 are provided corresponding to each of the multiple power lines 7. That is, each power line 7 is routed from the front side to the back side of the substrate 12 by the first wiring 31, the contact plug 32, and the second wiring 33.

The multiple first wirings 31 provided corresponding to each of the multiple power supply lines 7 are electrically connected to a common single second wiring 33 (hereinafter, distinguished as the "third back surface wiring 33C" as necessary) via multiple contact plugs 32 (hereinafter, distinguished as the "third contact plugs 32C" as necessary) provided corresponding to each of the multiple power supply lines 7.

In a region that overlaps with the display region E of the pixel circuit substrate 4 in a planar view, a plurality of third contact plugs 32C are arranged in one direction (vertical direction in FIG. 8). The plurality of third contact plugs 32C are electrically connected to a third back surface wiring 33C that extends in one direction (vertical direction in FIG. 8).

The first wiring 31, the contact plug 32, and the second wiring 33 are provided in correspondence with the GND line 19. That is, the GND line 19 is routed from the front side to the back side of the substrate 12 by the first wiring 31, the contact plug 32, and the second wiring 33.

The first wiring 31 provided in correspondence with the GND line 19 is electrically connected to a common second wiring 33 (hereinafter, distinguished as the "fourth back surface wiring 33D" as necessary) via a plurality of contact plugs 32 (hereinafter, distinguished as the "fourth contact plugs 32D" as necessary) provided in correspondence with the GND line 19.

In a region that overlaps with the display region E of the pixel circuit substrate 4 in a planar view, a plurality of fourth contact plugs 32D are arranged in one direction (vertical direction in FIG. 8). The plurality of fourth contact plugs 32D are electrically connected to a fourth back surface wiring 33D that extends in one direction (vertical direction in FIG. 8).

The pixel circuit board 4 is provided with an interlayer insulating layer 38 that covers the back surface of the substrate 12. The first back surface wiring 33A and the third back surface wiring 33C are electrically connected to the first contact plug 32A and the third contact plug 32C that penetrate the substrate 12 and the interlayer insulating layer 38. On the other hand, the second back surface wiring 33B and the fourth back surface wiring 33D are electrically connected to the second contact plug 32B and the fourth contact plug 32D that penetrate the substrate 12.

As a result, a part of the first back surface wiring 33A and a part of the second back surface wiring 33B are arranged in a crossing state. Also, the third back surface wiring 33C and a part of the second back surface wiring 33B are arranged in a crossing state.

As shown in FIG. 2(A), the multiple display panel units 2 are arranged in one direction (the vertical direction in FIG. 2(A)) and adjacent ones are connected via pixel circuit boards 4.

The multiple first connection parts 34A are arranged side by side in one direction (vertical direction in FIG. 2(A)) on either side of the connection position of each pixel circuit board 4 (display panel unit 2). That is, on each pixel circuit board 4, the multiple first connection parts 34A are positioned on the center side in the other direction (horizontal direction in FIG. 2(A)) and arranged side by side in one direction (vertical direction in FIG. 2(A)).

As a result, on the rear side of each display panel unit 2, multiple first FPCs 35A, each having a gate driver 36 for each row of multiple scanning lines 5, are positioned at the center of the other direction (horizontal direction in FIG. 2(A)) and aligned in one direction (vertical direction in FIG. 2(A)).

On the other hand, on each pixel circuit board 4, multiple second connection parts 34B are positioned toward the center in one direction (the vertical direction in FIG. 2(A)) and arranged side by side in the other direction (the horizontal direction in FIG. 2(A)).

As a result, on the rear side of each display panel unit 2, multiple second FPCs 35B, each having a data driver 37 for each row of multiple signal lines 6, are positioned at the center in one direction (the vertical direction in FIG. 2(A)) and aligned in the other direction (the horizontal direction in FIG. 2(A)).

In the display panel unit 2 having the above-mentioned configuration, a plurality of connection parts 34 (first connection part 34A and second connection part 34B) are provided in the area overlapping with the above-mentioned display area E in a planar view. This makes it possible to connect the first FPC 35A and the second FPC 35B via the plurality of connection parts 34 in the area overlapping with the display area E of the display panel unit 2 in a planar view, and to arrange the gate driver 36 and the data driver 37 provided on the first FPC 35A and the second FPC 35B on the back side of the pixel circuit board 4.

In addition, the area of the pixel circuit substrate 4 that overlaps with the display area E in a planar view roughly matches the outer shape of the substrate 12. This eliminates the need to provide a peripheral area for arranging the gate driver 36 and data driver 37 outside the display area E, making it possible to reduce the peripheral area of the display panel unit 2.

Therefore, in the multi-display 1A of this embodiment, when multiple display panel units 2 are arranged in a plane to display as a single screen, it is possible to construct a seamless (unnoticeable) display screen S.

Next, a method for manufacturing the display panel unit 2 will be described with reference to FIGS.
9 to 16 are cross-sectional views for explaining the process of manufacturing the pixel circuit substrate 4. As shown in FIG.

The manufacturing process of the display panel unit 2 includes the step of fabricating the pixel circuit board 4.

In the process of manufacturing the pixel circuit board 4, first, as shown in FIG. 9, a substrate 12 formed in a film shape on the surface of a first glass substrate 101 is prepared. Then, on one surface (front surface) of this substrate 12, the first wiring 31 including the above-mentioned scanning line 5, signal line 6, power supply line 7, and GND line 19, contact plug 21a, contact electrode 21b, and contact plug 21c, the organic EL element 8 (pixel electrode 13, organic functional layer 14, and common electrode 15) constituting the pixel circuit 3, the capacitor 9, the selection TFT element 10 including the gate insulating layer 20, and the driving TFT element 11, the interlayer insulating layer 16, the bank layer 17, and the protective layer 18 are formed.

These formation processes can be performed using conventionally known film formation processes, photolithography processes, and the like, and there are no particular limitations on the formation method.

Next, as shown in FIG. 10, a second glass substrate 103 is attached to the top layer of the substrate 12 via an adhesive layer 102.

Next, as shown in FIG. 11, laser light L is irradiated from the first glass substrate 101 side toward the substrate 12. At this time, the laser light L passes through the first glass substrate 101 and is absorbed by the substrate 12, causing a part of the plastic film near the interface with the first glass substrate 101 to evaporate due to heat. This allows the first glass substrate 101 to be peeled off from the other surface (rear surface) of the substrate 12, as shown in FIG. 12.

Next, as shown in FIG. 13, contact holes 104 are formed through the substrate 12 and the gate insulating layer 20 at the positions where the second contact plug 32B and the fourth contact plug 32D are to be formed on the substrate 12.

Next, as shown in FIG. 14, the second contact plug 32B and the fourth contact plug 32D are embedded in the contact hole 104, and then the second back surface wiring 33B and the fourth back surface wiring 33D are patterned on the back surface of the substrate 12.

Next, as shown in FIG. 15, an interlayer insulating layer 38 is formed on the rear surface of the substrate 12, and then contact holes 105 are formed through the substrate 12 and the interlayer insulating layer 38 at the positions where the first contact plug 32A and the third contact plug 32C of the substrate 12 are to be formed.

Next, as shown in FIG. 16, the first contact plug 32A and the third contact plug 32C are embedded in the contact hole 105, and then the first back surface wiring 33A and the third back surface wiring 33C are patterned on the back surface of the substrate 12.

Next, the ACP that becomes the first connection portion 34A and the second connection portion 34B is formed, and then the first FPC 35A and the second FPC 35B are connected via the first connection portion 34A and the second connection portion 34B. Finally, the second glass substrate 103 is removed together with the adhesive layer 102. This makes it possible to fabricate the display panel unit 2.

The display panel units 2 are connected to each other via the pixel circuit board 4. Therefore, it is possible to collectively manufacture a plurality of display panel units 2 connected to each other using the substrate 12.

In the manufacturing method of the display panel unit 2, by providing a plurality of connection parts 34 (first connection part 34A and second connection part 34B) in an area overlapping with the above-mentioned display area E in a planar view, it is possible to arrange the gate driver 36 and data driver 37 provided on the first FPC 35A and the second FPC 35B on the back side of the pixel circuit substrate 4. This makes it unnecessary to provide a peripheral area for arranging the gate driver 36 and data driver 37 outside the display area E, and it is possible to manufacture a display panel unit 2 with a reduced peripheral area.

In addition, by using a film-like plastic substrate with a thickness of 10 μm or less as the substrate 12, it is possible to reduce the size (opening diameter) of the contact holes 104 and 105 described above. This makes it possible to reduce the size of the pixel P and achieve high definition for the display panel unit 2.

Next, a method for manufacturing the multi-display 1A will be described with reference to FIG.
FIG. 17 is a perspective view for explaining the process of producing the multi-display 1A.

When manufacturing the multi-display 1A, as shown in FIG. 17, adjacent ones of the above-mentioned multiple display panel units 2 are butted against each other while being curved, and the multiple display panel units 2 are bonded to one surface (outer surface) of a support member 50 via a first adhesive layer 51. In addition, an anti-reflection layer 52 is bonded to the other surface (inner surface) of the support member 50 via a second adhesive layer 53. This makes it possible to produce the multi-display 1A.

In the multi-display 1A of this embodiment, when the above-mentioned multiple display panel units 2 are arranged to form a single curved display screen S, it is possible to form a seamless curved surface by eliminating gaps between the units. Therefore, in this multi-display 1A, it is possible to suppress deterioration of image quality between adjacent display panel units 2.

In addition, in the multi-display 1A, the above-mentioned multiple display panel units 2 are arranged side by side in one direction (vertical direction), and multiple first connection parts 34A (gate drivers 36) are arranged side by side in one direction (vertical direction) on either side of the connection positions of each display panel unit 2.

In contrast to this, it is also possible to arrange multiple display panel units 2 side by side in another direction (horizontal direction), and to arrange multiple second connection parts 34B (data drivers 37) side by side in another direction (horizontal direction) on either side of the connected positions of each display panel unit 2.

In the multi-display 1A, the above-mentioned multiple display panel units 2 are connected via the pixel circuit board 4, but at least some or all of the display panel units 2 may be unconnected. In this case, the multiple display panel units 2 can be connected using the support member 50 as a connecting member.

In the multi-display 1A, the concave display screen S is formed by the spherical concave inner surface described above, but it is also possible to form a convex display screen S by a spherical convex outer surface. In this case, the multiple display panel units 2 may be bonded to the inner surface side of the support member 50 via a first adhesive layer 51.

When a concave display screen S is configured, it is preferable to connect the FPC 35 to each display panel unit 2 after bonding the multiple display panel units 2 to the support member 50. On the other hand, when a convex display screen S is configured, it is preferable to connect the FPC 35 to each display panel unit 2 before bonding the multiple display panel units 2 to the support member 50.

Second Embodiment
Next, as a second embodiment of the present invention, a multi-display 1B shown in, for example, FIGS. 18 and 19 will be described.

FIG. 18 is a plan view of the multiple display panel units 2 that make up the multi-display 1B when unfolded. FIG. 19 is a cross-sectional view showing the configuration of the multi-display 1. In the following explanation, the same parts as those in the multi-display 1A will not be described and will be given the same reference numerals in the drawings.

As shown in Figures 18 and 19, the multi-display 1B of this embodiment has a structure in which the above-mentioned multiple display panel units 2 are connected via an FPC 35, instead of the configuration in which the multiple display panel units 2 are connected via a pixel circuit board 4.

Specifically, the multiple display panel units 2 are arranged in one direction (the vertical direction in FIG. 18) and adjacent ones are connected via the first FPC 35A. In other words, the multiple display panel units 2 are connected using the first FPC 35A as a connecting member.

As a result, a first FPC 35A, on which a gate driver 36 is provided for each row of scanning lines 5, is provided on the rear side of each display panel unit 2, located at the center side of the other direction (horizontal direction in FIG. 18) and extending in one direction (vertical direction in FIG. 18).

In the multi-display 1B of this embodiment, when the above-mentioned multiple display panel units 2 are arranged to form a single curved display screen S, it is possible to form a seamless curved surface by eliminating gaps between the units. Therefore, in this multi-display 1B, it is possible to suppress deterioration of image quality between adjacent display panel units 2.

In addition, in the multi-display 1B, the above-mentioned multiple display panel units 2 are arranged side by side in one direction (vertical direction), and multiple first connection parts 34A (gate drivers 36) are arranged side by side in one direction (vertical direction) on either side of the connection positions of each display panel unit 2.

In contrast to this, it is also possible to arrange multiple display panel units 2 side by side in another direction (horizontal direction), and to arrange multiple second connection parts 34B (data drivers 37) side by side in another direction (horizontal direction) on either side of the connected positions of each display panel unit 2.

In this case, the multiple display panel units 2 can be configured such that adjacent ones arranged in the other direction (horizontal direction) are connected via the second FPC 35B, with the second FPC 35B serving as a connecting member.

In addition, in the multi-display 1B, similar to the multi-display 1A, it is not limited to the case where a concave display screen S is formed by the spherical concave inner surface described above, but it is also possible to form a convex display screen S by a spherical concave outer surface.

Third Embodiment
Next, as a third embodiment of the present invention, a multi-display 1C shown in, for example, FIGS. 20 to 23 will be described.

Note that FIG. 20 is a plan view showing the configuration of multi-display 1C. FIG. 21 is a cross-sectional view showing the configuration of multi-display 1C. FIG. 22 is a cross-sectional view showing the configuration of pixel circuit board 4 and connecting member 43. FIG. 23 is a perspective plan view showing the configuration of pixel circuit board 4 and connection wiring 44. In the following explanation, the same parts as those in multi-display 1A will not be described and will be given the same reference numerals in the drawings.

As shown in Figs. 20 and 21, instead of the non-rectangular display panel unit 2 and hemispherical support member 50 described above, the multi-display 1C of this embodiment includes a rectangular display panel unit 41, a plate-shaped support member 42 that supports the multiple display panel units 41 in a lined-up state, and a plate-shaped connecting member 43 that connects adjacent ones of the multiple display panel units 41.

In the multi-display 1C, the display areas E of the multiple display panel units 41 form a single display screen S by bonding the front sides of the multiple display panel units 41 to one side of the support member 42 via a first adhesive layer 51 while adjacent ones of the multiple display panel units 41 are butted against each other.

In this embodiment, pixel units Pu, each of which is rectangular in plan view, are arranged in a matrix on the surface of a display area E, which is rectangular in plan view, to form a display panel unit 41, which is rectangular in plan view. Apart from this, the display panel unit 41 has basically the same configuration as the display panel unit 2 described above.

In this embodiment, nine display panel units 41 are arranged in a vertical line of three and a horizontal line of three to form a rectangular display screen G in a plan view, but the number of display panel units 41 can be changed as appropriate.

The support member 42 is made of a transparent flexible substrate such as a plastic substrate, and has a shape corresponding to the display screen S. The plastic substrate is made of a resin material such as polyimide. Note that the support member 42 is not necessarily limited to the configuration using the flexible substrate described above, and when a rigid substrate is used for the substrate 12, it is also possible to use a transparent rigid substrate such as a glass substrate.

An anti-reflection layer 52 is disposed on the other surface of the support member 42. The anti-reflection layer 52 is attached to the surface of the support member 42 opposite to each display panel unit 41 via a second adhesive layer 53.

Of the multiple display panel units 41, the multiple display panel units 41 (hereinafter, as necessary, distinguished as "display panel units 41A") that are located at one end side (right end side in FIG. 20) of the other direction (horizontal direction in FIG. 20) and lined up in one direction (vertical direction in FIG. 20) have multiple first FPCs 35A on which gate drivers 36 are provided.

On the rear side of each display panel unit 41A, multiple first FPCs 35A, each of which has a gate driver 36 for each row of multiple scanning lines 5, are arranged in one direction (vertical direction in Figure 20).

On the other hand, among the multiple display panel units 41, the display panel unit 41 (hereinafter, distinguished as "display panel unit 41B" as necessary) that is located at one end side (top end side in FIG. 20) in one direction (vertical direction in FIG. 20) and aligned in the other direction (horizontal direction in FIG. 20) has multiple second FPCs 35B provided with data drivers 37.

On the rear side of each display panel unit 41B, multiple second FPCs 35B, each of which has a data driver 37 for each of the signal lines 6, are arranged in the other direction (horizontally in FIG. 20).

21, 22, and 23, the connecting members 43 are arranged in a grid pattern in plan view along the boundary lines between adjacent display panel units 2. In addition, a plurality of connection wirings 44 that electrically connect adjacent display panel units 41 are provided on the surface of the connecting member 43 that faces the display panel units 41. The connection wirings 44 are formed in a linear pattern using the same conductive material as the first wiring 31 and the second wiring 33.

Specifically, between the adjacent display panel units 41, among the multiple connection wirings 44, there are multiple connection wirings 44 (hereinafter, distinguished as "first connection wirings 44A" as necessary) that electrically connect between the multiple scanning lines 5 (first back wiring 33A), multiple connection wirings 44 (hereinafter, distinguished as "second connection wirings 44B" as necessary) that electrically connect between the multiple signal lines 6 (second back wiring 33B), multiple connection wirings 44 (hereinafter, distinguished as "third connection wirings 44C" as necessary) that electrically connect between the multiple power supply lines 7 (third back wiring 33C), and multiple connection wirings 44 (hereinafter, distinguished as "fourth connection wirings 44D" as necessary) that electrically connect between the GND lines 19 (fourth back wiring 33D).

This allows the scanning lines 5 between adjacent display panel units 41 in the horizontal direction to be connected and driven by the gate driver 36 provided in the right-most display panel unit 41A.

In addition, between multiple display panel units 41 adjacent to each other in the vertical direction, the signal lines 6 can be connected and driven by the data driver 37 provided in the uppermost display panel unit 41B.

In the multi-display 1C of the embodiment having the above-mentioned configuration, it is not necessary to provide gate drivers 36 and data drivers 37 for all of the display panel units 41 described above. Therefore, in this multi-display 1C, when multiple display panel units 41 are arranged to form one display screen S, it is possible to reduce the number of gate drivers 36 and data drivers 37 that drive each display panel unit 41.

In addition, in the multi-display 1C of this embodiment, when the above-mentioned multiple display panel units 41 are arranged to form one display screen S, it is possible to form a seamless plane by eliminating gaps between the units. Therefore, in this multi-display 1C, it is possible to suppress deterioration of image quality between adjacent display panel units 41.

The multi-display 1C is configured using the plate-shaped connecting member 43 described above, but the connecting member 43 may be configured using an FPC. In other words, the connecting member 43 may be electrically connected using an FPC instead of the connection wiring 44 that electrically connects the adjacent display panel units 41 described above.

The connecting member 43 may also be divided into one connecting member 43 that is provided with a first connecting wire 44A and a third connecting wire 44C and extends vertically, and another connecting member 43 that is provided with a second connecting wire 44B and a fourth connecting wire 44D and extends horizontally.

(Fourth embodiment)
Next, as a fourth embodiment of the present invention, a multi-display 1D shown in FIG. 24 will be described.

Note that FIG. 24 is a cross-sectional view showing the configuration of multi-display 1D. In the following explanation, the same parts as those in multi-displays 1A and 1C will not be described and will be denoted by the same reference numerals in the drawings.

As shown in FIG. 24, the multi-display 1D of this embodiment is configured to use the above-mentioned connecting member 43 as a support member. That is, the connecting member 43 has a shape corresponding to the display screen S, electrically connects the above-mentioned adjacent display panel units 41 via a plurality of connection wirings 44, and is attached to the back side of the plurality of display panel units 41 via an adhesive layer 45.

In this case, the adhesive layer 45 is not limited to the same transparent adhesive material as the first adhesive layer 51, and an opaque adhesive material can be used. Also, the support member 42 that supports the front side of the multiple display panel units 41 can be omitted.

In this embodiment, the support member 42 is omitted, and thus the first adhesive layer 51, the anti-reflection layer 52, and the second adhesive layer 53 are omitted. However, the anti-reflection layer 52 may be attached to the front side of the multiple display panel units 41 via the second adhesive layer 53.

In the multi-display 1D of the embodiment having the above-mentioned configuration, it is not necessary to provide gate drivers 36 and data drivers 37 for all of the display panel units 41 described above. Therefore, in this multi-display 1D, when multiple display panel units 41 are arranged to form one display screen S, it is possible to reduce the number of gate drivers 36 and data drivers 37 that drive each display panel unit 41.

In addition, in the multi-display 1D of this embodiment, when the above-mentioned multiple display panel units 41 are arranged to form one display screen S, it is possible to form a seamless plane by eliminating gaps between the units. Therefore, in this multi-display 1C, it is possible to suppress deterioration of image quality between adjacent display panel units 41.

In the multi-display 1D, the plate-shaped connecting member 43 is used as a support member (support substrate), but when using the connecting member 43 as a support member, the shape of the connecting member 43 can be changed as appropriate. In addition, the connecting member 43 may be configured such that the connection wiring 44 is provided on a support member such as a frame or housing that supports the rear side of the multiple display panel units 41.

Fifth Embodiment
Next, as a fifth embodiment of the present invention, a multi-display 1E shown in, for example, FIGS. 25 to 27 will be described.

FIG. 25 is a perspective view showing the configuration of multi-display 1E. FIG. 26 shows the configuration of multi-display 1E, with (A) being a plan view of multiple display panel units 2 unfolded, and (B) being a perspective view showing support member 50. FIG. 27 is a cross-sectional view showing the configuration of multi-display 1E. Note that FIG. 27 shows the cross-sectional shape of multi-display 1E in a planar shape. In the following explanation, the same parts as those in multi-display 1A will not be explained and will be given the same reference numerals in the drawings.

As shown in Figures 25, 26, and 27, the multi-display 1E of this embodiment has a plurality of display panel units 2 that are butted against each other while being curved, and are attached to the other surface (inner surface) of the support member 50 via an adhesive layer 45.

In addition, the support member 50 serves as the connecting member 43, electrically connecting the adjacent display panel units 2 via a plurality of connection wirings 44, and is attached to the rear side of the plurality of display panel units 2 via an adhesive layer 45.

On the rear side of each display panel unit 2, multiple first FPCs 35A, each of which has a gate driver 36 for each row of multiple scanning lines 5, are positioned at the center of the other direction (horizontal direction in FIG. 26(A)) and aligned in one direction (vertical direction in FIG. 26(A)).

On the other hand, among the multiple display panel units 41, the display panel unit 2 (hereinafter, as necessary, will be distinguished as "display panel unit 2AB") located at the center in one direction (the vertical direction in FIG. 26(A)) has multiple second FPCs 35B on which data drivers 37 are provided.

On the rear side of the display panel unit 2A, multiple second FPCs 35B, each having a data driver 37 for each row of multiple signal lines 6, are positioned at the center in one direction (the vertical direction in FIG. 26(A)) and aligned in the other direction (the horizontal direction in FIG. 26(A)).

Between adjacent display panel units 2, among the multiple connection wirings 44, multiple connection wirings 44 (hereinafter, "second connection wirings 44B" as necessary) are provided, which electrically connect the multiple signal lines 6 (second back surface wirings 33B) via second connection parts 34B.

This allows the signal lines 6 between multiple vertically adjacent display panel units 2 to be connected and driven by the data driver 37 provided in the central display panel unit 2A.

The support member 50 has a first opening 50a through which the first FPC 35A is pulled out to the outer surface side, and a second opening 50b through which the second FPC 35B is pulled out to the outer surface side. As a result, the gate driver 36 and the data driver 37 are disposed on the outer surface side of the support member 50.

In the embodiment of the multi-display 1E having the above-mentioned configuration, it is not necessary to provide a data driver 37 in all of the display panel units 2 described above. Therefore, in this multi-display 1E, when multiple display panel units 2 are arranged to form a single curved display screen S, it is possible to reduce the number of data drivers 37 that drive each display panel unit 2.

In addition, in the multi-display 1E of this embodiment, when the above-mentioned multiple display panel units 2 are arranged to form a single curved display screen S, it is possible to form a seamless curved surface by eliminating gaps between the units. Therefore, in this multi-display 1E, it is possible to suppress deterioration of image quality between adjacent display panel units 2.

In the multi-display 1E, the back sides of the above-mentioned multiple display panel units 2 are supported by a support member 50, so that the first adhesive layer 51, anti-reflection layer 52, and second adhesive layer 53 are omitted. However, the anti-reflection layer 52 may be attached to the front sides of the multiple display panel units 2 via the second adhesive layer 53.

Sixth Embodiment
Next, as a sixth embodiment of the present invention, a multi-display 1F shown in, for example, FIGS. 28 to 30 will be described.

FIG. 28 is a plan view showing the configuration of multi-display 1F. FIG. 29 is a cross-sectional view showing the configuration of multi-display 1F. FIG. 30 is a cross-sectional view showing another configuration of multi-display 1F. Note that in FIGS. 29 and 30, the cross-sectional shape of multi-display 1F is shown in a planar shape. In the following explanation, the same parts as those in multi-display 1A will not be described and will be given the same reference numerals in the drawings.

The multi-display 1F of this embodiment has the same configuration as the multi-display 1A described above, but also has a shielding layer 54A as shown in Figures 28 and 29.

The shielding layer 54A is made of a resin having light-shielding properties, such as a black resist material used as a black matrix. The shielding layer 54A is provided between the display panel unit 2 and the support member 50. It is preferable to provide the shielding layer 54A on the side closer to the display panel unit 2. For this reason, in this embodiment, the shielding layer 54A is provided on the surface of the support member 50 that faces the display panel unit 2.

The shielding layer 54A is arranged in a grid pattern in a plan view along the boundary lines between adjacent display panel units 2 and the boundary lines between adjacent pixel units Pu.

In the multi-display 1F of this embodiment, by providing a shielding layer 54A between the adjacent display panel units 2 described above, the seams between these panels can be hidden by the shielding layer 54A. This makes it possible to suppress deterioration of image quality between the adjacent display panel units 2.

Furthermore, in the multi-display 1F of this embodiment, by providing a shielding layer 54A between the above-mentioned adjacent pixel units Pu, it is possible to eliminate the distinction between the boundary lines between adjacent display panel units 2 and the boundary lines between adjacent pixel units Pu. As a result, when the multi-display 1A is formed by arranging multiple display panel units 2 in a plane and displaying them as a single screen, it is possible to configure a seamless (unnoticeable) display screen S.

The multi-display 1F of this embodiment may be configured with a shielding layer 54B as shown in FIG. 30 instead of the shielding layer 54A.

The shielding layer 54B is made of a metal having light reflectivity, such as silver or aluminum. The shielding layer 54B is provided between the support member 50 and the anti-reflection layer 52. It is preferable to provide the shielding layer 54B on the side closer to the anti-reflection layer 52. For this reason, in this embodiment, the shielding layer 54B is provided on the surface of the anti-reflection layer 52 facing the support member 50.

The shielding layer 54B is arranged in a grid pattern in a plan view along the boundary lines between adjacent display panel units 2 and the boundary lines between adjacent pixel units Pu.

In the multi-display 1F of this embodiment, by providing a shielding layer 54B between the adjacent display panel units 2 described above, the seam between these panels can be hidden by the shielding layer 54B. In particular, the anti-reflection layer 52 blocks light reflected by the shielding layer 54B using a circular polarizer, so the portion where this shielding layer 54B is provided appears black without reflection. This makes it possible to suppress deterioration of image quality between the adjacent display panel units 2.

Furthermore, in the multi-display 1F of this embodiment, by providing a shielding layer 54B between the above-mentioned adjacent pixel units Pu, it is possible to eliminate the distinction between the boundary lines between adjacent display panel units 2 and the boundary lines between adjacent pixel units Pu. As a result, when the multi-display 1B is formed by arranging multiple display panel units 2 in a plane and displaying them as a single screen, it is possible to configure a seamless (unnoticeable) display screen S.

The multi-display 1F of this embodiment is not limited to the configuration of the multi-display 1A, but can be configured by adding the shielding layers 54A and 54B to the configuration of the multi-displays 1B to 1F.

The present invention is not necessarily limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the present invention.
For example, in the above embodiment, the above-mentioned hemispherical (dome) shaped three-dimensional (3D) multi-displays 1A, 1B, 1D-1F and the planar multi-display 1C are exemplified, but the multi-displays to which the present invention is applied are not necessarily limited to such shapes, and the shape can be changed as appropriate, for example, to a spherical shape, a cylindrical shape, a round (arch) shape, etc.

In the above embodiment, a display panel unit 2 having a boat-shaped cone shape (non-rectangular shape) that is a hemisphere expanded on a plane is shown as an example, but the shape of the display panel unit 2 can also be changed as appropriate.

In the above embodiment, the present invention is applied to the organic EL display described above. However, the light-emitting element is not necessarily limited to an organic EL element, and may be an LED element such as a micro LED or a light-emitting element such as a quantum dot. The present invention can also be applied to liquid crystal displays.

The present invention can be widely applied to a variety of uses as the above-mentioned three-dimensional (3D) multi-display, such as displays for virtual reality (VR), planetariums, globes, driving simulators, in-car displays, and omnidirectional displays.

1A to 1F... Multi-display 2... Display panel unit 3... Pixel circuit 4... Pixel circuit board 5... Scanning line 6... Signal line 7... Power supply line 8... Organic EL element 9... Capacitor 10... Selection TFT element 11... Driving TFT element 12... Substrate 13... Pixel electrode 14... Organic functional layer 15... Common electrode 16... Interlayer insulating layer 17... Bank layer 18... Protective layer 19... GND line 20... Gate insulating layer 31... First wiring 32... Contact plug 32A... First contact plug 32B... Second contact plug 32C... Third contact plug 32D... Fourth contact plug 33... Second wiring 33A... First back wiring 33B... Second back wiring 33C... Third back wiring 33D... Fourth back wiring 34... Connection part 34A...first connection portion 34B...second connection portion 35...flexible printed circuit board (FPC) 35A...first FPC 35B...second FPC 36...scanning line driving circuit (gate driver) 37...signal line driving circuit (data driver) 38...interlayer insulating layer 41...display panel unit 42...support member 43...connecting member 44...connecting wiring 44A...first connection wiring 44B...second connection wiring 44C...third connection wiring 44D...fourth connection wiring 50...support member 50a...first opening 50b...second opening 45...adhesive layer 51...first adhesive layer 52...anti-reflection layer (circular polarizer) 53...second adhesive layer 54A...shielding layer (resin) 54B...shielding layer (metal) C...storage capacitance P...pixel Pu...pixel unit E...display area S...Display screen

Claims (6)

A display device includes a plurality of display panel units each including a display area in which a plurality of pixels are arranged side by side within a plane,
a multi-display in which adjacent ones of the plurality of display panel units are butted against each other, so that display areas of the plurality of display panel units form a single display screen,
a connecting member that connects adjacent ones of the plurality of display panel units to each other,
the connecting member has a connection wiring that electrically connects the adjacent display panel units,
The display panel unit includes a pixel circuit substrate on which a plurality of pixel circuits constituting the plurality of pixels are provided;
a plurality of first wirings arranged on one surface side of the pixel circuit substrate and electrically connected to each of the plurality of pixel circuits;
a plurality of contact plugs arranged in a thickness direction of the pixel circuit substrate and electrically connected to the plurality of first wirings,
a plurality of second wirings arranged on the other surface side of the pixel circuit substrate and electrically connected to each of the plurality of contact plugs;
a plurality of connection portions disposed on the other surface side of the pixel circuit substrate and electrically connected to the plurality of second wirings,
the plurality of connection portions are provided in a region overlapping with the display region in a plan view,
the pixel circuit substrate includes a plurality of scanning lines arranged in one direction intersecting within a plane of the display area, and a plurality of signal lines arranged in another direction intersecting within the plane of the display area,
the pixel circuit is provided for each area partitioned by the plurality of scanning lines and the plurality of signal lines;
the first wiring, the contact plug, and the second wiring are provided corresponding to the scanning lines and the signal lines, respectively;
the plurality of connection portions are provided in a line row corresponding to each of the plurality of scanning lines and the plurality of signal lines,
the plurality of scanning lines are electrically connected to a first flexible printed wiring board via the plurality of connection portions;
the plurality of signal lines are electrically connected to a second flexible printed wiring board via the plurality of connection portions;
A multi-display characterized in that the connecting member has a first opening through which the first flexible printed wiring board is pulled out, and a second opening through which the second flexible printed wiring board is pulled out . The multi-display according to claim 1, characterized in that the display panel units are flexible and have a shape formed by developing a curved surface into a flat surface, and by butting adjacent units together while curving them, each of the display areas forms a single curved display screen. The multi-display according to claim 2, characterized in that the multiple display panel units have shapes that match each other. The multi-display according to any one of claims 1 to 3, characterized in that it is provided with a support member that supports the plurality of display panel units in a state in which they are arranged in a plane. The multi-display according to claim 4, characterized in that the connecting member is formed by the supporting member. the plurality of scanning lines are electrically connected to a scanning line driving circuit via the first flexible printed wiring board;
6. The multi-display according to claim 1, wherein the plurality of signal lines are electrically connected to a signal line drive circuit via the second flexible printed wiring board.

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