JP7736059B2 - Semiconductor Devices - Google Patents

Description

The present disclosure relates to a semiconductor device.

This application claims priority to Japanese Application No. 2021-061026, filed on March 31, 2021, and incorporates by reference all of the contents of that Japanese application.

Semiconductor modules in which multiple semiconductor devices are connected by wire bonding have been proposed (see, for example, Patent Document 1). Semiconductor devices that aim to improve breakdown voltage through the placement of termination structures, etc. have also been proposed (see, for example, Patent Documents 2 and 3).

International Publication No. 2018/029801 International Publication No. 2013/168795 International Publication No. 2015/145593

The semiconductor device disclosed herein comprises a silicon carbide substrate having a first main surface, an electrode on the first main surface, and a connection member connected to the electrode, wherein the first main surface is inclined from (0001), and the planar shape of the electrode when viewed from a direction perpendicular to the first main surface is a rectangle or rounded rectangle having a first side and a second side parallel to the [1-100] direction of the silicon carbide substrate, wherein the first side is on the [-1-120] side of the second side, and the second side is on the [11-20] side of the first side, and wherein the shortest distance between the first side and a contact region where the connection member contacts the electrode is defined as a first distance and the shortest distance between the second side and the contact region is defined as a second distance, and the first distance is greater than the second distance.

FIG. 1 is a top view showing a semiconductor device according to the first embodiment. FIG. 2 is a cross-sectional view showing the semiconductor device according to the first embodiment. FIG. 3 is a top view showing the semiconductor device according to the second embodiment. FIG. 4 is a top view showing a semiconductor device according to the third embodiment. FIG. 5 is a cross-sectional view showing a semiconductor device according to the third embodiment. FIG. 6 is a top view showing a semiconductor device according to the fourth embodiment. FIG. 7 is a cross-sectional view showing a semiconductor device according to the fourth embodiment. FIG. 8 is a top view showing a semiconductor device according to the fifth embodiment. FIG. 9 is a top view showing a semiconductor module according to the sixth embodiment. FIG. 10 is a circuit diagram showing a semiconductor module according to the sixth embodiment.

[Problem to be solved by the present disclosure]
In conventional semiconductor devices, sufficient avalanche resistance may not be obtained after mounting.

The present disclosure aims to provide a semiconductor device that can improve avalanche resistance after mounting.

[Effects of the present disclosure]
According to the present disclosure, it is possible to improve the avalanche resistance after mounting.

The form for implementation is described below.

Description of the embodiments of the present disclosure
First, embodiments of the present disclosure will be listed and described. In the following description, the same or corresponding elements will be given the same symbols, and the same description will not be repeated. In the crystallographic descriptions in this specification, individual directions are represented by [ ], collective directions by <>, individual planes by ( ), and collective planes by { }. Furthermore, negative indices in crystallography are usually represented by placing a "-" (bar) above the number, but in this specification, a negative sign is placed before the number.

[1] A semiconductor device according to one aspect of the present disclosure includes a silicon carbide substrate having a first main surface, an electrode on the first main surface, and a connection member connected to the electrode, wherein the first main surface is inclined from (0001), and the planar shape of the electrode when viewed from a direction perpendicular to the first main surface is a rectangle or rounded rectangle having a first side and a second side parallel to the [1-100] plane of the silicon carbide substrate, the first side being on the [-1-120] side of the second side, and the second side being on the [11-20] side of the first side, wherein the shortest distance between the first side and a contact region where the connection member contacts the electrode is defined as a first distance, and the shortest distance between the second side and the contact region is defined as a second distance, and the first distance is greater than the second distance.

Silicon carbide has anisotropy in dielectric breakdown strength. For example, if the electric field strength is the same, when an electric field is applied to [11-20], dielectric breakdown is more likely to occur when compared to when an electric field is applied to [0001]. In this semiconductor device, the first edge is on the [-1-120] side of the second edge, and the second edge is on the [11-20] side of the first edge. Therefore, avalanche breakdown is more likely to occur in the region overlapping with the first edge in plan view than in the region overlapping with the second edge in plan view. Furthermore, in this semiconductor device, the first distance is greater than the second distance. Therefore, when avalanche breakdown occurs in the region overlapping with the first edge in plan view, avalanche current flows through the electrode to the connecting member, but the electrical resistance of the electrode reduces the current flowing to the connecting member. This improves avalanche resistance.

[2] A semiconductor device according to another aspect of the present disclosure includes a silicon carbide substrate having a first main surface, an electrode on the first main surface, and a connection member connected to the electrode, wherein the first main surface is inclined from (000-1), and the planar shape of the electrode when viewed from a direction perpendicular to the first main surface is a rectangle or rounded rectangle having a first side and a second side parallel to the [1-100] plane of the silicon carbide substrate, the first side being on the [-1-120] side of the second side, and the second side being on the [11-20] side of the first side, wherein the shortest distance between the first side and a contact region where the connection member contacts the electrode is defined as a first distance, and the shortest distance between the second side and the contact region is defined as a second distance, and the first distance is greater than the second distance.

As with the semiconductor device described in [1], when avalanche breakdown occurs in the region overlapping with the first edge in plan view, avalanche current flows through the electrode to the connection member, but the electrical resistance of the electrode reduces the current flowing through the connection member. This improves avalanche resistance.

[3] A semiconductor device according to another aspect of the present disclosure includes a silicon carbide substrate having a first main surface, an electrode on the first main surface, and a connection member connected to the electrode, wherein the first main surface is inclined from {0001}, and the planar shape of the electrode when viewed from a direction perpendicular to the first main surface is a rectangle or a rounded rectangle with first and second sides parallel to the [1-100] direction of the silicon carbide substrate, and when viewed from a direction perpendicular to the first main surface, the silicon carbide substrate has a first region overlapping the first side and a second region overlapping the second side, and the dielectric breakdown strength of the first region is lower than the dielectric breakdown strength of the second region, and wherein the shortest distance between the first side and a contact region where the connection member contacts the electrode is defined as a first distance and the shortest distance between the second side and the contact region is defined as a second distance, the first distance is greater than the second distance.

In this semiconductor device, the dielectric breakdown strength of the first region is lower than that of the second region, so avalanche breakdown is more likely to occur in the first region than in the second region. Furthermore, in this semiconductor device, the first distance is greater than the second distance. Therefore, when avalanche breakdown occurs in the first region in a planar view, avalanche current flows through the electrode to the connecting member, but the electrical resistance of the electrode reduces the current flowing through the connecting member. This improves avalanche resistance.

[4] In [1] to [3], multiple connection members may be connected to the electrodes in a [1-100] arrangement. In this case, it is easier to ensure a large first distance.

[5] In [1] to [3], multiple connection members may be arranged in a [11-20] pattern and connected to the electrodes. Even when multiple connection members are arranged in a [11-20] pattern, the avalanche resistance can be improved if the first distance is greater than the second distance.

[6] In [1] to [5], the connection member may be a bonding wire and may be stitch-connected to the electrode at multiple locations. In this case, the connection reliability of the connection member can be improved.

[7] In [1] to [3], the connecting member may be a metal plate. In this case, the electrical resistance of the connecting member is reduced, making it easier to reduce power loss.

[8] In any of [1] to [7], the first main surface may be a plane inclined from {0001} toward the <11-20> direction at an off-angle of 0.1 degrees or more and 8 degrees or less. In this case, good crystals are more likely to be obtained.

[9] In any of [1] to [8], the silicon carbide substrate or the electrode may have a mark that identifies the crystal orientation of the silicon carbide substrate. In this case, when mounting the silicon carbide substrate, it is easy to determine in which direction the silicon carbide substrate should be placed.

[10] In [1] to [9], the difference between the first distance and the second distance may be 500 μm or more. In this case, better avalanche resistance is obtained.

[11] In [1] to [10], the combination of the silicon carbide substrate and the electrode may form a transistor or a diode. In this case, the avalanche resistance of the transistor or diode can be improved.

[12] In [1] to [11], the connection member may be electrically connected to an external terminal. In this case, the resistance to avalanche breakdown caused by application of voltage from the external terminal can be improved.

[13] In [1] to [12], there may be multiple combinations of the silicon carbide substrate, the electrode, and the connection member. In this case, the avalanche resistance can be improved for multiple combinations.

[14] In [13], in a first combination included in the plurality of combinations, the combination of the silicon carbide substrate and the electrode may form a transistor, and in a second combination included in the plurality of combinations, the combination of the silicon carbide substrate and the electrode may form a diode, and the transistor and the diode may be connected in parallel to each other. In this case, the diode may function as a freewheeling diode for the transistor. This may improve the avalanche resistance of each of the transistor and the diode.

[15] In [13], in a first combination included in the plurality of combinations, the combination of the silicon carbide substrate and the electrode may form a first transistor, and in a second combination included in the plurality of combinations, the combination of the silicon carbide substrate and the electrode may form a second transistor, and the first transistor and the second transistor may be connected in series with each other. In this case, a power module including the first transistor and the second transistor can be configured. For example, the first transistor can be included in the upper arm, and the second transistor can be included in the lower arm. The avalanche resistance of each of the first transistor and the second transistor can be improved.

[Details of the embodiment of the present disclosure]
Embodiments of the present disclosure will be described in detail below, but the present embodiments are not limited thereto. Note that, in this specification and drawings, components having substantially the same functional configurations may be designated by the same reference numerals to avoid redundant description. In this specification and drawings, the X1-X2 direction, the Y1-Y2 direction, and the Z1-Z2 direction are defined as mutually orthogonal directions. The plane including the X1-X2 direction and the Y1-Y2 direction is defined as the XY plane, the plane including the Y1-Y2 direction and the Z1-Z2 direction is defined as the YZ plane, and the plane including the Z1-Z2 direction and the X1-X2 direction is defined as the ZX plane. For convenience, the Z1 direction is defined as the upward direction, and the Z2 direction is defined as the downward direction. Furthermore, in this disclosure, a planar view refers to viewing an object from the Z1 side.

(First embodiment)
First, a first embodiment will be described. The first embodiment relates to a PN junction diode. FIG. 1 is a top view showing a semiconductor device according to the first embodiment. FIG. 2 is a cross-sectional view showing the semiconductor device according to the first embodiment. FIG. 2 corresponds to a cross-sectional view taken along line II-II in FIG. 1.

As shown in Figures 1 and 2, the semiconductor device 100 of the first embodiment has a silicon carbide substrate 10, an anode electrode 20, a cathode electrode 30, and a bonding wire 40.

The silicon carbide substrate 10 includes a silicon carbide single crystal substrate 101 and a silicon carbide epitaxial layer 102 on the silicon carbide single crystal substrate 101. The silicon carbide substrate 10 has a first main surface 10A and a second main surface 10B opposite the first main surface 10A. The silicon carbide epitaxial layer 102 constitutes the first main surface 10A, and the silicon carbide single crystal substrate 101 constitutes the second main surface 10B. The silicon carbide substrate 10 has, for example, a rectangular parallelepiped shape. The first main surface 10A is a plane perpendicular to the Z1-Z2 direction. [1-100] is a direction parallel to the X1-X2 direction. The silicon carbide single crystal substrate 101 and the silicon carbide epitaxial layer 102 are composed of, for example, hexagonal silicon carbide of polytype 4H. Silicon carbide epitaxial layer 102 on silicon carbide single crystal substrate 101 contains n-type impurities such as nitrogen (N) and has n-type conductivity.

The first major surface 10A is a surface inclined from (0001) to the off direction. For example, the off direction is [11-20]. For example, the first major surface 10A is a surface inclined from (0001) to the off direction ([11-20]) by an off angle of 8° or less. The off angle may be, for example, 0.8° or more, or 2° or more. The off angle may be 6° or less, or 4° or less.

[11-20] is an orientation within (0001). However, because the first major surface 10A is a surface inclined in the off-axis direction from (0001), [11-20] is not an orientation within the first major surface 10A. The Y1 direction corresponds to the orientation of [-1-120] projected onto the first major surface 10A, and the Y2 direction corresponds to the orientation of [11-20] projected onto the first major surface 10A.

A first P-type region 16 and a second P-type region 17 are formed on the first major surface 10A. In a plan view, the second P-type region 17 surrounds the first P-type region 16. The second P-type region 17 functions as a breakdown voltage maintaining region.

The anode electrode 20 is provided on the first main surface 10A. The anode electrode 20 contains, for example, aluminum (Al). The anode electrode 20 is provided, for example, on a portion of the first main surface 10A, and the edge of the anode electrode 20 may be located inside the edge of the silicon carbide substrate 10 in a planar view. When viewed from a direction perpendicular to the first main surface 10A, the planar shape of the anode electrode 20 is, for example, a rounded rectangle having a first side 21 and a second side 22 parallel to the [1-100] direction of the silicon carbide substrate 10. The first side 21 and the second side 22 are parallel to the X1-X2 direction. The first side 21 is located on the Y1 side relative to the second side 22. In other words, the first side 21 is located on the [-1-120] side relative to the second side 22. Furthermore, the second side 22 is located on the Y2 side relative to the first side 21. That is, second side 22 is on the [11-20] side with respect to first side 21. The planar shape of anode electrode 20 when viewed in a direction perpendicular to first main surface 10A may be a rectangle having first side 21 and second side 22 that are parallel to the [1-100] direction of silicon carbide substrate 10.

A mark 19 specifying the crystal orientation of the silicon carbide substrate 10 may be provided on the portion of the first main surface 10A exposed from the anode electrode 20. The mark 19 may directly indicate the crystal orientation. For example, the direction of [11-20] may be indicated using Miller indices or a graphic such as a triangle. The crystal orientation of the silicon carbide substrate 10 may also be indirectly indicated by the orientation of the product number, etc.

The cathode electrode 30 is provided on the second main surface 10B. The cathode electrode 30 contains, for example, nickel (Ni), nickel silicide (NiSi), or titanium aluminum silicide (TiAlSi). The cathode electrode 30 may be provided, for example, on the entire surface of the second main surface 10B. The cathode electrode 30 is bonded, for example, onto a conductive layer 91 formed on the main surface of the insulating substrate 90 using a bonding material (not shown) such as solder. The conductive layer 91 is electrically connected to an external terminal, for example, a power supply terminal or an output terminal. The insulating substrate 90 and conductive layer 91 are omitted from Figure 1.

Multiple, for example, four bonding wires 40 are connected to the anode electrode 20. The multiple bonding wires 40 contact the anode electrode 20 at a contact region 50 of the anode electrode 20. The contact region 50 has, for example, a rectangular planar shape with two sides parallel to the X1-X2 direction and two sides parallel to the Y1-Y2 direction. In plan view, the dimension of the contact region 50 in the Y1-Y2 direction is smaller than the dimension in the X1-X2 direction, and the multiple bonding wires 40 contact the anode electrode 20 aligned in the X1-X2 direction. In other words, the multiple bonding wires 40 are connected to the anode electrode 20 aligned in a [1-100] pattern. The bonding wires 40 are electrically connected to an external terminal, such as a power terminal or an output terminal. The bonding wires 40 are an example of a connecting member. The number of bonding wires 40 is not limited. There may be only one bonding wire 40. The contact area 50 is an area within which the bonding wire 40 contacts the anode electrode 20 , and is the smallest rectangular area including two sides parallel to the first side 21 and the second side 22 .

When the shortest distance between the first side 21 and the contact area 50 is the first distance L1 and the shortest distance between the second side 22 and the contact area 50 is the second distance L2, the first distance L1 is greater than the second distance L2.

Here, we will explain the effects of the first embodiment.

The first major surface 10A is a surface inclined toward the off-axis direction (0001). For example, the off-axis direction is [11-20]. Therefore, as shown in Figure 2, [11-20] is non-parallel to the first major surface 10A. Silicon carbide has anisotropy in dielectric breakdown strength. For example, if the electric field strength is the same, when an electric field is applied to [11-20] of silicon carbide and when an electric field is applied to [0001] of silicon carbide, the former has a lower dielectric breakdown strength and is more likely to cause dielectric breakdown. Therefore, the dielectric breakdown strength of the first region 11 that overlaps with the first edge 21 of the anode electrode 20 in a planar view is lower than the dielectric breakdown strength of the second region 12 that overlaps with the second edge 22 of the anode electrode 20 in a planar view.

Furthermore, when a voltage is applied between the anode electrode 20 and the cathode electrode 30, an equipotential electric field is generated with a distribution as shown by the dashed lines in Figure 2. The strength of the electric field E1 in the first region 11 is equal to the strength of the electric field E2 in the second region 12, but the proportion of the [11-20] component in the electric field E1 is greater than that in the electric field E2, and the proportion of the [0001] component in the electric field E1 is smaller than that in the electric field E2. For this reason, avalanche breakdown is more likely to occur in the first region 11 than in the second region 12.

In this embodiment, the first distance L1 is greater than the second distance L2. Therefore, when avalanche breakdown occurs in the first region 11, an avalanche current flows through the anode electrode 20 to the bonding wire 40, but the electrical resistance of the anode electrode 20 reduces the current flowing through the bonding wire 40. This improves the avalanche resistance.

In addition, since the bonding wire 40 is connected to the anode electrode 20 in a [1-100] arrangement, it is easy to ensure a large first distance L1, making it easier to further improve avalanche resistance.

If the mark 19 is provided, it becomes easier to recognize in which direction the silicon carbide substrate 10 should be placed when mounting the silicon carbide substrate 10. Note that the mark 19 may be provided on the anode electrode 20 instead of the silicon carbide substrate 10.

Second Embodiment
Next, a second embodiment will be described with reference to Fig. 3, which is a top view showing a semiconductor device according to the second embodiment.

As shown in FIG. 3, in the semiconductor device 200 according to the second embodiment, each bonding wire 40 is stitch-connected to the anode electrode 20 at multiple locations, for example, at two locations. In the second embodiment, each bonding wire 40 also contacts the anode electrode 20 at a contact region 50 of the anode electrode 20 and is connected to the anode electrode 20 in a [1-100] arrangement. Also, in the second embodiment, the first distance L1 is greater than the second distance L2.

Other configurations are the same as in the first embodiment.

The second embodiment also achieves the same effects as the first embodiment. Furthermore, since each bonding wire 40 is connected to the anode electrode 20 at multiple locations, connection reliability can be improved.

(Third embodiment)
Next, a third embodiment will be described. Fig. 4 is a top view showing a semiconductor device according to the third embodiment. Fig. 5 is a cross-sectional view showing the semiconductor device according to the third embodiment. Fig. 5 corresponds to a cross-sectional view taken along line VV in Fig. 4.

As shown in Figures 4 and 5, the semiconductor device 300 according to the third embodiment includes a silicon carbide substrate 10, an anode electrode 20, a cathode electrode 30, and a metal plate 60. In other words, the metal plate 60 replaces the bonding wires 40. The metal plate 60 is, for example, a copper (Cu) plate. The metal plate 60 has a surface 61 that contacts the contact region 50, and contacts the anode electrode 20 at the contact region 50 of the anode electrode 20. The metal plate 60 is electrically connected to an external terminal, such as a power terminal or an output terminal. The metal plate 60 is an example of a connecting member. Also, in the third embodiment, the first distance L1 is greater than the second distance L2. The contact region 50 is the region within which the metal plate 60 contacts the anode electrode 20, and is the smallest rectangular region including two sides parallel to the first side 21 and the second side 22.

Other configurations are the same as in the first embodiment.

The third embodiment also achieves the same effects as the first embodiment. In addition, the provision of the metal plate 60 reduces electrical resistance and reduces power loss.

(Fourth embodiment)
Next, a fourth embodiment will be described. Fig. 6 is a top view showing a semiconductor device according to the fourth embodiment. Fig. 7 is a cross-sectional view showing the semiconductor device according to the fourth embodiment. Fig. 7 corresponds to a cross-sectional view taken along line VII-VII in Fig. 6.

6 and 7, in the semiconductor device 400 according to the fourth embodiment, in a plan view, the dimension of the contact region 50 in the Y1-Y2 direction is larger than the dimension in the X1-X2 direction, and the multiple bonding wires 40 are aligned in the Y1-Y2 direction and contact the anode electrode 20. In other words, the multiple bonding wires 40 are aligned in [11-20] and connected to the anode electrode 20. Also in the fourth embodiment, the first distance L1 is larger than the second distance L2.

Other configurations are the same as in the first embodiment.

The fourth embodiment also achieves the same effects as the first embodiment.

The difference between the first distance L1 and the second distance L2 is, for example, 200 μm or more. The difference between the first distance L1 and the second distance L2 is preferably 500 μm or more, more preferably 600 μm or more, and even more preferably 700 μm or more. This is because a better avalanche resistance can be obtained.

Fifth Embodiment
Next, a fifth embodiment will be described. The fifth embodiment relates to a MOS field effect transistor (FET). Fig. 8 is a top view showing a semiconductor device according to the fifth embodiment.

As shown in FIG. 8, the semiconductor device 500 of the fifth embodiment has a silicon carbide substrate 10, a source electrode 70, a gate electrode 80, a drain electrode (not shown), a bonding wire 41, and a bonding wire 42.

The source electrode 70 is provided on the first main surface 10A. The source electrode 70 contains, for example, aluminum (Al). The source electrode 70 is provided, for example, on a portion of the first main surface 10A, and the edge of the source electrode 70 may be located inside the edge of the silicon carbide substrate 10 in a planar view. When viewed from a direction perpendicular to the first main surface 10A, the planar shape of the source electrode 70 is, for example, a rounded rectangle having a first side 71 and a second side 72 parallel to the [1-100] direction of the silicon carbide substrate 10. The first side 71 and the second side 72 are parallel to the X1-X2 direction. The first side 71 is located on the Y1 side relative to the second side 72. In other words, the first side 71 is located on the [-1-120] side relative to the second side 72. Furthermore, the second side 72 is located on the Y2 side relative to the first side 71. That is, second side 72 is on the [11-20] side with respect to first side 71. The planar shape of source electrode 70 when viewed in a direction perpendicular to first main surface 10A may be a rectangle having first side 71 and second side 72 that are parallel to the [1-100] direction of silicon carbide substrate 10.

A recess 73 recessed toward the second side 72 is formed on the first side 71 of the source electrode 70, and a gate electrode 80 is formed inside the recess 73. The drain electrode is provided on the second major surface 10B. The drain electrode may be provided, for example, on the entire surface of the second major surface 10B.

Multiple, e.g., four, bonding wires 41 are connected to the source electrode 70. The multiple bonding wires 41 contact the source electrode 70 at the contact region 50 of the source electrode 70. The contact region 50 has, for example, a rectangular planar shape with two sides parallel to the X1-X2 direction and two sides parallel to the Y1-Y2 direction. In plan view, the dimension of the contact region 50 in the Y1-Y2 direction is smaller than the dimension in the X1-X2 direction, and the multiple bonding wires 41 contact the source electrode 70 aligned in the X1-X2 direction. In other words, the multiple bonding wires 41 are aligned in a [1-100] pattern and connected to the source electrode 70. The bonding wires 41 are electrically connected to an external terminal, such as a power terminal or an output terminal. The bonding wires 41 are an example of a connecting member. The number of bonding wires 41 is not limited. A single bonding wire 41 may also be used. In the fifth embodiment, the first distance L1 is greater than the second distance L2.

The bonding wire 42 is connected to the gate electrode 80. A mark 19 may be provided on the silicon carbide substrate 10 or the source electrode 70.

The fifth embodiment also achieves the same effects as the first embodiment.

In the fifth embodiment, as in the second embodiment, the bonding wire 41 may be stitched to the source electrode 70 at multiple locations. In the fifth embodiment, as in the third embodiment, a metal plate may be used instead of the bonding wire 41. In the fifth embodiment, as in the fourth embodiment, in a plan view, the dimension of the contact region 50 in the Y1-Y2 direction may be larger than the dimension in the X1-X2 direction, and multiple bonding wires 41 may be aligned in the Y1-Y2 direction and contact the source electrode 70.

Note that the semiconductor device is not limited to a PN junction diode and a MOSFET. For example, the semiconductor device may be a Schottky barrier diode or an insulated gate bipolar transistor (IGBT).

Also, the first main surface of the silicon carbide substrate may be a surface inclined from (000-1). In this case, too, the first side is on the [-1-120] side relative to the second side, the second side is on the [11-20] side relative to the first side, and the first distance is greater than the second distance.

Sixth Embodiment
Next, a sixth embodiment will be described. The sixth embodiment relates to a semiconductor module. The semiconductor module is an example of a semiconductor device. Fig. 9 is a top view showing the semiconductor module according to the sixth embodiment. Fig. 10 is a circuit diagram showing the semiconductor module according to the sixth embodiment.

As shown in Figure 6, the semiconductor module 600 according to the sixth embodiment has a P terminal 601, an N terminal 602, an O terminal 603, a first conductive pattern 611, a second conductive pattern 612, and a third conductive pattern 613. The semiconductor module 600 further has a first transistor 621, a second transistor 622, a first diode 631, and a second diode 632.

The P terminal 601 is electrically connected to the first conductive pattern 611, the O terminal 603 is electrically connected to the second conductive pattern 612, and the N terminal 602 is electrically connected to the third conductive pattern 613.

The first transistor 621 and the first diode 631 are provided on the first conductive pattern 611. The drain electrode of the first transistor 621 and the cathode electrode of the first diode 631 are joined to the first conductive pattern 611 using a bonding material (not shown) such as solder. The source electrode 641 of the first transistor 621 is connected to the second conductive pattern 612 by multiple bonding wires 661. The anode electrode 651 of the first diode 631 is connected to the source electrode 641 of the first transistor 621 by multiple bonding wires 671.

The first transistor 621 has a contact region similar to the contact region 50 of the fifth embodiment, and a bonding wire 661 contacts the source electrode 641 of the first transistor 621 at this contact region. The first diode 631 has a contact region similar to the contact region 50 of the first to fourth embodiments, and a bonding wire 671 contacts the anode electrode 651 of the first diode 631 at this contact region.

The second transistor 622 and the second diode 632 are provided on the second conductive pattern 612. The drain electrode of the second transistor 622 and the cathode electrode of the second diode 632 are bonded to the second conductive pattern 612 using a bonding material (not shown) such as solder. The source electrode 642 of the second transistor 622 is connected to the third conductive pattern 613 by multiple bonding wires 662. The anode electrode 652 of the second diode 632 is connected to the source electrode 642 of the second transistor 622 by multiple bonding wires 672.

The second transistor 622 has a contact region similar to the contact region 50 of the fifth embodiment, and a bonding wire 662 contacts the source electrode 642 of the second transistor 622 at this contact region. The second diode 632 has a contact region similar to the contact region 50 of the first to fourth embodiments, and a bonding wire 672 contacts the anode electrode 652 of the second diode 632 at this contact region.

In the sixth embodiment, as shown in FIG. 10, a first transistor 621 and a second transistor 622 are connected in series between a P terminal 601 and an N terminal 602, and an O terminal 603 is connected between the first transistor 621 and the second transistor 622. In addition, a first diode 631 is connected in parallel to the first transistor 621, and a second diode 632 is connected in parallel to the second transistor 622. An upper arm 681 is configured including the first transistor 621 and the first diode 631, and a lower arm 682 is configured including the second transistor 622 and the second diode 632.

In the sixth embodiment, the first transistor 621, the second transistor 622, the first diode 631, and the second diode 632 have excellent avalanche resistance.

In addition, it is preferable that the bonding wire contacts a contact area similar to contact area 50 in all of the first transistor 621, second transistor 622, first diode 631 and second diode 632, but this is not limited to this.

Although the embodiments have been described in detail above, they are not limited to specific embodiments, and various modifications and variations are possible within the scope of the claims.

10: Silicon carbide substrate 10A: First main surface 10B: Second main surface 11: First region 12: Second region 16: First P-type region 17: Second P-type region 19: Mark 20: Anode electrode 21: First side 22: Second side 30: Cathode electrode 40, 41, 42: Bonding wire (connecting member)
50: Contact area 60: Metal plate (connecting member)
61: Surface 70: Source electrode 71: First side 72: Second side 73: Recess 80: Gate electrode 90: Insulating substrate 91: Conductive layers 100, 200, 300, 400, 500: Semiconductor device 101: Silicon carbide single crystal substrate 102: Silicon carbide epitaxial layer 600: Semiconductor module 601: P terminal 602: N terminal 603: O terminal 611: First conductive pattern 612: Second conductive pattern 613: Third conductive pattern 621: First transistor 622: Second transistor 631: First diode 632: Second diode 641, 642: Source electrodes 651, 652: Anode electrodes 661, 662, 671, 672: Bonding wires (connecting members)
681: Upper arm 682: Lower arm

Claims (15)

a silicon carbide substrate having a first main surface;
an electrode on the first major surface;
a connection member connected to the electrode;
and
the first main surface is inclined from (0001),
a planar shape of the electrode when viewed in a direction perpendicular to the first main surface is a rectangle or a rounded rectangle having first and second sides parallel to a [1-100] direction of the silicon carbide substrate;
the first side is on the [-1-120] side with respect to the second side,
the second side is on the [11-20] side with respect to the first side,
a first distance is a shortest distance between the first side and a contact area where the connection member contacts the electrode;
When the shortest distance between the second side and the contact area is defined as a second distance,
The semiconductor device wherein the first distance is greater than the second distance. a silicon carbide substrate having a first main surface;
an electrode on the first major surface;
a connection member connected to the electrode;
and
the first main surface is inclined from (000-1),
a planar shape of the electrode when viewed in a direction perpendicular to the first main surface is a rectangle or a rounded rectangle having first and second sides parallel to a [1-100] direction of the silicon carbide substrate;
the first side is on the [-1-120] side with respect to the second side,
the second side is on the [11-20] side with respect to the first side,
a first distance is a shortest distance between the first side and a contact area where the connection member contacts the electrode;
When the shortest distance between the second side and the contact area is defined as a second distance,
The semiconductor device wherein the first distance is greater than the second distance. a silicon carbide substrate having a first main surface;
an electrode on the first major surface;
a connection member connected to the electrode;
and
the first main surface is inclined from {0001},
a planar shape of the electrode when viewed in a direction perpendicular to the first main surface is a rectangle or a rounded rectangle having first and second sides parallel to a [1-100] direction of the silicon carbide substrate;
When viewed in a plan view from a direction perpendicular to the first main surface, the silicon carbide substrate has
a first region overlapping the first side;
a second region overlapping the second side;
and
The dielectric breakdown strength of the first region is lower than the dielectric breakdown strength of the second region;
a first distance is a shortest distance between the first side and a contact area where the connection member contacts the electrode;
When the shortest distance between the second side and the contact area is defined as a second distance,
The semiconductor device wherein the first distance is greater than the second distance. A semiconductor device described in any one of claims 1 to 3, wherein multiple connection members are arranged in a [1-100] pattern and connected to the electrodes. A semiconductor device described in any one of claims 1 to 3, wherein multiple connection members are arranged in [11-20] and connected to the electrodes. A semiconductor device described in any one of claims 1 to 5, wherein the connection member is a bonding wire and is stitch-connected to the electrode at multiple locations. A semiconductor device described in any one of claims 1 to 3, wherein the connecting member is a metal plate. A semiconductor device described in any one of claims 1 to 7, wherein the first major surface is a surface inclined from {0001} in the <11-20> direction at an off-angle of 0.1 degrees or more and 8 degrees or less. A semiconductor device described in any one of claims 1 to 8, having a mark provided on the silicon carbide substrate or the electrode that identifies the crystal orientation of the silicon carbide substrate. A semiconductor device described in any one of claims 1 to 9, wherein the difference between the first distance and the second distance is 500 μm or more. A semiconductor device described in any one of claims 1 to 10, wherein the combination of the silicon carbide substrate and the electrode forms a transistor or a diode. A semiconductor device described in any one of claims 1 to 11, wherein the connection member is electrically connected to an external terminal. A semiconductor device described in any one of claims 1 to 12, having multiple combinations of the silicon carbide substrate, the electrode, and the connecting member. In a first combination included in the plurality of combinations, a combination of the silicon carbide substrate and the electrode constitutes a transistor;
In a second combination included in the plurality of combinations, the combination of the silicon carbide substrate and the electrode forms a diode;
14. The semiconductor device according to claim 13, wherein the transistor and the diode are connected in parallel with each other. In a first combination included in the plurality of combinations, a combination of the silicon carbide substrate and the electrode constitutes a first transistor;
In a second combination included in the plurality of combinations, a combination of the silicon carbide substrate and the electrode constitutes a second transistor;
The semiconductor device according to claim 13 , wherein the first transistor and the second transistor are connected in series with each other.