JP7737915B2 - Communication system, communication method and program - Google Patents

Description

This disclosure relates to a communication system, a communication method, and a program.

Communication systems that transmit and receive data between multiple devices are known. When transmitting and receiving data in such a communication system, delays can occur during data transmission. For example, Patent Document 1 describes a system in which a master station and a slave station are connected by wire, time information (pseudo-noise code) is transmitted from the slave station to the master station via wired communication, and the master station calculates the delay time based on the time information.

Patent No. 3107994

However, as in Patent Document 1, delays occur when transmitting time information from the slave station to the master station, so there is a risk that the delay time cannot be calculated with high accuracy. Furthermore, because the master station and slave stations are connected by wire, it may not be possible to calculate the delay time by communicating information between, for example, three or more devices.

The present disclosure aims to solve the above-mentioned problems by providing a communication system, communication method, and program that can calculate delay time with high accuracy.

A communication system according to the present disclosure includes a transmitter and a receiver that receives packets from the transmitter. The transmitter includes a transmission unit that outputs a clock signal with a predetermined cycle, a reference signal reception unit that receives a reference signal that serves as a time reference from a reference signal transmitter, a first time information generation unit that generates first time information indicating the time at the transmitter based on the clock signal and the reference signal, and a communication control unit that transmits packets including the first time information to the receiver. The receiver includes a transmission unit that outputs a clock signal with a predetermined cycle, a reference signal reception unit that receives the reference signal from the reference signal transmitter, a second time information generation unit that generates second time information indicating the time at the receiver based on the clock signal and the reference signal, a communication control unit that receives the packets from the transmitter, and a delay time calculation unit that calculates a delay time based on the first time information and the second time information included in the packets.

A communication method according to the present disclosure uses a transmitter and a receiver that receives packets from the transmitter, and includes the steps of: causing the transmitter to output a clock signal with a predetermined cycle; causing the transmitter to receive a reference signal that serves as a time reference from a reference signal transmitter; generating first time information indicating the time at the transmitter based on the clock signal and the reference signal; transmitting a packet including the first time information to the receiver; causing the receiver to output a clock signal with a predetermined cycle; causing the receiver to receive the reference signal from the reference signal transmitter; generating second time information indicating the time at the receiver based on the clock signal and the reference signal; causing the receiver to receive the packet from the transmitter; and calculating a delay time based on the first time information and the second time information included in the packet.

The program disclosed herein is a program that causes a computer to execute a communication method using a transmitter and a receiver that receives packets from the transmitter. The program causes the computer to execute the following steps: causing the transmitter to output a clock signal with a predetermined cycle; causing the transmitter to receive a reference signal that serves as a time reference from a reference signal transmitter; generating first time information indicating the time at the transmitter based on the clock signal and the reference signal; transmitting a packet including the first time information to the receiver; causing the receiver to transmit a clock signal with a predetermined cycle; causing the receiver to receive the reference signal from the reference signal transmitter; generating second time information indicating the time at the receiver based on the clock signal and the reference signal; causing the receiver to receive the packet from the transmitter; and calculating a delay time based on the first time information and the second time information included in the packet.

This disclosure makes it possible to calculate delay time with high accuracy.

FIG. 1 is a schematic block diagram of a communication system according to the first embodiment. FIG. 2 is a schematic block diagram of a transmitter. FIG. 3 is a diagram showing an example of the time waveform of each signal. FIG. 4 is a schematic block diagram of a receiver. FIG. 5 is a flowchart illustrating a processing flow of the transmitter and receiver according to the first embodiment. FIG. 6 is a schematic block diagram of a receiver according to the second embodiment. FIG. 7 is a graph showing an example of the average delay time. FIG. 8 is a graph showing an example of the average delay time. FIG. 9 is a flowchart illustrating a processing flow according to the second embodiment.

Preferred embodiments of the present disclosure are described in detail below with reference to the accompanying drawings. Note that the present disclosure is not limited to these embodiments, and when there are multiple embodiments, they also include configurations that combine the respective embodiments.

(First embodiment)
(Communication System)
FIG. 1 is a schematic block diagram of a communication system according to a first embodiment. As shown in FIG. 1, the communication system 100 according to the first embodiment includes a transmitter 10A and a receiver 10B. The transmitter 10A transmits data to the receiver 10B using a packet communication method, and the receiver 10B receives the data from the transmitter 10A. Hereinafter, data transmitted from the transmitter 10A to the receiver 10B will be referred to as a packet P. In this embodiment, the transmitter 10A and the receiver 10B transmit and receive the packet P via wireless communication, but the communication method may be any, such as wired communication. In the example of FIG. 1, the communication system 100 includes one transmitter 10A and one receiver 10B, but the number of transmitters 10A and receivers 10B may be any. For example, the communication system 100 may include multiple receivers 10B, and the transmitter 10A may transmit a packet P to each of the multiple receivers 10B. Furthermore, for example, the communication system 100 may have a plurality of transmitters 10A, and may transmit packets P from the plurality of transmitters 10A to the receiver 10B.

Transmitter 10A and receiver 10B receive a reference signal SR, which serves as a time reference, from a reference signal transmitter R, which is a common device. The reference signal SR may be any signal that serves as a time reference, but in this embodiment, it is a pulsed signal with a predetermined period that is generated by the reference signal transmitter R. Transmitter 10A and receiver 10B receive the reference signal SR from the reference signal transmitter R via wireless communication. However, any communication method may be used; for example, transmitter 10A and receiver 10B may be connected to the reference signal transmitter R via a wired connection and receive the reference signal SR via wired communication.

The reference signal transmitter R may be any device that generates and transmits a reference signal SR, but in this embodiment, it may be an artificial satellite. That is, in this embodiment, the transmitter 10A and the receiver 10B receive the reference signal SR from an artificial satellite for the Global Navigation Satellite System (GSNN).

(Transmitter)
Fig. 2 is a schematic block diagram of a transmitter. Fig. 3 is a diagram showing an example of the time waveform of each signal. As shown in Fig. 2, transmitter 10A has a transmission unit 20A, a reference signal reception unit 22A, a frequency division unit 24A, a communication unit 26A, a storage unit 28A, and a control unit 30A.

(Dissemination Department)
The transmitting unit 20A outputs a clock signal SCA with a predetermined period. As shown in FIG. 3, the clock signal SCA is a pulsed signal with a predetermined period. In this embodiment, the transmitting unit 20A is an oscillator element that outputs the clock signal SCA with a constant period, such as a quartz crystal or ceramic oscillator. However, the transmitting unit 20A may be any element that outputs the clock signal SCA. The frequency of the clock signal SCA is, for example, 12.8 MHz, but the frequency and period of the clock signal SCA may be any.

(Reference signal receiving unit)
The reference signal receiving unit 22A receives a reference signal SR from a reference signal transmitter R. The reference signal receiving unit 22A is a module capable of receiving the reference signal SR from the reference signal transmitter R, and in this embodiment is, for example, a GSNN receiver. As described above, the reference signal SR is a pulsed signal with a predetermined period. The period of the reference signal SR may be any period, but in this embodiment it is longer than the period of the clock signal SCA.

(Frequency division part)
The frequency divider 24A receives the reference signal SR received by the reference signal receiver 22A and the clock signal SCA output from the transmitter 20A. The frequency divider 24A generates a first time signal STA with a predetermined period by dividing the clock signal SCA output from the transmitter 20A based on the reference signal SR received by the reference signal receiver 22A. That is, the frequency divider 24A converts the period (frequency) of the clock signal SCA based on the reference signal SR to generate the first time signal STA. The frequency divider 24A is a frequency divider that divides the clock signal SCA. The first time signal STA is a pulsed signal with a predetermined period. The period of the first time signal STA may be any period, but in this embodiment, it is longer than the period of the clock signal SCA and shorter than the period of the reference signal SR.

As shown in FIG. 3, in this embodiment, the frequency divider unit 24A generates a count-up signal SU by integrating the clock signal SCA based on the reference signal SR. The frequency divider unit 24A starts integrating the clock signal SCA at a timing corresponding to the timing at which it receives a pulse of the reference signal SR (the same timing as the timing at which it receives a pulse of the reference signal SR in the example of FIG. 3), and generates a count-up signal SU by integrating the clock signal SCA. That is, after receiving a pulse of the reference signal SR, the frequency divider unit 24A increases the signal strength of the count-up signal SU each time it receives a pulse of the clock signal SCA. Then, when the signal strength of the count-up signal SU becomes equal to or greater than a threshold, i.e., after it has integrated a predetermined number of pulses of the clock signal SCA, the frequency divider unit 24A resets the signal strength of the count-up signal SU and resumes integrating the clock signal SCA. The frequency divider unit 24A generates a first time signal STA based on the clock signal SCA. More specifically, the frequency divider 24A generates the first time signal STA with a cycle corresponding to the period from when the integration of the clock signal SCA begins to when the count-up signal SU is reset. In this embodiment, the frequency divider 24A generates the first time signal STA so that the period from when the integration of the clock signal SCA begins to when the count-up signal SU is reset is 1/2 of the cycle.

When the next pulse of the reference signal SR is received, the frequency divider unit 24A resets the signal strength of the count-up signal SU and then resumes the accumulation of the clock signal SCA. In other words, when the next pulse of the reference signal SR is received, the frequency divider unit 24A forcibly resets the signal strength of the count-up signal SU and resumes the accumulation of the clock signal SCA, even if the current signal strength of the count-up signal SU is below the threshold. This allows the period of the first time signal STA to be adjusted each time the reference signal SR is received.

(Communications Department)
The communication unit 26A is a communication module for transmitting and receiving data to and from the receiver 10B, and may be, for example, an antenna or a Wi-Fi (registered trademark) module. Note that, although the communication unit 26A and the reference signal receiving unit 22A are separate pieces of hardware in the example of this embodiment, the communication unit 26A and the reference signal receiving unit 22A may also be a single piece of hardware.

(Storage part)
The storage unit 28A is a memory that stores the calculation contents and program information of the control unit 30A, and includes, for example, at least one of a RAM (Random Access Memory), a ROM (Read Only Memory), and an external storage device such as an HDD (Hard Disk Drive). The program for the control unit 30A stored in the storage unit 28A may be stored in a recording medium that can be read by the transmitter 10A.

(Control unit)
The control unit 30A is a computing device and includes an arithmetic circuit such as a CPU (Central Processing Unit). The control unit 30A includes a first time information generating unit 32A and a communication control unit 34A. The control unit 30A implements the first time information generating unit 32A and the communication control unit 34A and executes their processes by reading and executing a program (software) from the storage unit 28A. The control unit 30A may execute these processes using a single CPU, or may include multiple CPUs and execute the processes using the multiple CPUs. At least a portion of the processes performed by the first time information generating unit 32A and the communication control unit 34A may be implemented using hardware circuits. The control unit 30A may also include a device control unit that controls devices included in the transmitter 10A, such as the transmitting unit 20A, the reference signal receiving unit 22A, and the frequency dividing unit 24A.

(First time information generation unit)
The first time information generation unit 32A generates first time information indicating the time at the transmitter 10A based on the clock signal SCA and the reference signal SR. That is, the first time information indicates the internal time of the transmitter 10A. Specifically, the first time information generation unit 32A generates the first time information based on the first time signal STA, which is generated by the frequency divider unit 24A based on the clock signal SCA and the reference signal SR. Because the first time signal STA is a signal generated to have a predetermined period, the first time information generation unit 32A can generate the first time information based on the first time signal STA, that is, by counting pulses of the first time signal STA, for example. The first time information generation unit 32A sequentially counts the pulses of the first time signal STA to sequentially update the first time information.

(Communication control unit)
The communication control unit 34A transmits a packet P including the first time information generated by the first time information generation unit 32A to the receiver 10B via the communication unit 26A. That is, the communication control unit 34A includes the first time information in the packet P and transmits the packet P including the first time information to the receiver 10B. The communication control unit 34A includes the first time information indicating the time when the packet P is transmitted, i.e., the first time information indicating the most recent time, in the packet P and transmits the packet P to the receiver 10B. Note that the packet P may be any information including the first time information, and may, for example, include application information for causing the receiver 10B to execute a predetermined process (application), as shown in a second embodiment described below. In this case, the receiver 10B executes the predetermined process using the application information included in the packet P.

(Receiver)
4 is a schematic block diagram of a receiver 10B. As shown in FIG. 4, the receiver 10B includes a transmitter 20B, a reference signal receiver 22B, a frequency divider 24B, a communication unit 26B, a storage unit 28B, and a control unit 30B.

(Dissemination Department)
The transmitter 20B outputs a clock signal SCB with a predetermined period. As shown in FIG. 3, the clock signal SCB is a pulsed signal with a predetermined period. In this embodiment, the transmitter 20B is an oscillator element that outputs the clock signal SCB with a constant period, such as a quartz crystal or ceramic oscillator. However, the transmitter 20B may be any element that outputs the clock signal SCB. The frequency of the clock signal SCB is, for example, 12.8 MHz, but the frequency and period of the clock signal SCB may be any.

(Reference signal receiving unit)
The reference signal receiving unit 22B receives the reference signal SR from the reference signal transmitter R. The reference signal receiving unit 22B is a module capable of receiving the reference signal SR from the reference signal transmitter R, and in this embodiment is, for example, a GSNN receiver. The period of the reference signal SR may be any period, but in this embodiment it is longer than the period of the clock signal SCB.

(Frequency division part)
The frequency divider 24B receives the reference signal SR received by the reference signal receiver 22B and the clock signal SCB output from the transmitter 20B. The frequency divider 24B generates a second time signal STB with a predetermined period by dividing the clock signal SCB output from the transmitter 20B based on the reference signal SR received by the reference signal receiver 22B. The frequency divider 24B is a frequency divider that divides the clock signal SCB. The second time signal STB is a pulsed signal with a predetermined period. The period of the second time signal STB may be any period, but in this embodiment, it is longer than the period of the clock signal SCB and shorter than the period of the reference signal SR.

As shown in FIG. 3, in this embodiment, the frequency divider unit 24B generates a count-up signal SU by integrating the clock signal SCB based on the reference signal SR. The frequency divider unit 24B starts integrating the clock signal SCB at a timing corresponding to the timing at which it receives a pulse of the reference signal SR (the same timing as the timing at which it receives a pulse of the reference signal SR in the example of FIG. 3), and generates a count-up signal SU by integrating the clock signal SCB. That is, after receiving the reference signal SR, the frequency divider unit 24B increases the signal strength of the count-up signal SU each time it receives a pulse of the clock signal SCB. Then, when the signal strength of the count-up signal SU becomes equal to or greater than a threshold, i.e., after it has integrated a predetermined number of pulses of the clock signal SCB, the frequency divider unit 24B resets the signal strength of the count-up signal SU and resumes integrating the clock signal SCB. The frequency divider unit 24B generates a second time signal STB based on the clock signal SCB. More specifically, the frequency divider 24B generates the second time signal STB with a cycle corresponding to the period from when the integration of the clock signal SCB begins to when the count-up signal SU is reset. In this embodiment, the frequency divider 24B generates the second time signal STB so that the period from when the integration of the clock signal SCB begins to when the count-up signal SU is reset is 1/2 of the cycle.

When the frequency divider unit 24B receives the next pulse of the reference signal SR, it resets the signal strength of the count-up signal SU and then resumes the accumulation of the clock signal SCB. In other words, when the frequency divider unit 24B receives the next pulse of the reference signal SR, it forcibly resets the signal strength of the count-up signal SU and resumes the accumulation of the clock signal SCB, even if the current signal strength of the count-up signal SU is below the threshold. This allows the period of the second time signal STB to be adjusted each time the reference signal SR is received.

(Communications Department)
The communication unit 26B is a communication module for transmitting and receiving data to and from the transmitter 10A, and may be, for example, an antenna or a Wi-Fi module. Note that, although the communication unit 26B and the reference signal receiving unit 22B are separate pieces of hardware in the example of this embodiment, the communication unit 26B and the reference signal receiving unit 22B may be integrated into a single piece of hardware.

(Storage part)
The storage unit 28B is a memory that stores the calculation contents and program information of the control unit 30B, and includes, for example, at least one of a RAM, a ROM, and an external storage device such as an HDD. The program for the control unit 30B stored in the storage unit 28B may be stored in a recording medium readable by the receiver 10B.

(Control unit)
The control unit 30B is a calculation device and includes a calculation circuit such as a CPU. The control unit 30B includes a second time information generation unit 32B, a communication control unit 34B, and a delay time calculation unit 36B. The control unit 30B implements the second time information generation unit 32B, the communication control unit 34B, and the delay time calculation unit 36B by reading and executing a program (software) from the storage unit 28B. The control unit 30B may implement these processes using a single CPU, or may include multiple CPUs and execute the processes using the multiple CPUs. At least a portion of the processes performed by the second time information generation unit 32B, the communication control unit 34B, and the delay time calculation unit 36B may be implemented using hardware circuits. The control unit 30B may also include a device control unit that controls devices included in the receiver 10B, such as the transmitter 20B, the reference signal receiver 22B, and the frequency divider 24B.

(Second time information generation unit)
The second time information generation unit 32B generates second time information indicating the time in the receiver 10B based on the clock signal SCB and the reference signal SR. In other words, the second time information indicates the internal time of the receiver 10B. Specifically, the second time information generation unit 32B generates the second time information based on the second time signal STB generated by the frequency divider unit 24B based on the clock signal SCB and the reference signal SR. Because the second time signal STB is a signal generated to have a predetermined period, the second time information generation unit 32B can generate the second time information based on the second time signal STB, i.e., by counting pulses of the second time signal STB, for example. The second time information generation unit 32B sequentially counts the pulses of the second time signal STB to sequentially update the second time information.

(Communication control unit)
The communication control unit 34B receives the packet P including the first time information from the transmitter 10A via the communication unit 26B.

(Delay time calculation unit)
The delay time calculation unit 36B calculates the delay time based on the first time information included in the packet P received from the transmitter 10A and the second time information generated by the second time information generation unit 32B. The delay time calculation unit 36B calculates the difference between the time indicated by the first time information and the time indicated by the second time information as the delay time. The time indicated by the first time information here is the time corresponding to the timing at which the transmitter 10A transmitted the packet P (i.e., for example, the time at which the packet P was transmitted measured by the transmitter 10A), and the time indicated by the second time information is the time corresponding to the timing at which the receiver 10B received the packet P (i.e., for example, the time at which the packet P was received measured by the receiver 10B). Therefore, the delay time can be said to be a delay time due to communication, or the time required to transmit the packet P from the transmitter 10A to the receiver 10B.

The delay time calculation unit 36B may output the calculated delay time. For example, the delay time calculation unit 36B may output the calculated delay time to the memory unit 28B and store it in the memory unit 28B, transmit the calculated delay time to an external device, or output the calculated delay time to a display (not shown). Outputting the calculated delay time in this manner makes it possible to use it for various purposes, such as adjusting the communication environment.

(Processing flow)
The processing flow of the transmitter 10A and receiver 10B described above will now be described. FIG. 5 is a flowchart illustrating the processing flow of the transmitter and receiver according to the first embodiment. As shown in FIG. 5, the transmitter 10A acquires the clock signal SCA output by the transmitting unit 20A and acquires the reference signal SR from the reference signal transmitter R by the reference signal receiving unit 22A (step S10A). The transmitter 10A then divides the clock signal SCA based on the reference signal SR using the frequency dividing unit 24A to generate a first time signal STA (step S12A), and generates first time information based on the first time signal STA using the first time information generating unit 32A (step S14A). The transmitter 10A then transmits a packet P including the first time information to the receiver 10B using the communication control unit 34A (step S16).

Receiver 10B also acquires clock signal SCB output by transmitter 20B, acquires reference signal SR from reference signal transmitter R using reference signal receiver 22B (step S10B), divides clock signal SCB based on reference signal SR using frequency divider 24B to generate second time signal STB (step S12B), and generates second time information based on second time signal STB using second time information generator 32B (step S14B). After generating the second time information and receiving packet P containing the first time information, receiver 10B calculates the delay time based on the first time information and second time information using delay time calculator 36B (step S18).

As described above, in this embodiment, transmitter 10A generates first time information based on the reference signal SR received from reference signal transmitter R, and receiver 10B also generates second time information based on the reference signal SR received from the same device, reference signal transmitter R. Receiver 10B then receives the first time information from transmitter 10A and calculates the delay time by comparing the first time information with the second time information it has generated. That is, in this embodiment, the first time information and the second time information can be synchronized using the reference signal SR obtained from a common device, thereby preventing deviations between the first time information and the second time information due to communication delays and the like. Therefore, this embodiment makes it possible to reduce deviations between the first time information and the second time information and calculate the delay time with high accuracy.

Second Embodiment
Next, a second embodiment will be described. The second embodiment differs from the first embodiment in that an average delay time is calculated from the delay time for each packet P, and the execution start timing of an application is adjusted for each packet P based on the average delay time. In the second embodiment, a description of parts of the configuration common to the first embodiment will be omitted.

(Receiver)
Fig. 6 is a schematic block diagram of a receiver according to the second embodiment. As shown in Fig. 6, a control unit 30Ba of a receiver 10Ba according to the second embodiment includes a second time information generation unit 32B, a communication control unit 34B, a delay time calculation unit 36Ba, and an execution unit 38Ba.

(Sending and receiving packets)
In the second embodiment, the communication control unit 34A of the transmitter 10A transmits a packet P including first time information and application information to the receiver 10Ba. The application information is information for the receiver 10Ba to execute a predetermined process (a predetermined application). For example, if the receiver 10Ba performs image display as the predetermined process, the application information may be image data. However, the process and application information performed by the receiver 10Ba are not limited to this and may be arbitrary.

The transmitter 10A sequentially transmits packets P containing different first time information and application information to the receiver 10Ba. The communication control unit 34B of the receiver 10Ba sequentially receives packets P containing the first time information and application information from the transmitter 10A.

(Calculation of average delay time)
FIG. 7 is a graph showing an example of an average delay time. The delay time calculation unit 36Ba of the receiver 10Ba calculates the delay time for a packet P based on first time information included in the packet P and second time information at the time the packet P is received. The delay time calculation unit 36Ba calculates the delay time for each packet P received at different times. The delay time calculation unit 36Ba calculates the average delay time based on the delay time for each packet P, i.e., based on multiple calculated delay times. The delay time calculation unit 36Ba may calculate the average delay time using any method based on the delay time for each packet P. For example, the delay time calculation unit 36Ba may calculate the arithmetic mean value of the delay times for each packet P as the average delay time, or may calculate the average delay time by adding the standard deviation of each delay time to the arithmetic mean value of the delay times for each packet P. In FIG. 7, line L1 indicates the delay time for each packet P, and line L indicates the average delay time calculated from the delay times for each packet P.

(Processing execution)
The execution unit 38Ba executes a predetermined process based on the application information included in the packet P. That is, for example, the execution unit 38Ba uses image data as the application information to perform image display, which is a predetermined process.

Figure 8 is a graph showing an example of average delay time. The execution unit 38Ba continuously executes a predetermined process by sequentially updating the application information used for the predetermined process using the application information contained in successively received packets P. That is, when the execution unit 38Ba completes processing using the application information contained in one packet P, it switches to processing using the application information contained in the next packet P, thereby continuing the processing. In this case, the execution unit 38Ba executes processing based on the application information contained in each packet P at a timing delayed by the average delay time from the timing at which the packet P was received. That is, the execution unit 38Ba starts processing based on each packet P at a common average delay time from the timing at which the packet P was received. Therefore, by maintaining a constant cycle for the start of processing for each packet P, it is possible to prevent delays in the execution of only some packets P, for example, thereby enabling appropriate processing. Note that line L2 in Figure 8 indicates the delay time for each packet P. As shown in Figure 8, even if the actual delay time of packet P is shorter than the average delay time, the timing to start processing using packet P is postponed until the average delay time has elapsed. As a result, even if the delay time varies for each packet P, the cycle of processing start timing can be made constant by setting the processing start timing using a constant value called the average delay time. Note that, as shown in Figure 8, for packets P with delay times longer than the average delay time, processing using those packets P does not need to be performed.

The execution unit 38Ba may compress the application information included in the packet P based on the delay time of the packet P. In this case, for example, the execution unit 38Ba may compress the application information included in the packet P if the delay time of the packet P is longer than the average delay time. This makes it possible to shorten the time required for processing even for packets P with delay times longer than the average delay time by compressing them, thereby making it possible to appropriately process the packet P. Also, for example, the execution unit 38Ba may increase the compression rate of the application information the longer the delay time of the packet P.

(Processing flow)
The processing flow according to the second embodiment described above will now be described. FIG. 9 is a flowchart illustrating the processing flow according to the second embodiment. As shown in FIG. 9 , the receiver 10Ba calculates a delay time using the delay time calculation unit 36Ba based on the first time information included in the packet P and the second time information at the time the packet P is received (step S20). The delay time calculation unit 36Ba determines whether the amount of data for the calculated delay time is equal to or greater than a predetermined amount (step S22). If the amount of data for the calculated delay time is equal to or greater than a predetermined amount (step S22; Yes), the delay time calculation unit 36Ba calculates an average delay time based on the delay times calculated for each packet P up to that point (step S24). On the other hand, if the amount of data for the calculated delay time is not equal to or greater than a predetermined amount (step S22; No), the process returns to step S20 and continues calculating the delay time for the next packet P. Note that the amount of data for the delay time being equal to or greater than a predetermined amount may refer to the number of delay times calculated for each packet P being equal to or greater than a predetermined number. The period until the average delay time is calculated as described above can be used as an initialization period, and processing (e.g., image display) using the packets P received during the initialization period need not be performed. Also, for example, during the initialization period, processing using a packet may be started every time a packet P is received, without using the average delay time.

Once the average delay time is calculated, the receiver 10Ba sets the timing for starting processing of each subsequently received packet P based on the average delay time. That is, the receiver 10Ba receives the packet P using the communication control unit 34B (step S26), and then delays the timing for starting processing using that packet P using the execution unit 38Ba by the average delay time, and executes processing based on the application information contained in that packet P (step S28).

After that, if processing is to be ended (Step S30; Yes), this processing ends. On the other hand, if processing is not to be ended (Step S30; No) and a predetermined time has not elapsed since the average delay time was calculated (Step S32; No), processing returns to Step S26, the next packet P is received, and processing continues using the calculated average delay time. On the other hand, if a predetermined time has elapsed since the average delay time was calculated (Step S32; Yes), processing returns to Step S20 (i.e., returns to the initialization period) and the average delay time is updated. In other words, in this embodiment, the average delay time is updated every time a predetermined time has elapsed, making it possible to appropriately respond to changes in the communication environment. However, updating the average delay time is not essential.

(effect)
As described above, the communication system 100 according to the present disclosure includes a transmitter 10A and a receiver 10B that receives a packet P from the transmitter 10A. The transmitter 10A includes a transmission unit 20A that outputs a clock signal SCA of a predetermined period, a reference signal reception unit 22A that receives a reference signal SR that serves as a time reference from a reference signal transmitter R, a first time information generation unit 32A that generates first time information that indicates the time at the transmitter 10A based on the clock signal SCA and the reference signal SR, and a communication control unit 34A that transmits a packet P including the first time information to the receiver 10B. The receiver 10B includes a transmitter 20B that outputs a clock signal SCB of a predetermined period, a reference signal receiver 22B that receives a reference signal SR from a reference signal transmitter R, a second time information generator 32B that generates second time information indicating the time at the receiver 10B based on the clock signal SCB and the reference signal SR, a communication controller 34B that receives a packet P from the transmitter 10A, and a delay time calculator 36B that calculates a delay time based on the first time information and the second time information included in the packet P.

According to the communication system 100 disclosed herein, the first time information and the second time information can be synchronized using a reference signal SR obtained from a common device, thereby preventing the first time information and the second time information from becoming out of sync due to factors such as communication delays. Therefore, according to this embodiment, it is possible to reduce the lag between the first time information and the second time information and calculate the delay time with high accuracy.

Transmitter 10A further includes a frequency divider 24A that divides the clock signal SCA based on the reference signal SR on the transmitter 10A side to generate a first time signal STA with a predetermined period, and first time information generation unit 32A generates first time information based on the first time signal STA. Receiver 10B further includes a frequency divider 24B that divides the clock signal SCB based on the reference signal SR on the receiver 10B side to generate a second time signal STB with a predetermined period, and second time information generation unit 32B generates second time information based on the second time signal STB. According to this embodiment, by using the first time signal STA and second time signal STB that have been divided based on the reference signal SR, it is possible to reduce the discrepancy between the first time information and the second time information and calculate the delay time with high accuracy.

The reference signal receiving unit 22A of the transmitter 10A and the reference signal receiving unit 22B of the receiver 10B receive a reference signal SR from a satellite acting as a reference signal transmitter R. By receiving the reference signal SR from the satellite, it is possible to properly synchronize the first time information and the second time information and calculate the delay time with high precision.

The delay time calculation unit 36Ba calculates the delay time for each packet P received at different times, and calculates the average delay time based on each delay time. The receiver 10B also includes an execution unit 38Ba that executes predetermined processing based on application information included in the packet P, and the execution unit 38Ba executes predetermined processing based on the application information at a timing delayed by the average delay time from the timing at which the packet P was received. This makes it possible to maintain a constant cycle for the timing at which processing starts for each packet P, allowing for appropriate execution of processing.

The execution unit 38Ba increases the compression rate of the application information contained in the packet P as the delay time increases, and then executes the specified processing. This allows appropriate processing to be performed even on packets P with long delay times.

The communication method according to the present disclosure uses a transmitter 10A and a receiver 10B that receives a packet P from the transmitter 10A. This communication method includes the steps of causing the transmitter 10A to output a clock signal SCA with a predetermined cycle, causing the transmitter 10A to receive a reference signal SR that serves as a time reference from a reference signal transmitter R, generating first time information indicating the time at the transmitter 10A based on the clock signal SCA and the reference signal SR, transmitting a packet P including the first time information to the receiver 10B, causing the receiver 10B to output a clock signal SCB with a predetermined cycle, causing the receiver 10B to receive the reference signal SR from the reference signal transmitter R, generating second time information indicating the time at the receiver 10B based on the clock signal SCB and the reference signal SR, causing the receiver 10B to receive the packet P from the transmitter 10A, and calculating a delay time based on the first time information and the second time information included in the packet P. This communication method allows delay times to be calculated with high accuracy.

Although the embodiments of the present disclosure have been described above, the embodiments are not limited to the content of these embodiments. Furthermore, the aforementioned components include those that would be easily conceivable to a person skilled in the art, those that are substantially identical, and those that are within the scope of what is known as equivalents. Furthermore, the aforementioned components can be combined as appropriate. Furthermore, various omissions, substitutions, or modifications of the components can be made without departing from the spirit of the aforementioned embodiments.

10A Transmitter 10B Receiver 20A, 20B Transmission section 22A, 22B Reference signal receiving section 24A, 24B Frequency dividing section 32A First time information generating section 32B Second time information generating section 34A, 34B Communication control section 100 Communication system P Packet R Reference signal transmitter SCA, SCB Clock signal SR Reference signal STA First time signal STB Second time signal

Claims (8)

1. A communication system having a transmitter and a receiver for receiving packets from the transmitter,
The transmitter
an oscillator that outputs a clock signal with a predetermined period;
a reference signal receiving unit that receives a reference signal that is a time reference from a reference signal transmitter;
a first time information generating unit that generates first time information indicating a time at the transmitter based on the clock signal and the reference signal;
a communication control unit that transmits a packet including the first time information to the receiver;
Including,
The receiver includes:
an oscillator that outputs a clock signal with a predetermined period;
a reference signal receiving unit that receives the reference signal from the reference signal transmitter;
a second time information generating unit that generates second time information indicating a time in the receiver based on the clock signal and the reference signal;
a communication control unit that receives the packets from the transmitter;
a delay time calculation unit that calculates a delay time based on the first time information and the second time information included in the packet;
Including,
the transmitter further includes a frequency dividing unit that divides the clock signal based on the reference signal on the transmitter side to generate a first time signal with a predetermined period, and the first time information generating unit generates the first time information based on the first time signal;
The receiver further includes a frequency division unit that divides the clock signal based on the reference signal on the receiver side to generate a second time signal with a predetermined period, and the second time information generation unit generates the second time information based on the second time signal,
The frequency divider units of the transmitter and the receiver include:
starting integration of the clock signal at a timing corresponding to a timing of receiving the reference signal, and generating a count-up signal by integrating the clock signal;
When the signal strength of the count-up signal becomes equal to or greater than a threshold value, the signal strength of the count-up signal is reset and integration is resumed;
When the next reference signal is received, the signal strength of the count-up signal is forcibly reset to restart the integration of the clock signal;
generating the first time signal and the second time signal based on the count-up signal;
Communication system. The communication system according to claim 1 , wherein the reference signal receiving unit of the transmitter and the reference signal receiving unit of the receiver receive the reference signal from an artificial satellite serving as the reference signal transmitter. 3. The communication system according to claim 1, wherein the delay time calculation unit calculates the delay time for each of the packets received at different timings, and calculates an average delay time based on the respective delay times. The communication system according to claim 3 , wherein the delay time calculation unit updates the average delay time every time a predetermined threshold time elapses. the receiver further includes an execution unit that executes a predetermined process based on application information included in the packet;
5. The communication system according to claim 3 , wherein the execution unit executes the predetermined process based on the application information at a timing delayed by the average delay time from a timing at which the packet is received. The communication system according to claim 5 , wherein the execution unit executes the predetermined process by increasing the compression rate of the application information included in the packet as the delay time increases. A communication method using a transmitter and a receiver that receives packets from the transmitter, comprising:
causing the transmitter to output a clock signal having a predetermined period;
a step of causing the transmitter to receive a reference signal serving as a time reference from a reference signal transmitter;
generating first time information indicating a time at the transmitter based on the clock signal and the reference signal;
transmitting a packet including the first time information to the receiver;
causing the receiver to output a clock signal having a predetermined period;
causing the receiver to receive the reference signal from the reference signal transmitter;
generating second time information indicating a time at the receiver based on the clock signal and the reference signal;
causing the receiver to receive the packet from the transmitter;
calculating a delay time based on the first time information and the second time information included in the packet;
Including,
In the step of generating the first time information, the clock signal is divided based on the reference signal of the transmitter to generate a first time signal having a predetermined period, and the first time information is generated based on the first time signal;
In the step of generating the second time information, the clock signal is divided based on the reference signal on the receiver side to generate a second time signal having a predetermined period, and the second time information is generated based on the second time signal;
In the step of generating the first time information and the second time information,
starting integration of the clock signal at a timing corresponding to a timing of receiving the reference signal, and generating a count-up signal by integrating the clock signal;
When the signal strength of the count-up signal becomes equal to or greater than a threshold value, the signal strength of the count-up signal is reset and integration is resumed;
When the next reference signal is received, the signal strength of the count-up signal is forcibly reset to restart the integration of the clock signal;
generating the first time signal and the second time signal based on the count-up signal;
Communication method. A program that causes a computer to execute a communication method using a transmitter and a receiver that receives packets from the transmitter,
causing the transmitter to output a clock signal having a predetermined period;
a step of causing the transmitter to receive a reference signal serving as a time reference from a reference signal transmitter;
generating first time information indicating a time at the transmitter based on the clock signal and the reference signal;
transmitting a packet including the first time information to the receiver;
causing the receiver to transmit a clock signal with a predetermined period;
causing the receiver to receive the reference signal from the reference signal transmitter;
generating second time information indicating a time at the receiver based on the clock signal and the reference signal;
causing the receiver to receive the packet from the transmitter;
calculating a delay time based on the first time information and the second time information included in the packet;
The computer executes the following .
In the step of generating the first time information, the clock signal is divided based on the reference signal of the transmitter to generate a first time signal having a predetermined period, and the first time information is generated based on the first time signal;
In the step of generating the second time information, the clock signal is divided based on the reference signal on the receiver side to generate a second time signal having a predetermined period, and the second time information is generated based on the second time signal;
In the step of generating the first time information and the second time information,
starting integration of the clock signal at a timing corresponding to a timing of receiving the reference signal, and generating a count-up signal by integrating the clock signal;
When the signal strength of the count-up signal becomes equal to or greater than a threshold value, the signal strength of the count-up signal is reset and integration is resumed;
When the next reference signal is received, the signal strength of the count-up signal is forcibly reset to restart the integration of the clock signal;
generating the first time signal and the second time signal based on the count-up signal;
program.