JPH04109705A - Variable gain amplifier - Google Patents
Variable gain amplifierInfo
- Publication number
- JPH04109705A JPH04109705A JP22771690A JP22771690A JPH04109705A JP H04109705 A JPH04109705 A JP H04109705A JP 22771690 A JP22771690 A JP 22771690A JP 22771690 A JP22771690 A JP 22771690A JP H04109705 A JPH04109705 A JP H04109705A
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- voltage
- input
- circuit
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- control
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Links
- 230000000295 complement effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 5
- 238000000034 method Methods 0.000 description 2
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Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は可変利得増幅器に関し、特に制御電圧に対して
指数関数的に電圧利得が変化する可変利得増幅回路に関
する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a variable gain amplifier, and particularly to a variable gain amplifier circuit whose voltage gain changes exponentially with respect to a control voltage.
従来の可変利得増幅回路の一例を第2図に、その具体的
回路例を第3図に示す。An example of a conventional variable gain amplifier circuit is shown in FIG. 2, and a specific example of the circuit is shown in FIG.
第2図において、本回路は、電流出力型差動回路A1.
A2と、抵抗R1,:R2と、入力端子dと、出力端子
すと、定電源電圧V + 、 V 2と、制御電圧源■
。と、定電流源■。と、制御回路10とを含み、構成さ
れる。第3図において、トランジスタQ1〜Q15.抵
抗R,、R2,定電流源工。、定電圧源V、、V2.制
御電圧源Vcが示されている。ここで、トランジスタQ
1〜Q、と定電流源工。r I3とは、第2図の電流
出力型差動回路A1を構成し、トランジスタQ、〜Q1
gと定電流源I、とは、第2図の電流出力型差動回路A
2を構成する。また、トランジスタQB、Qy、定電流
源■。、定電圧源v2.制御電圧源voにて制御回路1
0を構成する。但し、トランジスタQよは、トランジス
タQ 4 。In FIG. 2, this circuit includes a current output type differential circuit A1.
A2, resistors R1, :R2, input terminal d, output terminal, constant power supply voltage V + , V 2, and control voltage source ■
. And constant current source■. and a control circuit 10. In FIG. 3, transistors Q1 to Q15. Resistor R,, R2, constant current source. , constant voltage source V, ,V2. A control voltage source Vc is shown. Here, transistor Q
1 to Q, and constant current source engineering. r I3 constitutes the current output type differential circuit A1 in FIG.
g and constant current source I are current output type differential circuit A in Fig. 2.
2. Also, transistors QB, Qy, constant current source ■. , constant voltage source v2. Control circuit 1 with control voltage source vo
Configure 0. However, transistor Q is transistor Q 4 .
Q、のベース電流による誤差を少なくする為、バッファ
として入れである。It is inserted as a buffer to reduce the error caused by the base current of Q.
次に、第2図により従来回路の動作を簡単に説明する。Next, the operation of the conventional circuit will be briefly explained with reference to FIG.
ここで、差動回路A + 、 A 2の入力インピーダ
ンスは充分高いものとする。Here, it is assumed that the input impedance of the differential circuits A + and A 2 is sufficiently high.
今、入力端子dに入力信号V、が印加さhた時、出力端
子すでの出力信号V。は次式で求められる。Now, when the input signal V is applied to the input terminal d, the output signal V at the output terminal. is calculated using the following formula.
まず、差動回路A1の入圧力特性を求めると、次式とな
る。First, the input pressure characteristics of the differential circuit A1 are determined by the following equation.
vo=:v、+i −R+ ””’
・■2ニーgいユ・Vc ・・・
・・・■前記■、■式より、次式が得られる。vo=:v, +i −R+ ””'
・■2 Niggi Yu・Vc...
...■ From the above formulas ■ and ■, the following formula is obtained.
v、=v、/ (1+gm+−R+) +・+
・0次に、差動回路A2の出力電流ioは、次式とな1
。= gイ2”VC
ゆえに、■。=gカ=vc−Rz ・・・・
・・■以上前記■、■式より、従来回路の電圧利得は、
次式として得られる。v, = v, / (1+gm+-R+) +・+
・Next, the output current io of the differential circuit A2 is given by the following formula: 1
. = g I2” VC Therefore, ■. = g Ka = vc-Rz ・・・・
...■ From the above formulas ■ and ■, the voltage gain of the conventional circuit is:
It is obtained as the following equation.
ここで、v、:d点での入力信号電圧、VC:C点での
出力信号電圧、V□tb点での出力信号電圧、i:差動
回路A1の交流出力電流、1゜;差動回路A2の交流出
力電流rgml:差動回路A1の相互コンダクタンスr
g m2 ’差動回路A2の相互コンダクタンス。Here, v,: input signal voltage at point d, VC: output signal voltage at point C, output signal voltage at point V□tb, i: AC output current of differential circuit A1, 1°; differential AC output current rgml of circuit A2: mutual conductance r of differential circuit A1
g m2 'Transconductance of differential circuit A2.
ここで、電圧利得A、の制御を、差動回路At。Here, the voltage gain A is controlled by a differential circuit At.
A + ノ相互コンダクタンスg。zgm2の制御で行
う。A + mutual conductance g. This is done under the control of zgm2.
次に、相互コンダクタンスg。i+gm2の制御につい
て説明する。Next, the mutual conductance g. Control of i+gm2 will be explained.
差動回路A I、 A 2の相互コンダクタンスg m
l +gm2は、次式により求まる。Mutual conductance g m of differential circuit A I, A 2
l +gm2 is determined by the following formula.
ここで、gffi+−R+>1という条件を満たす時、
前記0式及び前記0式より、次式が得られる。Here, when the condition gffi+-R+>1 is satisfied,
From the above equation 0 and the above equation 0, the following equation is obtained.
ここで、相互コンダクタンスgいの制御は、第1図の電
流り、I2で行う。従って、次式が得られる。Here, the mutual conductance g is controlled by the current I2 shown in FIG. Therefore, the following equation is obtained.
また、前記■、■式より、次式となる。Moreover, from the above formulas (1) and (2), the following formula is obtained.
I2 g+12 11 gml 前記■、■式より、次式が得られる。I2 g+12 11 gml From the above equations (1) and (2), the following equation is obtained.
・・・・・・■ gml g+ez =e 恰・ΔV□) ・・・・・・■ gml ここで、Il:トランジスタQ6のコレクタ電流。・・・・・・■ gml g+ez =e ΔV□) ・・・・・・■ gml Here, Il: collector current of transistor Q6.
■2;トランジスタQ、のコレクタ電流、■2;定電圧
源、V+;制御電圧源。■2: Collector current of transistor Q, ■2: Constant voltage source, V+: Control voltage source.
このように、従来の電圧制御型増幅器の場合、使用条件
が常にg。1・R1>1の条件を満たす時のみ、制御電
圧■、に対して電圧利得A7が指数関数的に制御出来る
。In this way, in the case of conventional voltage-controlled amplifiers, the operating condition is always g. Only when the condition 1.R1>1 is satisfied, the voltage gain A7 can be controlled exponentially with respect to the control voltage (2).
前述した従来の可変利得増幅器の場合、単純に増幅器の
電圧利得が相互コンダクタンスの比で決まらず、特に電
圧利得が大きくなった時、即ち〔g、、1・R1〕の値
が小さくなり、Cg=i ・R1+1;gア、・R1〕
という近似が出来なくなった時、誤差成分が支配的とな
り、制御特性が、設定した指数関数特性よりずれるとい
う欠点がある。In the case of the conventional variable gain amplifier mentioned above, the voltage gain of the amplifier is not simply determined by the ratio of mutual conductance, and especially when the voltage gain becomes large, that is, the value of [g, 1・R1] becomes small, and Cg =i ・R1+1; ga, ・R1]
When this approximation is no longer possible, the error component becomes dominant and the control characteristic deviates from the set exponential characteristic.
本発明の目的は、前記欠点が解決され、制御特性が、設
定した指数関数特性に沿うようにした可変利得増幅器を
提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a variable gain amplifier in which the above-mentioned drawbacks are solved and the control characteristics follow a set exponential characteristic.
本発明の構成は、第1.第2の抵抗と、電流出力型の第
1.第2の差動回路と、電圧出力型加算器と、利得制御
手段とを備え、前記第1の抵抗の一端を、前記第1の差
動回路の圧力及び反転入力と、前記第2の差動回路の非
反転入力とに接続し、前記第1の差動回路の非反転入力
と前記第2の差動回路の反転入力とを定電位源に接続し
、前記第2の差動回路の出力に第2の抵抗を接続してな
る並列接続差動増幅器を設け、前記第1及び第2の差動
回路の相互コンタクタンスを相補的に制御するように前
記利得制御手段を設けた可変利得増幅回路において、第
1の入力を入力端子に接続し、かつ出力を前記第1の抵
抗の他端に接続し、かつ第2の入力を前記第1の差動回
路の出力に接続してなる2入力の電圧出力型加算器を設
けたことを特徴とする。The configuration of the present invention is as follows. a second resistor, and a current output type first resistor. a second differential circuit, a voltage output type adder, and a gain control means, one end of the first resistor is connected to the pressure and inverting input of the first differential circuit, and the second difference the non-inverting input of the first differential circuit and the inverting input of the second differential circuit are connected to a constant potential source; A variable gain comprising a parallel-connected differential amplifier having a second resistor connected to its output, and the gain control means configured to complementarily control the mutual contactance of the first and second differential circuits. In an amplifier circuit, a first input is connected to an input terminal, an output is connected to the other end of the first resistor, and a second input is connected to the output of the first differential circuit. It is characterized by the provision of a two-input voltage output type adder.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第1図は本発明の一実施例の可変利得増幅器を示すフロ
ック図である。第1図において、本実施例の可変利得増
幅器は、電流出力型差動回路AI。FIG. 1 is a block diagram showing a variable gain amplifier according to an embodiment of the present invention. In FIG. 1, the variable gain amplifier of this embodiment is a current output type differential circuit AI.
A2と、電圧出力型加算器A3と、抵抗R,,R2と、
入力端子aと、出力端子すと、制御回路10と、定電圧
V、、V2と、可変の制御電圧源■oとを備えている。A2, voltage output type adder A3, resistors R,, R2,
It has an input terminal a, an output terminal S, a control circuit 10, constant voltages V, V2, and a variable control voltage source (2).
第1図において、第2区と同一記号、同一番号の素子は
同一素子を示す。In FIG. 1, elements having the same symbols and numbers as in the second section indicate the same elements.
本実施例において、第2図の従来回路と同様に差動回路
A1.A+、抵抗R+ 、 R2等で構成されるが、入
力回路に加算器A3を付加している点が従来と異なる。In this embodiment, similarly to the conventional circuit shown in FIG. 2, the differential circuit A1. It is composed of A+, resistors R+, R2, etc., but differs from the conventional one in that an adder A3 is added to the input circuit.
この加算器A3の入力インピーダンスは充分高いものと
する。また、相互コンダクタンスの制御は、従来回路と
同様に、制御回路1o、制御電圧源V9.定電圧源V
2 、定電流源工。にて行う。It is assumed that the input impedance of this adder A3 is sufficiently high. Further, mutual conductance is controlled by a control circuit 1o, a control voltage source V9. Constant voltage source V
2. Constant current power supply. It will be held at
次に第1図に示した本実施例の可変利得増幅器の動作を
説明する。但し、電圧利得の制御方法は、従来回路と同
様なので省略する。Next, the operation of the variable gain amplifier of this embodiment shown in FIG. 1 will be explained. However, the method of controlling the voltage gain is the same as that of the conventional circuit, so a description thereof will be omitted.
入力端子aに入力信号電圧v1が印加された時、出力端
子すでの出力信号電圧v0は次式により求められる。When the input signal voltage v1 is applied to the input terminal a, the output signal voltage v0 at the output terminal is determined by the following equation.
まず、0点における電圧は次式により求まる。First, the voltage at the 0 point is determined by the following equation.
vc= (v、+ve)+iR+ ・−・・
@1−−g□1・ve ・・・・・
・0前記0.o式より、次式とたる。vc= (v, +ve)+iR+ ・−・・
@1--g□1・ve・・・・・・
・0 above 0. From the formula o, the following formula is obtained.
V x ” ” l / g ml ’ Rl
’・・・・・0次に差動回路A2の出力電流
は+ 10 ” g m2 V zであるので、次式
となる。V x ” ” l / g ml ' Rl
'... Since the output current of the zero-order differential circuit A2 is +10'' g m2 Vz, the following equation is obtained.
V O: gll、2 ・v c−R2−−@以上前記
0,0式より、本実施例の電圧利得は、次式となる。VO: gll, 2 ·v c-R2--@ From the above equation 0, 0, the voltage gain of this embodiment is expressed as follows.
ここで、従来回路と同様の制御方法より、前記0式・前
記0式より、次式が得られる。Here, the following equation can be obtained from the above equation 0 and the above equation 0 using a control method similar to that of the conventional circuit.
拘
このように、常に制御電圧に対して、電圧利得AVが指
数関数に変化する電圧制御型増幅器を得ることが出来る
。In this way, it is possible to obtain a voltage controlled amplifier in which the voltage gain AV always changes exponentially with respect to the control voltage.
本実施例では、第2の差動回路の出力を負荷抵抗に接続
して電圧をとりだし、第1および第2の差動回路A1.
A2の相互コンダクタンスを制御し、電圧利得を可変し
ている。In this embodiment, the output of the second differential circuit is connected to a load resistor to take out the voltage, and the output of the second differential circuit A1.
The mutual conductance of A2 is controlled and the voltage gain is varied.
以上説明したように、本発明は、入力回路に加算器を有
することにより、制御電圧に対する電圧利得変化が、常
に所要の指数関数で制御出来るという効果がある。As described above, the present invention has the advantage that by including the adder in the input circuit, the change in voltage gain with respect to the control voltage can always be controlled using a required exponential function.
第1図は本発明の一実施例の可変利得増幅器のフロック
図、第2図は従来の可変利得増幅器のブロック図、第3
図は第2図の従来回路の具体的回路図である。
A I、 A 2・・・・・・差動回路、A3・・・・
・・加算器、R1゜R2・・・・・・抵抗、a、d・・
・・・入力端子、b・・・・・・出力端子、Q1〜Q1
5・・・・・・トランジスタ+IO+I!・・・・・・
定電流回路、V、、V2・・・・・・定電圧回路、v。
・・・・・・制御電圧源。
代理人 弁理士 内 原 音Figure 1 is a block diagram of a variable gain amplifier according to an embodiment of the present invention, Figure 2 is a block diagram of a conventional variable gain amplifier, and Figure 3 is a block diagram of a conventional variable gain amplifier.
The figure is a specific circuit diagram of the conventional circuit shown in FIG. A I, A2...Differential circuit, A3...
...Adder, R1゜R2...Resistance, a, d...
...Input terminal, b...Output terminal, Q1~Q1
5...Transistor+IO+I!・・・・・・
Constant current circuit, V,, V2... Constant voltage circuit, v. ...Control voltage source. Agent Patent Attorney Oto Uchihara
Claims (1)
路と、電圧出力型加算器と、利得制御手段とを備え、前
記第1の抵抗の一端を、前記第1の差動回路の出力及び
反転入力と、前記第2の差動回路の非反転入力とに接続
し、前記第1の差動回路の非反転入力と前記第2の差動
回路の反転入力とを定電位源に接続し、前記第2の差動
回路の出力に第2の抵抗を接続してなる並列接続差動増
幅器を設け、前記第1及び第2の差動回路の相互コンダ
クタンスを相補的に制御するように前記利得制御手段を
設けた可変利得増幅回路において、第1の入力を入力端
子に接続し、かつ出力を前記第1の抵抗の他端に接続し
、かつ第2の入力を前記第1の差動回路の出力に接続し
てなる2入力の電圧出力型加算器を設けたことを特徴と
する可変利得増幅器。The device includes first and second resistors, first and second current output type differential circuits, a voltage output type adder, and gain control means, and one end of the first resistor is connected to the first resistor. and an output and an inverting input of the differential circuit, and a non-inverting input of the second differential circuit, and a non-inverting input of the first differential circuit and an inverting input of the second differential circuit. is connected to a constant potential source and a second resistor is connected to the output of the second differential circuit to complement the mutual conductance of the first and second differential circuits. In the variable gain amplifier circuit provided with the gain control means so as to control the gain, the first input is connected to the input terminal, the output is connected to the other end of the first resistor, and the second input A variable gain amplifier comprising a two-input voltage output type adder connected to the output of the first differential circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2227716A JP2538708B2 (en) | 1990-08-29 | 1990-08-29 | Variable gain amplifier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2227716A JP2538708B2 (en) | 1990-08-29 | 1990-08-29 | Variable gain amplifier |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04109705A true JPH04109705A (en) | 1992-04-10 |
| JP2538708B2 JP2538708B2 (en) | 1996-10-02 |
Family
ID=16865235
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2227716A Expired - Fee Related JP2538708B2 (en) | 1990-08-29 | 1990-08-29 | Variable gain amplifier |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2538708B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6867650B2 (en) | 2001-12-10 | 2005-03-15 | Nec Electronics Corporation | Variable gain amplifier circuit |
-
1990
- 1990-08-29 JP JP2227716A patent/JP2538708B2/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6867650B2 (en) | 2001-12-10 | 2005-03-15 | Nec Electronics Corporation | Variable gain amplifier circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2538708B2 (en) | 1996-10-02 |
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