JPH04111531A - Digital control oscillator - Google Patents

Abstract

PURPOSE:To improve the resolution without increasing the operation speed of a counter by providing clock generating means which generate a main clock having a prescribed frequency and a subclock having a specific frequency, upper and lower counters, and comparing means. CONSTITUTION:After an upper counter 15 and a lower counter 16 are reset by arrival of an upper coincidence signal, the main clock having the prescribed frequency is counted; and when the counted value of the lower counter 16 coincides with the value of lover n bits of set data, a lower coincidence signal is outputted from a lower comparing means 18. Then, the m-bit upper counter 15 counts the subclock having (2<n>-1<n>)/2 prescribed frequency, and an upper coincidence signal is outputted when the counted value coincides with m-bit set data. This upper coincidence signal is outputted as an output pulse Po to obtain the output pulse which has a high resolution corresponding to set data. Thus, the high resolution is obtained without increasing the counter operation speed.

Description

DETAILED DESCRIPTION OF THE INVENTION "Field of Industrial Application" The present invention relates to a digitally controlled oscillator to which three circuits such as a digital PLL (phase locked loop) circuit are applied.

"Prior Art" Conventionally, a digital PLL circuit is configured as shown in FIG. In this figure, an input pulse Pi serially supplied from the outside is supplied to a DPC (digital phase comparator) 1. This DPCI is
It is composed of a counter, etc., and detects the phase difference between the input I < pulse Pi supplied from the outside and the output pulse Po supplied from the DCO (digital control oscillation @) 3, which will be described later. The pulse signal is supplied to the loop filter 2. In this loop filter 2,
High frequency components and noise components included in the output pulse signal of the DPCI are removed, and the setting data Ds is created according to the actual phase difference.
is supplied to DCO3. This DC03 outputs a pulse signal of a frequency according to the setting data Ds, and is configured as shown in FIG. 4. That is, the setting data Ds is held by the input register 4, and the held data is supplied to one input terminal A of the comparator 5. The count value of the counter 6 is supplied to the other input terminal B of the comparator 5. This counter 6 is a counter that counts clock pulses φ having a constant frequency. and,
The comparator 5 compares the value of the setting data Ds supplied via the input register 4 with the count value of the counter 6, and when the two match, outputs a match signal EQ from its output terminal Y.
Output.

This coincidence signal EQ is supplied to the reset input terminal R of the counter 6 and is output as an output pulse Pa.

In addition to this, the count value of the up counter 6 is the clock pulse φ
, and is reset each time it becomes the same value as the setting data Ds. As a result, an output pulse PO having a frequency corresponding to the setting data Ds is obtained. The output pulse Po outputted from the CO3 is outputted to the outside and also supplied to the DPCI, as shown in FIG.

And DPCI and DCO3 are normal analog P
LL circuit phase comparator and VCO (voltage controlled oscillator)
As a result, the pulses as a whole operate in accordance with the frequency of the input pulse Pi, and operate in the direction of always keeping the phase difference between the input pulse Pi and the output pulse PO at "0".

"Problem to be Solved by the Invention" By the way, in the digital PLL circuit described above, in order to improve the resolution, the resolution of the DCO 3 itself must be improved. In this case, the DC with the above configuration
In O3, in order to improve its resolution, it is sufficient to increase the frequency of the clock pulse φ, but since there is also a limit to the operating speed of the counter 6, it is difficult to increase the frequency of the clock pulse φ indefinitely. was desired.

The present invention has been made in view of the above-mentioned circumstances, and an object of the present invention is to provide a digitally controlled oscillator that can improve resolution without increasing the operating speed of the counter.

"Means for Solving the Problems" The present invention provides clock generation means for generating a main clock of a predetermined frequency and a sub-clock of a frequency of (2'-1)/2n of the predetermined frequency, and a clock generation means for counting the supplied clock. At the same time, a 1-bit high-order counter that is reset by the arrival of the high-order match signal, and a high-order unit that compares the 1-bit setting data with the count value of the high-order counter and outputs the high-order match signal when the two match. a comparison means and counting the clocks supplied;
An n-bit lower counter that is reset by the arrival of the upper match signal compares the value of the lower n bits of the setting data with the count value of the lower counter, and outputs a lower match signal when the two match. a lower comparing means, and selecting the main clock and supplying it to each of the counters after the arrival of the Moeki upper matching signal;
It is characterized by comprising a switching means for selecting the sub-clock and supplying the selected sub-clock to each of the counters after the arrival of the lower-order match signal.

"Operation" According to the above configuration, after the upper counter and the lower counter are reset by the arrival of the upper match signal, the main clock of a predetermined frequency is counted, and the count value of the lower counter is the value of the lower n bits of the setting data. When it matches, a lower matching signal is output from the lower comparing means, and this time the 1-bit upper counter registers the predetermined frequency (2n-1)/
The subclock with a frequency of 2n is counted, and when the count value matches the setting data, the upper match signal is output, so the frequency of the subclock is fs, the value of the setting data is Dll, and the lower n bits of the setting data If the value of is DL, it becomes the frequency fci of the upper match signal, and therefore, if this higher match signal is output lx, a high-resolution output pulse corresponding to the setting data DI can be obtained.

"Example" Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a diagram showing the configuration of an embodiment of the present invention. In this figure, l is a reference oscillation circuit using a crystal resonator 2, which outputs a reference clock φX having a frequency fx. This reference clock φX is frequency-divided by 1/X by the frequency divider circuit 3 and then supplied to the PLL circuits 4 and 8. PLL
The circuit 4 includes a vCO (voltage controlled oscillator) 5 and a
A frequency divider circuit 6 divides the frequency of the clock signal generated by s into 1/2n, and the phases of the clock signal output from this frequency divider circuit 6 and the clock signal output from the frequency divider circuit 3 are compared, and the phase of the clock signal output from the frequency divider circuit 3 is calculated. It is composed of a phase comparator 7 that outputs a signal according to the phase difference to vCO5, and outputs a clock signal of frequency f+a generated by vCO5 as main clock φl. Here, n is a positive integer.

PLL circuit 8 includes vCO9 and a frequency dividing circuit l that divides the frequency of the clock signal generated by vCO9 by 1/(2n-1).
0, and a phase comparator 11 that compares the phases of the clock signal output from the frequency divider circuit 10 and the clock signal output from the frequency divider circuit 3, and outputs a signal according to the phase difference to the vCO9. The clock signal of frequency fs generated by vCO9 is output as subclock φS. In this case, the frequency f11 of the main clock φ
The relationship between and the frequency rx of the reference clock φX is,
Also, the frequency r8 of the sub clock φS and the reference clock φ
The relationship between X and the frequency Ex is, therefore, the frequency fI of the main clock φ■! 1 and the frequency f of the subclock φS
The relationship with s is as follows. Therefore, with respect to the main clock φm of a predetermined frequency fm output from the PLL circuit 4, a sub-clock φS with a frequency “S” which is (2°−1)/2n times the main clock φm is outputted from the PLL circuit 8.

Either the main clock φm or the subclock φS output from the PLL circuits 4 and 8, respectively, is supplied to the upper counter 15 and the lower counter 16 via an AND gate 23 or 24.

The upper counter 15 counts the main clock φ- or the sub clock φS supplied to its clock input terminal CK, and also counts the one bit that is reset when an upper match signal EQH, which will be described later, arrives at its reset input terminal R. It is a counter. Here, san is a positive integer greater than n. Further, the lower counter 16 counts the main clock φ- or the sub clock φS supplied to its clock input terminal CK, and is reset when an upper match signal EQL, which will be described later, arrives at its reset input terminal R. It is a bit counter.

The count value of the upper counter 15 is supplied to the input terminal of the upper comparator 17. The input terminal A of the upper comparator 17 is supplied with the upper setting data DH of the request bit held in the upper register 19. This upper register 1
9 is all bits of upper setting data Dt+) 1m-+~b
It holds 0.

Then, the upper comparator 17 compares the upper setting data Dll supplied from the upper register 19 and the count value supplied from the upper counter 15, and when the two match, the upper comparator 17 outputs the upper setting data from its output terminal Y. Outputs signal EQH. This upper match signal EQH is supplied to the reset input terminal R of the upper counter 15 and the lower counter 16 and the set input terminal S of the RS flip-flop 21, and is outputted from the output terminal T out as an output pulse Po.

On the other hand, the count value of the lower counter 16 is
It is supplied to input terminal B of 8. The n-bit lower setting data DL held in the lower register 20 is supplied to the input terminal A of the lower comparator 18 . This lower renostar 20 holds lower setting data DL consisting of lower n bits of the m-bit upper setting data DI (ie, bits bn-1 to b). The lower setting data DL supplied from the register 20 and the count value supplied from the lower counter 16 are compared, and if they match, a lower match signal E is generated.
Output QL. This lower match signal EQL is supplied to the reset input terminal R of the RS flip-flop 21, and the Q output of this RS flip-flop 21 is supplied to the input terminal of the AND gate 23, and after being inverted by the inverter 22, the It is supplied to the input end of gate 24.

Next, the operation of the above-mentioned embodiment will be explained with reference to FIG.

First, due to the arrival of the upper match signal EQH shown in FIG. 2(c), the RS flip-flop 2
1 is set and its Q output is at °H° level, the AND gate 23 is open and the AND gate 24 is closed, so that the main clock φ
l is selected and supplied to the upper counter 15 and lower counter 16.

Then, while the upper counter 15 and the lower counter 16 are counting the main clock φm of the frequency If, when the count value of the lower counter 16 matches the lower setting data DL, the lower comparator 18 outputs the main clock φm of the frequency If. (
The lower match signal EQL shown in (d) is output, and the lower match signal EQL shown in (a) of the same figure is output.
The RS flip-flop 21 is reset as shown in FIG. After that, the Q output of the RS flip-flop 21 becomes “L”.
“During the period when the level is
is in a closed state, and the AND gate 24 is in an open state, whereby the subclock φS is selected and supplied to the upper counter 15 and the lower counter 16.

Next, while the upper counter 15 is counting the sub-clock φS of the frequency fs, when the count value matches the upper setting data D)l, that is, the upper counter 15 converts the main clock φm into the lower setting data D). After counting the number of pulses corresponding to DL, the subclock φS is changed from the upper setting data D)l to the lower setting data DL.
When the number of pulses corresponding to the value obtained by subtracting . Set.

Here, the period Tm of the main clock φm is , and the period Ts of the subclock φS is .

Also, during the period when the Q output of the flip-flop 21 is at the "H" level, that is, the upper counter 15 and the lower counter 16 count the main clock φm until their count values match the lower setting data DL. The period is DL-T■, and after the period when the Q output of the flip-flop 2I is at "L" level, that is, after the count value of the upper counter 16 matches the lower setting data DL, the upper counter 16 is the subclock φ
S, and the count value is the upper setting data DH.
The period until it matches is (DH-DC)・Ts, so the period T0 of the upper match signal EQH is To=Dt
, -Tm+(DHDL) ・Ts =...(7)
It is. Therefore, the frequency f0 of the upper match signal EQH
is f. = 1 DL, To++CDI-DL), Ts """ (8
), and in this equation (8), the above (4), (5), (6
), it becomes DH-DL/2・---(9). Then, this upper match signal EQH of frequency r0 is output as an output pulse Po.

In this way, according to the embodiment described above, it is possible to obtain a high-resolution output pulse PO with a frequency determined by the upper setting data DB of m bits and the lower setting data DL consisting of its lower n bits. In this case, since the frequency rs of the sub clock φS is smaller than the frequency rm of the main clock φm, each counter 15 and 16
There is no need to increase the operating speed.

"Effects of the Invention" As explained above, according to the present invention, after the upper counter and the lower counter are reset by the arrival of the upper match signal, the main clock of a predetermined frequency is counted, and the count value of the lower counter is When the value matches the value of the lower n bits of the setting data, the lower comparing means outputs a lower matching signal, and the upper counter of the garden bit then outputs a subclock with a frequency of (2n-1)/2n of the predetermined frequency. The upper match signal is output when the count value matches the 1-bit setting data, so by using this upper match signal as the output pulse,
High-resolution output pulses can be obtained according to the setting data, and this provides the effect that high resolution can be achieved without increasing the operating speed of the counter.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a digitally controlled oscillator according to an embodiment of the present invention, FIG. 2 is a waveform diagram of each part to explain the operation of the embodiment, and FIG. 3 is a digital PL
FIG. 4 is a block diagram showing the structure of the L circuit. FIG. 4 is a block diagram showing the structure of a conventional digitally controlled oscillator. , 8... PLL circuit (clock generation means), 5
...Upper counter, 6...Lower counter, 7...Upper comparator (upper comparison means), 8...
...lower comparator (lower comparison means), l...R
S flip-flop, 2...inverter, 3.24...AND gate (21 to 24 are switching means).

Claims (1)

[Claims] A main clock with a predetermined frequency and a main clock with a predetermined frequency (
a clock generating means that generates a sub-clock with a frequency of 2^n-1)/2^n; an m-bit upper counter that counts the supplied clock and is reset by the arrival of a higher-order match signal; an upper comparing means that compares the setting data of the upper counter with the count value of the upper counter and outputs the upper match signal when the two match; a low-order counter of n bits, which compares the value of the low-order n bits of the setting data with the count value of the low-order counter, and outputs a low-order match signal when the two match; switching means that selects the main clock and supplies it to each of the counters after the arrival of the signal, and selects the subclock and supplies it to each of the counters after the arrival of the lower match signal; A digitally controlled oscillator comprising: .