JPH04112550A - Testing method for semiconductor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor testing method, and more particularly to a semiconductor testing method that allows high-temperature accelerated testing (hereinafter referred to as burn-in) to be performed at low cost in a wafer state. be.

[Conventional technology]

Conventionally, as a method of performing burn-in in a wafer state, a method has been proposed in which a needle is brought into contact with a pad (electrode) portion on a wafer, but it requires a large amount of cost to realize it.

For this reason, many methods have been implemented in which pads for external connection are formed on the periphery of the wafer, pads within the chip are connected in parallel to the pads, and a needle is brought into contact with only the external connection pads.

Hereinafter, a conventional example will be explained with reference to the drawings.

Fig. 5 is a top perspective view when the needle is brought into contact with the pad portion on the wafer, and Fig. 6 shows the connection wiring of the pad on the wafer in parallel to the pad formed on the periphery of the wafer. FIG. 6 is a top perspective view when the needles are brought into contact.

In the figure, 1 is a wafer, 4 is a pad on the wafer, 5 is a signal supply power source, and 7 is a needle that is brought into contact with the pad 4.

Next, the operation will be explained.

First, the needle 7 is brought into contact with the pad 4 on the wafer 1, and each chip on the wafer 1 is actuated by applying a signal from the signal supply source 5. Leave it for a certain period of time.

After the burn-in is completed, the needle 7 is brought into contact with the pad 4 on the wafer 1 and a signal is applied from the signal source 5 in order to check the reaction of the chip.

FIG. 5 shows how the needles 7 are brought into contact with all the pads 4 on the wafer 1 to supply signals;
The figure shows that parallel connection wiring is provided on the wafer 1, and signals are supplied to each chip simply by contacting 41 external connection pads with the needle 7.

[Problem to be solved by the invention]

The conventional semiconductor testing method that performs burn-in in the wafer state is configured as described above, so the method of performing burn-in by contacting the pad part on the wafer requires a large amount of cost, and also requires There was a problem in that it was difficult to obtain uniform stylus pressure (contact pressure) on the pad.

In addition, when performing burn-in by making parallel connection wiring on a wafer and touching a single pad with a needle, additional space is required for the wiring, which reduces the number of chips per wafer and further reduces the number of chips on the wafer. There were also problems such as disconnection of parallel connection wiring.

This invention was made in order to solve the above-mentioned problems, and provides a semiconductor testing method that can perform burn-in in a wafer state at low cost and in which uniform contact pressure can be obtained on the pads on the wafer. The purpose is to provide

[Means to solve the problem]

In the semiconductor testing method according to the present invention, a wafer on which elements are formed is held in a closed container, a film having a wiring pattern is held above the wafer in parallel, and the film is pressurized with high-pressure gas. The wiring pattern is electrically connected to the electrodes on the wafer.

[Effect]

In the semiconductor testing method of the present invention, the wiring pattern of the film is connected to the electrode on the wafer with equal contact pressure by applying pressure with high-pressure gas, thereby performing burn-in in the wafer state.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a cross-sectional side view of an apparatus for a semiconductor testing method according to an embodiment of the present invention, and FIG. 4 shows the relationship between a wafer and a film provided with a wiring pattern according to an embodiment of the present invention. FIG. 3 shows a top perspective view.

In these figures, I is a wafer, 2 is a film with a wiring pattern superimposed on the pad (electrode) on the wafer L, 3 is a gas supply hole for supplying high-pressure gas to pressurize the film 2, 5 is a signal supply source, 8 is a sealed container for keeping the wafer 1 and film 2 at high temperature and high pressure, and 9 is an O-ring for preventing high pressure gas in the sealed container 8 from leaking outside.

Next, the operation will be explained.

In the semiconductor testing apparatus configured as described above, first, high pressure gas is supplied through the hole 3 on the closed container 8, and pressure is applied so that the film 2 on which the wiring pattern is applied comes into contact with the wafer 1. By contacting the film 2 and the wafer l,
As shown in FIG. 4, the wiring pattern of the film 2 and the pads on the wafer 1 are connected, and a signal from the signal supply source 5 is applied to the pads on the wafer l, so that each chip on the wafer l is activated.

Next, the sealed container 8 is left in a high-temperature oven (not shown) for a certain period of time while the chip remains in operation.

After the burn-in is completed, a signal is applied again from the signal supply source 5 and the reaction of the chip is examined.

In this example, as described above, a wiring pattern was formed on a film provided on a wafer, and the pad on the wafer and the wiring pattern on the film were connected by pressurizing the film with high-pressure gas. In addition to being able to obtain uniform contact pressure, burn-in can be performed in a wafer state at a relatively low cost without using a needle.

In addition, there is no need to separately provide a parallel connection wiring section for burn-in or a pad section for external connection on the wafer, so there is no need to reduce the number of chips per wafer, and there is no risk of disconnection of parallel connection wiring on the wafer. Not at all.

The above embodiments have been explained.
The figure shows an example in which bumps are provided on the pad portion of the wafer 1 or on the wiring portion of the film 2 that overlaps with the pad of the wafer 1. By providing a bump electrode instead of a pad electrode in this way, compared to the above embodiment,
A more stable and reliable contact pressure can be obtained. In this case, the bumps preferably have a thickness of 2 μm or more, since the thickness of the glass coat covering the semiconductor elements formed on the wafer 1 is about 1 to 2 μm.

The conditions set during burn-in may vary depending on the durability and performance required of the semiconductor chip being tested.
1 Okg/cnf, tip operating time = 4-40 hours. Further, as the high pressure gas, an inert gas such as nitrogen (N) or argon (Ar) is used so as not to oxidize the wiring patterns on the wafer 1 and the film 2.

〔Effect of the invention〕

As described above, according to the present invention, a burn-in test is performed by forming a wiring pattern on a film and bringing the wiring pattern into contact with an electrode on a wafer using high-pressure gas, so that uniform contact pressure can be obtained. In addition, it has the effect of enabling inexpensive burn-in in a wafer state.

Furthermore, since there is no need to separately provide space for wiring and pad portions on the wafer, there are also effects such as a reduction in the number of chips per wafer and no disconnection of wiring on the wafer.

[Brief explanation of drawings]

FIG. 1 is a sectional side view showing an apparatus used in a semiconductor testing method according to an embodiment of the present invention, and FIG. 2 is a sectional side view showing a semiconductor testing apparatus used in a semiconductor testing method according to another embodiment of the invention. FIG. 3 is a cross-sectional side view showing a semiconductor testing device used in a semiconductor testing method according to yet another embodiment of the present invention, and FIG. 4 shows a wafer and a film with a wiring pattern applied thereto according to a semiconductor testing method according to an embodiment of the present invention. FIG. 5 is a top perspective view showing the correlation between the two, FIG. 5 is a top perspective view of a conventional example in which the needles are brought into contact with all pads of a wafer, and FIG. 6 is still another conventional example. FIG. 3 is a top perspective view when parallel connection wiring is provided on a wafer. In the figure, 1 is a wafer, 2 is a film with a wiring pattern, 3 is a hole for supplying high-pressure gas and applying pressure to the film 2, 4 is a pad, 4a and 4b are bumps formed on the wafer l and the film 2, 5 is a signal supply source, 6 is wiring, 7
8 is the needle that contacts the pad 4, the wafer 1 and the film 2
9 is an O-ring to prevent the high pressure gas inside the sealed container 8 from leaking outside. In the drawings, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] (1) A semiconductor testing method in which a high-temperature accelerated test is performed in a wafer state, which includes: holding a film having a wiring pattern in a closed container; holding a wafer on which elements are formed below the film in parallel; and the film. A step of introducing high pressure gas into the sealed container from above and pressurizing the film brings the wiring pattern on the film into contact with the electrode on the wafer and electrically connects them. A semiconductor testing method characterized by: