JPH04137653A - Designing method for semiconductor integrated circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Objective of the Invention (Industrial Application Field) The present invention relates to a method for designing a semiconductor integrated circuit, and particularly to an automatic designing method using a stander cell method.

(Prior Art) In recent years, in addition to mass-produced integrated circuits such as general-purpose products, there has been an increasing demand for semi-custom integrated circuits designed in response to user requests, so-called ASICs.

Standard cell method and gate array method are ASIC
This is a typical method used in the design and manufacturing of However, the standard cell method has advantages over the gate array method, such as a higher cell usage rate and no unused wiring tracks.

FIG. 4 shows a flowchart relating to a method for automatically designing a semiconductor integrated circuit using the standard cell method.

First, a logic design is performed (step S1), then a virtual external load capacity is estimated from the fan-in and fan-out numbers and virtual wiring capacity (step S2), and a logic simulation with delay is performed using this virtual wiring capacity (step S
3) Verify the design for logic errors, timing errors, etc.

(Step S4).

If an error is detected, examine the defective location in step 5IO.
), jump to logic design (step Sl) and repeat the above steps (Sl-S4.510) until there are no errors.

If no error is detected in the logic simulation with delay using virtual wiring capacitance (step S3), the process jumps to step S5, and layout design is performed using automatic placement and wiring. Next, read the actual wiring load capacitance of each signal line from the layout result (step S6), perform a logic simulation with delay using this actual wiring capacitance (step S7), and verify whether there are any logic errors, timing errors, etc. Step S8).

If there is no error, the process jumps to step S9 and the layout design ends. If there is an error, examine the defective location (Step 512), jump to logic design (Step Sl), and repeat the above-mentioned step (Sl-512) until there is no error.

Logic simulation with delay is performed by taking into account the delay time due to wiring capacitance, but since the value of wiring capacitance cannot be determined until the actual layout is done, when designing the system for the first time, it is necessary to calculate the temporary wiring capacitance as described above. It is done using In this case, there is no problem if the actual wiring capacitance and the virtual wiring capacitance match after the layout is designed by automatic placement and wiring (step S5), but large-scale discrepancies often occur in large-scale ASICs. Therefore, if the desired circuit behavior is not achieved through simulation, it is necessary to go back to the initial logic design and redo the design (Sl-512
). As a result, the period from logical design to the end of layout design, that is, the design TA T (Turn And T
There was a problem that il1e) became long.

Redoing the logic design due to a mismatch between the virtual wiring capacitance and the actual wiring capacitance is particularly likely to occur when designing a GaAs integrated circuit. The load driving capacity of a GaAs integrated circuit is S
This is because since it is smaller than that of an i-integrated circuit, the signal delay increases at a rate that depends on the wiring capacitance, that is, the wiring length. In other words, even with the same wiring length, GaAs integrated circuits are better than Si.
This is because the delay time of signals is longer than that of integrated circuits, and the timing deviation of signals becomes large, increasing the probability that the circuit will not operate normally. Furthermore, among the standard cell systems, those with a hierarchical layout tend to have longer wire lengths between logic blocks, which may lead to misestimation of virtual wire capacitance or timing errors.

(Invention or Solving Lesson 8) Up until now, integrated circuit designs using the standard cell method have not had a very high degree of integration, so the virtual wiring capacitance and the actual wiring capacitance have not differed greatly. Therefore, the signal delay did not have a large effect on the electrical characteristics of the circuit. However, recently, the integration of large-scale systems has increased, and often a large discrepancy occurs between the actual wiring capacitance and the virtual wiring capacitance. the result,
When an error is detected during design verification, it becomes necessary to go back to the logical design and reconsider the design, which poses a problem in that design and development take a lot of time.

The present invention has been made in consideration of the above circumstances, and its purpose is to design a semiconductor integrated circuit with higher integration, higher speed, and lower power consumption while shortening the period from logic design to completion of layout design. The purpose is to provide a method.

[Structure of the Invention (Means for Solving the Problems)] In order to achieve the above object, the present invention provides a method for designing a semiconductor integrated circuit using standard cells, which includes a step of designing a logic, and a step of designing the logic. a step of later placing and routing; a step of determining the delay time of each signal line from the result of the placement and routing, and redoing the logic design or automatic placement and routing so as to keep the delay time of each signal line within a predetermined time; A semiconductor integrated circuit is designed in a step including the step of verifying the design by logic simulation with delay using actual wiring capacitance after determining the layout and wiring that the delay time of each signal line is within a predetermined time. (Function) According to the present invention, the logical design or placement and wiring of all signal lines is corrected until the delay time falls within a predetermined range, so when the difference between the actual wiring capacitance and the virtual wiring capacitance is large, However, it becomes easier to pass design verification using delayed logic simulation using actual wiring capacitance. As a result, when an error is detected at the design verification stage, the time-consuming step of returning to the logic design, examining the defective location, and replacing the cell there is less likely to occur, thereby reducing the design TAT. . Additionally, if a delay time or a signal line that is not within a predetermined range is detected, the design can be easily modified by replacing the cell that has this signal line in its output stage with a cell that has the same function as this cell but has a different driving capacity. can. Also,
Since it is possible to select a cell with the optimum driving capacity for the external load capacity, it is possible to realize a highly integrated circuit with high speed and low power consumption.

(Example) Examples will be described below with reference to the drawings.

FIG. 1 shows a flowchart relating to a method for automatically designing a semiconductor logic integrated circuit according to an embodiment of the present invention.

First, logic design (step S1) is performed, and design verification is performed by logic simulation with delay using virtual wiring capacitance (steps S3 and S4).

Step S2. until no errors are detected. S3゜S4
．． S10. Repeat Sl. If there is no problem in this design verification, the process jumps to step S23 and layout design is performed using automatic placement and wiring. Then, read the external load capacity of each signal line from the result of this layout design (step 5).
24). Here, the capacitance of the external load is determined as the sum of the wiring capacitance used for connection with the next stage cell and the fan-out capacitance.

Next, the delay time due to the external load capacitance of each signal line is expressed by formula (1).
(step 525).

(Delay time due to external load capacity) −α (external load capacity)/(cell drive current)
is a proportionality constant.

Next, it is determined whether the delay time due to the capacity of the external load is within a set range for all signal lines (step 526).

If there is a signal line whose delay time is not within the set range, select a cell for that signal line from the cell library that has the same function as the cell for that signal line but has a different output stage drive current. , and the signal delay is kept within the set range (step S27°528). When selecting a cell, for example, when the relationship between external load capacity and drive current is expressed by straight line ab shown in Fig. 2, the slopes tanθa and tanθb of straight lines a and b respectively mean delay time Therefore, depending on the external load capacitance or C0, the delay time setting or tanθa
˜tanθb, it is sufficient to select a cell whose drive current is Ia−1b from the cell library.

When replacing a cell with a different drive current, the cell size and transistor size will change, so the wiring capacitance will change.

Fan-out capacity also changes. Therefore, in order to optimize the layout design, it is necessary to determine whether the fan-out capacity of each cell exceeds a set value (step 52).
2) The circuit is modified (step 521) so that the delay time due to the external load capacity of each cell falls within the set range, and steps 521 to 528 are repeated.

If the delay time is within the set range, step S
Proceeding to step 29, design verification is performed by logic simulation with delay using actual wiring capacitance.

If no error is detected, the layout design ends (step 532), or if an error is detected, the process jumps to step S30 to change the setting range of the delay time based on the external load capacity, or the process goes to step S31 to adjust the fan-out capacity. Change the setting value and check the fan-out capacity again (
After that, automatic placement and wiring layout (523) is performed, and steps S21 to S31 are repeated until the desired result is obtained, and the layout design is completed (step 532).

The inventors of the present invention designed a GaAs logic integrated circuit with a gate using a conventional method and the method of this embodiment for comparison. As a result, it took about four months to design using the conventional method. In contrast, with the method of this embodiment, the design period could be shortened to about two months. Further, when comparing the power consumption, it was found that the GaAs logic integrated circuit designed by the method of this embodiment has lower power consumption. This is because the cell selected by the method of this embodiment has a more optimal drive current for the external load capacitance. This makes it possible to efficiently optimize power consumption. Since cells with an optimal drive current are used, the cell size is also optimized, resulting in a GaAs logic integrated circuit with high integration density.

Thus, by applying the present invention to the design of GaAs logic integrated circuits, design TAT and layout area can be reduced.

Power consumption can be improved.

FIG. 3 shows a schematic chip diagram of a GaAs logic integrated circuit designed by the hierarchical layout design method to which the present invention is applied.

The layout has a relatively large number of cells with large drive current and cell size in the periphery of the logic block 41, and a relatively large number of cells with small drive current and cell size in the center. The length of the signal wiring 42 connecting the blocks 41 can be shortened. As a result, an increase in load capacitance between the logic blocks 41 can be suppressed, so a large timing margin can be achieved. Furthermore, the wiring length of the signal wiring 44 connecting the terminal bat 43 and the logic block 41 is also shortened. As described above, by applying the present invention to the hierarchical layout design method, an optimized placement and wiring layout can be obtained.

In this embodiment, GaAsLSI has been described, but other 5iLSIs can be designed in exactly the same manner.

C. Effects of the Invention] As described above, according to the present invention, design verification is performed by logic simulation with delay using actual wiring capacitance after all the delay times of each signal line are within a predetermined range, which is time-consuming. Design TAT is reduced as the rate of design revisions is lower.
can be significantly shortened. Further, according to the present invention, when a signal line whose delay time does not fall within a predetermined range is detected, the cell at the defective location is replaced with a cell having the optimum driving ability, so that design correction can be easily performed.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a flowchart regarding an automatic design method for a semiconductor integrated circuit according to an embodiment of the present invention, FIG. 2 is a diagram showing the relationship between external load capacity and drive current, and FIG. 3 is a diagram showing the relationship between external load capacity and drive current. FIG. 4 is a schematic diagram of a chip of a GaAs logic integrated circuit designed by the applied hierarchical layout design method. FIG. 4 is a flowchart of a conventional automatic design method. S21...Logic correction, S22...Judgment of fan-out capacity, 323...Automatic wiring layout, S24...
Automatic reading of external load capacity, S25... Calculation of delay time, S26... Judgment of pass/fail of delay time of each signal line, S2
7...Cell selection, S28...Cell replacement, S
29...Logic simulation, S30...Delay time setting, 531...Fan-out capacity setting, S32
...Layout design completed, 41...Logic block,
42.44...Signal wiring, 43...Ponding pad. Applicant's agent Patent attorney Takehiko Suzue

Claims (2)

[Claims] (1) In a method for designing a semiconductor integrated circuit using standard cells, there are a step of performing logic design, a step of placing and routing after the logic design, and determining the delay time of each signal line from the result of the placement and routing. A step of correcting the logic design or placement and wiring so that all the delay times of the signal lines are within a predetermined time, and after determining the placement and wiring that the delay times of each signal line are all within a predetermined time, an implementation step is performed. 1. A method for designing a semiconductor integrated circuit, comprising: performing design verification by logic simulation with delay using wiring capacitance. (2) If a signal line is found from the result of the placement and wiring that the delay time of each signal line does not fall within the predetermined time, a cell that has the signal line in the output stage has the same function as this cell and has the same driving capacity. 2. The method of designing a semiconductor integrated circuit according to claim 1, further comprising replacing cells with cells having different signal lines, and modifying logic design or layout and wiring so that delay times of each signal line are all within a predetermined time.