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JPH04137941A - Atm traffic line concentrator system - Google Patents

Atm traffic line concentrator system

Info

Publication number
JPH04137941A
JPH04137941A JP2261328A JP26132890A JPH04137941A JP H04137941 A JPH04137941 A JP H04137941A JP 2261328 A JP2261328 A JP 2261328A JP 26132890 A JP26132890 A JP 26132890A JP H04137941 A JPH04137941 A JP H04137941A
Authority
JP
Japan
Prior art keywords
input
line
atm
time
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2261328A
Other languages
Japanese (ja)
Inventor
Isao Okazaki
岡崎 勲
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP2261328A priority Critical patent/JPH04137941A/en
Publication of JPH04137941A publication Critical patent/JPH04137941A/en
Pending legal-status Critical Current

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  • Time-Division Multiplex Systems (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)

Abstract

PURPOSE:To flexibly decide a line concentration ratio by assigning a time slot to each input line and applying time division multiplex to a data. CONSTITUTION:Input lines 001-003 are accommodated respectively in input cell buffers 111-113. A time division multiplex circuit 201 gives an output to an output line 101 at a transmission speed of nearly 150Mbit/s the same speed as that for each input line. A frame memory 301 is a memory having n-sets of time slots for one frame and controls a time division multiplex circuit 201. The assignment of a time slot for each of the input cell buffers 111-113 is implemented for each call or semi-fixedly by taking the traffic characteristic of each of the input lines 001-003 into account.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はATMトラヒック集線方式に関し、特にATM
 (非同期転送モード)セルを運ぶ低トラヒツク能率の
回線を多数収容して高能率回線へ集線する集線方式に関
する。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an ATM traffic concentration system, and in particular to an ATM traffic concentration system.
(Asynchronous transfer mode) This relates to a line concentration method that accommodates a large number of lines with low traffic efficiency that carry cells and concentrates them into a high efficiency line.

〔従来の技術〕[Conventional technology]

従来、広帯域I SDNの究極解と言われ、固定長短パ
ケットのセル単位で統計多重・交換を行うATM方式の
トラヒック集線を行うには、単位ATMスイッチを複数
段縦列接続して絞っていく方法と、低能率トラヒック回
線の物理転送速度を下げておいて、時分割多重を行った
後にATMセル化する方法とがある。
Conventionally, traffic concentration using the ATM method, which is said to be the ultimate solution to wideband ISDN and statistically multiplexes and exchanges fixed-length and short packets on a cell-by-cell basis, has been achieved by connecting multiple ATM switches in series and concentrating the traffic. Another method is to reduce the physical transfer rate of a low-efficiency traffic line, perform time division multiplexing, and then convert the data into ATM cells.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

ATM方式では物理転送速度が約150Mbit / 
sという高速ラインを単位としているので、メイントラ
ヒックと考えられる音声トラヒックは、64kbit/
sなので、約1/2,000の集線を効率的に行う必要
がある。又、広帯域トラヒックへの柔軟な対応からその
集線比率を可変にする必要がある。
In the ATM method, the physical transfer speed is approximately 150Mbit/
Since the unit is a high-speed line called s, the voice traffic that can be considered as the main traffic is 64 kbit/
s, it is necessary to efficiently concentrate the lines by about 1/2,000. Furthermore, it is necessary to make the line concentration ratio variable in order to flexibly handle broadband traffic.

上述した従来の方法のうち、ATMスイッチを用いる方
法で1/2,000から数分の一程度まで集線比を可変
にしようとすれば、結局、2.0OOX2,000のA
TMスイッチにせざるを得す、集線による経済的効果は
得られない。
Among the conventional methods mentioned above, if you try to vary the concentration ratio from 1/2,000 to a fraction of a fraction by using an ATM switch, you will end up with an A of 2.0OOX2,000.
There is no choice but to use a TM switch, and the economic effect of concentrating the lines cannot be obtained.

又、低速時分割多重後のATMセル化方決方法、加入者
アクセス・ラインではATMの持つ帯域フリーというメ
リットが得られない。
Furthermore, the ATM cell formation method and subscriber access line after low-speed time division multiplexing do not provide the advantage of free bandwidth that ATM has.

〔課題を解決するための手段〕[Means to solve the problem]

本発明のATMトラヒック集線方式は、ATMセルを運
ぶ入力回線n本を1本の出力回線へ集線するATMトラ
ヒック集線方式において、前記各入力回線ごとのATM
セルを一時格納する入力セルバッファと、前記出力回線
の1フレームn個に時分割されたタイム・スロットの番
号と前記各入力回線の番号との対応を記憶するフレーム
・メモリとを備え、前記フレーム・メモリのタイム・ス
ロット番号と入力回線番号との対応を呼ごと又は半固定
的に設定し、前記タイム・スロットごとに前記フレーム
・メモリを参照し前記入力セルバッファから対応する入
力回線のATMセルを読み出し前記出力回線に出力する
構成である。
The ATM traffic concentration method of the present invention is an ATM traffic concentration method in which n input lines carrying ATM cells are concentrated into one output line.
an input cell buffer for temporarily storing cells; and a frame memory for storing a correspondence between the number of time slots of one frame of the output line, which are time-divided into n pieces, and the number of each of the input lines; - The correspondence between the time slot number of the memory and the input line number is set for each call or semi-fixedly, and the frame memory is referred to for each time slot and the ATM cell of the corresponding input line is retrieved from the input cell buffer. The configuration is such that the data is read out and output to the output line.

また、上記構成において、空セル生成回路を備え、対応
する入力回線が割当てられなかったタイムスロットに対
して空セルを出力する構成とすることもできる。
Further, in the above configuration, an empty cell generation circuit may be provided, and an empty cell may be output to a time slot to which a corresponding input line is not assigned.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図は本発明の一実施例を示すブロック図である。各
入力回線001〜003は、約150Mb i t /
 sの伝送速度でATMセルを運び、入力セルバッファ
111〜113のそれぞれに収容されている。入力セル
バッファ111〜113のバッファ数は1セル分でも良
く、確保したタイム・スロットで運べるトラピック特性
と実際に入力されるトラヒック特性との差を埋めるため
にバッファ容量を増やしても良い0時分割多重回路20
1は、入力セルバッファ111〜113のセルを時分割
多重し、各入力回線と同じ約150Mbit/Sの伝送
速度で出力回線101に出力する。空セル生成回路21
1は、出力すべきセルがないタイム・スロット時に空セ
ルを挿入する。フレーム・メモリ301は、1フレーム
、n個のタイム・スロットを持つメモリで、時分割多重
回路201を制御する。
FIG. 1 is a block diagram showing one embodiment of the present invention. Each input line 001 to 003 has a capacity of approximately 150 Mbit/
ATM cells are carried at a transmission rate of 100 s, and are accommodated in each of input cell buffers 111 to 113. The number of input cell buffers 111 to 113 may be one cell, or the buffer capacity may be increased to fill the difference between the traffic characteristics that can be carried in the secured time slot and the traffic characteristics that are actually input. multiplex circuit 20
1 time-division multiplexes the cells in the input cell buffers 111 to 113 and outputs them to the output line 101 at the same transmission speed of about 150 Mbit/S as each input line. Empty cell generation circuit 21
1 inserts empty cells during time slots when there are no cells to output. The frame memory 301 is a memory having one frame and n time slots, and controls the time division multiplexing circuit 201.

各入力セルバッファ111〜13中のセルは、規定のタ
イム・スロット時にのみ、出力回線101へ読出される
。各人力セルバッファ111〜113ごとのタイム・ス
ロットの割当ては、各入力回線001〜003のトラヒ
ック特性を考慮して呼ごとに、あるいは半固定的に行う
、呼ごとの場合は、各入力回線001〜003から信号
セルでドロップして信号処理を行う回路が必要となる。
Cells in each input cell buffer 111-13 are read out to output line 101 only during specified time slots. Time slot allocation for each human cell buffer 111 to 113 is done for each call or semi-fixedly, taking into account the traffic characteristics of each input line 001 to 003. From ~003 onwards, a circuit that performs signal processing by dropping signal cells is required.

半固定の場合は、オフラインで操作コンソールから書き
込む、1つの入力ボートに複数のタイム・スロットを割
当てても良い、更にその間隔も等間隔でも変動間隔でも
良い。
In the case of semi-fixed time slots, multiple time slots may be assigned to one input port that is written offline from the operation console, and the intervals may be equal or variable.

第2図は、第1図のフレームメモリ301の構成を示す
、0〜nのアドレスを持ち、タイム・スロット周期と同
期して常に巡回している。1タイム・スロット区間には
唯ひとつの入力セルバッファのみゲートを開く。
FIG. 2 shows the structure of the frame memory 301 in FIG. 1, which has addresses 0 to n and always cycles in synchronization with the time slot period. Only one input cell buffer gate is opened during one time slot period.

第3図は、各入力セルバッファ111〜113中のセル
が時分割多重される概念を示す。入力回線001にはタ
イム・スロット1が、入力回線002にはタイム・スロ
ット0と3とが割当てられている。出力回線101上に
多重されたセルが出力される。Uで示されたセルは空セ
ルである。
FIG. 3 shows the concept that cells in each input cell buffer 111-113 are time-division multiplexed. Input line 001 is assigned time slot 1, and input line 002 is assigned time slots 0 and 3. Multiplexed cells are output onto the output line 101. Cells indicated by U are empty cells.

〔発明の効果〕 以上説明したように本発明は、各入力回線にタイム・ス
ロットを割当てて、時分割多重することにより、集線比
率を柔軟に決められる経済的なATMトラピック集線装
置を作ることができる。
[Effects of the Invention] As explained above, the present invention makes it possible to create an economical ATM traffic concentrator that can flexibly determine the concentration ratio by allocating time slots to each input line and performing time division multiplexing. can.

又、ATM交換機においては、自由な振舞いをする入力
トラヒック特性についてスイッチ・リソースふくそうを
防ぐ流入トラヒック規制制御が必要である。本発明によ
る集線装置をATMスイッチ分配段の前に設置すること
で、ATMスイッチ網へ入力されるトラヒックを規制す
ることもできる。
Furthermore, in an ATM switch, incoming traffic regulation control is required to prevent switch resource congestion due to input traffic characteristics that behave freely. By installing the line concentrator according to the present invention in front of the ATM switch distribution stage, it is also possible to regulate the traffic input to the ATM switch network.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例を示すブロック図、第2図は
フレーム・メモリの構成を示す図、第3図は各入力セル
バッファが時分割多重される様子を示す概念図である。 001〜003・・・入力回線、101・・・出力回線
、111〜113・・・入力セルバッファ、201・・
・時分割多重回路、211・・・空セル生成回路、30
1・・・フレーム・メモリ。
FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing the configuration of a frame memory, and FIG. 3 is a conceptual diagram showing how each input cell buffer is time-division multiplexed. 001-003...Input line, 101...Output line, 111-113...Input cell buffer, 201...
- Time division multiplexing circuit, 211...Empty cell generation circuit, 30
1...Frame memory.

Claims (1)

【特許請求の範囲】[Claims] 1、ATMセルを運ぶ入力回線n本を1本の出力回線へ
集線するATMトラヒック集線方式において、前記各入
力回線ごとのATMセルを一時格納する入力セルバッフ
ァと、前記出力回線の1フレームn個に時分割されたタ
イム・スロットの番号と前記各入力回線の番号との対応
を記憶するフレーム・メモリとを備え、前記フレーム・
メモリのタイム・スロット番号と入力回線番号との対応
を呼ごと又は半固定的に設定し、前記タイム・スロット
ごとに前記フレーム・メモリを参照し前記入力セルバッ
ファから対応する入力回線のATMセルを読み出し前記
出力回線に出力することを特徴とするATMトラヒック
集線方式。2、請求項1記載のATMトラヒック集線方
式において、空セル生成回路を備え、対応する入力回線
が割当てられなかったタイム・スロットに対して空セル
を出力することを特徴とするATMトラヒック集線方式
1. In an ATM traffic concentration method in which n input lines carrying ATM cells are concentrated into one output line, an input cell buffer temporarily stores ATM cells for each input line, and n frames of one frame of the output line. a frame memory for storing the correspondence between the number of time slots time-divided into each input line and the number of each of the input lines;
The correspondence between the time slot number of the memory and the input line number is set for each call or semi-fixed, and the ATM cell of the corresponding input line is retrieved from the input cell buffer by referring to the frame memory for each time slot. An ATM traffic concentration system characterized in that reading is output to the output line. 2. The ATM traffic concentration system according to claim 1, further comprising an empty cell generation circuit and outputting empty cells to time slots to which no corresponding input line is assigned.
JP2261328A 1990-09-28 1990-09-28 Atm traffic line concentrator system Pending JPH04137941A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2261328A JPH04137941A (en) 1990-09-28 1990-09-28 Atm traffic line concentrator system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2261328A JPH04137941A (en) 1990-09-28 1990-09-28 Atm traffic line concentrator system

Publications (1)

Publication Number Publication Date
JPH04137941A true JPH04137941A (en) 1992-05-12

Family

ID=17360289

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2261328A Pending JPH04137941A (en) 1990-09-28 1990-09-28 Atm traffic line concentrator system

Country Status (1)

Country Link
JP (1) JPH04137941A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2421397A (en) * 2004-12-14 2006-06-21 Agilent Technologies Inc Low cost multi-port analysis and monitoring
KR200482034Y1 (en) * 2016-03-18 2016-12-07 주식회사 니프코코리아 Structure for Preventing Movement of Arm Rest

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2421397A (en) * 2004-12-14 2006-06-21 Agilent Technologies Inc Low cost multi-port analysis and monitoring
GB2421397B (en) * 2004-12-14 2009-03-18 Agilent Technologies Inc Apparatus and method for low cost, multi-port protocol analysis and monitoring
US7710891B2 (en) 2004-12-14 2010-05-04 Agilent Technologies, Inc. Apparatus and method for low cost, multi-port protocol analysis and monitoring
KR200482034Y1 (en) * 2016-03-18 2016-12-07 주식회사 니프코코리아 Structure for Preventing Movement of Arm Rest

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