JPH04139864A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH04139864A JPH04139864A JP26361490A JP26361490A JPH04139864A JP H04139864 A JPH04139864 A JP H04139864A JP 26361490 A JP26361490 A JP 26361490A JP 26361490 A JP26361490 A JP 26361490A JP H04139864 A JPH04139864 A JP H04139864A
- Authority
- JP
- Japan
- Prior art keywords
- die pad
- semiconductor element
- semiconductor device
- present
- sealing resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 37
- 229920005989 resin Polymers 0.000 claims description 10
- 239000011347 resin Substances 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims description 4
- 238000007789 sealing Methods 0.000 description 8
- 101100226116 Neurospora crassa (strain ATCC 24698 / 74-OR23-1A / CBS 708.71 / DSM 1257 / FGSC 987) esa-1 gene Proteins 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229920006015 heat resistant resin Polymers 0.000 description 1
- 239000000463 material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】 ［産業上の利用分野］ 本発明は半導体装置の半導体素子搭載部構造に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a structure of a semiconductor element mounting portion of a semiconductor device.
［従来の技術］
従来の半導体装置の半導体素子搭載部構造は第４図、第
５図に示すように、リードフレーム外枠２よりタイバー
３によって吊られ、半導体素子１より大きく一体ででき
たダイパッド４上に、半導体素子裏面の全面が接合され
る構造であった。[Prior Art] As shown in FIGS. 4 and 5, the structure of the semiconductor element mounting portion of a conventional semiconductor device includes a die pad that is hung from a lead frame outer frame 2 by tie bars 3 and is larger than the semiconductor element 1 and made of one piece. 4, the entire back surface of the semiconductor element was bonded to the top surface of the semiconductor element.
［発明が解決しようとする課題］
しかし前述の従来技術では、樹脂封止した半導体装置に
熱が加わると、
半導体素子とダイパッドの膨張率の違いから半導体素子
に応力が発生し特性不良を起こす、ダイパッドと封止樹
脂の界面の水分９が膨張し、ダイパッドエツジ部で応力
集中を起こした封止樹脂に割れ１２が生じる、という課
題を有する。[Problems to be Solved by the Invention] However, with the above-mentioned conventional technology, when heat is applied to a resin-sealed semiconductor device, stress is generated in the semiconductor element due to the difference in expansion coefficient between the semiconductor element and the die pad, causing characteristic defects. The problem is that moisture 9 at the interface between the die pad and the sealing resin expands, causing stress concentration at the edge of the die pad and causing cracks 12 in the sealing resin.
そこで本発明はこのような課題を解決するもので、その
目的とするところは半導体素子に応力を発生させず、ま
た封止樹脂に割れを生じない半導体装置を提供するとこ
ろにある。SUMMARY OF THE INVENTION The present invention is intended to solve these problems, and its purpose is to provide a semiconductor device that does not generate stress in the semiconductor element and does not cause cracks in the sealing resin.
［課題を解決するための手段］
本発明の半導体装置は、金属製リードフレームのダイパ
ッドに半導体素子を搭載し、該半導体素子電極とインナ
ーリードとを金属細線にて配線した後、樹脂封止してな
る半導体装置において、前記ダイパッドが多数ブロック
からなる切り欠き構造であることを特徴とする特
［作用］
本発明の上記の構成によれば、ダイパッドが切り欠き構
造であるため半導体素子とダイパッドとの膨張率の差を
緩和し、またダイパッド裏面での水分膨張が小さいため
エツジ部の応力集中も小さい。[Means for Solving the Problems] The semiconductor device of the present invention mounts a semiconductor element on a die pad of a metal lead frame, connects the semiconductor element electrode and an inner lead with a thin metal wire, and then seals the semiconductor element with a resin. Features of the semiconductor device characterized in that the die pad has a cutout structure consisting of a large number of blocks [Function] According to the above structure of the present invention, since the die pad has a cutout structure, the semiconductor element and the die pad can be easily connected to each other. This reduces the difference in the expansion rate of the die pad, and because the moisture expansion on the back surface of the die pad is small, the stress concentration at the edge is also small.
［実施例コ
第１図は本発明の実施例における半導体装置の内部平面
図である。半導体素子１ば裏面において、リードフレー
ム外枠２よりタイバー３に吊られた切り欠き構造である
ダイハツト４に搭載、接合され、ワイヤー５により半導
体素子電極とインナーリード６を配線した後、封止樹脂
７によって封止される。ダイパッド４は切り欠き構造に
よって多数ブロックから構成され、該多数ブロックは同
一材料で同一平面に一連に連なっている。Embodiment FIG. 1 is an internal plan view of a semiconductor device in an embodiment of the present invention. The semiconductor element 1 is mounted and bonded on the back side of the die hat 4, which is a cutout structure suspended from the lead frame outer frame 2 to the tie bar 3, and after wiring the semiconductor element electrode and the inner lead 6 with the wire 5, the sealing resin is applied. 7. The die pad 4 is composed of multiple blocks having a cutout structure, and the multiple blocks are made of the same material and are connected in series on the same plane.
第２図は本発明の実施例における半導体装置の側面断面
図である。半導体素子１がほとんど熱膨張しないのに対
し、ダイパッドは常温時のダイハツト４から熱膨張した
ダイパッド８へと大きな膨張を示す。しかし多数ブロッ
クとなったダイパッド４は多数ブロック各々の側方に膨
張するため半導体素子１を反らせる力が働かず、半導体
素子１の表面に応力は発生しない。FIG. 2 is a side sectional view of a semiconductor device in an embodiment of the present invention. While the semiconductor element 1 exhibits almost no thermal expansion, the die pad exhibits large expansion from the die hat 4 at room temperature to the thermally expanded die pad 8. However, since the die pad 4, which has become a large number of blocks, expands to the sides of each of the large number of blocks, no force is applied to warp the semiconductor element 1, and no stress is generated on the surface of the semiconductor element 1.
またダイパッド４と封止樹脂７の界面に存在する水分９
が熱膨張するが、多数ブロックの各々の面積が小さいた
め封止樹脂７に割れを生じるほど大きな膨張力とはなら
ず、悪くとも亀裂１０程度で外部までの割れとはならな
い。In addition, moisture 9 existing at the interface between the die pad 4 and the sealing resin 7
However, since the area of each of the multiple blocks is small, the expansion force is not large enough to cause cracks in the sealing resin 7, and at worst, the cracks are about 10 and do not extend to the outside.
第３図は本発明の他実施例における半導体装置のダイパ
ッド構造を示す平面図である。ダイパッド４は完全に多
数ブロックに分離され一連とはなっていないが、ダイパ
ッド４の下面よりポリイミドテープ１１などの耐熱性樹
脂によって固定され、その上に半導体素子１が接合され
る。FIG. 3 is a plan view showing a die pad structure of a semiconductor device in another embodiment of the present invention. Although the die pad 4 is completely separated into a number of blocks and does not form a series, the die pad 4 is fixed from the lower surface with a heat-resistant resin such as polyimide tape 11, and the semiconductor element 1 is bonded thereon.
［発明の効果］
以上述べたように本発明によればダイパッドを切り欠き
構造とした事により、半導体素子に応力が発生せず、ま
た封止樹脂に割れを生じないという効果を有する。[Effects of the Invention] As described above, according to the present invention, since the die pad has a cutout structure, stress is not generated in the semiconductor element and cracks are not generated in the sealing resin.
第１図は本発明の半導体装置の一実施例を示す内部平面
図、第２図は同側面断面図。
第３図は本発明の半導体装置の他実施例を示す平面図。
第４図は従来の半導体装置を示す内部平面図、第５図は
同側面断面図。
１・・・半導体素子
２・・・リードフレーム外枠
３・・・タイバー
４・・・ダイパッド
５・・・ワイヤー
６・・・インナーリード
７・・・封止樹脂
８・・・熱膨張したダイパッド
９・・・水分
１０・・・亀裂
１１・・・ポリイミドテープ
１２・・・割れ
以上FIG. 1 is an internal plan view showing an embodiment of the semiconductor device of the present invention, and FIG. 2 is a side sectional view of the same. FIG. 3 is a plan view showing another embodiment of the semiconductor device of the present invention. FIG. 4 is an internal plan view showing a conventional semiconductor device, and FIG. 5 is a side sectional view of the same. 1... Semiconductor element 2... Lead frame outer frame 3... Tie bar 4... Die pad 5... Wire 6... Inner lead 7... Sealing resin 8... Thermally expanded die pad 9...Moisture 10...Crack 11...Polyimide tape 12...Crack or more
Claims (1)
載し、該半導体素子電極とインナーリードとを金属細線
にて配線した後、樹脂封止してなる半導体装置において
、前記ダイパッドが多数ブロックからなる切り欠き構造
であることを特徴とする半導体装置。In a semiconductor device in which a semiconductor element is mounted on a die pad of a metal lead frame, the semiconductor element electrode and an inner lead are wired with thin metal wires, and then sealed with a resin, the die pad has a cutout structure consisting of a large number of blocks. A semiconductor device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26361490A JPH04139864A (en) | 1990-10-01 | 1990-10-01 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26361490A JPH04139864A (en) | 1990-10-01 | 1990-10-01 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04139864A true JPH04139864A (en) | 1992-05-13 |
Family
ID=17391985
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP26361490A Pending JPH04139864A (en) | 1990-10-01 | 1990-10-01 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04139864A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08204106A (en) * | 1995-01-25 | 1996-08-09 | Nec Corp | Resin sealed semiconductor device |
| WO1997012387A3 (en) * | 1995-09-29 | 1997-06-12 | Siemens Ag | Mounting frame for integrated circuits |
| EP0853817A1 (en) * | 1995-10-04 | 1998-07-22 | International Business Machines Corporation | Electronic package with enhanced pad design |
| US5825628A (en) * | 1996-10-03 | 1998-10-20 | International Business Machines Corporation | Electronic package with enhanced pad design |
-
1990
- 1990-10-01 JP JP26361490A patent/JPH04139864A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08204106A (en) * | 1995-01-25 | 1996-08-09 | Nec Corp | Resin sealed semiconductor device |
| EP0724294A3 (en) * | 1995-01-25 | 1998-09-02 | Nec Corporation | Semiconductor device mounted on tub having central slit pattern and peripheral slit pattern for absorbing thermal stress |
| WO1997012387A3 (en) * | 1995-09-29 | 1997-06-12 | Siemens Ag | Mounting frame for integrated circuits |
| EP0853817A1 (en) * | 1995-10-04 | 1998-07-22 | International Business Machines Corporation | Electronic package with enhanced pad design |
| US5825628A (en) * | 1996-10-03 | 1998-10-20 | International Business Machines Corporation | Electronic package with enhanced pad design |
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