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JPH04133451A - Semiconductor integrated circuit package - Google Patents

Semiconductor integrated circuit package

Info

Publication number
JPH04133451A
JPH04133451A JP2256695A JP25669590A JPH04133451A JP H04133451 A JPH04133451 A JP H04133451A JP 2256695 A JP2256695 A JP 2256695A JP 25669590 A JP25669590 A JP 25669590A JP H04133451 A JPH04133451 A JP H04133451A
Authority
JP
Japan
Prior art keywords
integrated circuit
semiconductor integrated
chip
circuit chip
package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2256695A
Other languages
Japanese (ja)
Inventor
Takeo Yoshikawa
吉川　武夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP2256695A priority Critical patent/JPH04133451A/en
Publication of JPH04133451A publication Critical patent/JPH04133451A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PURPOSE:To obtain a package to make the heat dissipation effect of a semiconductor integrated circuit chip improve by a method wherein the package is constituted into one having the chip, a mounting structure and metal pillars, which are buried in the mounted structure and dissipate heat, which is generated in the chip at the time of drive. CONSTITUTION:In a semiconductor integrated circuit package having a semiconductor integrated circuit chip 1, a mounting structure 3 and metal pillars 7, the chip 1 is one mounted on the structure 3, the structure 3 is one for sealing hermetically the mounted body 1 and the pillars 7 are provided in such a way that they are buried in the structure 3 and are ones for dissipating heat, which is generated in the chip 1 at the time of drive. For example, a semiconductor integrated circuit chip 1 is mounted on the surface of a ceramic wiring structure 3 comprising a wring conductor 12 and is hermetically sealed by a cap 6. A plurality of metal pillars 7 are buried in the structure 3 in such a way that they are provided being insulated electrically from both of the chip 1 and the conductor 2 in the interior of the structure 3.

Description

【発明の詳細な説明】 ［産業上の利用分野］ 本発明は、半導体集積回路用パッケージに関し、特に熱
抵抗の低いセラミックパッケージに関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a package for a semiconductor integrated circuit, and particularly to a ceramic package with low thermal resistance.

［従来の技術］ 従来、この種の半導体集積回路用パッケージは、半導体
集積回路チップを導電性接着剤を介してセラミックケー
スに実装し、次に金属あるいはセラミック材料で気密封
止して半導体集積回路パッケージを構成するのが一般的
であった。そして、半導体集積回路チップを実装するセ
ラミックケースには、その内部に配線導体を含みながら
ヒートシンクとしての作用を有するものと、配線導体を
含まずヒートシンクのみの作用を有するものとの２種類
があった。[Prior Art] Conventionally, this type of semiconductor integrated circuit package has been manufactured by mounting a semiconductor integrated circuit chip in a ceramic case via a conductive adhesive, and then hermetically sealing the semiconductor integrated circuit with a metal or ceramic material. It was common to configure packages. There were two types of ceramic cases for mounting semiconductor integrated circuit chips: those that contained wiring conductors inside and acted as heat sinks, and those that did not contain wiring conductors and acted only as heat sinks. .

〔発明が解決しようとする課題］ 上述した従来の半導体集積回路パッケージに、消費電力
の太きい、つまり発熱量の大きい半導体集積回路チップ
を実装すると、パッケージのもつ高い熱抵抗のため、半
導体集積回路チップの熱による破壊が発生しやすいとい
う欠点があった。更に半導体集積回路パッケージのキャ
ップに放熱フィンを設けてパッケージの熱抵抗を下げる
というパッケージ構造の場合も、ある値以上のハイパワ
ーの半導体集積回路チップに対しては十分でないという
欠点を有していた。[Problems to be Solved by the Invention] When a semiconductor integrated circuit chip that consumes a large amount of power, that is, generates a large amount of heat, is mounted on the above-mentioned conventional semiconductor integrated circuit package, the semiconductor integrated circuit may be damaged due to the high thermal resistance of the package. The drawback was that the chip was easily destroyed by heat. Furthermore, even in the case of a package structure in which heat dissipation fins are provided on the cap of a semiconductor integrated circuit package to lower the thermal resistance of the package, it has the disadvantage that it is not sufficient for high-power semiconductor integrated circuit chips exceeding a certain value. .

本発明の目的は半導体集積回路チップの放熱効果を向上
した半導体集積回路パッケージを提供することにある。An object of the present invention is to provide a semiconductor integrated circuit package that improves the heat dissipation effect of a semiconductor integrated circuit chip.

［課題を解決するための手段］ 前記目的を達成するため、本発明に係る半導体集積回路
パッケージにおいては、半導体集積回路チップと、実装
構造体と、金属柱とを有する半導体集積回路パッケージ
であって、 半導体集積回路チップは、実装構造体に実装されたもの
であり、 実装構造体は、実装された半導体集積回路チップを気密
封止するものであり、 金属柱は、実装構造体に埋設され、駆動時に半導体集積
回路チップに生ずる熱を放熱するものである。[Means for Solving the Problems] In order to achieve the above object, a semiconductor integrated circuit package according to the present invention includes a semiconductor integrated circuit chip, a mounting structure, and a metal pillar. , the semiconductor integrated circuit chip is mounted in a mounting structure, the mounting structure hermetically seals the mounted semiconductor integrated circuit chip, the metal pillar is embedded in the mounting structure, It radiates heat generated in the semiconductor integrated circuit chip during driving.

［作用〕 半導体集積回路チップｌに対向し、かつ隣接して金属柱
７が設けられている。これにより、金属柱７を介してチ
ップ１からの熱が効率的に放熱される。[Operation] A metal pillar 7 is provided opposite to and adjacent to the semiconductor integrated circuit chip l. Thereby, heat from the chip 1 is efficiently radiated via the metal pillar 7.

［実施例］ 次に本発明について図面を参照して説明する。[Example] Next, the present invention will be explained with reference to the drawings.

（実施例１） 第１図は、本発明の実施例１を示す縦断面図である。(Example 1) FIG. 1 is a longitudinal sectional view showing Example 1 of the present invention.

図において、半導体集積回路チップｌは、配線導体２を
含むセラミック配線構造体３の表面に実装され、配線導
体２は、外部接続端子４に接続されている。ここに、セ
ラミック配線構造体３は、チップ１を実装する実装構造
体を構成する。５は半導体集積回路チップ］と配線導体
２を接続する接続線であり、６は、気密封止用キャップ
である。In the figure, a semiconductor integrated circuit chip 1 is mounted on the surface of a ceramic wiring structure 3 including wiring conductors 2, and the wiring conductors 2 are connected to external connection terminals 4. Here, the ceramic wiring structure 3 constitutes a mounting structure on which the chip 1 is mounted. 5 is a connection line connecting the semiconductor integrated circuit chip and the wiring conductor 2, and 6 is an airtight sealing cap.

セラミック配線構造体３の内部には、半導体集積回路チ
ップ１と配線導体２の両者と電気的に絶縁し、かつ半導
体集積回路チップ１に対向し、かつ隣接して複数の金属
柱７，７．・・・が設けられている。Inside the ceramic wiring structure 3, there are a plurality of metal columns 7, 7, . ...is provided.

この隣接した金属柱７によって半導体集積回路チップ１
からの熱を効率的に放熱する。つまりセラミック配線構
造体３の熱伝導率を高めることができる。一方、セラミ
ック配線構造体３の熱応力は金属柱７との一体化によっ
て増加するので、金属柱７を多数個設ける場合は注意が
必要であるが、この場合、半導体集積回路チップ１と金
属柱７とが分離されているため、熱応力的には軽微であ
る。The semiconductor integrated circuit chip 1 is
Efficiently dissipate heat from the In other words, the thermal conductivity of the ceramic wiring structure 3 can be increased. On the other hand, the thermal stress of the ceramic wiring structure 3 increases when it is integrated with the metal pillars 7, so care must be taken when providing a large number of metal pillars 7. 7 is separated, the thermal stress is slight.

８はヒートシンクであり、セラミック配線構造体３によ
る放熱で十分でないとき設けられる。8 is a heat sink, which is provided when heat dissipation by the ceramic wiring structure 3 is not sufficient.

（実施例２） 第２図は、本発明の実施例２を示す縦断面図である。(Example 2) FIG. 2 is a longitudinal sectional view showing a second embodiment of the present invention.

本実施例では、半導体集積回路チップｌを導電性接着剤
１０によって、セラミックより構成されるセラミック封
止構造体９上に実装した例である。In this embodiment, a semiconductor integrated circuit chip 1 is mounted on a ceramic sealing structure 9 made of ceramic using a conductive adhesive 10.

ここに、セラミック封止構造体９は、チップ１を実装す
る実装構造体を構成する。セラミツク封止構造体９内部
に半導体集積回路チップ１と絶縁して、かつ半導体集積
回路チップｌに対向し、かつ隣接して金属柱７を複数個
設け、セラミック封止構造体９の熱伝導率を向上させる
ことは、前記第１図に示す実施例に示す場合と同じであ
る。Here, the ceramic sealing structure 9 constitutes a mounting structure on which the chip 1 is mounted. A plurality of metal pillars 7 are provided inside the ceramic sealing structure 9 insulated from the semiconductor integrated circuit chip 1 and facing and adjacent to the semiconductor integrated circuit chip 1, so that the thermal conductivity of the ceramic sealing structure 9 is This improvement is the same as that shown in the embodiment shown in FIG. 1 above.

［発明の効果］ 以上説明したように本発明はセラミック配線構造体内部
、あるいはセラミック封止構造体内部に金属柱を埋込む
ことにより、半導体集積回路チップの放熱効果を高め、
熱抵抗の小さい半導体集積回路パッケージを実現できる
効果がある。[Effects of the Invention] As explained above, the present invention improves the heat dissipation effect of a semiconductor integrated circuit chip by embedding metal pillars inside a ceramic wiring structure or a ceramic sealing structure.
This has the effect of realizing a semiconductor integrated circuit package with low thermal resistance.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は、本発明の実施例１を示す縦断面図、第２図は
、本発明の実施例２を示す縦断面図である。 ■・・・半導体集積回路チップ　２・・・配線導体３・
・・セラミック配線構造体　４・・・外部接続端子５・
・・接続線　　　　　　　　　６・・・キャップ７・・
・金属柱　　　　　　　　　８・・・ヒートシンク９・
・・セラミック封止構造体　１０・・・導電性接着剤特
許出願人　　日本電気株式会社 第 図FIG. 1 is a longitudinal sectional view showing a first embodiment of the present invention, and FIG. 2 is a longitudinal sectional view showing a second embodiment of the present invention. ■...Semiconductor integrated circuit chip 2...Wiring conductor 3.
...Ceramic wiring structure 4...External connection terminal 5.
・・Connection wire 6・Cap 7・・
・Metal pillar 8...Heat sink 9・
... Ceramic sealing structure 10 ... Conductive adhesive patent applicant NEC Corporation Figure

Claims (1)

【特許請求の範囲】[Claims] （１）半導体集積回路チップと、実装構造体と、金属柱
とを有する半導体集積回路パッケージであって、 半導体集積回路チップは、実装構造体に実装されたもの
であり、 実装構造体は、実装された半導体集積回路チップを気密
封止するものであり、 金属柱は、実装構造体に埋設され、駆動時に半導体集積
回路チップに生ずる熱を放熱するものであることを特徴
とする半導体集積回路パッケージ。(1) A semiconductor integrated circuit package including a semiconductor integrated circuit chip, a mounting structure, and a metal pillar, wherein the semiconductor integrated circuit chip is mounted on a mounting structure, and the mounting structure is a mounting structure. A semiconductor integrated circuit package for hermetically sealing a semiconductor integrated circuit chip, the metal pillar being embedded in the mounting structure and dissipating heat generated in the semiconductor integrated circuit chip during operation. .
JP2256695A 1990-09-26 1990-09-26 Semiconductor integrated circuit package Pending JPH04133451A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2256695A JPH04133451A (en) 1990-09-26 1990-09-26 Semiconductor integrated circuit package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2256695A JPH04133451A (en) 1990-09-26 1990-09-26 Semiconductor integrated circuit package

Publications (1)

Publication Number Publication Date
JPH04133451A true JPH04133451A (en) 1992-05-07

Family

ID=17296196

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2256695A Pending JPH04133451A (en) 1990-09-26 1990-09-26 Semiconductor integrated circuit package

Country Status (1)

Country Link
JP (1) JPH04133451A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5675183A (en) * 1995-07-12 1997-10-07 Dell Usa Lp Hybrid multichip module and methods of fabricating same
US6812066B2 (en) * 2000-12-04 2004-11-02 Fujitsu Limited Semiconductor device having an interconnecting post formed on an interposer within a sealing resin

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5675183A (en) * 1995-07-12 1997-10-07 Dell Usa Lp Hybrid multichip module and methods of fabricating same
US6812066B2 (en) * 2000-12-04 2004-11-02 Fujitsu Limited Semiconductor device having an interconnecting post formed on an interposer within a sealing resin

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